Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.38 97.30 89.76 97.22 72.62 94.40 98.44 89.89


Total test records in report: 1858
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html
T218 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2925363750 Jul 17 05:24:22 PM PDT 24 Jul 17 05:24:25 PM PDT 24 129787371 ps
T1772 /workspace/coverage/cover_reg_top/39.i2c_intr_test.4063333277 Jul 17 05:27:02 PM PDT 24 Jul 17 05:27:03 PM PDT 24 48972198 ps
T197 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.4179702515 Jul 17 05:23:07 PM PDT 24 Jul 17 05:23:10 PM PDT 24 273164169 ps
T1773 /workspace/coverage/cover_reg_top/43.i2c_intr_test.819674354 Jul 17 05:23:21 PM PDT 24 Jul 17 05:23:24 PM PDT 24 25267617 ps
T207 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3875344067 Jul 17 05:22:56 PM PDT 24 Jul 17 05:23:01 PM PDT 24 372692077 ps
T1774 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2084529664 Jul 17 05:23:39 PM PDT 24 Jul 17 05:23:42 PM PDT 24 19155401 ps
T1775 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2220595925 Jul 17 05:22:58 PM PDT 24 Jul 17 05:23:02 PM PDT 24 15804415 ps
T177 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2478463182 Jul 17 05:24:40 PM PDT 24 Jul 17 05:24:42 PM PDT 24 93732986 ps
T1776 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2929083656 Jul 17 05:25:32 PM PDT 24 Jul 17 05:25:33 PM PDT 24 19228748 ps
T1777 /workspace/coverage/cover_reg_top/16.i2c_intr_test.149893551 Jul 17 05:23:07 PM PDT 24 Jul 17 05:23:09 PM PDT 24 132238957 ps
T1778 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1123416917 Jul 17 05:24:51 PM PDT 24 Jul 17 05:24:54 PM PDT 24 29845750 ps
T1779 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.308347067 Jul 17 05:23:59 PM PDT 24 Jul 17 05:24:01 PM PDT 24 37555838 ps
T1780 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3766218860 Jul 17 05:23:02 PM PDT 24 Jul 17 05:23:06 PM PDT 24 27405183 ps
T1781 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4122513477 Jul 17 05:24:53 PM PDT 24 Jul 17 05:24:55 PM PDT 24 41746098 ps
T1782 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1660089755 Jul 17 05:26:50 PM PDT 24 Jul 17 05:26:59 PM PDT 24 953498058 ps
T1783 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4214973068 Jul 17 05:24:51 PM PDT 24 Jul 17 05:24:56 PM PDT 24 231266986 ps
T1784 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1876155272 Jul 17 05:23:05 PM PDT 24 Jul 17 05:23:08 PM PDT 24 241823095 ps
T1785 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3398369183 Jul 17 05:23:01 PM PDT 24 Jul 17 05:23:05 PM PDT 24 199573042 ps
T1786 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2087353202 Jul 17 05:24:17 PM PDT 24 Jul 17 05:24:22 PM PDT 24 545176535 ps
T219 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.4091113451 Jul 17 05:23:41 PM PDT 24 Jul 17 05:23:43 PM PDT 24 28373218 ps
T1787 /workspace/coverage/cover_reg_top/47.i2c_intr_test.4060220160 Jul 17 05:24:59 PM PDT 24 Jul 17 05:25:01 PM PDT 24 17690523 ps
T1788 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3173649314 Jul 17 05:24:17 PM PDT 24 Jul 17 05:24:20 PM PDT 24 61972099 ps
T1789 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2345933350 Jul 17 05:23:14 PM PDT 24 Jul 17 05:23:15 PM PDT 24 18950513 ps
T1790 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.965203288 Jul 17 05:22:57 PM PDT 24 Jul 17 05:23:02 PM PDT 24 143272583 ps
T1791 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2766138953 Jul 17 05:23:40 PM PDT 24 Jul 17 05:23:44 PM PDT 24 261071693 ps
T1792 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2162497199 Jul 17 05:24:17 PM PDT 24 Jul 17 05:24:19 PM PDT 24 32917479 ps
T224 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.46821922 Jul 17 05:23:17 PM PDT 24 Jul 17 05:23:24 PM PDT 24 529009005 ps
T220 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1660757170 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:54 PM PDT 24 15979259 ps
T266 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1428823842 Jul 17 05:24:21 PM PDT 24 Jul 17 05:24:25 PM PDT 24 595673155 ps
T1793 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2764681104 Jul 17 05:23:22 PM PDT 24 Jul 17 05:23:24 PM PDT 24 147047613 ps
T200 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1925115535 Jul 17 05:23:09 PM PDT 24 Jul 17 05:23:11 PM PDT 24 78625672 ps
T1794 /workspace/coverage/cover_reg_top/21.i2c_intr_test.638690416 Jul 17 05:23:28 PM PDT 24 Jul 17 05:23:31 PM PDT 24 51293630 ps
T1795 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4090961812 Jul 17 05:22:55 PM PDT 24 Jul 17 05:23:00 PM PDT 24 85052585 ps
T221 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1981523993 Jul 17 05:23:05 PM PDT 24 Jul 17 05:23:07 PM PDT 24 25207518 ps
T1796 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.727525178 Jul 17 05:23:01 PM PDT 24 Jul 17 05:23:05 PM PDT 24 58251215 ps
T1797 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2895489728 Jul 17 05:22:57 PM PDT 24 Jul 17 05:23:01 PM PDT 24 123780064 ps
T1798 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3845546824 Jul 17 05:23:05 PM PDT 24 Jul 17 05:23:07 PM PDT 24 19579912 ps
T1799 /workspace/coverage/cover_reg_top/37.i2c_intr_test.2691826190 Jul 17 05:23:45 PM PDT 24 Jul 17 05:23:46 PM PDT 24 17746595 ps
T1800 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4213813722 Jul 17 05:23:40 PM PDT 24 Jul 17 05:23:42 PM PDT 24 117714884 ps
T222 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2791946734 Jul 17 05:24:12 PM PDT 24 Jul 17 05:24:15 PM PDT 24 17644846 ps
T1801 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3468843080 Jul 17 05:24:59 PM PDT 24 Jul 17 05:25:03 PM PDT 24 150312419 ps
T1802 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2075177237 Jul 17 05:22:56 PM PDT 24 Jul 17 05:23:00 PM PDT 24 22454516 ps
T1803 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3477119832 Jul 17 05:24:52 PM PDT 24 Jul 17 05:24:55 PM PDT 24 23751767 ps
T1804 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1165264169 Jul 17 05:24:17 PM PDT 24 Jul 17 05:24:21 PM PDT 24 36337455 ps
T1805 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1772805055 Jul 17 05:23:38 PM PDT 24 Jul 17 05:23:40 PM PDT 24 138483225 ps
T1806 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2087342533 Jul 17 05:26:52 PM PDT 24 Jul 17 05:27:00 PM PDT 24 122000887 ps
T223 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1022251253 Jul 17 05:24:17 PM PDT 24 Jul 17 05:24:19 PM PDT 24 78594588 ps
T1807 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2143774651 Jul 17 05:24:14 PM PDT 24 Jul 17 05:24:16 PM PDT 24 73202108 ps
T1808 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3914319600 Jul 17 05:24:17 PM PDT 24 Jul 17 05:24:19 PM PDT 24 15810796 ps
T1809 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3823610109 Jul 17 05:22:49 PM PDT 24 Jul 17 05:22:54 PM PDT 24 295712074 ps
T1810 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2470767599 Jul 17 05:26:49 PM PDT 24 Jul 17 05:26:56 PM PDT 24 41877985 ps
T1811 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2666012236 Jul 17 05:23:34 PM PDT 24 Jul 17 05:23:36 PM PDT 24 25796816 ps
T1812 /workspace/coverage/cover_reg_top/1.i2c_intr_test.13512663 Jul 17 05:23:31 PM PDT 24 Jul 17 05:23:33 PM PDT 24 18881184 ps
T1813 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.677319433 Jul 17 05:23:59 PM PDT 24 Jul 17 05:24:01 PM PDT 24 27305239 ps
T225 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.820001798 Jul 17 05:24:14 PM PDT 24 Jul 17 05:24:16 PM PDT 24 48321476 ps
T1814 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1643365300 Jul 17 05:23:01 PM PDT 24 Jul 17 05:23:05 PM PDT 24 23737772 ps
T1815 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3556568311 Jul 17 05:23:40 PM PDT 24 Jul 17 05:23:42 PM PDT 24 46530438 ps
T1816 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1876807829 Jul 17 05:24:00 PM PDT 24 Jul 17 05:24:03 PM PDT 24 62975917 ps
T226 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1876602486 Jul 17 05:22:57 PM PDT 24 Jul 17 05:23:01 PM PDT 24 66619051 ps
T1817 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3555374055 Jul 17 05:23:20 PM PDT 24 Jul 17 05:23:22 PM PDT 24 25404460 ps
T1818 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.925437382 Jul 17 05:24:22 PM PDT 24 Jul 17 05:24:24 PM PDT 24 87639326 ps
T1819 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1066714182 Jul 17 05:23:40 PM PDT 24 Jul 17 05:23:43 PM PDT 24 198200355 ps
T227 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3691781961 Jul 17 05:24:20 PM PDT 24 Jul 17 05:24:24 PM PDT 24 40057797 ps
T1820 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2172751000 Jul 17 05:24:57 PM PDT 24 Jul 17 05:24:59 PM PDT 24 18830497 ps
T201 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2338973859 Jul 17 05:22:49 PM PDT 24 Jul 17 05:22:55 PM PDT 24 250394085 ps
T1821 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.444780953 Jul 17 05:24:53 PM PDT 24 Jul 17 05:24:56 PM PDT 24 56085191 ps
T1822 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4228523385 Jul 17 05:23:05 PM PDT 24 Jul 17 05:23:08 PM PDT 24 279334602 ps
T1823 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3587752371 Jul 17 05:24:08 PM PDT 24 Jul 17 05:24:10 PM PDT 24 21884118 ps
T1824 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4288472913 Jul 17 05:23:59 PM PDT 24 Jul 17 05:24:01 PM PDT 24 21785918 ps
T1825 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.565127756 Jul 17 05:24:51 PM PDT 24 Jul 17 05:24:55 PM PDT 24 553592175 ps
T208 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.714206062 Jul 17 05:23:02 PM PDT 24 Jul 17 05:23:06 PM PDT 24 79750857 ps
T1826 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.918765512 Jul 17 05:24:14 PM PDT 24 Jul 17 05:24:16 PM PDT 24 42321753 ps
T228 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1093386487 Jul 17 05:26:50 PM PDT 24 Jul 17 05:26:57 PM PDT 24 114226299 ps
T1827 /workspace/coverage/cover_reg_top/12.i2c_intr_test.60347947 Jul 17 05:26:52 PM PDT 24 Jul 17 05:26:58 PM PDT 24 20565980 ps
T199 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4284216850 Jul 17 05:24:52 PM PDT 24 Jul 17 05:24:56 PM PDT 24 533277996 ps
T1828 /workspace/coverage/cover_reg_top/49.i2c_intr_test.4081396174 Jul 17 05:23:25 PM PDT 24 Jul 17 05:23:27 PM PDT 24 33037244 ps
T1829 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3974994926 Jul 17 05:24:48 PM PDT 24 Jul 17 05:24:52 PM PDT 24 33883138 ps
T1830 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.272553271 Jul 17 05:24:53 PM PDT 24 Jul 17 05:24:56 PM PDT 24 29873993 ps
T1831 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1338975595 Jul 17 05:23:57 PM PDT 24 Jul 17 05:23:59 PM PDT 24 66253512 ps
T1832 /workspace/coverage/cover_reg_top/41.i2c_intr_test.75536498 Jul 17 05:24:56 PM PDT 24 Jul 17 05:24:58 PM PDT 24 27808576 ps
T1833 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3514584764 Jul 17 05:23:28 PM PDT 24 Jul 17 05:23:31 PM PDT 24 48990647 ps
T1834 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1624368931 Jul 17 05:24:59 PM PDT 24 Jul 17 05:25:03 PM PDT 24 117951580 ps
T204 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1856134554 Jul 17 05:26:52 PM PDT 24 Jul 17 05:26:59 PM PDT 24 276168551 ps
T1835 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.712323956 Jul 17 05:23:09 PM PDT 24 Jul 17 05:23:12 PM PDT 24 35758830 ps
T1836 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.543062169 Jul 17 05:23:12 PM PDT 24 Jul 17 05:23:14 PM PDT 24 57450373 ps
T1837 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1749960054 Jul 17 05:24:59 PM PDT 24 Jul 17 05:25:01 PM PDT 24 67524978 ps
T229 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1037346335 Jul 17 05:22:58 PM PDT 24 Jul 17 05:23:02 PM PDT 24 31437979 ps
T1838 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.255692393 Jul 17 05:22:50 PM PDT 24 Jul 17 05:22:54 PM PDT 24 222817792 ps
T1839 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2943337685 Jul 17 05:24:08 PM PDT 24 Jul 17 05:24:10 PM PDT 24 25480926 ps
T1840 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.378302182 Jul 17 05:23:57 PM PDT 24 Jul 17 05:23:59 PM PDT 24 276787265 ps
T1841 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3700328118 Jul 17 05:23:09 PM PDT 24 Jul 17 05:23:11 PM PDT 24 15700847 ps
T1842 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2030753512 Jul 17 05:25:08 PM PDT 24 Jul 17 05:25:11 PM PDT 24 15280063 ps
T1843 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3778885447 Jul 17 05:24:07 PM PDT 24 Jul 17 05:24:09 PM PDT 24 18097749 ps
T1844 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.4001437137 Jul 17 05:24:14 PM PDT 24 Jul 17 05:24:17 PM PDT 24 120542223 ps
T1845 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.151741653 Jul 17 05:24:00 PM PDT 24 Jul 17 05:24:03 PM PDT 24 77077162 ps
T1846 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.950415539 Jul 17 05:23:12 PM PDT 24 Jul 17 05:23:14 PM PDT 24 60178500 ps
T1847 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3894922041 Jul 17 05:23:57 PM PDT 24 Jul 17 05:23:59 PM PDT 24 20624646 ps
T1848 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3139330338 Jul 17 05:23:23 PM PDT 24 Jul 17 05:23:25 PM PDT 24 20000268 ps
T1849 /workspace/coverage/cover_reg_top/35.i2c_intr_test.102893895 Jul 17 05:23:41 PM PDT 24 Jul 17 05:23:43 PM PDT 24 69576244 ps
T1850 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4033601161 Jul 17 05:22:58 PM PDT 24 Jul 17 05:23:03 PM PDT 24 36024053 ps
T1851 /workspace/coverage/cover_reg_top/25.i2c_intr_test.678162626 Jul 17 05:25:32 PM PDT 24 Jul 17 05:25:33 PM PDT 24 18904061 ps
T1852 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2079943263 Jul 17 05:23:18 PM PDT 24 Jul 17 05:23:20 PM PDT 24 91161929 ps
T1853 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3323192994 Jul 17 05:23:23 PM PDT 24 Jul 17 05:23:25 PM PDT 24 27224008 ps
T1854 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3639098044 Jul 17 05:23:10 PM PDT 24 Jul 17 05:23:13 PM PDT 24 35449510 ps
T1855 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2323605507 Jul 17 05:23:07 PM PDT 24 Jul 17 05:23:09 PM PDT 24 64413709 ps
T1856 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.236209785 Jul 17 05:23:02 PM PDT 24 Jul 17 05:23:06 PM PDT 24 253952049 ps
T1857 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2362398101 Jul 17 05:23:08 PM PDT 24 Jul 17 05:23:10 PM PDT 24 51487029 ps
T1858 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3422886319 Jul 17 05:23:59 PM PDT 24 Jul 17 05:24:01 PM PDT 24 47066448 ps

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.467744035
Short name T9
Test name
Test status
Simulation time 443645407 ps
CPU time 5.48 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 247040 kb
Host smart-eac678e8-6b87-4531-9f58-e17df688bcc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467744035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
467744035
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2090778127
Short name T5
Test name
Test status
Simulation time 1077765086 ps
CPU time 6.78 seconds
Started Jul 17 05:47:58 PM PDT 24
Finished Jul 17 05:48:07 PM PDT 24
Peak memory 230260 kb
Host smart-3132e686-7761-4358-81df-91d22196899b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090778127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2090778127
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3207770310
Short name T24
Test name
Test status
Simulation time 63500757010 ps
CPU time 693.34 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:58:24 PM PDT 24
Peak memory 1653796 kb
Host smart-e294cbeb-dd05-4028-9834-5e9ae5059d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207770310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3207770310
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1019850780
Short name T49
Test name
Test status
Simulation time 9864267400 ps
CPU time 10.03 seconds
Started Jul 17 05:39:36 PM PDT 24
Finished Jul 17 05:39:46 PM PDT 24
Peak memory 214248 kb
Host smart-8bc57f3d-1750-4fdd-9daa-ec388ae73d68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019850780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1019850780
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1468994767
Short name T108
Test name
Test status
Simulation time 130334404 ps
CPU time 2.54 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:06 PM PDT 24
Peak memory 204788 kb
Host smart-977c4aa3-da01-42d5-889b-8dc523f2fb44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468994767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1468994767
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.1734944112
Short name T3
Test name
Test status
Simulation time 1974340792 ps
CPU time 2.34 seconds
Started Jul 17 05:47:16 PM PDT 24
Finished Jul 17 05:47:20 PM PDT 24
Peak memory 205644 kb
Host smart-865cce3a-cfed-4f8e-99dd-ab00dd57a132
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734944112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.1734944112
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2560394092
Short name T31
Test name
Test status
Simulation time 8062820502 ps
CPU time 749.8 seconds
Started Jul 17 05:43:22 PM PDT 24
Finished Jul 17 05:55:53 PM PDT 24
Peak memory 1523828 kb
Host smart-5810fabf-1c0f-413b-a922-fee02db46990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560394092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2560394092
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.997536981
Short name T14
Test name
Test status
Simulation time 1082209141 ps
CPU time 14.56 seconds
Started Jul 17 05:39:30 PM PDT 24
Finished Jul 17 05:39:45 PM PDT 24
Peak memory 205464 kb
Host smart-bc924fe4-1aca-4dc4-9252-820a01fc9c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997536981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.997536981
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.280079830
Short name T134
Test name
Test status
Simulation time 20267558 ps
CPU time 0.7 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:43:08 PM PDT 24
Peak memory 205248 kb
Host smart-677b7ee3-d6cd-4ce4-8cbd-1f758c542e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280079830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.280079830
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.3217556679
Short name T58
Test name
Test status
Simulation time 43707094207 ps
CPU time 445.68 seconds
Started Jul 17 05:48:22 PM PDT 24
Finished Jul 17 05:55:50 PM PDT 24
Peak memory 2808524 kb
Host smart-1f1f0d67-594d-424b-a995-bb54d219cb47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217556679 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_stress_all.3217556679
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1918991109
Short name T180
Test name
Test status
Simulation time 67842883 ps
CPU time 0.86 seconds
Started Jul 17 05:39:28 PM PDT 24
Finished Jul 17 05:39:30 PM PDT 24
Peak memory 223800 kb
Host smart-6a21393e-fcd8-4cd0-810a-ce98ea6f1b39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918991109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1918991109
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/12.i2c_target_nack_txstretch.2693886796
Short name T160
Test name
Test status
Simulation time 1063269735 ps
CPU time 1.33 seconds
Started Jul 17 05:42:27 PM PDT 24
Finished Jul 17 05:42:29 PM PDT 24
Peak memory 222300 kb
Host smart-a6bdd40b-a3a8-452a-9580-b837d351eb31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693886796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_nack_txstretch.2693886796
Directory /workspace/12.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3113888847
Short name T35
Test name
Test status
Simulation time 959874348 ps
CPU time 1.02 seconds
Started Jul 17 05:47:03 PM PDT 24
Finished Jul 17 05:47:05 PM PDT 24
Peak memory 205224 kb
Host smart-cff1381b-2bb4-4afd-a1b9-4d93df6318e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113888847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3113888847
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1671953197
Short name T128
Test name
Test status
Simulation time 8478494701 ps
CPU time 175.67 seconds
Started Jul 17 05:47:47 PM PDT 24
Finished Jul 17 05:50:49 PM PDT 24
Peak memory 1036652 kb
Host smart-108cc23d-6681-44b6-aa43-4bd1cd0020a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671953197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1671953197
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.1194809976
Short name T61
Test name
Test status
Simulation time 5406414602 ps
CPU time 2.61 seconds
Started Jul 17 05:42:41 PM PDT 24
Finished Jul 17 05:42:45 PM PDT 24
Peak memory 205684 kb
Host smart-9a09f9c7-01e2-44e6-85df-7a56658b7ad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194809976 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.1194809976
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.270349865
Short name T103
Test name
Test status
Simulation time 931578054 ps
CPU time 2.29 seconds
Started Jul 17 05:23:02 PM PDT 24
Finished Jul 17 05:23:08 PM PDT 24
Peak memory 204668 kb
Host smart-6a0e765d-ed17-4546-97ac-e65f72c49c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270349865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.270349865
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1981523993
Short name T221
Test name
Test status
Simulation time 25207518 ps
CPU time 0.7 seconds
Started Jul 17 05:23:05 PM PDT 24
Finished Jul 17 05:23:07 PM PDT 24
Peak memory 204432 kb
Host smart-ab17cdc5-9e4d-431e-9d98-1ef98d6010e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981523993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1981523993
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.155173827
Short name T32
Test name
Test status
Simulation time 502577012 ps
CPU time 1.83 seconds
Started Jul 17 05:46:16 PM PDT 24
Finished Jul 17 05:46:19 PM PDT 24
Peak memory 213828 kb
Host smart-2d9f38ec-fb3e-460d-96fc-955edda3d519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155173827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.155173827
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3659608030
Short name T62
Test name
Test status
Simulation time 3504222862 ps
CPU time 5.01 seconds
Started Jul 17 05:42:15 PM PDT 24
Finished Jul 17 05:42:21 PM PDT 24
Peak memory 217820 kb
Host smart-73182ceb-9ab8-4eb6-8876-bf8eb0232e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659608030 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3659608030
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1652775570
Short name T16
Test name
Test status
Simulation time 23975954391 ps
CPU time 1443.65 seconds
Started Jul 17 05:45:51 PM PDT 24
Finished Jul 17 06:09:56 PM PDT 24
Peak memory 3795500 kb
Host smart-27e55161-de58-408d-a5a1-2308310f54a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652775570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1652775570
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.3007046857
Short name T30
Test name
Test status
Simulation time 9889969558 ps
CPU time 884.03 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 06:02:16 PM PDT 24
Peak memory 1625316 kb
Host smart-9e9750b1-5155-4997-9cea-b3457cfde248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007046857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.3007046857
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.2499803043
Short name T65
Test name
Test status
Simulation time 975123132 ps
CPU time 2.92 seconds
Started Jul 17 05:39:39 PM PDT 24
Finished Jul 17 05:39:43 PM PDT 24
Peak memory 213860 kb
Host smart-854a36e1-e610-478c-8cbd-dbebf8ef4374
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499803043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.2499803043
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.913094868
Short name T272
Test name
Test status
Simulation time 30781314828 ps
CPU time 173.16 seconds
Started Jul 17 05:38:56 PM PDT 24
Finished Jul 17 05:41:50 PM PDT 24
Peak memory 1139200 kb
Host smart-898dfa31-3c8a-44a8-9ff5-81e1ca35995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913094868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.913094868
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3383736260
Short name T173
Test name
Test status
Simulation time 159006901 ps
CPU time 4.34 seconds
Started Jul 17 05:46:59 PM PDT 24
Finished Jul 17 05:47:04 PM PDT 24
Peak memory 230360 kb
Host smart-1b706a95-5d37-4657-ac6b-2c68298ece24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383736260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3383736260
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2896798223
Short name T333
Test name
Test status
Simulation time 34527356 ps
CPU time 0.59 seconds
Started Jul 17 05:39:30 PM PDT 24
Finished Jul 17 05:39:31 PM PDT 24
Peak memory 204704 kb
Host smart-3225ee17-4d10-4ba8-9baa-839b918cec4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896798223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2896798223
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.4069822943
Short name T247
Test name
Test status
Simulation time 647354381 ps
CPU time 5.35 seconds
Started Jul 17 05:48:59 PM PDT 24
Finished Jul 17 05:49:08 PM PDT 24
Peak memory 205460 kb
Host smart-dcb07379-2bbe-44b5-bd07-aabf94182dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069822943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.4069822943
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1524062520
Short name T287
Test name
Test status
Simulation time 389829164 ps
CPU time 1.64 seconds
Started Jul 17 05:42:05 PM PDT 24
Finished Jul 17 05:42:07 PM PDT 24
Peak memory 205932 kb
Host smart-81043e42-fe86-4d7c-99cc-bf430e4debc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524062520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1524062520
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.2983747044
Short name T263
Test name
Test status
Simulation time 122844081 ps
CPU time 1.35 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:47:44 PM PDT 24
Peak memory 222052 kb
Host smart-a6f70428-3f6e-4369-a599-2673ca893331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983747044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.2983747044
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2724675231
Short name T215
Test name
Test status
Simulation time 23506590 ps
CPU time 0.79 seconds
Started Jul 17 05:24:21 PM PDT 24
Finished Jul 17 05:24:24 PM PDT 24
Peak memory 204420 kb
Host smart-776de08f-60f7-43f1-ad22-58a7199151e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724675231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2724675231
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2657205415
Short name T83
Test name
Test status
Simulation time 1297097696 ps
CPU time 20.13 seconds
Started Jul 17 05:43:34 PM PDT 24
Finished Jul 17 05:43:55 PM PDT 24
Peak memory 213760 kb
Host smart-9c12a05e-2a69-4cb4-a2f5-b2be70b367cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657205415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2657205415
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.4215287837
Short name T277
Test name
Test status
Simulation time 21068095 ps
CPU time 0.68 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:43 PM PDT 24
Peak memory 204620 kb
Host smart-ff6ef699-d06e-4e25-8f77-ff91348e8764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215287837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.4215287837
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.607955804
Short name T1186
Test name
Test status
Simulation time 2553086407 ps
CPU time 10.31 seconds
Started Jul 17 05:39:04 PM PDT 24
Finished Jul 17 05:39:16 PM PDT 24
Peak memory 205556 kb
Host smart-9c27093c-9349-4824-8bcb-6c7635325dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607955804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.607955804
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.3195275983
Short name T260
Test name
Test status
Simulation time 105043373 ps
CPU time 0.65 seconds
Started Jul 17 05:44:31 PM PDT 24
Finished Jul 17 05:44:32 PM PDT 24
Peak memory 205152 kb
Host smart-a13f54c3-46ef-4caf-8147-22c0341fff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195275983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3195275983
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3635807513
Short name T244
Test name
Test status
Simulation time 129328620 ps
CPU time 1.26 seconds
Started Jul 17 05:48:20 PM PDT 24
Finished Jul 17 05:48:23 PM PDT 24
Peak memory 205392 kb
Host smart-26bdd888-d051-4da2-86dc-52a1e3579b3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635807513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3635807513
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3875344067
Short name T207
Test name
Test status
Simulation time 372692077 ps
CPU time 2.11 seconds
Started Jul 17 05:22:56 PM PDT 24
Finished Jul 17 05:23:01 PM PDT 24
Peak memory 204732 kb
Host smart-63afe25d-bd3f-4ecf-823a-b0a5aca95583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875344067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3875344067
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.252574758
Short name T109
Test name
Test status
Simulation time 503219349 ps
CPU time 2.24 seconds
Started Jul 17 05:23:08 PM PDT 24
Finished Jul 17 05:23:11 PM PDT 24
Peak memory 204636 kb
Host smart-61f59c4c-0ff3-45f6-8635-84d78bff2fc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252574758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.252574758
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.2102481954
Short name T1077
Test name
Test status
Simulation time 123369748559 ps
CPU time 140.54 seconds
Started Jul 17 05:46:44 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 793812 kb
Host smart-45c2dda5-d4db-4a57-8084-b53d11e0ae1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102481954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.2102481954
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1484964928
Short name T80
Test name
Test status
Simulation time 4033818203 ps
CPU time 112.74 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:50:33 PM PDT 24
Peak memory 1182152 kb
Host smart-f787fc41-dc89-4dc4-9706-da26c5c0730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484964928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1484964928
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1415900240
Short name T38
Test name
Test status
Simulation time 1798272388 ps
CPU time 83.28 seconds
Started Jul 17 05:46:12 PM PDT 24
Finished Jul 17 05:47:36 PM PDT 24
Peak memory 383028 kb
Host smart-1f1e1218-f516-4aab-807d-20ee54f024f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415900240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1415900240
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3556568311
Short name T1815
Test name
Test status
Simulation time 46530438 ps
CPU time 0.69 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:42 PM PDT 24
Peak memory 204416 kb
Host smart-76e76a43-60a4-4178-8c62-76b927871dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556568311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3556568311
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.2430701347
Short name T356
Test name
Test status
Simulation time 2307597638 ps
CPU time 49.44 seconds
Started Jul 17 05:39:05 PM PDT 24
Finished Jul 17 05:39:55 PM PDT 24
Peak memory 213896 kb
Host smart-3557439d-bce5-40de-b82c-227bd762c491
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430701347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.2430701347
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.4182589774
Short name T383
Test name
Test status
Simulation time 107035872 ps
CPU time 2.3 seconds
Started Jul 17 05:46:45 PM PDT 24
Finished Jul 17 05:46:48 PM PDT 24
Peak memory 205844 kb
Host smart-2a150420-52ba-4ef7-a002-07cdf126301b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182589774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.4182589774
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.4196904719
Short name T250
Test name
Test status
Simulation time 702819041 ps
CPU time 28.73 seconds
Started Jul 17 05:43:07 PM PDT 24
Finished Jul 17 05:43:37 PM PDT 24
Peak memory 205492 kb
Host smart-2a318aed-c0f6-48a6-b34c-e74a4effe141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196904719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.4196904719
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2339310358
Short name T258
Test name
Test status
Simulation time 412075058 ps
CPU time 6.48 seconds
Started Jul 17 05:43:54 PM PDT 24
Finished Jul 17 05:44:01 PM PDT 24
Peak memory 205460 kb
Host smart-dc604bbf-52fd-488b-b6eb-8d3caca1fe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339310358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2339310358
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.4158731089
Short name T248
Test name
Test status
Simulation time 175989863 ps
CPU time 6.94 seconds
Started Jul 17 05:44:02 PM PDT 24
Finished Jul 17 05:44:10 PM PDT 24
Peak memory 205568 kb
Host smart-5798d5ee-9f45-4947-8f91-039e3ea97b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158731089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.4158731089
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3000456944
Short name T251
Test name
Test status
Simulation time 197871514 ps
CPU time 3.02 seconds
Started Jul 17 05:49:16 PM PDT 24
Finished Jul 17 05:49:23 PM PDT 24
Peak memory 205088 kb
Host smart-8271c46d-5232-44ef-8aa4-198210b770f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000456944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3000456944
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1088292307
Short name T259
Test name
Test status
Simulation time 3263475406 ps
CPU time 13.23 seconds
Started Jul 17 05:41:28 PM PDT 24
Finished Jul 17 05:41:42 PM PDT 24
Peak memory 205580 kb
Host smart-7ba0ba8e-11e5-40ec-a0a0-11a35b3bb019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088292307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1088292307
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.2594063144
Short name T347
Test name
Test status
Simulation time 20587638905 ps
CPU time 408.22 seconds
Started Jul 17 05:39:03 PM PDT 24
Finished Jul 17 05:45:52 PM PDT 24
Peak memory 3389436 kb
Host smart-6a5b45e6-fab5-4bc2-937e-3df285242f70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594063144 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.2594063144
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.4179702515
Short name T197
Test name
Test status
Simulation time 273164169 ps
CPU time 2.02 seconds
Started Jul 17 05:23:07 PM PDT 24
Finished Jul 17 05:23:10 PM PDT 24
Peak memory 204612 kb
Host smart-42ebd8e3-cfc7-4579-8d37-e0d79cc58830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179702515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.4179702515
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2338973859
Short name T201
Test name
Test status
Simulation time 250394085 ps
CPU time 2.23 seconds
Started Jul 17 05:22:49 PM PDT 24
Finished Jul 17 05:22:55 PM PDT 24
Peak memory 204824 kb
Host smart-45ce5c7f-d142-42ae-97a7-fd968949226c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338973859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2338973859
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.714206062
Short name T208
Test name
Test status
Simulation time 79750857 ps
CPU time 1.48 seconds
Started Jul 17 05:23:02 PM PDT 24
Finished Jul 17 05:23:06 PM PDT 24
Peak memory 204680 kb
Host smart-6b8c007f-dcea-40c2-b047-a415047c47f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714206062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.714206062
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2478463182
Short name T177
Test name
Test status
Simulation time 93732986 ps
CPU time 0.79 seconds
Started Jul 17 05:24:40 PM PDT 24
Finished Jul 17 05:24:42 PM PDT 24
Peak memory 204464 kb
Host smart-37098d70-abd5-46d1-8c0d-6d2f9aa83de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478463182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2478463182
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1984274974
Short name T20
Test name
Test status
Simulation time 130830340 ps
CPU time 2.67 seconds
Started Jul 17 05:38:49 PM PDT 24
Finished Jul 17 05:38:53 PM PDT 24
Peak memory 220824 kb
Host smart-16635061-6bc9-4b16-98f1-1eb7d0c882c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984274974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1984274974
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2710444544
Short name T898
Test name
Test status
Simulation time 464965920 ps
CPU time 1.64 seconds
Started Jul 17 05:43:18 PM PDT 24
Finished Jul 17 05:43:21 PM PDT 24
Peak memory 213916 kb
Host smart-b5e463a3-48a1-47a4-9f98-cd40a8fd8e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710444544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2710444544
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3456932388
Short name T495
Test name
Test status
Simulation time 370720461 ps
CPU time 2.69 seconds
Started Jul 17 05:44:51 PM PDT 24
Finished Jul 17 05:44:54 PM PDT 24
Peak memory 213800 kb
Host smart-67656db4-07a2-44ab-a4ba-e795768fa77a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456932388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3456932388
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1353883009
Short name T75
Test name
Test status
Simulation time 52860972 ps
CPU time 1.66 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 05:47:33 PM PDT 24
Peak memory 213808 kb
Host smart-817f9f36-1fb1-49f8-81bd-971b1153cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353883009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1353883009
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.378302182
Short name T1840
Test name
Test status
Simulation time 276787265 ps
CPU time 1.32 seconds
Started Jul 17 05:23:57 PM PDT 24
Finished Jul 17 05:23:59 PM PDT 24
Peak memory 204604 kb
Host smart-9c554d9f-af4f-4bb0-b9c0-448c2be0ef21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378302182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.378302182
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2603185414
Short name T1771
Test name
Test status
Simulation time 372198191 ps
CPU time 5.02 seconds
Started Jul 17 05:23:17 PM PDT 24
Finished Jul 17 05:23:23 PM PDT 24
Peak memory 204632 kb
Host smart-f0a336f8-4c82-4efe-9cb7-8827039152a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603185414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2603185414
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1347900487
Short name T214
Test name
Test status
Simulation time 19721691 ps
CPU time 0.75 seconds
Started Jul 17 05:22:52 PM PDT 24
Finished Jul 17 05:22:57 PM PDT 24
Peak memory 204496 kb
Host smart-b9cfe94e-58f9-40f8-be4f-62fbd3f94677
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347900487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1347900487
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2079943263
Short name T1852
Test name
Test status
Simulation time 91161929 ps
CPU time 1.35 seconds
Started Jul 17 05:23:18 PM PDT 24
Finished Jul 17 05:23:20 PM PDT 24
Peak memory 213320 kb
Host smart-a52c89be-b640-4b4f-b375-a4ce92cefebc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079943263 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2079943263
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3778885447
Short name T1843
Test name
Test status
Simulation time 18097749 ps
CPU time 0.76 seconds
Started Jul 17 05:24:07 PM PDT 24
Finished Jul 17 05:24:09 PM PDT 24
Peak memory 204412 kb
Host smart-14f13fb8-a037-43b2-9149-e6b69137697d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778885447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3778885447
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.372612938
Short name T107
Test name
Test status
Simulation time 42517999 ps
CPU time 0.96 seconds
Started Jul 17 05:22:55 PM PDT 24
Finished Jul 17 05:22:59 PM PDT 24
Peak memory 204496 kb
Host smart-56182a06-6ea8-440a-9fc8-039816d60ea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372612938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out
standing.372612938
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.4001437137
Short name T1844
Test name
Test status
Simulation time 120542223 ps
CPU time 1.75 seconds
Started Jul 17 05:24:14 PM PDT 24
Finished Jul 17 05:24:17 PM PDT 24
Peak memory 204672 kb
Host smart-075064eb-077d-47d4-96ec-beb905d9bc55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001437137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.4001437137
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1428823842
Short name T266
Test name
Test status
Simulation time 595673155 ps
CPU time 2.3 seconds
Started Jul 17 05:24:21 PM PDT 24
Finished Jul 17 05:24:25 PM PDT 24
Peak memory 204620 kb
Host smart-5fb0e354-05c4-4ea5-aae9-76046669d777
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428823842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1428823842
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3691781961
Short name T227
Test name
Test status
Simulation time 40057797 ps
CPU time 1.83 seconds
Started Jul 17 05:24:20 PM PDT 24
Finished Jul 17 05:24:24 PM PDT 24
Peak memory 204628 kb
Host smart-bbd463b7-0e62-4b35-8558-0b22ad8d1674
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691781961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3691781961
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.46821922
Short name T224
Test name
Test status
Simulation time 529009005 ps
CPU time 5.36 seconds
Started Jul 17 05:23:17 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 204608 kb
Host smart-a5f2ebcf-28b5-479e-a690-81247f9ca63a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46821922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.46821922
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.925437382
Short name T1818
Test name
Test status
Simulation time 87639326 ps
CPU time 0.73 seconds
Started Jul 17 05:24:22 PM PDT 24
Finished Jul 17 05:24:24 PM PDT 24
Peak memory 204420 kb
Host smart-75e24d13-185b-4e17-9809-e20ac0144408
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925437382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.925437382
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3781782929
Short name T149
Test name
Test status
Simulation time 67555964 ps
CPU time 0.98 seconds
Started Jul 17 05:22:47 PM PDT 24
Finished Jul 17 05:22:52 PM PDT 24
Peak memory 204796 kb
Host smart-568ad623-5cae-44f7-8f77-faf235671ed5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781782929 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3781782929
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.820001798
Short name T225
Test name
Test status
Simulation time 48321476 ps
CPU time 0.67 seconds
Started Jul 17 05:24:14 PM PDT 24
Finished Jul 17 05:24:16 PM PDT 24
Peak memory 204456 kb
Host smart-918a3780-3db1-45ae-b237-5e0cfa94fd26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820001798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.820001798
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.13512663
Short name T1812
Test name
Test status
Simulation time 18881184 ps
CPU time 0.7 seconds
Started Jul 17 05:23:31 PM PDT 24
Finished Jul 17 05:23:33 PM PDT 24
Peak memory 204392 kb
Host smart-01e3902e-e88a-4e30-a87f-1118d847ae17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13512663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.13512663
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1338975595
Short name T1831
Test name
Test status
Simulation time 66253512 ps
CPU time 1.15 seconds
Started Jul 17 05:23:57 PM PDT 24
Finished Jul 17 05:23:59 PM PDT 24
Peak memory 204620 kb
Host smart-5eb2a5c3-d7c2-4eb6-9df5-8e570e09bd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338975595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1338975595
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.428122203
Short name T203
Test name
Test status
Simulation time 196885646 ps
CPU time 2.96 seconds
Started Jul 17 05:22:56 PM PDT 24
Finished Jul 17 05:23:03 PM PDT 24
Peak memory 204696 kb
Host smart-96baf4cb-0ffa-41ca-b50e-7f8ac28ebec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428122203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.428122203
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.4063621326
Short name T196
Test name
Test status
Simulation time 173042786 ps
CPU time 1.46 seconds
Started Jul 17 05:22:55 PM PDT 24
Finished Jul 17 05:23:00 PM PDT 24
Peak memory 204700 kb
Host smart-2e6112c0-bdf7-460b-98dc-0ceeef20a88f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063621326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.4063621326
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2470767599
Short name T1810
Test name
Test status
Simulation time 41877985 ps
CPU time 0.75 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:56 PM PDT 24
Peak memory 204588 kb
Host smart-dc47e549-5a04-411d-a23c-7687e8fd1ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470767599 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2470767599
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.255692393
Short name T1838
Test name
Test status
Simulation time 222817792 ps
CPU time 0.72 seconds
Started Jul 17 05:22:50 PM PDT 24
Finished Jul 17 05:22:54 PM PDT 24
Peak memory 204648 kb
Host smart-c77d3246-bd9b-4317-81df-6260bf06042c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255692393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.255692393
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2220595925
Short name T1775
Test name
Test status
Simulation time 15804415 ps
CPU time 0.67 seconds
Started Jul 17 05:22:58 PM PDT 24
Finished Jul 17 05:23:02 PM PDT 24
Peak memory 204468 kb
Host smart-6ab0e590-d737-405a-9fac-29051096250d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220595925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2220595925
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.21031635
Short name T1765
Test name
Test status
Simulation time 115093148 ps
CPU time 0.86 seconds
Started Jul 17 05:24:05 PM PDT 24
Finished Jul 17 05:24:07 PM PDT 24
Peak memory 204536 kb
Host smart-27bae29a-5890-402d-924b-80d0f3d99ef8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21031635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_out
standing.21031635
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4228523385
Short name T1822
Test name
Test status
Simulation time 279334602 ps
CPU time 1.7 seconds
Started Jul 17 05:23:05 PM PDT 24
Finished Jul 17 05:23:08 PM PDT 24
Peak memory 204664 kb
Host smart-080def56-2427-43e9-912a-6eed0968a57c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228523385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4228523385
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4033601161
Short name T1850
Test name
Test status
Simulation time 36024053 ps
CPU time 1.62 seconds
Started Jul 17 05:22:58 PM PDT 24
Finished Jul 17 05:23:03 PM PDT 24
Peak memory 204728 kb
Host smart-8f013360-ee82-4e28-8c5f-5745fa5b854e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033601161 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.4033601161
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1093386487
Short name T228
Test name
Test status
Simulation time 114226299 ps
CPU time 0.8 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 204508 kb
Host smart-0c7023d7-7578-43ea-ac86-2f6ebf644286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093386487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1093386487
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3914319600
Short name T1808
Test name
Test status
Simulation time 15810796 ps
CPU time 0.71 seconds
Started Jul 17 05:24:17 PM PDT 24
Finished Jul 17 05:24:19 PM PDT 24
Peak memory 204484 kb
Host smart-26fa2427-2cd3-4906-9938-18a36cd31adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914319600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3914319600
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.918765512
Short name T1826
Test name
Test status
Simulation time 42321753 ps
CPU time 0.86 seconds
Started Jul 17 05:24:14 PM PDT 24
Finished Jul 17 05:24:16 PM PDT 24
Peak memory 204492 kb
Host smart-80ec2908-4657-42bc-a325-82a96d8d7bdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918765512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.918765512
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3823610109
Short name T1809
Test name
Test status
Simulation time 295712074 ps
CPU time 1.52 seconds
Started Jul 17 05:22:49 PM PDT 24
Finished Jul 17 05:22:54 PM PDT 24
Peak memory 204856 kb
Host smart-0e16f86d-6d66-4bfb-ad39-eb8bf17a4b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823610109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3823610109
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4261926181
Short name T202
Test name
Test status
Simulation time 84941346 ps
CPU time 1.33 seconds
Started Jul 17 05:24:08 PM PDT 24
Finished Jul 17 05:24:11 PM PDT 24
Peak memory 204616 kb
Host smart-a3ee064c-5417-46cf-8222-f461fd58fb73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261926181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4261926181
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.308347067
Short name T1779
Test name
Test status
Simulation time 37555838 ps
CPU time 0.95 seconds
Started Jul 17 05:23:59 PM PDT 24
Finished Jul 17 05:24:01 PM PDT 24
Peak memory 204632 kb
Host smart-76ccd10e-4431-422f-84bc-6be036560105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308347067 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.308347067
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3422886319
Short name T1858
Test name
Test status
Simulation time 47066448 ps
CPU time 0.8 seconds
Started Jul 17 05:23:59 PM PDT 24
Finished Jul 17 05:24:01 PM PDT 24
Peak memory 204540 kb
Host smart-4dfba6b6-a5a5-4c08-a5af-f85447ece614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422886319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3422886319
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.60347947
Short name T1827
Test name
Test status
Simulation time 20565980 ps
CPU time 0.69 seconds
Started Jul 17 05:26:52 PM PDT 24
Finished Jul 17 05:26:58 PM PDT 24
Peak memory 204424 kb
Host smart-8c68d892-957f-4517-9b04-394c1098e1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60347947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.60347947
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.965203288
Short name T1790
Test name
Test status
Simulation time 143272583 ps
CPU time 0.95 seconds
Started Jul 17 05:22:57 PM PDT 24
Finished Jul 17 05:23:02 PM PDT 24
Peak memory 204588 kb
Host smart-3647c262-d133-41ec-89d1-082ac85f0d8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965203288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.965203288
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2087342533
Short name T1806
Test name
Test status
Simulation time 122000887 ps
CPU time 2.75 seconds
Started Jul 17 05:26:52 PM PDT 24
Finished Jul 17 05:27:00 PM PDT 24
Peak memory 204736 kb
Host smart-71d92996-7381-491a-858c-0bb8003faa6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087342533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2087342533
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.151741653
Short name T1845
Test name
Test status
Simulation time 77077162 ps
CPU time 1.52 seconds
Started Jul 17 05:24:00 PM PDT 24
Finished Jul 17 05:24:03 PM PDT 24
Peak memory 204748 kb
Host smart-503c0f0f-c3c6-44a3-8ffd-c94a55c689ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151741653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.151741653
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1643365300
Short name T1814
Test name
Test status
Simulation time 23737772 ps
CPU time 0.86 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:05 PM PDT 24
Peak memory 204588 kb
Host smart-161db0e4-9665-4566-9601-39d89f129f2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643365300 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1643365300
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1660757170
Short name T220
Test name
Test status
Simulation time 15979259 ps
CPU time 0.71 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:54 PM PDT 24
Peak memory 204504 kb
Host smart-8a6d92f6-dd38-4d43-b6ed-96ae0f701613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660757170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1660757170
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.984736546
Short name T232
Test name
Test status
Simulation time 26487779 ps
CPU time 0.82 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:04 PM PDT 24
Peak memory 204580 kb
Host smart-2b876672-9257-4a77-b828-614a3ee97122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984736546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.984736546
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2250215693
Short name T195
Test name
Test status
Simulation time 27679531 ps
CPU time 1.31 seconds
Started Jul 17 05:23:59 PM PDT 24
Finished Jul 17 05:24:02 PM PDT 24
Peak memory 204608 kb
Host smart-dbbf6ad0-05b5-4890-b456-36bf65c23108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250215693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2250215693
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2424258120
Short name T179
Test name
Test status
Simulation time 240344846 ps
CPU time 1.38 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:54 PM PDT 24
Peak memory 204656 kb
Host smart-02a32479-f0e1-49e4-a4f7-c51cc2f6b383
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424258120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2424258120
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1772805055
Short name T1805
Test name
Test status
Simulation time 138483225 ps
CPU time 1.09 seconds
Started Jul 17 05:23:38 PM PDT 24
Finished Jul 17 05:23:40 PM PDT 24
Peak memory 204768 kb
Host smart-703f25d0-b6ad-4e70-a692-02976bf77405
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772805055 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1772805055
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1123416917
Short name T1778
Test name
Test status
Simulation time 29845750 ps
CPU time 0.7 seconds
Started Jul 17 05:24:51 PM PDT 24
Finished Jul 17 05:24:54 PM PDT 24
Peak memory 204180 kb
Host smart-44d53299-1319-46b7-8b47-d244b698bdc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123416917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1123416917
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3514584764
Short name T1833
Test name
Test status
Simulation time 48990647 ps
CPU time 0.67 seconds
Started Jul 17 05:23:28 PM PDT 24
Finished Jul 17 05:23:31 PM PDT 24
Peak memory 204080 kb
Host smart-ffd39b3c-f62e-4d40-bb05-4d61a92778ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514584764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3514584764
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1876807829
Short name T1816
Test name
Test status
Simulation time 62975917 ps
CPU time 1.21 seconds
Started Jul 17 05:24:00 PM PDT 24
Finished Jul 17 05:24:03 PM PDT 24
Peak memory 204776 kb
Host smart-2424f86b-8a8e-45f5-8a0c-51e5a36d6ea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876807829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1876807829
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.236209785
Short name T1856
Test name
Test status
Simulation time 253952049 ps
CPU time 1.46 seconds
Started Jul 17 05:23:02 PM PDT 24
Finished Jul 17 05:23:06 PM PDT 24
Peak memory 204724 kb
Host smart-2e353d5e-4fdc-4701-a2b8-ee07fe336ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236209785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.236209785
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.272553271
Short name T1830
Test name
Test status
Simulation time 29873993 ps
CPU time 1.01 seconds
Started Jul 17 05:24:53 PM PDT 24
Finished Jul 17 05:24:56 PM PDT 24
Peak memory 204512 kb
Host smart-1a3bcf58-e05e-4da7-94ab-fb775b3bf75b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272553271 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.272553271
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.4091113451
Short name T219
Test name
Test status
Simulation time 28373218 ps
CPU time 0.76 seconds
Started Jul 17 05:23:41 PM PDT 24
Finished Jul 17 05:23:43 PM PDT 24
Peak memory 204560 kb
Host smart-d420d1ce-5e1e-4e99-9a1f-2497fbf26817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091113451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.4091113451
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3700328118
Short name T1841
Test name
Test status
Simulation time 15700847 ps
CPU time 0.66 seconds
Started Jul 17 05:23:09 PM PDT 24
Finished Jul 17 05:23:11 PM PDT 24
Peak memory 204376 kb
Host smart-162d9c64-5471-4f81-9d50-e4a2658fb718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700328118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3700328118
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.444780953
Short name T1821
Test name
Test status
Simulation time 56085191 ps
CPU time 0.9 seconds
Started Jul 17 05:24:53 PM PDT 24
Finished Jul 17 05:24:56 PM PDT 24
Peak memory 204468 kb
Host smart-5fb87b22-2952-4bc5-af3a-db1382ebdf34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444780953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.444780953
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3259877825
Short name T194
Test name
Test status
Simulation time 194396474 ps
CPU time 1.33 seconds
Started Jul 17 05:23:12 PM PDT 24
Finished Jul 17 05:23:14 PM PDT 24
Peak memory 204668 kb
Host smart-ab785ba7-b271-448d-bcc8-3f842b244cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259877825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3259877825
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4090961812
Short name T1795
Test name
Test status
Simulation time 85052585 ps
CPU time 2.03 seconds
Started Jul 17 05:22:55 PM PDT 24
Finished Jul 17 05:23:00 PM PDT 24
Peak memory 204580 kb
Host smart-7fb270ff-a231-4794-929a-f01a581cb361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090961812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.4090961812
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.712323956
Short name T1835
Test name
Test status
Simulation time 35758830 ps
CPU time 1.25 seconds
Started Jul 17 05:23:09 PM PDT 24
Finished Jul 17 05:23:12 PM PDT 24
Peak memory 212912 kb
Host smart-518fd539-4b2a-4364-8c21-aef72535ca7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712323956 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.712323956
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.149893551
Short name T1777
Test name
Test status
Simulation time 132238957 ps
CPU time 0.64 seconds
Started Jul 17 05:23:07 PM PDT 24
Finished Jul 17 05:23:09 PM PDT 24
Peak memory 204380 kb
Host smart-875b25db-09d9-47ae-8f90-47c7d1c13924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149893551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.149893551
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.543062169
Short name T1836
Test name
Test status
Simulation time 57450373 ps
CPU time 0.87 seconds
Started Jul 17 05:23:12 PM PDT 24
Finished Jul 17 05:23:14 PM PDT 24
Peak memory 204496 kb
Host smart-088d3e84-ec87-4bbe-9772-7cd6137b0b16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543062169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.543062169
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3846067364
Short name T198
Test name
Test status
Simulation time 294470341 ps
CPU time 1.57 seconds
Started Jul 17 05:24:53 PM PDT 24
Finished Jul 17 05:24:57 PM PDT 24
Peak memory 204676 kb
Host smart-c099f704-6e80-4a86-8fcf-539bb136b0d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846067364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3846067364
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4284216850
Short name T199
Test name
Test status
Simulation time 533277996 ps
CPU time 2.15 seconds
Started Jul 17 05:24:52 PM PDT 24
Finished Jul 17 05:24:56 PM PDT 24
Peak memory 204404 kb
Host smart-acf9a273-2bda-43c1-9eaf-0f2410342d78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284216850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.4284216850
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3565010616
Short name T205
Test name
Test status
Simulation time 342320767 ps
CPU time 1.3 seconds
Started Jul 17 05:23:09 PM PDT 24
Finished Jul 17 05:23:11 PM PDT 24
Peak memory 212992 kb
Host smart-18925e69-9030-4799-b91d-4131aa1e8361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565010616 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3565010616
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4122513477
Short name T1781
Test name
Test status
Simulation time 41746098 ps
CPU time 0.82 seconds
Started Jul 17 05:24:53 PM PDT 24
Finished Jul 17 05:24:55 PM PDT 24
Peak memory 204468 kb
Host smart-26d384a8-f6a0-4d8c-a21f-3c6263370943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122513477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4122513477
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1934352615
Short name T1760
Test name
Test status
Simulation time 43184150 ps
CPU time 0.72 seconds
Started Jul 17 05:23:09 PM PDT 24
Finished Jul 17 05:23:11 PM PDT 24
Peak memory 204360 kb
Host smart-afe1d216-526b-40c3-ba3b-152da625a79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934352615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1934352615
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2323605507
Short name T1855
Test name
Test status
Simulation time 64413709 ps
CPU time 0.86 seconds
Started Jul 17 05:23:07 PM PDT 24
Finished Jul 17 05:23:09 PM PDT 24
Peak memory 204464 kb
Host smart-4de91b67-cb5d-4de8-90f2-3581514cf3c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323605507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2323605507
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1925115535
Short name T200
Test name
Test status
Simulation time 78625672 ps
CPU time 1.46 seconds
Started Jul 17 05:23:09 PM PDT 24
Finished Jul 17 05:23:11 PM PDT 24
Peak memory 204576 kb
Host smart-3aa04174-6bfb-416b-bd89-91ec9364a484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925115535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1925115535
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3639098044
Short name T1854
Test name
Test status
Simulation time 35449510 ps
CPU time 1.33 seconds
Started Jul 17 05:23:10 PM PDT 24
Finished Jul 17 05:23:13 PM PDT 24
Peak memory 213036 kb
Host smart-0fd57aaa-3378-4446-b060-88eb04f5a7e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639098044 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3639098044
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2791946734
Short name T222
Test name
Test status
Simulation time 17644846 ps
CPU time 0.75 seconds
Started Jul 17 05:24:12 PM PDT 24
Finished Jul 17 05:24:15 PM PDT 24
Peak memory 204464 kb
Host smart-879f8a6d-864d-4aeb-a0b1-73e52348da0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791946734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2791946734
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2345933350
Short name T1789
Test name
Test status
Simulation time 18950513 ps
CPU time 0.7 seconds
Started Jul 17 05:23:14 PM PDT 24
Finished Jul 17 05:23:15 PM PDT 24
Peak memory 204448 kb
Host smart-008dbc7f-4c33-49aa-80e9-4e19c2f052c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345933350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2345933350
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1224732992
Short name T230
Test name
Test status
Simulation time 31235063 ps
CPU time 1.19 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:43 PM PDT 24
Peak memory 204848 kb
Host smart-ba96f05d-0b07-42a6-ba82-243d5061f1fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224732992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1224732992
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1876155272
Short name T1784
Test name
Test status
Simulation time 241823095 ps
CPU time 1.17 seconds
Started Jul 17 05:23:05 PM PDT 24
Finished Jul 17 05:23:08 PM PDT 24
Peak memory 204700 kb
Host smart-06896eca-d9fd-433b-8e11-f59ca898ea5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876155272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1876155272
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4253002496
Short name T104
Test name
Test status
Simulation time 50323500 ps
CPU time 0.9 seconds
Started Jul 17 05:24:08 PM PDT 24
Finished Jul 17 05:24:10 PM PDT 24
Peak memory 204616 kb
Host smart-8b544f55-e535-49e9-b62d-f30f74bd4878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253002496 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.4253002496
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.4139053670
Short name T217
Test name
Test status
Simulation time 29911426 ps
CPU time 0.7 seconds
Started Jul 17 05:23:12 PM PDT 24
Finished Jul 17 05:23:13 PM PDT 24
Peak memory 204428 kb
Host smart-62297fe8-4033-4e04-aa52-63f0d5d481ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139053670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.4139053670
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2084529664
Short name T1774
Test name
Test status
Simulation time 19155401 ps
CPU time 0.64 seconds
Started Jul 17 05:23:39 PM PDT 24
Finished Jul 17 05:23:42 PM PDT 24
Peak memory 204448 kb
Host smart-e8d44d9f-de61-4901-9db3-593f569b6f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084529664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2084529664
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2666012236
Short name T1811
Test name
Test status
Simulation time 25796816 ps
CPU time 0.84 seconds
Started Jul 17 05:23:34 PM PDT 24
Finished Jul 17 05:23:36 PM PDT 24
Peak memory 204528 kb
Host smart-d8cda66a-747c-4852-b7ad-cec3b330aa38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666012236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2666012236
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.950415539
Short name T1846
Test name
Test status
Simulation time 60178500 ps
CPU time 1.24 seconds
Started Jul 17 05:23:12 PM PDT 24
Finished Jul 17 05:23:14 PM PDT 24
Peak memory 204756 kb
Host smart-487745fa-64c2-4dfb-be6a-e873e49fce7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950415539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.950415539
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.565127756
Short name T1825
Test name
Test status
Simulation time 553592175 ps
CPU time 2.33 seconds
Started Jul 17 05:24:51 PM PDT 24
Finished Jul 17 05:24:55 PM PDT 24
Peak memory 204732 kb
Host smart-0ff93347-cb8e-4516-913a-f1a1f271b91e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565127756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.565127756
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2925363750
Short name T218
Test name
Test status
Simulation time 129787371 ps
CPU time 1.22 seconds
Started Jul 17 05:24:22 PM PDT 24
Finished Jul 17 05:24:25 PM PDT 24
Peak memory 204596 kb
Host smart-1699027c-b7c0-4f77-b611-b25fce55d67a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925363750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2925363750
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.4070811600
Short name T1754
Test name
Test status
Simulation time 428976921 ps
CPU time 4.7 seconds
Started Jul 17 05:24:07 PM PDT 24
Finished Jul 17 05:24:13 PM PDT 24
Peak memory 204640 kb
Host smart-69a10db6-8121-4fe2-ab63-2614a7767ae4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070811600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.4070811600
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1022251253
Short name T223
Test name
Test status
Simulation time 78594588 ps
CPU time 0.74 seconds
Started Jul 17 05:24:17 PM PDT 24
Finished Jul 17 05:24:19 PM PDT 24
Peak memory 204536 kb
Host smart-0addfb2a-ec7e-4d67-bd85-8ce2533c69a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022251253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1022251253
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2895489728
Short name T1797
Test name
Test status
Simulation time 123780064 ps
CPU time 0.91 seconds
Started Jul 17 05:22:57 PM PDT 24
Finished Jul 17 05:23:01 PM PDT 24
Peak memory 204568 kb
Host smart-c9496f09-8625-4b73-a169-a2b0406bc507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895489728 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2895489728
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3587752371
Short name T1823
Test name
Test status
Simulation time 21884118 ps
CPU time 0.73 seconds
Started Jul 17 05:24:08 PM PDT 24
Finished Jul 17 05:24:10 PM PDT 24
Peak memory 204500 kb
Host smart-055826eb-32cd-4260-a694-b0e688a5a5e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587752371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3587752371
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3894922041
Short name T1847
Test name
Test status
Simulation time 20624646 ps
CPU time 0.67 seconds
Started Jul 17 05:23:57 PM PDT 24
Finished Jul 17 05:23:59 PM PDT 24
Peak memory 204412 kb
Host smart-c0cde691-3f2f-4032-af40-a625ab805d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894922041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3894922041
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2943337685
Short name T1839
Test name
Test status
Simulation time 25480926 ps
CPU time 0.87 seconds
Started Jul 17 05:24:08 PM PDT 24
Finished Jul 17 05:24:10 PM PDT 24
Peak memory 204440 kb
Host smart-4b48085a-69ef-4997-b761-81ad42cd989c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943337685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2943337685
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.73530246
Short name T148
Test name
Test status
Simulation time 45561630 ps
CPU time 1.14 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:43 PM PDT 24
Peak memory 204916 kb
Host smart-1aa2aa0b-525e-4a1d-acc9-7925f799d25e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73530246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.73530246
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.301322564
Short name T112
Test name
Test status
Simulation time 560992051 ps
CPU time 2.42 seconds
Started Jul 17 05:23:17 PM PDT 24
Finished Jul 17 05:23:21 PM PDT 24
Peak memory 204600 kb
Host smart-3ac246a6-a6b4-497e-a709-8ce52fc7fe2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301322564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.301322564
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1511482008
Short name T1756
Test name
Test status
Simulation time 41695404 ps
CPU time 0.66 seconds
Started Jul 17 05:23:08 PM PDT 24
Finished Jul 17 05:23:09 PM PDT 24
Peak memory 204368 kb
Host smart-2043661a-6737-41e7-980a-403ee8361b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511482008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1511482008
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.638690416
Short name T1794
Test name
Test status
Simulation time 51293630 ps
CPU time 0.68 seconds
Started Jul 17 05:23:28 PM PDT 24
Finished Jul 17 05:23:31 PM PDT 24
Peak memory 204380 kb
Host smart-fa63ec0f-40da-4964-939f-eb418cf26e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638690416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.638690416
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2929083656
Short name T1776
Test name
Test status
Simulation time 19228748 ps
CPU time 0.68 seconds
Started Jul 17 05:25:32 PM PDT 24
Finished Jul 17 05:25:33 PM PDT 24
Peak memory 204624 kb
Host smart-309b385a-51fa-48b8-bfda-a19fa434c5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929083656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2929083656
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2403262378
Short name T1766
Test name
Test status
Simulation time 25513669 ps
CPU time 0.7 seconds
Started Jul 17 05:24:48 PM PDT 24
Finished Jul 17 05:24:52 PM PDT 24
Peak memory 204376 kb
Host smart-a782afb0-3cdd-4a32-9a2c-5c10173b8bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403262378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2403262378
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.472636327
Short name T1757
Test name
Test status
Simulation time 39207433 ps
CPU time 0.68 seconds
Started Jul 17 05:23:21 PM PDT 24
Finished Jul 17 05:23:23 PM PDT 24
Peak memory 204464 kb
Host smart-2c675723-6ce0-4177-b24c-7b1e881a662b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472636327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.472636327
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.678162626
Short name T1851
Test name
Test status
Simulation time 18904061 ps
CPU time 0.75 seconds
Started Jul 17 05:25:32 PM PDT 24
Finished Jul 17 05:25:33 PM PDT 24
Peak memory 204600 kb
Host smart-755a8098-c922-4be2-942e-e265d234d93e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678162626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.678162626
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.432482114
Short name T1753
Test name
Test status
Simulation time 50416438 ps
CPU time 0.72 seconds
Started Jul 17 05:23:22 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 204460 kb
Host smart-bca5d6ba-5c9c-42a6-82b7-db3bfa1303df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432482114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.432482114
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3567688347
Short name T1761
Test name
Test status
Simulation time 21209892 ps
CPU time 0.7 seconds
Started Jul 17 05:25:32 PM PDT 24
Finished Jul 17 05:25:33 PM PDT 24
Peak memory 204676 kb
Host smart-69bf1601-6253-4995-880a-f636ed6b6fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567688347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3567688347
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3323192994
Short name T1853
Test name
Test status
Simulation time 27224008 ps
CPU time 0.65 seconds
Started Jul 17 05:23:23 PM PDT 24
Finished Jul 17 05:23:25 PM PDT 24
Peak memory 204476 kb
Host smart-77e885c5-2029-4c37-a0da-c5412784925c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323192994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3323192994
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2063424689
Short name T216
Test name
Test status
Simulation time 111267252 ps
CPU time 1.76 seconds
Started Jul 17 05:24:07 PM PDT 24
Finished Jul 17 05:24:11 PM PDT 24
Peak memory 204632 kb
Host smart-b15bfcba-6eeb-439a-91b8-6c5fd0a083db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063424689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2063424689
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1660089755
Short name T1782
Test name
Test status
Simulation time 953498058 ps
CPU time 2.9 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:26:59 PM PDT 24
Peak memory 204600 kb
Host smart-f58f05e9-1ee7-46f7-b351-3e2137b74261
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660089755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1660089755
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2075177237
Short name T1802
Test name
Test status
Simulation time 22454516 ps
CPU time 0.73 seconds
Started Jul 17 05:22:56 PM PDT 24
Finished Jul 17 05:23:00 PM PDT 24
Peak memory 204560 kb
Host smart-1eb32386-7bc7-4002-8146-afe4175aa33b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075177237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2075177237
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.657670189
Short name T110
Test name
Test status
Simulation time 155209942 ps
CPU time 1.01 seconds
Started Jul 17 05:24:17 PM PDT 24
Finished Jul 17 05:24:20 PM PDT 24
Peak memory 204632 kb
Host smart-2f3cb876-a25e-4bb7-9e69-604af7d48a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657670189 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.657670189
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2143774651
Short name T1807
Test name
Test status
Simulation time 73202108 ps
CPU time 0.75 seconds
Started Jul 17 05:24:14 PM PDT 24
Finished Jul 17 05:24:16 PM PDT 24
Peak memory 204424 kb
Host smart-1b1a6b25-fd0f-474e-a8e7-27f5e7cee0b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143774651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2143774651
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2162497199
Short name T1792
Test name
Test status
Simulation time 32917479 ps
CPU time 0.69 seconds
Started Jul 17 05:24:17 PM PDT 24
Finished Jul 17 05:24:19 PM PDT 24
Peak memory 204484 kb
Host smart-6ef172fb-bc13-40d9-8b74-72feeab4e426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162497199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2162497199
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3173649314
Short name T1788
Test name
Test status
Simulation time 61972099 ps
CPU time 0.88 seconds
Started Jul 17 05:24:17 PM PDT 24
Finished Jul 17 05:24:20 PM PDT 24
Peak memory 204540 kb
Host smart-8d6f0592-819d-4bd7-9281-d2654dc0667e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173649314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3173649314
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1165264169
Short name T1804
Test name
Test status
Simulation time 36337455 ps
CPU time 1.66 seconds
Started Jul 17 05:24:17 PM PDT 24
Finished Jul 17 05:24:21 PM PDT 24
Peak memory 204808 kb
Host smart-b2558522-d92d-4541-8963-fd2475453be4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165264169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1165264169
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2030753512
Short name T1842
Test name
Test status
Simulation time 15280063 ps
CPU time 0.65 seconds
Started Jul 17 05:25:08 PM PDT 24
Finished Jul 17 05:25:11 PM PDT 24
Peak memory 204380 kb
Host smart-7d1290e6-ed15-4eff-9532-989a3aab2651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030753512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2030753512
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3139330338
Short name T1848
Test name
Test status
Simulation time 20000268 ps
CPU time 0.7 seconds
Started Jul 17 05:23:23 PM PDT 24
Finished Jul 17 05:23:25 PM PDT 24
Peak memory 204464 kb
Host smart-a9b7d622-4826-4de3-b241-47374813dd5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139330338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3139330338
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3974994926
Short name T1829
Test name
Test status
Simulation time 33883138 ps
CPU time 0.69 seconds
Started Jul 17 05:24:48 PM PDT 24
Finished Jul 17 05:24:52 PM PDT 24
Peak memory 204376 kb
Host smart-73a03f12-c2e1-458d-a2cc-725f9e6623f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974994926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3974994926
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.630064513
Short name T276
Test name
Test status
Simulation time 36680861 ps
CPU time 0.65 seconds
Started Jul 17 05:23:21 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 204472 kb
Host smart-a4c9713c-0c53-44a8-8d3d-21b81c02b108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630064513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.630064513
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.818966719
Short name T1762
Test name
Test status
Simulation time 46246313 ps
CPU time 0.73 seconds
Started Jul 17 05:23:22 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 204384 kb
Host smart-9779fb64-6d5b-42e5-96ef-dfb6c1baa648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818966719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.818966719
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.102893895
Short name T1849
Test name
Test status
Simulation time 69576244 ps
CPU time 0.64 seconds
Started Jul 17 05:23:41 PM PDT 24
Finished Jul 17 05:23:43 PM PDT 24
Peak memory 204376 kb
Host smart-4fec9998-b09f-4d88-883c-65cc2cb8c792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102893895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.102893895
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3194592298
Short name T1764
Test name
Test status
Simulation time 49960402 ps
CPU time 0.66 seconds
Started Jul 17 05:23:20 PM PDT 24
Finished Jul 17 05:23:22 PM PDT 24
Peak memory 204376 kb
Host smart-8cb1a8f6-ea63-4f32-933e-3af6d14c8083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194592298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3194592298
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.2691826190
Short name T1799
Test name
Test status
Simulation time 17746595 ps
CPU time 0.63 seconds
Started Jul 17 05:23:45 PM PDT 24
Finished Jul 17 05:23:46 PM PDT 24
Peak memory 204416 kb
Host smart-dc347ae3-57a9-4a2e-98ef-b83d5a467e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691826190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2691826190
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3555374055
Short name T1817
Test name
Test status
Simulation time 25404460 ps
CPU time 0.69 seconds
Started Jul 17 05:23:20 PM PDT 24
Finished Jul 17 05:23:22 PM PDT 24
Peak memory 204428 kb
Host smart-bf4fc494-96b3-446e-abd5-993bcfcb62de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555374055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3555374055
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.4063333277
Short name T1772
Test name
Test status
Simulation time 48972198 ps
CPU time 0.63 seconds
Started Jul 17 05:27:02 PM PDT 24
Finished Jul 17 05:27:03 PM PDT 24
Peak memory 204396 kb
Host smart-fa90cba7-dc20-4a36-a6a0-1ebaf38e3e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063333277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.4063333277
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1876602486
Short name T226
Test name
Test status
Simulation time 66619051 ps
CPU time 1.28 seconds
Started Jul 17 05:22:57 PM PDT 24
Finished Jul 17 05:23:01 PM PDT 24
Peak memory 204684 kb
Host smart-0f1b6d77-a4b0-4e11-b09e-06dd7597a30c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876602486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1876602486
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1442834219
Short name T1758
Test name
Test status
Simulation time 465306124 ps
CPU time 4.37 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:27:01 PM PDT 24
Peak memory 204628 kb
Host smart-cc428956-f7a2-4e98-b789-2445581deb80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442834219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1442834219
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1037346335
Short name T229
Test name
Test status
Simulation time 31437979 ps
CPU time 0.76 seconds
Started Jul 17 05:22:58 PM PDT 24
Finished Jul 17 05:23:02 PM PDT 24
Peak memory 204520 kb
Host smart-4cf8e402-dd48-45d0-8804-259af29f4b25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037346335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1037346335
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.677319433
Short name T1813
Test name
Test status
Simulation time 27305239 ps
CPU time 0.82 seconds
Started Jul 17 05:23:59 PM PDT 24
Finished Jul 17 05:24:01 PM PDT 24
Peak memory 204388 kb
Host smart-90b63cd3-d216-42fd-af2f-08811514de91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677319433 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.677319433
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1319754117
Short name T234
Test name
Test status
Simulation time 20174835 ps
CPU time 0.71 seconds
Started Jul 17 05:22:57 PM PDT 24
Finished Jul 17 05:23:01 PM PDT 24
Peak memory 204556 kb
Host smart-a0076253-816f-49b0-aed4-e45dce1844fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319754117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1319754117
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1961748606
Short name T133
Test name
Test status
Simulation time 17971005 ps
CPU time 0.65 seconds
Started Jul 17 05:26:49 PM PDT 24
Finished Jul 17 05:26:55 PM PDT 24
Peak memory 204420 kb
Host smart-62ef9858-f89e-454e-b9f3-3e061ee86ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961748606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1961748606
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1214531422
Short name T231
Test name
Test status
Simulation time 57683711 ps
CPU time 0.91 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:53 PM PDT 24
Peak memory 204504 kb
Host smart-bc6c9605-97cb-4aed-819d-074c82eb354c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214531422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1214531422
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2087353202
Short name T1786
Test name
Test status
Simulation time 545176535 ps
CPU time 2.53 seconds
Started Jul 17 05:24:17 PM PDT 24
Finished Jul 17 05:24:22 PM PDT 24
Peak memory 204812 kb
Host smart-f12ff3c8-a535-4978-9559-907db48078ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087353202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2087353202
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1856134554
Short name T204
Test name
Test status
Simulation time 276168551 ps
CPU time 1.39 seconds
Started Jul 17 05:26:52 PM PDT 24
Finished Jul 17 05:26:59 PM PDT 24
Peak memory 204704 kb
Host smart-af5010b6-b111-4cd0-aaf8-7782ddab7c06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856134554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1856134554
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.252974015
Short name T278
Test name
Test status
Simulation time 46225102 ps
CPU time 0.66 seconds
Started Jul 17 05:23:57 PM PDT 24
Finished Jul 17 05:23:59 PM PDT 24
Peak memory 204652 kb
Host smart-3caeb259-26d3-4284-9858-0028020f2541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252974015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.252974015
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.75536498
Short name T1832
Test name
Test status
Simulation time 27808576 ps
CPU time 0.69 seconds
Started Jul 17 05:24:56 PM PDT 24
Finished Jul 17 05:24:58 PM PDT 24
Peak memory 204376 kb
Host smart-ed604ac6-9623-45ef-8d80-f0d4226da635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75536498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.75536498
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2172751000
Short name T1820
Test name
Test status
Simulation time 18830497 ps
CPU time 0.65 seconds
Started Jul 17 05:24:57 PM PDT 24
Finished Jul 17 05:24:59 PM PDT 24
Peak memory 204460 kb
Host smart-2419ca9b-dc16-445d-9328-296fc6ab5f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172751000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2172751000
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.819674354
Short name T1773
Test name
Test status
Simulation time 25267617 ps
CPU time 0.71 seconds
Started Jul 17 05:23:21 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 204424 kb
Host smart-57a355bc-3ec4-4c58-8a39-78ccabb42cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819674354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.819674354
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2718672379
Short name T1755
Test name
Test status
Simulation time 129721354 ps
CPU time 0.67 seconds
Started Jul 17 05:24:58 PM PDT 24
Finished Jul 17 05:25:00 PM PDT 24
Peak memory 204460 kb
Host smart-6a122eee-0f00-4d8f-8e49-4853c798a8b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718672379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2718672379
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.191737190
Short name T1768
Test name
Test status
Simulation time 28176793 ps
CPU time 0.67 seconds
Started Jul 17 05:24:22 PM PDT 24
Finished Jul 17 05:24:25 PM PDT 24
Peak memory 204620 kb
Host smart-07930fca-4190-4334-84e0-2f795d3935c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191737190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.191737190
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2764681104
Short name T1793
Test name
Test status
Simulation time 147047613 ps
CPU time 0.67 seconds
Started Jul 17 05:23:22 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 204436 kb
Host smart-5cb4876b-464e-46f3-b332-5b5776fe6d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764681104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2764681104
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.4060220160
Short name T1787
Test name
Test status
Simulation time 17690523 ps
CPU time 0.69 seconds
Started Jul 17 05:24:59 PM PDT 24
Finished Jul 17 05:25:01 PM PDT 24
Peak memory 204460 kb
Host smart-8e5fc9c5-8005-483f-84e1-f41f181998dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060220160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.4060220160
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.519823710
Short name T1759
Test name
Test status
Simulation time 21469008 ps
CPU time 0.68 seconds
Started Jul 17 05:23:23 PM PDT 24
Finished Jul 17 05:23:25 PM PDT 24
Peak memory 204432 kb
Host smart-bebe11af-9bf2-414a-bd98-653f2b5f4a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519823710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.519823710
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.4081396174
Short name T1828
Test name
Test status
Simulation time 33037244 ps
CPU time 0.7 seconds
Started Jul 17 05:23:25 PM PDT 24
Finished Jul 17 05:23:27 PM PDT 24
Peak memory 204440 kb
Host smart-3c84aee8-8b9a-4111-85c5-f9e3e996fda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081396174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4081396174
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.727525178
Short name T1796
Test name
Test status
Simulation time 58251215 ps
CPU time 0.96 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:05 PM PDT 24
Peak memory 204620 kb
Host smart-7f7efb0f-5852-41da-aeea-46ba28542d33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727525178 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.727525178
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4288472913
Short name T1824
Test name
Test status
Simulation time 21785918 ps
CPU time 0.76 seconds
Started Jul 17 05:23:59 PM PDT 24
Finished Jul 17 05:24:01 PM PDT 24
Peak memory 204572 kb
Host smart-69d7d462-ddc9-4040-8925-07a59671fa99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288472913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.4288472913
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.645474877
Short name T275
Test name
Test status
Simulation time 18069211 ps
CPU time 0.68 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:53 PM PDT 24
Peak memory 204416 kb
Host smart-a24653bb-469c-4570-b43c-418dcbdf2998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645474877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.645474877
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4213813722
Short name T1800
Test name
Test status
Simulation time 117714884 ps
CPU time 0.89 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:42 PM PDT 24
Peak memory 204536 kb
Host smart-bbaff5ef-11c5-4b76-ae0d-1df12228714f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213813722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.4213813722
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1066714182
Short name T1819
Test name
Test status
Simulation time 198200355 ps
CPU time 1.46 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:43 PM PDT 24
Peak memory 204736 kb
Host smart-9e5b8837-4153-4ce8-9258-0b398fd11f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066714182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1066714182
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2766138953
Short name T1791
Test name
Test status
Simulation time 261071693 ps
CPU time 2.39 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:44 PM PDT 24
Peak memory 204700 kb
Host smart-52e933e4-3f16-45f8-94b3-ec75d4076d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766138953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2766138953
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1148514159
Short name T1769
Test name
Test status
Simulation time 76583589 ps
CPU time 0.81 seconds
Started Jul 17 05:23:02 PM PDT 24
Finished Jul 17 05:23:06 PM PDT 24
Peak memory 204540 kb
Host smart-06ed8a08-d506-4469-b366-5e3a3f85b318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148514159 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1148514159
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1091507131
Short name T206
Test name
Test status
Simulation time 103105988 ps
CPU time 0.69 seconds
Started Jul 17 05:23:28 PM PDT 24
Finished Jul 17 05:23:31 PM PDT 24
Peak memory 204176 kb
Host smart-f0bffb06-175c-4046-ac98-41a9fe99a645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091507131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1091507131
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1399806099
Short name T1763
Test name
Test status
Simulation time 20689176 ps
CPU time 0.68 seconds
Started Jul 17 05:23:58 PM PDT 24
Finished Jul 17 05:24:00 PM PDT 24
Peak memory 204484 kb
Host smart-038790ec-484e-4871-a4c0-d68f47784d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399806099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1399806099
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2916886274
Short name T111
Test name
Test status
Simulation time 64674437 ps
CPU time 1.13 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:04 PM PDT 24
Peak memory 204744 kb
Host smart-d8c5f79b-a377-4052-95b2-b1204896f9d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916886274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2916886274
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3398369183
Short name T1785
Test name
Test status
Simulation time 199573042 ps
CPU time 1.32 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:05 PM PDT 24
Peak memory 204784 kb
Host smart-f1ae0160-49c2-4d42-8473-1541998acf48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398369183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3398369183
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1624368931
Short name T1834
Test name
Test status
Simulation time 117951580 ps
CPU time 1.89 seconds
Started Jul 17 05:24:59 PM PDT 24
Finished Jul 17 05:25:03 PM PDT 24
Peak memory 212964 kb
Host smart-e9d8829a-de16-4bf6-9489-a52fd44f733f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624368931 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1624368931
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1749960054
Short name T1837
Test name
Test status
Simulation time 67524978 ps
CPU time 0.77 seconds
Started Jul 17 05:24:59 PM PDT 24
Finished Jul 17 05:25:01 PM PDT 24
Peak memory 204500 kb
Host smart-0c9f4b20-3063-4243-8ca1-14bb85794a56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749960054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1749960054
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2764446976
Short name T1767
Test name
Test status
Simulation time 23996536 ps
CPU time 0.68 seconds
Started Jul 17 05:23:02 PM PDT 24
Finished Jul 17 05:23:06 PM PDT 24
Peak memory 204444 kb
Host smart-4cf22c77-54d3-4d85-88ad-574aa9c71ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764446976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2764446976
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1425547866
Short name T105
Test name
Test status
Simulation time 40207837 ps
CPU time 0.94 seconds
Started Jul 17 05:24:58 PM PDT 24
Finished Jul 17 05:25:01 PM PDT 24
Peak memory 204464 kb
Host smart-63946d7d-c97d-46b3-87f4-d94cdbf405a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425547866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1425547866
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4214973068
Short name T1783
Test name
Test status
Simulation time 231266986 ps
CPU time 2.28 seconds
Started Jul 17 05:24:51 PM PDT 24
Finished Jul 17 05:24:56 PM PDT 24
Peak memory 204500 kb
Host smart-0d5608f7-884e-4bfd-8c0d-80ba96ad8874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214973068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4214973068
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3631301880
Short name T267
Test name
Test status
Simulation time 84837942 ps
CPU time 2.1 seconds
Started Jul 17 05:22:55 PM PDT 24
Finished Jul 17 05:23:01 PM PDT 24
Peak memory 204708 kb
Host smart-3a37fd6d-14a5-4a60-9a77-c61bff89ef13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631301880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3631301880
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.748393257
Short name T106
Test name
Test status
Simulation time 28551007 ps
CPU time 0.81 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:05 PM PDT 24
Peak memory 204576 kb
Host smart-e29197a5-b28a-4e3e-bddc-5b9d878c5c8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748393257 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.748393257
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3845546824
Short name T1798
Test name
Test status
Simulation time 19579912 ps
CPU time 0.68 seconds
Started Jul 17 05:23:05 PM PDT 24
Finished Jul 17 05:23:07 PM PDT 24
Peak memory 204436 kb
Host smart-dfdfef5b-28fc-4b12-8d2d-7ece7b322f8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845546824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3845546824
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3766218860
Short name T1780
Test name
Test status
Simulation time 27405183 ps
CPU time 0.66 seconds
Started Jul 17 05:23:02 PM PDT 24
Finished Jul 17 05:23:06 PM PDT 24
Peak memory 204424 kb
Host smart-30cdb026-6f8d-4ef0-92ea-9d3c0229963a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766218860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3766218860
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1836835632
Short name T233
Test name
Test status
Simulation time 33545116 ps
CPU time 0.88 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:04 PM PDT 24
Peak memory 204568 kb
Host smart-1c6ab3af-e8e3-4d33-ad43-bd2af90a7a1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836835632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1836835632
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3468843080
Short name T1801
Test name
Test status
Simulation time 150312419 ps
CPU time 1.89 seconds
Started Jul 17 05:24:59 PM PDT 24
Finished Jul 17 05:25:03 PM PDT 24
Peak memory 204740 kb
Host smart-d9d3a76e-cb84-4aa1-863b-1f9a17cf3a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468843080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3468843080
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3172572850
Short name T209
Test name
Test status
Simulation time 27115435 ps
CPU time 0.88 seconds
Started Jul 17 05:24:52 PM PDT 24
Finished Jul 17 05:24:55 PM PDT 24
Peak memory 204268 kb
Host smart-afda9bf3-eb12-41a2-b222-ad194c958576
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172572850 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3172572850
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3477119832
Short name T1803
Test name
Test status
Simulation time 23751767 ps
CPU time 0.73 seconds
Started Jul 17 05:24:52 PM PDT 24
Finished Jul 17 05:24:55 PM PDT 24
Peak memory 204376 kb
Host smart-b71d634e-22d3-4628-8fbc-0a2bba73b4d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477119832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3477119832
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3396982256
Short name T1770
Test name
Test status
Simulation time 33680421 ps
CPU time 0.9 seconds
Started Jul 17 05:23:02 PM PDT 24
Finished Jul 17 05:23:06 PM PDT 24
Peak memory 204568 kb
Host smart-8ce31123-0912-430c-9c97-4fc02398c540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396982256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3396982256
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2772676567
Short name T193
Test name
Test status
Simulation time 122405590 ps
CPU time 1.46 seconds
Started Jul 17 05:23:01 PM PDT 24
Finished Jul 17 05:23:06 PM PDT 24
Peak memory 204740 kb
Host smart-9bc55551-b596-4916-9d56-524b01bcca86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772676567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2772676567
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2362398101
Short name T1857
Test name
Test status
Simulation time 51487029 ps
CPU time 1.38 seconds
Started Jul 17 05:23:08 PM PDT 24
Finished Jul 17 05:23:10 PM PDT 24
Peak memory 204580 kb
Host smart-d17227ef-21f9-46dc-bd4c-c118f2868502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362398101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2362398101
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2466602540
Short name T1599
Test name
Test status
Simulation time 27250115 ps
CPU time 0.63 seconds
Started Jul 17 05:39:56 PM PDT 24
Finished Jul 17 05:39:58 PM PDT 24
Peak memory 204924 kb
Host smart-7c0b5857-4670-421f-bc60-2af5a2953938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466602540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2466602540
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.311630202
Short name T1455
Test name
Test status
Simulation time 579213767 ps
CPU time 14.16 seconds
Started Jul 17 05:38:50 PM PDT 24
Finished Jul 17 05:39:05 PM PDT 24
Peak memory 258744 kb
Host smart-1dcba69b-ab28-49b6-be22-ae3455cf7a03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311630202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.311630202
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.1373519288
Short name T701
Test name
Test status
Simulation time 18998376173 ps
CPU time 126.13 seconds
Started Jul 17 05:38:56 PM PDT 24
Finished Jul 17 05:41:02 PM PDT 24
Peak memory 837516 kb
Host smart-4791259a-1278-4d0f-aa0e-b8d0d7685f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373519288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1373519288
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.846904533
Short name T1381
Test name
Test status
Simulation time 2479717224 ps
CPU time 72.99 seconds
Started Jul 17 05:38:50 PM PDT 24
Finished Jul 17 05:40:03 PM PDT 24
Peak memory 747920 kb
Host smart-3596acbd-3fd6-43f2-9eaa-43baf8d53308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846904533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.846904533
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3040048803
Short name T1114
Test name
Test status
Simulation time 228469065 ps
CPU time 0.88 seconds
Started Jul 17 05:38:47 PM PDT 24
Finished Jul 17 05:38:49 PM PDT 24
Peak memory 205220 kb
Host smart-0e6ddd0f-add7-4386-8d81-fc0588a35dda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040048803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3040048803
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2998635172
Short name T1018
Test name
Test status
Simulation time 601511677 ps
CPU time 4.04 seconds
Started Jul 17 05:38:55 PM PDT 24
Finished Jul 17 05:38:59 PM PDT 24
Peak memory 229952 kb
Host smart-9c0b19b5-6e7d-4d63-affd-791fa9191375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998635172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2998635172
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1455512880
Short name T1513
Test name
Test status
Simulation time 4641345448 ps
CPU time 305.62 seconds
Started Jul 17 05:38:50 PM PDT 24
Finished Jul 17 05:43:56 PM PDT 24
Peak memory 1299936 kb
Host smart-1dc39b60-2e89-46fb-bcd6-cb2570a93301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455512880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1455512880
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_override.1385867338
Short name T845
Test name
Test status
Simulation time 28534787 ps
CPU time 0.69 seconds
Started Jul 17 05:38:50 PM PDT 24
Finished Jul 17 05:38:51 PM PDT 24
Peak memory 205184 kb
Host smart-09bfe889-656d-40fe-bcad-eb55c1311508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385867338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.1385867338
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3421943511
Short name T1484
Test name
Test status
Simulation time 6554005828 ps
CPU time 113.08 seconds
Started Jul 17 05:38:50 PM PDT 24
Finished Jul 17 05:40:44 PM PDT 24
Peak memory 797520 kb
Host smart-58b7648f-67b7-4009-95c0-2bf91c2d547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421943511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3421943511
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.2996696202
Short name T923
Test name
Test status
Simulation time 3147920346 ps
CPU time 61.45 seconds
Started Jul 17 05:39:22 PM PDT 24
Finished Jul 17 05:40:24 PM PDT 24
Peak memory 691808 kb
Host smart-683926fc-4a92-4d1e-a1c6-d2c3a7fe2365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996696202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.2996696202
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1310074843
Short name T651
Test name
Test status
Simulation time 26846649375 ps
CPU time 96.45 seconds
Started Jul 17 05:38:49 PM PDT 24
Finished Jul 17 05:40:26 PM PDT 24
Peak memory 418384 kb
Host smart-5b8f8b40-2a58-4b8e-ac41-577de3ba8494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310074843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1310074843
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1237782693
Short name T533
Test name
Test status
Simulation time 592937472 ps
CPU time 6.16 seconds
Started Jul 17 05:38:49 PM PDT 24
Finished Jul 17 05:38:56 PM PDT 24
Peak memory 213736 kb
Host smart-2d7f9b5c-7dd9-4a69-8db9-57facf058b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237782693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1237782693
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1933934192
Short name T184
Test name
Test status
Simulation time 306657272 ps
CPU time 0.93 seconds
Started Jul 17 05:39:44 PM PDT 24
Finished Jul 17 05:39:46 PM PDT 24
Peak memory 223984 kb
Host smart-8dfb0eb5-6de7-47ab-b673-b153e5fcfe37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933934192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1933934192
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3725123146
Short name T1002
Test name
Test status
Simulation time 4137332678 ps
CPU time 4.37 seconds
Started Jul 17 05:39:03 PM PDT 24
Finished Jul 17 05:39:09 PM PDT 24
Peak memory 213920 kb
Host smart-9ab31111-dbef-4dc1-9f0e-d9ac4df5626a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725123146 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3725123146
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.649539887
Short name T337
Test name
Test status
Simulation time 1493292921 ps
CPU time 0.95 seconds
Started Jul 17 05:39:02 PM PDT 24
Finished Jul 17 05:39:04 PM PDT 24
Peak memory 205404 kb
Host smart-11a1440d-60bf-4079-b48b-a7ec8549aa58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649539887 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_acq.649539887
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.511219298
Short name T315
Test name
Test status
Simulation time 137032960 ps
CPU time 1.05 seconds
Started Jul 17 05:39:02 PM PDT 24
Finished Jul 17 05:39:04 PM PDT 24
Peak memory 213664 kb
Host smart-801596a4-f347-47d5-838e-e8ceddb53c86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511219298 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.511219298
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.2714992589
Short name T809
Test name
Test status
Simulation time 633492610 ps
CPU time 3.03 seconds
Started Jul 17 05:39:03 PM PDT 24
Finished Jul 17 05:39:07 PM PDT 24
Peak memory 205676 kb
Host smart-42b5427e-c5a7-4c2a-99db-6a41b22b79dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714992589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.2714992589
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.1667568783
Short name T1148
Test name
Test status
Simulation time 351448296 ps
CPU time 1.51 seconds
Started Jul 17 05:40:32 PM PDT 24
Finished Jul 17 05:40:34 PM PDT 24
Peak memory 205432 kb
Host smart-a8563f46-268d-4691-a275-649636793feb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667568783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.1667568783
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2257130026
Short name T50
Test name
Test status
Simulation time 2200069308 ps
CPU time 11.75 seconds
Started Jul 17 05:38:51 PM PDT 24
Finished Jul 17 05:39:03 PM PDT 24
Peak memory 214180 kb
Host smart-79f4df5c-3db5-4cf1-ba6d-58b21361026d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257130026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2257130026
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.142063269
Short name T1328
Test name
Test status
Simulation time 669518017 ps
CPU time 2 seconds
Started Jul 17 05:39:03 PM PDT 24
Finished Jul 17 05:39:07 PM PDT 24
Peak memory 213780 kb
Host smart-f8b17ea5-d7a3-4e04-b597-cb23814bc64a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142063269 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_hrst.142063269
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.508260422
Short name T776
Test name
Test status
Simulation time 1347682780 ps
CPU time 8.61 seconds
Started Jul 17 05:39:03 PM PDT 24
Finished Jul 17 05:39:13 PM PDT 24
Peak memory 222016 kb
Host smart-91e3c4b5-a2d9-47c5-a74f-b36f7e094874
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508260422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.508260422
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.2441268031
Short name T1021
Test name
Test status
Simulation time 470552458 ps
CPU time 2.76 seconds
Started Jul 17 05:39:30 PM PDT 24
Finished Jul 17 05:39:34 PM PDT 24
Peak memory 213804 kb
Host smart-523530b2-694c-4a13-bd70-e1862507705b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441268031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_nack_acqfull.2441268031
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.2317707558
Short name T884
Test name
Test status
Simulation time 2201006508 ps
CPU time 2.58 seconds
Started Jul 17 05:39:17 PM PDT 24
Finished Jul 17 05:39:21 PM PDT 24
Peak memory 205692 kb
Host smart-042960bb-a442-4bad-8ee9-f851d20902ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317707558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.2317707558
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_txstretch.3765619507
Short name T1740
Test name
Test status
Simulation time 140226967 ps
CPU time 1.32 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:39:18 PM PDT 24
Peak memory 222360 kb
Host smart-3d86bf16-3022-4f0d-bd1f-39fff2b0e09a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765619507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_nack_txstretch.3765619507
Directory /workspace/0.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/0.i2c_target_perf.2212851448
Short name T1290
Test name
Test status
Simulation time 6809718411 ps
CPU time 6.6 seconds
Started Jul 17 05:39:37 PM PDT 24
Finished Jul 17 05:39:44 PM PDT 24
Peak memory 230188 kb
Host smart-7f47e9c4-7eb4-49c8-91dc-508b6c5eac75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212851448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.2212851448
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.200384082
Short name T1530
Test name
Test status
Simulation time 8866142561 ps
CPU time 2.39 seconds
Started Jul 17 05:39:04 PM PDT 24
Finished Jul 17 05:39:07 PM PDT 24
Peak memory 205476 kb
Host smart-7ad300f3-f49f-46f9-b7d9-49d149418338
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200384082 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_smbus_maxlen.200384082
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2601136607
Short name T908
Test name
Test status
Simulation time 3986214749 ps
CPU time 29.02 seconds
Started Jul 17 05:39:03 PM PDT 24
Finished Jul 17 05:39:33 PM PDT 24
Peak memory 213904 kb
Host smart-7ddd8a17-20ef-424b-b807-8bb595695e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601136607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2601136607
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.1084573272
Short name T375
Test name
Test status
Simulation time 31890338188 ps
CPU time 124.41 seconds
Started Jul 17 05:39:04 PM PDT 24
Finished Jul 17 05:41:09 PM PDT 24
Peak memory 1355692 kb
Host smart-f650b939-639e-4fff-9fad-2916518549e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084573272 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_stress_all.1084573272
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1807751
Short name T1189
Test name
Test status
Simulation time 35771187262 ps
CPU time 407.1 seconds
Started Jul 17 05:39:03 PM PDT 24
Finished Jul 17 05:45:52 PM PDT 24
Peak memory 3838960 kb
Host smart-9759548d-00ad-44fe-b1fd-9747e38c21c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stress_wr.1807751
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.2602208408
Short name T1257
Test name
Test status
Simulation time 1626254536 ps
CPU time 5.59 seconds
Started Jul 17 05:39:04 PM PDT 24
Finished Jul 17 05:39:11 PM PDT 24
Peak memory 219776 kb
Host smart-9924dca6-fe11-4e57-8f51-e77117f8c20c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602208408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.2602208408
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2714712882
Short name T1276
Test name
Test status
Simulation time 1447924611 ps
CPU time 6.68 seconds
Started Jul 17 05:39:49 PM PDT 24
Finished Jul 17 05:39:57 PM PDT 24
Peak memory 230024 kb
Host smart-25fbb628-d7bb-47d3-83fd-bc5c151788be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714712882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2714712882
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.866209083
Short name T999
Test name
Test status
Simulation time 181625778 ps
CPU time 3.95 seconds
Started Jul 17 05:39:05 PM PDT 24
Finished Jul 17 05:39:10 PM PDT 24
Peak memory 205636 kb
Host smart-d527b005-39ff-4863-8abc-38d3fd1a3fe1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866209083 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.866209083
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2863496689
Short name T1318
Test name
Test status
Simulation time 1068077015 ps
CPU time 3.64 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:39:20 PM PDT 24
Peak memory 221952 kb
Host smart-8ce932ef-cb1b-404b-b32f-3e9d12b3d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863496689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2863496689
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2819471387
Short name T506
Test name
Test status
Simulation time 1695011917 ps
CPU time 7.19 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:39:24 PM PDT 24
Peak memory 283756 kb
Host smart-02d7697a-8774-48df-a6d1-4bbd02c2c673
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819471387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2819471387
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3989984064
Short name T1747
Test name
Test status
Simulation time 3363631701 ps
CPU time 93.28 seconds
Started Jul 17 05:39:50 PM PDT 24
Finished Jul 17 05:41:24 PM PDT 24
Peak memory 624456 kb
Host smart-0a4c966d-a70e-40c4-b21c-eeefad2b0aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989984064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3989984064
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1779305520
Short name T527
Test name
Test status
Simulation time 2290864936 ps
CPU time 159.08 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:41:57 PM PDT 24
Peak memory 683412 kb
Host smart-3f5c17d0-1fe1-4721-8b74-05d530f65f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779305520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1779305520
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.175988744
Short name T1741
Test name
Test status
Simulation time 233705559 ps
CPU time 0.93 seconds
Started Jul 17 05:39:17 PM PDT 24
Finished Jul 17 05:39:19 PM PDT 24
Peak memory 205160 kb
Host smart-e1399f48-bcc5-45b8-8dd5-fd38ad42aff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175988744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt
.175988744
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1070174597
Short name T1289
Test name
Test status
Simulation time 628897639 ps
CPU time 10.19 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:39:27 PM PDT 24
Peak memory 239616 kb
Host smart-6ba7aaac-c934-4507-824d-411518f93ff6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070174597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1070174597
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1507413965
Short name T1702
Test name
Test status
Simulation time 15392622035 ps
CPU time 258.97 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:43:36 PM PDT 24
Peak memory 1129048 kb
Host smart-ed23a385-4fe4-4cee-b2a3-671c679528a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507413965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1507413965
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_override.260829465
Short name T1031
Test name
Test status
Simulation time 53561913 ps
CPU time 0.67 seconds
Started Jul 17 05:40:34 PM PDT 24
Finished Jul 17 05:40:35 PM PDT 24
Peak memory 205220 kb
Host smart-f0cb3761-4ad1-455f-8d90-1358f200f383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260829465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.260829465
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3098007443
Short name T403
Test name
Test status
Simulation time 3335887061 ps
CPU time 21.35 seconds
Started Jul 17 05:39:37 PM PDT 24
Finished Jul 17 05:39:59 PM PDT 24
Peak memory 405300 kb
Host smart-a4ccab7d-ab68-4558-88b4-06ca36a961b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098007443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3098007443
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.739936255
Short name T346
Test name
Test status
Simulation time 98253165 ps
CPU time 1.19 seconds
Started Jul 17 05:39:15 PM PDT 24
Finished Jul 17 05:39:17 PM PDT 24
Peak memory 222992 kb
Host smart-fed5e7d9-7850-40b2-b5ae-7534f2c50f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739936255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.739936255
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2872947599
Short name T168
Test name
Test status
Simulation time 3167649394 ps
CPU time 59.32 seconds
Started Jul 17 05:39:15 PM PDT 24
Finished Jul 17 05:40:15 PM PDT 24
Peak memory 376416 kb
Host smart-f4f546e1-8cdc-40a8-bf59-92aeb0a3be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872947599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2872947599
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2580984574
Short name T1553
Test name
Test status
Simulation time 2151059461 ps
CPU time 17.98 seconds
Started Jul 17 05:39:18 PM PDT 24
Finished Jul 17 05:39:37 PM PDT 24
Peak memory 220856 kb
Host smart-98371213-e22a-428e-9c97-9059fbdac6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580984574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2580984574
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3216225590
Short name T1072
Test name
Test status
Simulation time 550073713 ps
CPU time 3.86 seconds
Started Jul 17 05:39:19 PM PDT 24
Finished Jul 17 05:39:24 PM PDT 24
Peak memory 217700 kb
Host smart-39a7d62f-6e22-423d-9602-b06351e978f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216225590 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3216225590
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3078732396
Short name T783
Test name
Test status
Simulation time 212471075 ps
CPU time 1.44 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:39:19 PM PDT 24
Peak memory 205592 kb
Host smart-0a0d700d-ff80-48f0-a8ea-9538003f25ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078732396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3078732396
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1267534048
Short name T1436
Test name
Test status
Simulation time 221485707 ps
CPU time 1.41 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:39:18 PM PDT 24
Peak memory 205616 kb
Host smart-80318633-5538-412a-8e0e-3b8d88e323ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267534048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1267534048
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.608679203
Short name T1352
Test name
Test status
Simulation time 1149382395 ps
CPU time 1.3 seconds
Started Jul 17 05:39:30 PM PDT 24
Finished Jul 17 05:39:32 PM PDT 24
Peak memory 205464 kb
Host smart-e92fcbc6-3df1-4b7e-b73a-7809a0644b74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608679203 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.608679203
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.955199153
Short name T1212
Test name
Test status
Simulation time 1232969714 ps
CPU time 1.49 seconds
Started Jul 17 05:39:28 PM PDT 24
Finished Jul 17 05:39:30 PM PDT 24
Peak memory 205424 kb
Host smart-bf4ffe00-bf92-4670-8bf0-48886fe208a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955199153 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.955199153
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3293600542
Short name T1302
Test name
Test status
Simulation time 179757090 ps
CPU time 1.39 seconds
Started Jul 17 05:39:17 PM PDT 24
Finished Jul 17 05:39:20 PM PDT 24
Peak memory 221304 kb
Host smart-f6bd24af-c957-46f6-99e4-59be96e8b802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293600542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3293600542
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2528466104
Short name T726
Test name
Test status
Simulation time 1522435977 ps
CPU time 4.85 seconds
Started Jul 17 05:39:17 PM PDT 24
Finished Jul 17 05:39:23 PM PDT 24
Peak memory 215548 kb
Host smart-91da1bf8-3ea5-4fd9-aed1-b149c8963969
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528466104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2528466104
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.187703687
Short name T1095
Test name
Test status
Simulation time 6327584402 ps
CPU time 4.96 seconds
Started Jul 17 05:39:15 PM PDT 24
Finished Jul 17 05:39:21 PM PDT 24
Peak memory 205688 kb
Host smart-eff93dcf-bf15-40b6-a26f-e284f06b2258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187703687 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.187703687
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.605649203
Short name T1572
Test name
Test status
Simulation time 439209770 ps
CPU time 2.68 seconds
Started Jul 17 05:39:28 PM PDT 24
Finished Jul 17 05:39:32 PM PDT 24
Peak memory 213860 kb
Host smart-9e4c8db1-ba8d-46ba-a934-ac2acd8bec02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605649203 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_nack_acqfull.605649203
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.961136377
Short name T1068
Test name
Test status
Simulation time 452267834 ps
CPU time 2.17 seconds
Started Jul 17 05:39:28 PM PDT 24
Finished Jul 17 05:39:30 PM PDT 24
Peak memory 205596 kb
Host smart-b8a03231-1957-455a-ad76-9c9829fce5ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961136377 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.961136377
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_txstretch.1272617785
Short name T1602
Test name
Test status
Simulation time 477837569 ps
CPU time 1.31 seconds
Started Jul 17 05:39:28 PM PDT 24
Finished Jul 17 05:39:30 PM PDT 24
Peak memory 222464 kb
Host smart-3bc6bf76-69b5-4042-8e4b-5aa46f4249c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272617785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_nack_txstretch.1272617785
Directory /workspace/1.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/1.i2c_target_perf.2400795960
Short name T786
Test name
Test status
Simulation time 613554276 ps
CPU time 4.46 seconds
Started Jul 17 05:39:16 PM PDT 24
Finished Jul 17 05:39:21 PM PDT 24
Peak memory 208872 kb
Host smart-41b8aa8f-7b01-4c28-9bfc-d13b250649ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400795960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.2400795960
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.2317747120
Short name T668
Test name
Test status
Simulation time 1633337533 ps
CPU time 2.17 seconds
Started Jul 17 05:39:28 PM PDT 24
Finished Jul 17 05:39:31 PM PDT 24
Peak memory 205448 kb
Host smart-6666ae40-866a-4217-b72f-8fdf770867a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317747120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_smbus_maxlen.2317747120
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3732851889
Short name T907
Test name
Test status
Simulation time 910801491 ps
CPU time 26.73 seconds
Started Jul 17 05:39:57 PM PDT 24
Finished Jul 17 05:40:25 PM PDT 24
Peak memory 213888 kb
Host smart-f6a8d91c-12c3-4b61-9532-e60fed423d14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732851889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3732851889
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.2283257339
Short name T1267
Test name
Test status
Simulation time 90031885504 ps
CPU time 546.84 seconds
Started Jul 17 05:39:56 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 2983360 kb
Host smart-7a485c63-da89-4606-aff8-6552e7169fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283257339 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.2283257339
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2073058504
Short name T1672
Test name
Test status
Simulation time 1483832922 ps
CPU time 13.2 seconds
Started Jul 17 05:39:42 PM PDT 24
Finished Jul 17 05:39:56 PM PDT 24
Peak memory 219120 kb
Host smart-26207efb-2a29-46b0-bb92-90591d00af8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073058504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2073058504
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3246483813
Short name T1166
Test name
Test status
Simulation time 24145071009 ps
CPU time 79.65 seconds
Started Jul 17 05:39:14 PM PDT 24
Finished Jul 17 05:40:35 PM PDT 24
Peak memory 1114356 kb
Host smart-8d3e30d6-bd2d-4a4a-ad9a-215f43588a3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246483813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3246483813
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.4256615008
Short name T1180
Test name
Test status
Simulation time 1263251518 ps
CPU time 1.73 seconds
Started Jul 17 05:39:17 PM PDT 24
Finished Jul 17 05:39:20 PM PDT 24
Peak memory 213888 kb
Host smart-afcf088a-1ed7-44e0-b3b3-a83e1abe24ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256615008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.4256615008
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.4248356058
Short name T830
Test name
Test status
Simulation time 11354776362 ps
CPU time 7.23 seconds
Started Jul 17 05:39:17 PM PDT 24
Finished Jul 17 05:39:25 PM PDT 24
Peak memory 222100 kb
Host smart-35e5556c-ad8d-4487-878a-852be6e63d10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248356058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.4248356058
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.3643329472
Short name T1193
Test name
Test status
Simulation time 60355900 ps
CPU time 1.44 seconds
Started Jul 17 05:39:29 PM PDT 24
Finished Jul 17 05:39:31 PM PDT 24
Peak memory 205656 kb
Host smart-5cd4cebf-35cd-453c-b4fc-b4395c11110b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643329472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.3643329472
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3947899194
Short name T399
Test name
Test status
Simulation time 24233474 ps
CPU time 0.63 seconds
Started Jul 17 05:42:07 PM PDT 24
Finished Jul 17 05:42:08 PM PDT 24
Peak memory 204820 kb
Host smart-bcc22ead-80e2-47e7-9a1f-6f7b11e55bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947899194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3947899194
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1616908527
Short name T1746
Test name
Test status
Simulation time 59100558 ps
CPU time 1.25 seconds
Started Jul 17 05:46:25 PM PDT 24
Finished Jul 17 05:46:28 PM PDT 24
Peak memory 213788 kb
Host smart-19d6d043-b974-4941-acf0-b292c04d2239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616908527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1616908527
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2574430450
Short name T370
Test name
Test status
Simulation time 480540363 ps
CPU time 22.67 seconds
Started Jul 17 05:41:50 PM PDT 24
Finished Jul 17 05:42:13 PM PDT 24
Peak memory 272136 kb
Host smart-f32ee261-d7ea-4f9b-8f52-7dbc7891657c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574430450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2574430450
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.239460610
Short name T1085
Test name
Test status
Simulation time 10578486987 ps
CPU time 85.99 seconds
Started Jul 17 05:41:49 PM PDT 24
Finished Jul 17 05:43:16 PM PDT 24
Peak memory 568948 kb
Host smart-80536c83-4bcb-4ea5-bc89-adec3318698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239460610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.239460610
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.52524895
Short name T797
Test name
Test status
Simulation time 7639813254 ps
CPU time 77.76 seconds
Started Jul 17 05:41:50 PM PDT 24
Finished Jul 17 05:43:09 PM PDT 24
Peak memory 742172 kb
Host smart-9cf64e76-d3a5-4dc9-a442-d979a0081d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52524895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.52524895
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.888069646
Short name T897
Test name
Test status
Simulation time 90416307 ps
CPU time 0.88 seconds
Started Jul 17 05:46:26 PM PDT 24
Finished Jul 17 05:46:28 PM PDT 24
Peak memory 205264 kb
Host smart-3050270f-afe0-4713-a19d-086b557898d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888069646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.888069646
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1570803458
Short name T692
Test name
Test status
Simulation time 486277425 ps
CPU time 5.99 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:02 PM PDT 24
Peak memory 205560 kb
Host smart-7cfd2997-af53-4162-a122-3bc62b9700bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570803458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1570803458
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1084948527
Short name T115
Test name
Test status
Simulation time 11053514807 ps
CPU time 128.1 seconds
Started Jul 17 05:41:51 PM PDT 24
Finished Jul 17 05:44:00 PM PDT 24
Peak memory 1516848 kb
Host smart-0124c8db-b696-472e-a4b7-284220da3d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084948527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1084948527
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1635555776
Short name T1298
Test name
Test status
Simulation time 984040272 ps
CPU time 10.57 seconds
Started Jul 17 05:42:04 PM PDT 24
Finished Jul 17 05:42:16 PM PDT 24
Peak memory 205484 kb
Host smart-8a5de91a-8a4d-4bfa-8a32-265c6355ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635555776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1635555776
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_override.2311430640
Short name T404
Test name
Test status
Simulation time 26895954 ps
CPU time 0.68 seconds
Started Jul 17 05:41:46 PM PDT 24
Finished Jul 17 05:41:48 PM PDT 24
Peak memory 205404 kb
Host smart-6954f8ba-2fc5-405e-bb3d-2c90003bce18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311430640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2311430640
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3935366492
Short name T944
Test name
Test status
Simulation time 13173029034 ps
CPU time 72.04 seconds
Started Jul 17 05:46:42 PM PDT 24
Finished Jul 17 05:47:55 PM PDT 24
Peak memory 213828 kb
Host smart-46ebc243-edfc-4a58-ab4d-bdea59bca2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935366492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3935366492
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.1305373592
Short name T1464
Test name
Test status
Simulation time 1887778789 ps
CPU time 37.78 seconds
Started Jul 17 05:41:50 PM PDT 24
Finished Jul 17 05:42:29 PM PDT 24
Peak memory 205464 kb
Host smart-b3f093f9-7da6-4757-8765-1ca232240a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305373592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1305373592
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.935074716
Short name T813
Test name
Test status
Simulation time 6881191236 ps
CPU time 14.15 seconds
Started Jul 17 05:41:49 PM PDT 24
Finished Jul 17 05:42:04 PM PDT 24
Peak memory 315024 kb
Host smart-001c8ee0-5117-4290-9619-137142ea6061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935074716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.935074716
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3961876032
Short name T264
Test name
Test status
Simulation time 3754956822 ps
CPU time 43.36 seconds
Started Jul 17 05:41:51 PM PDT 24
Finished Jul 17 05:42:36 PM PDT 24
Peak memory 221984 kb
Host smart-0b9c281b-b10c-4ddd-a7da-b665f52fb800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961876032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3961876032
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2639620400
Short name T746
Test name
Test status
Simulation time 6646629584 ps
CPU time 6.09 seconds
Started Jul 17 05:42:09 PM PDT 24
Finished Jul 17 05:42:16 PM PDT 24
Peak memory 222040 kb
Host smart-1f0bb19d-f3e5-4ec5-a31a-b1d16374adbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639620400 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2639620400
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3882454482
Short name T1518
Test name
Test status
Simulation time 198672920 ps
CPU time 1.25 seconds
Started Jul 17 05:42:03 PM PDT 24
Finished Jul 17 05:42:05 PM PDT 24
Peak memory 213836 kb
Host smart-4f8ef5bb-a772-41ce-bc55-f6da050972e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882454482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3882454482
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.1262332578
Short name T145
Test name
Test status
Simulation time 511392678 ps
CPU time 2.83 seconds
Started Jul 17 05:46:41 PM PDT 24
Finished Jul 17 05:46:45 PM PDT 24
Peak memory 205628 kb
Host smart-80d623d7-a22d-4b21-98fd-611f499f5544
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262332578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.1262332578
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2662166338
Short name T290
Test name
Test status
Simulation time 111148010 ps
CPU time 0.81 seconds
Started Jul 17 05:42:06 PM PDT 24
Finished Jul 17 05:42:07 PM PDT 24
Peak memory 205416 kb
Host smart-27deabe4-48db-4f30-9d3c-96a5a40b7df0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662166338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2662166338
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.4240749162
Short name T1630
Test name
Test status
Simulation time 2969574334 ps
CPU time 4.55 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:47:55 PM PDT 24
Peak memory 213976 kb
Host smart-3ba39c7b-5f3b-41ba-b2a1-b295bf6ef0db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240749162 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.4240749162
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2613044175
Short name T298
Test name
Test status
Simulation time 8868628220 ps
CPU time 17.43 seconds
Started Jul 17 05:46:25 PM PDT 24
Finished Jul 17 05:46:44 PM PDT 24
Peak memory 631956 kb
Host smart-32591ebc-1980-4731-a505-68c822b85a4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613044175 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2613044175
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.1025006423
Short name T589
Test name
Test status
Simulation time 426250126 ps
CPU time 2.55 seconds
Started Jul 17 05:47:13 PM PDT 24
Finished Jul 17 05:47:16 PM PDT 24
Peak memory 213880 kb
Host smart-79fc92f4-c162-43fd-b7ec-33456ab83a6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025006423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_acqfull.1025006423
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.2265473301
Short name T1732
Test name
Test status
Simulation time 1620587513 ps
CPU time 2.08 seconds
Started Jul 17 05:42:02 PM PDT 24
Finished Jul 17 05:42:04 PM PDT 24
Peak memory 205632 kb
Host smart-dff4e1f8-678f-4b4e-af1a-97d29eb1c62c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265473301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.2265473301
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.2711278743
Short name T393
Test name
Test status
Simulation time 808952397 ps
CPU time 5.61 seconds
Started Jul 17 05:47:09 PM PDT 24
Finished Jul 17 05:47:16 PM PDT 24
Peak memory 216156 kb
Host smart-9f102dfc-3b1b-4007-848c-dd35fc836ac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711278743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.2711278743
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.2535116542
Short name T985
Test name
Test status
Simulation time 477482618 ps
CPU time 2.27 seconds
Started Jul 17 05:42:04 PM PDT 24
Finished Jul 17 05:42:07 PM PDT 24
Peak memory 205408 kb
Host smart-f6f18e5b-c9e1-474a-ad90-a5fb24ac002b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535116542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.2535116542
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2540266695
Short name T213
Test name
Test status
Simulation time 1160646001 ps
CPU time 26.66 seconds
Started Jul 17 05:41:46 PM PDT 24
Finished Jul 17 05:42:13 PM PDT 24
Peak memory 213788 kb
Host smart-7bdd695a-babe-474c-bc7a-5b9fde5512a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540266695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2540266695
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.2632557451
Short name T1345
Test name
Test status
Simulation time 25743725377 ps
CPU time 30.87 seconds
Started Jul 17 05:42:02 PM PDT 24
Finished Jul 17 05:42:34 PM PDT 24
Peak memory 229596 kb
Host smart-26e370ee-aca0-4c76-99f1-f8c0a8c0ac2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632557451 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.2632557451
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3740937514
Short name T418
Test name
Test status
Simulation time 327637593 ps
CPU time 13.73 seconds
Started Jul 17 05:41:53 PM PDT 24
Finished Jul 17 05:42:07 PM PDT 24
Peak memory 205624 kb
Host smart-7d24ae49-be78-4779-bc20-37ad4170cef8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740937514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3740937514
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.681268868
Short name T54
Test name
Test status
Simulation time 38534329756 ps
CPU time 31.56 seconds
Started Jul 17 05:41:48 PM PDT 24
Finished Jul 17 05:42:21 PM PDT 24
Peak memory 663832 kb
Host smart-75e8a4ff-7746-4cc2-978c-8c2bee399950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681268868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_wr.681268868
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3844555808
Short name T671
Test name
Test status
Simulation time 978531361 ps
CPU time 14.84 seconds
Started Jul 17 05:41:49 PM PDT 24
Finished Jul 17 05:42:04 PM PDT 24
Peak memory 375584 kb
Host smart-71af761c-d83b-4380-9059-229cc8d6c94d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844555808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3844555808
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.521126016
Short name T1674
Test name
Test status
Simulation time 1850777953 ps
CPU time 5.62 seconds
Started Jul 17 05:46:45 PM PDT 24
Finished Jul 17 05:46:51 PM PDT 24
Peak memory 229884 kb
Host smart-b97468ee-a491-45e7-baa5-b6d81a309e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521126016 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_timeout.521126016
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.2864199065
Short name T1601
Test name
Test status
Simulation time 154626994 ps
CPU time 3.23 seconds
Started Jul 17 05:42:07 PM PDT 24
Finished Jul 17 05:42:11 PM PDT 24
Peak memory 205616 kb
Host smart-eb86cd87-0f2f-4f6e-b517-00af623e5c58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864199065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2864199065
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.381476567
Short name T914
Test name
Test status
Simulation time 18148092 ps
CPU time 0.64 seconds
Started Jul 17 05:42:20 PM PDT 24
Finished Jul 17 05:42:21 PM PDT 24
Peak memory 204788 kb
Host smart-0bbb62b7-aa22-4fe3-8d13-ffa652ecd0e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381476567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.381476567
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.377730421
Short name T756
Test name
Test status
Simulation time 143282086 ps
CPU time 1.74 seconds
Started Jul 17 05:42:09 PM PDT 24
Finished Jul 17 05:42:11 PM PDT 24
Peak memory 213800 kb
Host smart-b96f9f3a-441f-4a0e-95bb-0adb347ea3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377730421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.377730421
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.448135656
Short name T936
Test name
Test status
Simulation time 707942727 ps
CPU time 6.94 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:46:25 PM PDT 24
Peak memory 260032 kb
Host smart-349f325c-7ae9-4d3c-917c-335d00ee1405
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448135656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.448135656
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1718810077
Short name T840
Test name
Test status
Simulation time 6539259871 ps
CPU time 135.85 seconds
Started Jul 17 05:47:09 PM PDT 24
Finished Jul 17 05:49:26 PM PDT 24
Peak memory 253972 kb
Host smart-287906e6-849b-499f-bf69-04884a1a4abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718810077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1718810077
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2640524373
Short name T1514
Test name
Test status
Simulation time 12508755469 ps
CPU time 64.82 seconds
Started Jul 17 05:42:04 PM PDT 24
Finished Jul 17 05:43:09 PM PDT 24
Peak memory 770024 kb
Host smart-053e315e-452b-45b4-9ec1-3a6e961cd575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640524373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2640524373
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2377363137
Short name T426
Test name
Test status
Simulation time 355827536 ps
CPU time 1.03 seconds
Started Jul 17 05:42:05 PM PDT 24
Finished Jul 17 05:42:07 PM PDT 24
Peak memory 205260 kb
Host smart-64a722fa-2fba-46cb-9b9f-e1ae10481709
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377363137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2377363137
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3758251178
Short name T947
Test name
Test status
Simulation time 255904534 ps
CPU time 3.48 seconds
Started Jul 17 05:42:05 PM PDT 24
Finished Jul 17 05:42:10 PM PDT 24
Peak memory 227432 kb
Host smart-0e5836e7-f0f5-46be-acb5-f074c72b53b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758251178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3758251178
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.520846498
Short name T1330
Test name
Test status
Simulation time 9910347251 ps
CPU time 276.87 seconds
Started Jul 17 05:42:10 PM PDT 24
Finished Jul 17 05:46:47 PM PDT 24
Peak memory 1159308 kb
Host smart-d2a4edb7-473e-4592-9466-451d930e993f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520846498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.520846498
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.800166327
Short name T1685
Test name
Test status
Simulation time 1685337836 ps
CPU time 12.98 seconds
Started Jul 17 05:42:14 PM PDT 24
Finished Jul 17 05:42:28 PM PDT 24
Peak memory 205468 kb
Host smart-0e3f24ec-87da-4934-82e8-1d5db115a8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800166327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.800166327
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_override.2404117638
Short name T1233
Test name
Test status
Simulation time 77314815 ps
CPU time 0.66 seconds
Started Jul 17 05:42:04 PM PDT 24
Finished Jul 17 05:42:06 PM PDT 24
Peak memory 205212 kb
Host smart-acd81266-e7c7-4651-a359-6d5791ad3470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404117638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2404117638
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.3528366193
Short name T1494
Test name
Test status
Simulation time 484197373 ps
CPU time 2 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:46:26 PM PDT 24
Peak memory 205512 kb
Host smart-478546aa-bad5-41e5-947a-45966c981e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528366193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.3528366193
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2857296913
Short name T328
Test name
Test status
Simulation time 6352624076 ps
CPU time 30.42 seconds
Started Jul 17 05:42:06 PM PDT 24
Finished Jul 17 05:42:37 PM PDT 24
Peak memory 334168 kb
Host smart-538fae33-dcc6-4d97-8f55-c3823ee63c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857296913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2857296913
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2372847277
Short name T1263
Test name
Test status
Simulation time 2104981131 ps
CPU time 23.06 seconds
Started Jul 17 05:42:09 PM PDT 24
Finished Jul 17 05:42:33 PM PDT 24
Peak memory 213716 kb
Host smart-c3b8f6b8-aaba-45c5-8d34-496217f4efc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372847277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2372847277
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3353046643
Short name T1232
Test name
Test status
Simulation time 204976520 ps
CPU time 0.9 seconds
Started Jul 17 05:43:59 PM PDT 24
Finished Jul 17 05:44:00 PM PDT 24
Peak memory 205360 kb
Host smart-555b058d-eae0-4e4a-a2b8-c7401e3eda4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353046643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3353046643
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.468906891
Short name T991
Test name
Test status
Simulation time 365458491 ps
CPU time 1.19 seconds
Started Jul 17 05:42:16 PM PDT 24
Finished Jul 17 05:42:19 PM PDT 24
Peak memory 205592 kb
Host smart-07d5d074-654d-4d88-878f-2cac8dc34279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468906891 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_tx.468906891
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.212752156
Short name T1447
Test name
Test status
Simulation time 379996824 ps
CPU time 2.27 seconds
Started Jul 17 05:42:14 PM PDT 24
Finished Jul 17 05:42:17 PM PDT 24
Peak memory 205604 kb
Host smart-9210787d-5537-4e7b-bfd4-b9b637c83fee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212752156 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.212752156
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.2828203402
Short name T1650
Test name
Test status
Simulation time 168017787 ps
CPU time 0.97 seconds
Started Jul 17 05:42:15 PM PDT 24
Finished Jul 17 05:42:17 PM PDT 24
Peak memory 205376 kb
Host smart-5777b040-455d-465f-855a-7bb88feb6a60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828203402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.2828203402
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.4099572499
Short name T396
Test name
Test status
Simulation time 1321391237 ps
CPU time 7.01 seconds
Started Jul 17 05:42:06 PM PDT 24
Finished Jul 17 05:42:13 PM PDT 24
Peak memory 213852 kb
Host smart-0e19016c-0866-4d61-9b28-6f43b8fd6b15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099572499 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.4099572499
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.2101225800
Short name T1555
Test name
Test status
Simulation time 27802052912 ps
CPU time 309.96 seconds
Started Jul 17 05:42:07 PM PDT 24
Finished Jul 17 05:47:18 PM PDT 24
Peak memory 3514532 kb
Host smart-34deeaad-f38e-45f0-a4e0-b40d7e4dc6d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101225800 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.2101225800
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.4242763026
Short name T380
Test name
Test status
Simulation time 553554836 ps
CPU time 2.93 seconds
Started Jul 17 05:42:15 PM PDT 24
Finished Jul 17 05:42:19 PM PDT 24
Peak memory 213856 kb
Host smart-271b284d-e2f2-4bae-9b36-c37d4b1798ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242763026 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_nack_acqfull.4242763026
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.1554540156
Short name T71
Test name
Test status
Simulation time 536274037 ps
CPU time 2.87 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:52 PM PDT 24
Peak memory 205640 kb
Host smart-0b3dc6b7-f7af-4323-8063-2fc114d83b86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554540156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.1554540156
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_txstretch.3429467420
Short name T1459
Test name
Test status
Simulation time 164723877 ps
CPU time 1.53 seconds
Started Jul 17 05:42:16 PM PDT 24
Finished Jul 17 05:42:18 PM PDT 24
Peak memory 222396 kb
Host smart-91c2d74c-e9da-45c1-aaa9-e074ee75deb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429467420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_nack_txstretch.3429467420
Directory /workspace/11.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/11.i2c_target_perf.3844118734
Short name T593
Test name
Test status
Simulation time 590429557 ps
CPU time 4.16 seconds
Started Jul 17 05:42:22 PM PDT 24
Finished Jul 17 05:42:28 PM PDT 24
Peak memory 213796 kb
Host smart-db4fe644-465d-4f37-97ee-c01fb50d8319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844118734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.3844118734
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.2041229585
Short name T902
Test name
Test status
Simulation time 1049760539 ps
CPU time 2.16 seconds
Started Jul 17 05:42:14 PM PDT 24
Finished Jul 17 05:42:17 PM PDT 24
Peak memory 205420 kb
Host smart-47dff046-0066-450c-b876-31b8083c5b55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041229585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_smbus_maxlen.2041229585
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2434013052
Short name T799
Test name
Test status
Simulation time 2966626956 ps
CPU time 11.96 seconds
Started Jul 17 05:42:03 PM PDT 24
Finished Jul 17 05:42:16 PM PDT 24
Peak memory 213856 kb
Host smart-cc2a9851-dac8-4c39-b072-87b008162983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434013052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2434013052
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.671899625
Short name T456
Test name
Test status
Simulation time 20009997661 ps
CPU time 340.23 seconds
Started Jul 17 05:42:14 PM PDT 24
Finished Jul 17 05:47:55 PM PDT 24
Peak memory 2571900 kb
Host smart-53922271-829f-4301-858a-66f2160303e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671899625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_stress_all.671899625
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.818844293
Short name T851
Test name
Test status
Simulation time 1968168827 ps
CPU time 17.26 seconds
Started Jul 17 05:46:43 PM PDT 24
Finished Jul 17 05:47:01 PM PDT 24
Peak memory 224644 kb
Host smart-9db4017a-265d-4731-aa11-b24510fc74a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818844293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.818844293
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.4030275013
Short name T1138
Test name
Test status
Simulation time 41462629456 ps
CPU time 744.14 seconds
Started Jul 17 05:42:02 PM PDT 24
Finished Jul 17 05:54:27 PM PDT 24
Peak memory 5387752 kb
Host smart-6aa32e6e-0696-41fb-b26e-591f254b9032
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030275013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.4030275013
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.146057781
Short name T1079
Test name
Test status
Simulation time 5563017053 ps
CPU time 12.53 seconds
Started Jul 17 05:45:32 PM PDT 24
Finished Jul 17 05:45:45 PM PDT 24
Peak memory 453892 kb
Host smart-9027cd35-a7a5-4332-a63a-e44d1d4ce3d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146057781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.146057781
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2681573758
Short name T1658
Test name
Test status
Simulation time 5734713308 ps
CPU time 7.23 seconds
Started Jul 17 05:42:17 PM PDT 24
Finished Jul 17 05:42:25 PM PDT 24
Peak memory 222068 kb
Host smart-8f332708-68b7-4767-9a16-5cc275ebbfb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681573758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2681573758
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.911190431
Short name T727
Test name
Test status
Simulation time 976572529 ps
CPU time 12.3 seconds
Started Jul 17 05:42:17 PM PDT 24
Finished Jul 17 05:42:30 PM PDT 24
Peak memory 206280 kb
Host smart-13f31801-23c4-49e3-b20e-1e71c85d36af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911190431 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.911190431
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.555155514
Short name T1362
Test name
Test status
Simulation time 34343325 ps
CPU time 0.6 seconds
Started Jul 17 05:42:29 PM PDT 24
Finished Jul 17 05:42:30 PM PDT 24
Peak memory 204868 kb
Host smart-709302c6-92c2-4943-aa75-42f103033e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555155514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.555155514
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3255226917
Short name T1491
Test name
Test status
Simulation time 1420972426 ps
CPU time 5.54 seconds
Started Jul 17 05:42:27 PM PDT 24
Finished Jul 17 05:42:33 PM PDT 24
Peak memory 235444 kb
Host smart-c16c4fb6-4cfe-488a-886f-b31d09dea47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255226917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3255226917
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2743337202
Short name T280
Test name
Test status
Simulation time 1280856511 ps
CPU time 18.85 seconds
Started Jul 17 05:42:14 PM PDT 24
Finished Jul 17 05:42:34 PM PDT 24
Peak memory 283720 kb
Host smart-b948acad-5b9c-4884-aff6-79d6f61e66a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743337202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2743337202
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.843787535
Short name T437
Test name
Test status
Simulation time 1781575125 ps
CPU time 124.89 seconds
Started Jul 17 05:42:19 PM PDT 24
Finished Jul 17 05:44:24 PM PDT 24
Peak memory 636360 kb
Host smart-95ac4f77-de9f-4125-8bd9-64e1bbd9f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843787535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.843787535
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1435963075
Short name T828
Test name
Test status
Simulation time 1758541333 ps
CPU time 118.14 seconds
Started Jul 17 05:42:16 PM PDT 24
Finished Jul 17 05:44:15 PM PDT 24
Peak memory 601244 kb
Host smart-d5478107-4fd6-4de9-a5df-bef7b17691f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435963075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1435963075
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.745936302
Short name T714
Test name
Test status
Simulation time 103948009 ps
CPU time 1.08 seconds
Started Jul 17 05:42:15 PM PDT 24
Finished Jul 17 05:42:16 PM PDT 24
Peak memory 205264 kb
Host smart-d5e92ecd-8fc0-4b85-be3e-bb3abadadfea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745936302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.745936302
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.466404455
Short name T1109
Test name
Test status
Simulation time 186202893 ps
CPU time 4.11 seconds
Started Jul 17 05:46:51 PM PDT 24
Finished Jul 17 05:46:57 PM PDT 24
Peak memory 205524 kb
Host smart-a13115f9-5b65-47d1-9031-c8e959da0a1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466404455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.
466404455
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.3589961669
Short name T815
Test name
Test status
Simulation time 17005356785 ps
CPU time 142.86 seconds
Started Jul 17 05:42:16 PM PDT 24
Finished Jul 17 05:44:40 PM PDT 24
Peak memory 1594500 kb
Host smart-feeb8ed3-d392-481a-bb2d-9d51c25d2a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589961669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3589961669
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.3345622668
Short name T761
Test name
Test status
Simulation time 525754819 ps
CPU time 7.07 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:36 PM PDT 24
Peak memory 205480 kb
Host smart-6fd89b79-0a80-4d97-b5ea-47c63d6b2762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345622668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3345622668
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.2324728881
Short name T97
Test name
Test status
Simulation time 130061355 ps
CPU time 0.64 seconds
Started Jul 17 05:42:16 PM PDT 24
Finished Jul 17 05:42:18 PM PDT 24
Peak memory 205220 kb
Host smart-60f898da-5b52-4b2d-9a8b-fcb60948e05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324728881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2324728881
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3960991911
Short name T1482
Test name
Test status
Simulation time 8121373905 ps
CPU time 32.32 seconds
Started Jul 17 05:47:09 PM PDT 24
Finished Jul 17 05:47:42 PM PDT 24
Peak memory 541232 kb
Host smart-8efb6845-e62b-4942-ac08-26284b058c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960991911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3960991911
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.2970004402
Short name T501
Test name
Test status
Simulation time 2948090867 ps
CPU time 10.88 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:47:01 PM PDT 24
Peak memory 205488 kb
Host smart-5ccde0e2-8e20-4d91-804c-e5f80ea215b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970004402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.2970004402
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.644853604
Short name T676
Test name
Test status
Simulation time 3143193228 ps
CPU time 27.02 seconds
Started Jul 17 05:42:15 PM PDT 24
Finished Jul 17 05:42:43 PM PDT 24
Peak memory 289304 kb
Host smart-705ec683-0740-4f39-aa4b-13ccb1291744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644853604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.644853604
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.1317929065
Short name T1613
Test name
Test status
Simulation time 21543866475 ps
CPU time 516.99 seconds
Started Jul 17 05:42:27 PM PDT 24
Finished Jul 17 05:51:05 PM PDT 24
Peak memory 1739084 kb
Host smart-cb491248-1737-4ab4-a810-2a420747b175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317929065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.1317929065
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3640259855
Short name T402
Test name
Test status
Simulation time 1979163059 ps
CPU time 18.05 seconds
Started Jul 17 05:42:19 PM PDT 24
Finished Jul 17 05:42:37 PM PDT 24
Peak memory 219688 kb
Host smart-4f61d518-1282-4041-93e4-bba963f5b255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640259855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3640259855
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.4135230034
Short name T1410
Test name
Test status
Simulation time 3049517944 ps
CPU time 6.79 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:36 PM PDT 24
Peak memory 222100 kb
Host smart-3f243780-8ad7-402a-ba3f-b465922c44eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135230034 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.4135230034
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.4182611713
Short name T711
Test name
Test status
Simulation time 296484286 ps
CPU time 1.08 seconds
Started Jul 17 05:46:45 PM PDT 24
Finished Jul 17 05:46:47 PM PDT 24
Peak memory 205672 kb
Host smart-83c93543-4508-4e11-a865-0839d68948c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182611713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.4182611713
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.529457129
Short name T713
Test name
Test status
Simulation time 401803247 ps
CPU time 1.03 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:30 PM PDT 24
Peak memory 205456 kb
Host smart-c44764e2-c0d4-4372-bc49-2cd2abd21533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529457129 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.529457129
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.3706346269
Short name T1354
Test name
Test status
Simulation time 1601914021 ps
CPU time 2.62 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:32 PM PDT 24
Peak memory 205636 kb
Host smart-055ec549-4710-4552-a87f-3140e45286b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706346269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.3706346269
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.3731766182
Short name T554
Test name
Test status
Simulation time 107751549 ps
CPU time 0.98 seconds
Started Jul 17 05:42:27 PM PDT 24
Finished Jul 17 05:42:29 PM PDT 24
Peak memory 205428 kb
Host smart-5f0d3607-f60e-4a28-a742-1aa880993b85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731766182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.3731766182
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1684079989
Short name T970
Test name
Test status
Simulation time 1495411577 ps
CPU time 5.07 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:35 PM PDT 24
Peak memory 219544 kb
Host smart-3072eaba-3ded-42f8-b219-16ab236d7d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684079989 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1684079989
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2169477938
Short name T562
Test name
Test status
Simulation time 5799129720 ps
CPU time 60.68 seconds
Started Jul 17 05:47:12 PM PDT 24
Finished Jul 17 05:48:14 PM PDT 24
Peak memory 1506468 kb
Host smart-775a4f71-dce9-4ab3-8a57-329978c541af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169477938 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2169477938
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.2969360863
Short name T915
Test name
Test status
Simulation time 518426616 ps
CPU time 2.8 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:33 PM PDT 24
Peak memory 213808 kb
Host smart-bbb2e6cd-2d29-423e-a30b-6eba400b6e59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969360863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_acqfull.2969360863
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.220486351
Short name T642
Test name
Test status
Simulation time 884376545 ps
CPU time 2.74 seconds
Started Jul 17 05:42:27 PM PDT 24
Finished Jul 17 05:42:31 PM PDT 24
Peak memory 205816 kb
Host smart-9cba7ad2-67d6-4181-b01c-1d192e6c2270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220486351 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.220486351
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.1333210206
Short name T1143
Test name
Test status
Simulation time 2144203494 ps
CPU time 3.96 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:33 PM PDT 24
Peak memory 214880 kb
Host smart-762f5272-9b66-4f27-a51e-acf3cded4eac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333210206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.1333210206
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.2214571729
Short name T1043
Test name
Test status
Simulation time 2569326823 ps
CPU time 2.29 seconds
Started Jul 17 05:42:26 PM PDT 24
Finished Jul 17 05:42:29 PM PDT 24
Peak memory 205488 kb
Host smart-861c467f-f7ff-4575-94a2-f8ff85b564f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214571729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.2214571729
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.4214938106
Short name T1254
Test name
Test status
Simulation time 1079240497 ps
CPU time 33.56 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:43:03 PM PDT 24
Peak memory 213824 kb
Host smart-fabb2dab-179a-4769-8a81-d86ad529cf4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214938106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.4214938106
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.1545097257
Short name T1421
Test name
Test status
Simulation time 44320052423 ps
CPU time 282.38 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:52:32 PM PDT 24
Peak memory 1571604 kb
Host smart-ec517a5d-5072-4869-9e6d-de2e7ebc9fa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545097257 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.1545097257
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3329182147
Short name T1120
Test name
Test status
Simulation time 566622587 ps
CPU time 11.16 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:40 PM PDT 24
Peak memory 216216 kb
Host smart-d1f37b53-dfcf-4d64-a9ac-f2c1d428785c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329182147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3329182147
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.4022855466
Short name T1707
Test name
Test status
Simulation time 43322980852 ps
CPU time 536.73 seconds
Started Jul 17 05:42:29 PM PDT 24
Finished Jul 17 05:51:27 PM PDT 24
Peak memory 4621080 kb
Host smart-92f4ff8c-3c79-4f40-8ee8-02e55bcf4241
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022855466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.4022855466
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3579043452
Short name T1106
Test name
Test status
Simulation time 2088730643 ps
CPU time 6.65 seconds
Started Jul 17 05:46:25 PM PDT 24
Finished Jul 17 05:46:33 PM PDT 24
Peak memory 273716 kb
Host smart-1366218d-9260-4068-93d6-0673630ece13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579043452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3579043452
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1010829143
Short name T816
Test name
Test status
Simulation time 1283370703 ps
CPU time 7.36 seconds
Started Jul 17 05:42:27 PM PDT 24
Finished Jul 17 05:42:35 PM PDT 24
Peak memory 221960 kb
Host smart-020de587-58d4-417b-8404-cbbe32390e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010829143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1010829143
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.941706754
Short name T144
Test name
Test status
Simulation time 30666684 ps
CPU time 0.63 seconds
Started Jul 17 05:42:51 PM PDT 24
Finished Jul 17 05:42:52 PM PDT 24
Peak memory 204740 kb
Host smart-c4f98385-4dc6-4607-82d8-782e638e19cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941706754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.941706754
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.565819027
Short name T1517
Test name
Test status
Simulation time 327700739 ps
CPU time 5.08 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:55 PM PDT 24
Peak memory 247264 kb
Host smart-3ac85d6a-f2f8-4bfd-8db0-1afcd30689f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565819027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.565819027
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1990958086
Short name T1054
Test name
Test status
Simulation time 1101442370 ps
CPU time 13.47 seconds
Started Jul 17 05:42:39 PM PDT 24
Finished Jul 17 05:42:53 PM PDT 24
Peak memory 260708 kb
Host smart-3bdce16d-f5a2-4ac3-984e-fe0fa2d5281b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990958086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1990958086
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1735801374
Short name T580
Test name
Test status
Simulation time 40211397505 ps
CPU time 138.38 seconds
Started Jul 17 05:42:38 PM PDT 24
Finished Jul 17 05:44:57 PM PDT 24
Peak memory 213760 kb
Host smart-bad921bc-187c-42c1-abb6-8d74b2934c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735801374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1735801374
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3600541101
Short name T1397
Test name
Test status
Simulation time 8987599329 ps
CPU time 137.08 seconds
Started Jul 17 05:42:30 PM PDT 24
Finished Jul 17 05:44:48 PM PDT 24
Peak memory 677328 kb
Host smart-d1bdeea6-a9e2-4cfb-b0d8-f33a4f95bd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600541101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3600541101
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.4000756236
Short name T1074
Test name
Test status
Simulation time 118912771 ps
CPU time 1.22 seconds
Started Jul 17 05:42:40 PM PDT 24
Finished Jul 17 05:42:42 PM PDT 24
Peak memory 205436 kb
Host smart-d03e47f5-cf05-4720-ba43-a8b6ebc4ae05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000756236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.4000756236
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3467334702
Short name T1691
Test name
Test status
Simulation time 956169227 ps
CPU time 6.36 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:46:30 PM PDT 24
Peak memory 251724 kb
Host smart-c3b96a99-46db-4a33-9b11-5ce7f0903227
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467334702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3467334702
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2511061477
Short name T772
Test name
Test status
Simulation time 4304087955 ps
CPU time 97.4 seconds
Started Jul 17 05:42:26 PM PDT 24
Finished Jul 17 05:44:04 PM PDT 24
Peak memory 1205652 kb
Host smart-96a1a890-8cb4-4b47-af9f-fe4470fa9224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511061477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2511061477
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.445523299
Short name T1529
Test name
Test status
Simulation time 403458007 ps
CPU time 16.4 seconds
Started Jul 17 05:42:41 PM PDT 24
Finished Jul 17 05:42:58 PM PDT 24
Peak memory 205504 kb
Host smart-11d7c338-5890-4e02-b31c-a51110156698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445523299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.445523299
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.2158978743
Short name T1214
Test name
Test status
Simulation time 120630773 ps
CPU time 0.65 seconds
Started Jul 17 05:42:27 PM PDT 24
Finished Jul 17 05:42:29 PM PDT 24
Peak memory 205180 kb
Host smart-336e0150-fc74-4850-bf18-9b2acdede378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158978743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2158978743
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2425387709
Short name T824
Test name
Test status
Simulation time 12446728738 ps
CPU time 107.17 seconds
Started Jul 17 05:42:38 PM PDT 24
Finished Jul 17 05:44:26 PM PDT 24
Peak memory 761028 kb
Host smart-268575fd-9aac-48bb-af0e-dc6ce65dd6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425387709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2425387709
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.1037160798
Short name T292
Test name
Test status
Simulation time 260904980 ps
CPU time 2.49 seconds
Started Jul 17 05:42:37 PM PDT 24
Finished Jul 17 05:42:40 PM PDT 24
Peak memory 223936 kb
Host smart-dbc4cf74-02d5-4ba8-9b82-82ab9aab0aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037160798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.1037160798
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.685093993
Short name T529
Test name
Test status
Simulation time 1733847050 ps
CPU time 25.53 seconds
Started Jul 17 05:42:28 PM PDT 24
Finished Jul 17 05:42:55 PM PDT 24
Peak memory 322252 kb
Host smart-f74ea15c-9525-4907-a315-d41465801b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685093993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.685093993
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1456624799
Short name T1394
Test name
Test status
Simulation time 1908524217 ps
CPU time 12.66 seconds
Started Jul 17 05:42:40 PM PDT 24
Finished Jul 17 05:42:53 PM PDT 24
Peak memory 221564 kb
Host smart-e6f6b124-5df3-44f8-9ad7-d0bf3d3a8e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456624799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1456624799
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.528082665
Short name T957
Test name
Test status
Simulation time 4086117322 ps
CPU time 5.54 seconds
Started Jul 17 05:42:38 PM PDT 24
Finished Jul 17 05:42:45 PM PDT 24
Peak memory 213900 kb
Host smart-b2bb85a6-dfdc-4b6a-8c7f-1500de89cf41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528082665 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.528082665
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1052665180
Short name T1389
Test name
Test status
Simulation time 507460299 ps
CPU time 1.08 seconds
Started Jul 17 05:42:40 PM PDT 24
Finished Jul 17 05:42:42 PM PDT 24
Peak memory 205388 kb
Host smart-9de7675b-ec09-44ce-b935-70f25e3f42ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052665180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1052665180
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.987481662
Short name T384
Test name
Test status
Simulation time 159785751 ps
CPU time 1.03 seconds
Started Jul 17 05:42:40 PM PDT 24
Finished Jul 17 05:42:42 PM PDT 24
Peak memory 205428 kb
Host smart-0a6f38d7-80f1-42cb-8449-7a3ed3e06f03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987481662 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.987481662
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.2976416797
Short name T169
Test name
Test status
Simulation time 883481436 ps
CPU time 2.59 seconds
Started Jul 17 05:42:38 PM PDT 24
Finished Jul 17 05:42:42 PM PDT 24
Peak memory 205612 kb
Host smart-896e982d-c04b-4c15-9bb1-eb78f5d2d293
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976416797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.2976416797
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.1819647583
Short name T363
Test name
Test status
Simulation time 65363057 ps
CPU time 0.86 seconds
Started Jul 17 05:42:41 PM PDT 24
Finished Jul 17 05:42:43 PM PDT 24
Peak memory 205224 kb
Host smart-31cadcf0-7275-4f77-a6ab-0f4e674d147e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819647583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.1819647583
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2870093589
Short name T457
Test name
Test status
Simulation time 1118187934 ps
CPU time 6.58 seconds
Started Jul 17 05:42:39 PM PDT 24
Finished Jul 17 05:42:47 PM PDT 24
Peak memory 219064 kb
Host smart-0300b53e-d91b-4d42-aae5-d9eb7e751979
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870093589 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2870093589
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.4187218914
Short name T1107
Test name
Test status
Simulation time 1442175967 ps
CPU time 1.99 seconds
Started Jul 17 05:42:37 PM PDT 24
Finished Jul 17 05:42:40 PM PDT 24
Peak memory 205584 kb
Host smart-b5ec5b80-fcdd-4b34-82ad-593fede24159
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187218914 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.4187218914
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.1128671161
Short name T1292
Test name
Test status
Simulation time 1086334997 ps
CPU time 2.89 seconds
Started Jul 17 05:42:41 PM PDT 24
Finished Jul 17 05:42:45 PM PDT 24
Peak memory 213808 kb
Host smart-f7788bfa-9011-4d50-ac70-15977307f41c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128671161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.1128671161
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_txstretch.1169418187
Short name T45
Test name
Test status
Simulation time 304976607 ps
CPU time 1.34 seconds
Started Jul 17 05:42:41 PM PDT 24
Finished Jul 17 05:42:44 PM PDT 24
Peak memory 222104 kb
Host smart-09f14517-c110-47d8-827c-b53d4a504fa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169418187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_nack_txstretch.1169418187
Directory /workspace/13.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/13.i2c_target_perf.2706894309
Short name T186
Test name
Test status
Simulation time 1041463697 ps
CPU time 3.77 seconds
Started Jul 17 05:43:58 PM PDT 24
Finished Jul 17 05:44:02 PM PDT 24
Peak memory 221984 kb
Host smart-4efe0b47-fe15-44e1-81b5-ad4fb4a6ea9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706894309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.2706894309
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.2033102816
Short name T6
Test name
Test status
Simulation time 1762189705 ps
CPU time 2.39 seconds
Started Jul 17 05:42:37 PM PDT 24
Finished Jul 17 05:42:40 PM PDT 24
Peak memory 205456 kb
Host smart-aad3d319-7001-4c22-ad4f-c272c17d7ce1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033102816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_smbus_maxlen.2033102816
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3041589762
Short name T329
Test name
Test status
Simulation time 825934316 ps
CPU time 10.77 seconds
Started Jul 17 05:42:37 PM PDT 24
Finished Jul 17 05:42:49 PM PDT 24
Peak memory 213800 kb
Host smart-1260f3ec-4aab-4a13-944b-f6e9bc61958c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041589762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3041589762
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.4067895769
Short name T812
Test name
Test status
Simulation time 34405613895 ps
CPU time 214.21 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:49:53 PM PDT 24
Peak memory 3254772 kb
Host smart-779c98d9-1c70-4af3-adcf-f661b7be5d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067895769 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.4067895769
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3934423154
Short name T334
Test name
Test status
Simulation time 682187573 ps
CPU time 12.62 seconds
Started Jul 17 05:42:40 PM PDT 24
Finished Jul 17 05:42:53 PM PDT 24
Peak memory 205620 kb
Host smart-e08580c6-6c3c-4577-8329-2f9bd32a28e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934423154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3934423154
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2772011762
Short name T1589
Test name
Test status
Simulation time 25466032445 ps
CPU time 81.91 seconds
Started Jul 17 05:42:38 PM PDT 24
Finished Jul 17 05:44:02 PM PDT 24
Peak memory 1341968 kb
Host smart-48af5e15-2e09-4eac-89c9-0a3c4d0f7856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772011762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2772011762
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1816540247
Short name T644
Test name
Test status
Simulation time 1128872105 ps
CPU time 6.35 seconds
Started Jul 17 05:42:41 PM PDT 24
Finished Jul 17 05:42:49 PM PDT 24
Peak memory 213588 kb
Host smart-8c319398-cdec-4e2c-8b66-57b579b31183
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816540247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1816540247
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.1681821190
Short name T440
Test name
Test status
Simulation time 443794794 ps
CPU time 5.84 seconds
Started Jul 17 05:42:37 PM PDT 24
Finished Jul 17 05:42:44 PM PDT 24
Peak memory 205608 kb
Host smart-46f29fad-48dc-41e3-be77-ac8fc2198488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681821190 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.1681821190
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.1151727887
Short name T1545
Test name
Test status
Simulation time 51177247 ps
CPU time 0.63 seconds
Started Jul 17 05:43:04 PM PDT 24
Finished Jul 17 05:43:06 PM PDT 24
Peak memory 204732 kb
Host smart-68def5d3-6617-4520-9180-0f36a0dde73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151727887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1151727887
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.32614168
Short name T682
Test name
Test status
Simulation time 369930430 ps
CPU time 6.29 seconds
Started Jul 17 05:42:52 PM PDT 24
Finished Jul 17 05:43:00 PM PDT 24
Peak memory 232604 kb
Host smart-f3a31e89-b553-4374-b879-dc3f9cf44539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32614168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.32614168
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2972119511
Short name T1445
Test name
Test status
Simulation time 530920882 ps
CPU time 26.47 seconds
Started Jul 17 05:42:52 PM PDT 24
Finished Jul 17 05:43:20 PM PDT 24
Peak memory 323520 kb
Host smart-60b622ed-dbce-4e84-8601-925ef1e3be17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972119511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2972119511
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1618702603
Short name T1633
Test name
Test status
Simulation time 8606528920 ps
CPU time 66.55 seconds
Started Jul 17 05:42:48 PM PDT 24
Finished Jul 17 05:43:55 PM PDT 24
Peak memory 643940 kb
Host smart-49b4c8d3-2416-4ae1-ba58-6789ce189c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618702603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1618702603
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.1091934831
Short name T1176
Test name
Test status
Simulation time 5720861214 ps
CPU time 43.22 seconds
Started Jul 17 05:42:50 PM PDT 24
Finished Jul 17 05:43:34 PM PDT 24
Peak memory 546756 kb
Host smart-febbfd7c-4c7d-43c8-b3bd-76bc103902c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091934831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1091934831
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1716771212
Short name T1119
Test name
Test status
Simulation time 1665631235 ps
CPU time 0.94 seconds
Started Jul 17 05:42:51 PM PDT 24
Finished Jul 17 05:42:54 PM PDT 24
Peak memory 205220 kb
Host smart-54f000a3-82f6-4177-b1fe-184b191f6ba1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716771212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1716771212
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1203547221
Short name T1015
Test name
Test status
Simulation time 339953163 ps
CPU time 4.86 seconds
Started Jul 17 05:42:51 PM PDT 24
Finished Jul 17 05:42:58 PM PDT 24
Peak memory 235604 kb
Host smart-95efb79d-248c-4818-b75b-8d336b66ac51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203547221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1203547221
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3023099188
Short name T316
Test name
Test status
Simulation time 6239463691 ps
CPU time 187.7 seconds
Started Jul 17 05:42:50 PM PDT 24
Finished Jul 17 05:45:59 PM PDT 24
Peak memory 885708 kb
Host smart-a41dd3f1-e506-43d5-aa04-3eca3e6e66e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023099188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3023099188
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_override.4061312467
Short name T138
Test name
Test status
Simulation time 53509227 ps
CPU time 0.75 seconds
Started Jul 17 05:42:50 PM PDT 24
Finished Jul 17 05:42:52 PM PDT 24
Peak memory 205356 kb
Host smart-d50a14ab-ae47-478f-b202-1a100bec4e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061312467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.4061312467
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2919730570
Short name T1440
Test name
Test status
Simulation time 2488319479 ps
CPU time 25.84 seconds
Started Jul 17 05:42:52 PM PDT 24
Finished Jul 17 05:43:19 PM PDT 24
Peak memory 230104 kb
Host smart-de7a4bb6-3a1e-4df6-b8aa-27e07f2e2544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919730570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2919730570
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.1476893584
Short name T1480
Test name
Test status
Simulation time 6106465103 ps
CPU time 85.31 seconds
Started Jul 17 05:42:51 PM PDT 24
Finished Jul 17 05:44:18 PM PDT 24
Peak memory 911604 kb
Host smart-97d3507d-c07a-474c-aead-a90cf20829d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476893584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.1476893584
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2885018608
Short name T1543
Test name
Test status
Simulation time 5622728319 ps
CPU time 35.97 seconds
Started Jul 17 05:42:50 PM PDT 24
Finished Jul 17 05:43:26 PM PDT 24
Peak memory 406704 kb
Host smart-79a5b0cb-5fc8-42ec-9741-3650cafd1ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885018608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2885018608
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2066560986
Short name T1029
Test name
Test status
Simulation time 9734292479 ps
CPU time 746.24 seconds
Started Jul 17 05:42:50 PM PDT 24
Finished Jul 17 05:55:18 PM PDT 24
Peak memory 1145324 kb
Host smart-ec447c87-9c9c-47e9-9de7-864b5852f401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066560986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2066560986
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1590219590
Short name T882
Test name
Test status
Simulation time 2756821911 ps
CPU time 14.85 seconds
Started Jul 17 05:42:50 PM PDT 24
Finished Jul 17 05:43:05 PM PDT 24
Peak memory 221932 kb
Host smart-1a0e90de-4f1a-416c-9ab3-8c4bcad6b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590219590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1590219590
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1247644886
Short name T598
Test name
Test status
Simulation time 679399433 ps
CPU time 4.01 seconds
Started Jul 17 05:43:06 PM PDT 24
Finished Jul 17 05:43:12 PM PDT 24
Peak memory 213836 kb
Host smart-f6c99d54-4f10-48e2-8852-e276ce16da77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247644886 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1247644886
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.602452053
Short name T1469
Test name
Test status
Simulation time 387445444 ps
CPU time 0.95 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:43:07 PM PDT 24
Peak memory 205388 kb
Host smart-fb824916-4c4c-4165-a244-329a78c7b34b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602452053 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.602452053
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3319931001
Short name T1323
Test name
Test status
Simulation time 242837045 ps
CPU time 1.62 seconds
Started Jul 17 05:43:06 PM PDT 24
Finished Jul 17 05:43:09 PM PDT 24
Peak memory 205624 kb
Host smart-ee79c48b-e18b-4939-ba64-64d5a2aa00d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319931001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3319931001
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.972973359
Short name T1632
Test name
Test status
Simulation time 311161862 ps
CPU time 1.89 seconds
Started Jul 17 05:43:07 PM PDT 24
Finished Jul 17 05:43:11 PM PDT 24
Peak memory 205440 kb
Host smart-415c92f8-0804-4530-9425-8fcd3c5ab254
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972973359 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.972973359
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.1096549877
Short name T1291
Test name
Test status
Simulation time 480290862 ps
CPU time 1.45 seconds
Started Jul 17 05:43:04 PM PDT 24
Finished Jul 17 05:43:06 PM PDT 24
Peak memory 205404 kb
Host smart-fdfa5c59-f9e0-4ce2-9fc2-82570255486c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096549877 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.1096549877
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.2769335561
Short name T1398
Test name
Test status
Simulation time 493974524 ps
CPU time 1.86 seconds
Started Jul 17 05:46:53 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 221936 kb
Host smart-f5bd1a13-65c7-4b5c-82ce-2956ce702b55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769335561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.2769335561
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2817715634
Short name T1167
Test name
Test status
Simulation time 1076225380 ps
CPU time 7.04 seconds
Started Jul 17 05:42:50 PM PDT 24
Finished Jul 17 05:42:57 PM PDT 24
Peak memory 222068 kb
Host smart-6de20251-9699-453f-9757-a8dba53fa0c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817715634 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2817715634
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1670783649
Short name T89
Test name
Test status
Simulation time 6133543083 ps
CPU time 4.5 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:43:11 PM PDT 24
Peak memory 205604 kb
Host smart-6ed62755-6a55-4738-bb7b-f9e25e08b923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670783649 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1670783649
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.1010421997
Short name T1638
Test name
Test status
Simulation time 2318515797 ps
CPU time 3.05 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:43:09 PM PDT 24
Peak memory 213904 kb
Host smart-fe16c164-3ed9-4e24-b479-60a92b802324
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010421997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_nack_acqfull.1010421997
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.3154309668
Short name T597
Test name
Test status
Simulation time 2331879872 ps
CPU time 2.65 seconds
Started Jul 17 05:45:38 PM PDT 24
Finished Jul 17 05:45:41 PM PDT 24
Peak memory 205676 kb
Host smart-bc436451-3a7d-405b-bb4e-20dc67f60c9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154309668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.3154309668
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_txstretch.2990124361
Short name T1720
Test name
Test status
Simulation time 168974350 ps
CPU time 1.49 seconds
Started Jul 17 05:43:08 PM PDT 24
Finished Jul 17 05:43:10 PM PDT 24
Peak memory 222140 kb
Host smart-7ea6ddbc-79a5-4017-ad78-02a359eab452
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990124361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_nack_txstretch.2990124361
Directory /workspace/14.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/14.i2c_target_perf.1051591496
Short name T572
Test name
Test status
Simulation time 582297934 ps
CPU time 4.31 seconds
Started Jul 17 05:43:03 PM PDT 24
Finished Jul 17 05:43:08 PM PDT 24
Peak memory 219852 kb
Host smart-5e19e5ee-1fc7-4def-877c-d0eea172e3b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051591496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.1051591496
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.1165548295
Short name T1646
Test name
Test status
Simulation time 508948662 ps
CPU time 2.33 seconds
Started Jul 17 05:43:07 PM PDT 24
Finished Jul 17 05:43:11 PM PDT 24
Peak memory 205388 kb
Host smart-4867d7a0-1c7f-4e7a-9227-8114fa684342
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165548295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.1165548295
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.21342690
Short name T427
Test name
Test status
Simulation time 912778515 ps
CPU time 10.98 seconds
Started Jul 17 05:42:50 PM PDT 24
Finished Jul 17 05:43:02 PM PDT 24
Peak memory 213868 kb
Host smart-1593f77a-408d-45a1-bb67-c341ebc805eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21342690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_targ
et_smoke.21342690
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.474443694
Short name T1090
Test name
Test status
Simulation time 32119900175 ps
CPU time 312.07 seconds
Started Jul 17 05:43:07 PM PDT 24
Finished Jul 17 05:48:21 PM PDT 24
Peak memory 1934744 kb
Host smart-0dbdfa0c-1e14-460e-9090-776374741af8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474443694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.i2c_target_stress_all.474443694
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.2528877656
Short name T1723
Test name
Test status
Simulation time 4201385409 ps
CPU time 21.21 seconds
Started Jul 17 05:42:52 PM PDT 24
Finished Jul 17 05:43:15 PM PDT 24
Peak memory 230124 kb
Host smart-1a2145ea-c244-4555-9f4d-77c7b80aa63e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528877656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.2528877656
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.587635558
Short name T170
Test name
Test status
Simulation time 23923932669 ps
CPU time 73.68 seconds
Started Jul 17 05:42:51 PM PDT 24
Finished Jul 17 05:44:06 PM PDT 24
Peak memory 1102816 kb
Host smart-3d1d8c69-7f7c-4c63-a27e-fa332f807a87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587635558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.587635558
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1094899867
Short name T364
Test name
Test status
Simulation time 415677177 ps
CPU time 1.08 seconds
Started Jul 17 05:42:51 PM PDT 24
Finished Jul 17 05:42:54 PM PDT 24
Peak memory 205568 kb
Host smart-cf53f4a3-745a-48e0-a12b-f9aa588c6407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094899867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1094899867
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1286002656
Short name T44
Test name
Test status
Simulation time 1013692265 ps
CPU time 6.21 seconds
Started Jul 17 05:43:04 PM PDT 24
Finished Jul 17 05:43:11 PM PDT 24
Peak memory 222052 kb
Host smart-409e2387-bd3a-4c2b-b8d7-02c35c908da5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286002656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1286002656
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.488361690
Short name T371
Test name
Test status
Simulation time 402128389 ps
CPU time 5.47 seconds
Started Jul 17 05:43:07 PM PDT 24
Finished Jul 17 05:43:14 PM PDT 24
Peak memory 205612 kb
Host smart-12194d1b-c4a8-402d-ade2-dcf4d66591e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488361690 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.488361690
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1378627852
Short name T507
Test name
Test status
Simulation time 51544829 ps
CPU time 0.63 seconds
Started Jul 17 05:43:22 PM PDT 24
Finished Jul 17 05:43:24 PM PDT 24
Peak memory 204776 kb
Host smart-668363bb-53ab-4e4e-bbb2-73849cd87d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378627852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1378627852
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.625375110
Short name T1473
Test name
Test status
Simulation time 232868841 ps
CPU time 2.91 seconds
Started Jul 17 05:43:11 PM PDT 24
Finished Jul 17 05:43:15 PM PDT 24
Peak memory 234040 kb
Host smart-5ffdfd3c-547f-4ee3-81d9-d435d4879ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625375110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.625375110
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1325087714
Short name T922
Test name
Test status
Simulation time 2128848204 ps
CPU time 25.19 seconds
Started Jul 17 05:43:06 PM PDT 24
Finished Jul 17 05:43:33 PM PDT 24
Peak memory 300384 kb
Host smart-5ed30428-0bab-4d57-b432-18195ad84777
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325087714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1325087714
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.382955709
Short name T986
Test name
Test status
Simulation time 10724294869 ps
CPU time 63.68 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:44:10 PM PDT 24
Peak memory 518380 kb
Host smart-a594be4c-7b51-46f9-b24f-2aa293e6bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382955709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.382955709
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1761524863
Short name T1673
Test name
Test status
Simulation time 4398160760 ps
CPU time 141.34 seconds
Started Jul 17 05:43:04 PM PDT 24
Finished Jul 17 05:45:26 PM PDT 24
Peak memory 700348 kb
Host smart-fc6cd001-1ca2-4826-b754-daf4e00e7a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761524863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1761524863
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.4233230613
Short name T1483
Test name
Test status
Simulation time 411791694 ps
CPU time 0.94 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:43:08 PM PDT 24
Peak memory 205224 kb
Host smart-874d1fc6-7316-4c31-a9c4-a4db4615be70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233230613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.4233230613
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1908799490
Short name T1644
Test name
Test status
Simulation time 911891169 ps
CPU time 7.92 seconds
Started Jul 17 05:43:02 PM PDT 24
Finished Jul 17 05:43:11 PM PDT 24
Peak memory 205512 kb
Host smart-eb9b3843-d6db-41b9-bfc3-aba4174eb43c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908799490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1908799490
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.584708204
Short name T400
Test name
Test status
Simulation time 4398557283 ps
CPU time 115.12 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:45:01 PM PDT 24
Peak memory 1193552 kb
Host smart-4cf12f8f-2d69-48e8-b217-fc4584cdc81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584708204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.584708204
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2730030806
Short name T252
Test name
Test status
Simulation time 629737195 ps
CPU time 13.11 seconds
Started Jul 17 05:43:16 PM PDT 24
Finished Jul 17 05:43:30 PM PDT 24
Peak memory 205660 kb
Host smart-61e9b991-0483-441a-b85e-7b5ed1c05cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730030806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2730030806
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1782620207
Short name T928
Test name
Test status
Simulation time 194348763 ps
CPU time 2.19 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:43:09 PM PDT 24
Peak memory 216224 kb
Host smart-6ea11bb2-d059-4dbc-bb0f-c68bb1047650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782620207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1782620207
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.3828293052
Short name T837
Test name
Test status
Simulation time 43155272 ps
CPU time 1.73 seconds
Started Jul 17 05:43:08 PM PDT 24
Finished Jul 17 05:43:11 PM PDT 24
Peak memory 214484 kb
Host smart-1b817f39-1b96-45b0-90f1-d8d0f8cc7bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828293052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.3828293052
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1002667754
Short name T1268
Test name
Test status
Simulation time 11209738036 ps
CPU time 68.75 seconds
Started Jul 17 05:43:59 PM PDT 24
Finished Jul 17 05:45:08 PM PDT 24
Peak memory 373460 kb
Host smart-7ffbad08-af1f-4e7d-b215-05c7a26abb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002667754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1002667754
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.1749385524
Short name T1488
Test name
Test status
Simulation time 3544721096 ps
CPU time 17.19 seconds
Started Jul 17 05:43:08 PM PDT 24
Finished Jul 17 05:43:27 PM PDT 24
Peak memory 221736 kb
Host smart-4148a499-176c-44dd-8106-98e35c466c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749385524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.1749385524
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2916439822
Short name T1165
Test name
Test status
Simulation time 2789410471 ps
CPU time 4.2 seconds
Started Jul 17 05:43:18 PM PDT 24
Finished Jul 17 05:43:23 PM PDT 24
Peak memory 213868 kb
Host smart-38e0c4e3-47de-47c8-9751-2507459a36bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916439822 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2916439822
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2196945325
Short name T1547
Test name
Test status
Simulation time 397456461 ps
CPU time 0.98 seconds
Started Jul 17 05:43:21 PM PDT 24
Finished Jul 17 05:43:23 PM PDT 24
Peak memory 205012 kb
Host smart-3dd57259-8091-4097-8204-217dc9f554d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196945325 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2196945325
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.331671373
Short name T766
Test name
Test status
Simulation time 574796005 ps
CPU time 1.29 seconds
Started Jul 17 05:43:17 PM PDT 24
Finished Jul 17 05:43:19 PM PDT 24
Peak memory 205684 kb
Host smart-3fac7059-71aa-40f3-a7f1-2189ced9aff6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331671373 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.331671373
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1388812659
Short name T724
Test name
Test status
Simulation time 502134727 ps
CPU time 2.98 seconds
Started Jul 17 05:43:18 PM PDT 24
Finished Jul 17 05:43:22 PM PDT 24
Peak memory 205648 kb
Host smart-1df9b1f4-d167-4739-ad07-31e702dca561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388812659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1388812659
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.569208240
Short name T718
Test name
Test status
Simulation time 117955389 ps
CPU time 0.88 seconds
Started Jul 17 05:45:39 PM PDT 24
Finished Jul 17 05:45:41 PM PDT 24
Peak memory 205428 kb
Host smart-46d63911-edad-41d6-9592-053d7c3bd818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569208240 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.569208240
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2147544081
Short name T210
Test name
Test status
Simulation time 981383309 ps
CPU time 5.16 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:46:30 PM PDT 24
Peak memory 221912 kb
Host smart-c76c4481-c049-4f75-9631-bf71dcdcf31e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147544081 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2147544081
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3928193243
Short name T472
Test name
Test status
Simulation time 7706142531 ps
CPU time 6.08 seconds
Started Jul 17 05:43:22 PM PDT 24
Finished Jul 17 05:43:29 PM PDT 24
Peak memory 205704 kb
Host smart-ef331a74-ed4a-4833-bf29-1525a031ebfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928193243 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3928193243
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.2073324364
Short name T1000
Test name
Test status
Simulation time 1785435585 ps
CPU time 3 seconds
Started Jul 17 05:43:17 PM PDT 24
Finished Jul 17 05:43:21 PM PDT 24
Peak memory 213824 kb
Host smart-acbcf19c-17ed-4de7-b577-4f8092724319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073324364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_nack_acqfull.2073324364
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.2630716007
Short name T1541
Test name
Test status
Simulation time 1054601315 ps
CPU time 2.51 seconds
Started Jul 17 05:43:17 PM PDT 24
Finished Jul 17 05:43:21 PM PDT 24
Peak memory 205636 kb
Host smart-ca46d9f8-86af-40f0-a28c-4437b0e960fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630716007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.2630716007
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_txstretch.3774512308
Short name T1655
Test name
Test status
Simulation time 286260981 ps
CPU time 1.41 seconds
Started Jul 17 05:43:17 PM PDT 24
Finished Jul 17 05:43:20 PM PDT 24
Peak memory 222220 kb
Host smart-aa805852-0ef9-4fff-9742-371d7ea2b3e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774512308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_nack_txstretch.3774512308
Directory /workspace/15.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/15.i2c_target_perf.4246012356
Short name T1036
Test name
Test status
Simulation time 3069728373 ps
CPU time 5.08 seconds
Started Jul 17 05:43:24 PM PDT 24
Finished Jul 17 05:43:30 PM PDT 24
Peak memory 222060 kb
Host smart-4a198165-a19b-435c-8bcf-513ba21d3986
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246012356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.4246012356
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.1136105647
Short name T1113
Test name
Test status
Simulation time 440446846 ps
CPU time 2.14 seconds
Started Jul 17 05:43:23 PM PDT 24
Finished Jul 17 05:43:26 PM PDT 24
Peak memory 205464 kb
Host smart-7da8ef77-5d5c-4989-8a42-17251e2eda14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136105647 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.1136105647
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3910395394
Short name T509
Test name
Test status
Simulation time 12214703482 ps
CPU time 12.18 seconds
Started Jul 17 05:43:06 PM PDT 24
Finished Jul 17 05:43:20 PM PDT 24
Peak memory 213844 kb
Host smart-ad330796-5601-4dc3-b1b5-9dc32445023d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910395394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3910395394
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.2007769310
Short name T282
Test name
Test status
Simulation time 32969480607 ps
CPU time 839.65 seconds
Started Jul 17 05:45:32 PM PDT 24
Finished Jul 17 05:59:33 PM PDT 24
Peak memory 5200496 kb
Host smart-23a3842f-a3b7-4ef4-8f8e-ff8944df46e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007769310 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.2007769310
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1222892178
Short name T1304
Test name
Test status
Simulation time 566967420 ps
CPU time 17.62 seconds
Started Jul 17 05:43:06 PM PDT 24
Finished Jul 17 05:43:26 PM PDT 24
Peak memory 205568 kb
Host smart-bcc23434-8465-4d5e-8c44-1910fd7e1783
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222892178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1222892178
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3965297399
Short name T1466
Test name
Test status
Simulation time 24223101340 ps
CPU time 15.63 seconds
Started Jul 17 05:43:05 PM PDT 24
Finished Jul 17 05:43:22 PM PDT 24
Peak memory 267520 kb
Host smart-0ff81b30-2031-4e96-b5cd-b335b9947ab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965297399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3965297399
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2817219525
Short name T1297
Test name
Test status
Simulation time 1194761832 ps
CPU time 6.28 seconds
Started Jul 17 05:43:21 PM PDT 24
Finished Jul 17 05:43:29 PM PDT 24
Peak memory 213956 kb
Host smart-d1f0e53d-cdf8-4a96-ba23-e9a7b05793ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817219525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2817219525
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.1242119745
Short name T753
Test name
Test status
Simulation time 149272562 ps
CPU time 3.07 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:46:27 PM PDT 24
Peak memory 205628 kb
Host smart-202e5405-77b0-442f-9320-2a4e23d00427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242119745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.1242119745
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1613936368
Short name T391
Test name
Test status
Simulation time 22353151 ps
CPU time 0.68 seconds
Started Jul 17 05:43:36 PM PDT 24
Finished Jul 17 05:43:37 PM PDT 24
Peak memory 204868 kb
Host smart-fd3a26eb-05f0-49db-b1c1-cede58115ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613936368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1613936368
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1020841767
Short name T1368
Test name
Test status
Simulation time 73743028 ps
CPU time 1.3 seconds
Started Jul 17 05:43:22 PM PDT 24
Finished Jul 17 05:43:24 PM PDT 24
Peak memory 213772 kb
Host smart-2d7569a0-4c1b-4fbc-bd21-d0faadd40f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020841767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1020841767
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2878676256
Short name T707
Test name
Test status
Simulation time 636878353 ps
CPU time 5.03 seconds
Started Jul 17 05:43:19 PM PDT 24
Finished Jul 17 05:43:25 PM PDT 24
Peak memory 238840 kb
Host smart-2f9b70aa-eb9c-4e7e-a649-dfb4783a7ba6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878676256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2878676256
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2435133239
Short name T1096
Test name
Test status
Simulation time 3235893816 ps
CPU time 71.83 seconds
Started Jul 17 05:43:21 PM PDT 24
Finished Jul 17 05:44:34 PM PDT 24
Peak memory 423592 kb
Host smart-85d6b76b-664f-4555-9417-e872ef27cb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435133239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2435133239
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2735106873
Short name T571
Test name
Test status
Simulation time 4488508375 ps
CPU time 55.28 seconds
Started Jul 17 05:46:24 PM PDT 24
Finished Jul 17 05:47:21 PM PDT 24
Peak memory 550168 kb
Host smart-696f0555-321a-4512-9376-8ff82a52b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735106873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2735106873
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2782935452
Short name T1657
Test name
Test status
Simulation time 377596873 ps
CPU time 0.89 seconds
Started Jul 17 05:43:19 PM PDT 24
Finished Jul 17 05:43:22 PM PDT 24
Peak memory 205204 kb
Host smart-40c5fb48-756c-4f8f-9f6b-6fe936559019
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782935452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2782935452
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.1730828325
Short name T841
Test name
Test status
Simulation time 185186307 ps
CPU time 9.75 seconds
Started Jul 17 05:43:21 PM PDT 24
Finished Jul 17 05:43:32 PM PDT 24
Peak memory 205520 kb
Host smart-ea076e46-fcc1-451b-b974-22257be7bff3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730828325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.1730828325
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1451618447
Short name T895
Test name
Test status
Simulation time 17135650151 ps
CPU time 289.84 seconds
Started Jul 17 05:43:22 PM PDT 24
Finished Jul 17 05:48:13 PM PDT 24
Peak memory 1240404 kb
Host smart-90a32d3e-e7e7-49bb-8333-e1dbdcd54c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451618447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1451618447
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2616791029
Short name T1634
Test name
Test status
Simulation time 754002773 ps
CPU time 15.34 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:43:46 PM PDT 24
Peak memory 205476 kb
Host smart-1bf54c54-9e8d-4f51-84ab-12db75fde16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616791029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2616791029
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.2051734316
Short name T137
Test name
Test status
Simulation time 20984035 ps
CPU time 0.66 seconds
Started Jul 17 05:43:16 PM PDT 24
Finished Jul 17 05:43:17 PM PDT 24
Peak memory 205320 kb
Host smart-894dcf49-f757-4002-986e-b857e108036e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051734316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2051734316
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2512407356
Short name T1032
Test name
Test status
Simulation time 7441330115 ps
CPU time 105.74 seconds
Started Jul 17 05:43:18 PM PDT 24
Finished Jul 17 05:45:06 PM PDT 24
Peak memory 636148 kb
Host smart-20f4e4f6-eda3-4456-88ac-e66dfa512838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512407356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2512407356
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.3949865214
Short name T750
Test name
Test status
Simulation time 363999270 ps
CPU time 7.99 seconds
Started Jul 17 05:43:18 PM PDT 24
Finished Jul 17 05:43:28 PM PDT 24
Peak memory 206412 kb
Host smart-fd8990c0-d37a-42a4-ab5b-f7f5af28edb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949865214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3949865214
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3588638970
Short name T1327
Test name
Test status
Simulation time 7049541144 ps
CPU time 31.71 seconds
Started Jul 17 05:43:18 PM PDT 24
Finished Jul 17 05:43:52 PM PDT 24
Peak memory 347640 kb
Host smart-3872e63f-f4be-4032-b608-f9a3d697b1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588638970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3588638970
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.4256267426
Short name T191
Test name
Test status
Simulation time 981675692 ps
CPU time 18.23 seconds
Started Jul 17 05:43:19 PM PDT 24
Finished Jul 17 05:43:39 PM PDT 24
Peak memory 220040 kb
Host smart-3c519e64-21ed-44f1-8f1b-482033b68402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256267426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.4256267426
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2570902127
Short name T1508
Test name
Test status
Simulation time 942174456 ps
CPU time 3.94 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:43:34 PM PDT 24
Peak memory 213860 kb
Host smart-d1f4f7a4-bf7b-451c-bd06-8aa90efbc3ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570902127 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2570902127
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3376818120
Short name T1246
Test name
Test status
Simulation time 519067247 ps
CPU time 1.35 seconds
Started Jul 17 05:43:21 PM PDT 24
Finished Jul 17 05:43:23 PM PDT 24
Peak memory 205612 kb
Host smart-81c97597-cff9-44a8-acf2-f4a5edbc736f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376818120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3376818120
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2339715761
Short name T1230
Test name
Test status
Simulation time 294224471 ps
CPU time 0.89 seconds
Started Jul 17 05:43:21 PM PDT 24
Finished Jul 17 05:43:23 PM PDT 24
Peak memory 205444 kb
Host smart-d05c5e9e-7f8d-45c6-9d1d-7fc4ca449d02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339715761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2339715761
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.1477104434
Short name T306
Test name
Test status
Simulation time 1294003776 ps
CPU time 2.17 seconds
Started Jul 17 05:43:30 PM PDT 24
Finished Jul 17 05:43:33 PM PDT 24
Peak memory 205424 kb
Host smart-2c0a12ee-eede-4f4d-898d-5d8fe66f3dec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477104434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.1477104434
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.3680923197
Short name T930
Test name
Test status
Simulation time 129801552 ps
CPU time 0.86 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:43:31 PM PDT 24
Peak memory 205364 kb
Host smart-9f622abd-4045-4b31-b0e2-b4113be1b28b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680923197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.3680923197
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2849509496
Short name T953
Test name
Test status
Simulation time 2673711054 ps
CPU time 2.11 seconds
Started Jul 17 05:43:34 PM PDT 24
Finished Jul 17 05:43:37 PM PDT 24
Peak memory 213828 kb
Host smart-ab0a8563-2d6d-431c-ac06-6ce60ee68230
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849509496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2849509496
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.923716135
Short name T788
Test name
Test status
Simulation time 1325633332 ps
CPU time 8.12 seconds
Started Jul 17 05:43:22 PM PDT 24
Finished Jul 17 05:43:32 PM PDT 24
Peak memory 223096 kb
Host smart-de6e2c71-eafc-4fbf-8572-8460525421dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923716135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.923716135
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3934256275
Short name T1353
Test name
Test status
Simulation time 3709229963 ps
CPU time 13.48 seconds
Started Jul 17 05:43:21 PM PDT 24
Finished Jul 17 05:43:36 PM PDT 24
Peak memory 577520 kb
Host smart-3ef35733-ea49-429c-9b16-9dbb0aa97bc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934256275 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3934256275
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.2270247535
Short name T1325
Test name
Test status
Simulation time 1843310625 ps
CPU time 2.73 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:43:34 PM PDT 24
Peak memory 213848 kb
Host smart-aa4b62a5-98f6-45bd-91bf-444dc49f7009
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270247535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_nack_acqfull.2270247535
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.4106729697
Short name T800
Test name
Test status
Simulation time 2326987374 ps
CPU time 2.83 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:43:33 PM PDT 24
Peak memory 205644 kb
Host smart-7c0aaac0-8e9f-48ba-bf7c-2bb1010777aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106729697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.4106729697
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_txstretch.1017088528
Short name T1681
Test name
Test status
Simulation time 1926695463 ps
CPU time 1.43 seconds
Started Jul 17 05:43:27 PM PDT 24
Finished Jul 17 05:43:30 PM PDT 24
Peak memory 222328 kb
Host smart-2c848dc1-47af-407f-8dfb-e2c7fe204e99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017088528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_nack_txstretch.1017088528
Directory /workspace/16.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/16.i2c_target_perf.4031063218
Short name T483
Test name
Test status
Simulation time 1710923923 ps
CPU time 6.32 seconds
Started Jul 17 05:43:20 PM PDT 24
Finished Jul 17 05:43:27 PM PDT 24
Peak memory 230728 kb
Host smart-5a1d1581-b205-4409-940c-ce63356330b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031063218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.4031063218
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.2686827944
Short name T1406
Test name
Test status
Simulation time 1880674763 ps
CPU time 2.33 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:43:33 PM PDT 24
Peak memory 205412 kb
Host smart-5f4cf552-ae60-4866-80f8-343026a51d7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686827944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.2686827944
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3799760949
Short name T1648
Test name
Test status
Simulation time 4295572962 ps
CPU time 36.27 seconds
Started Jul 17 05:43:16 PM PDT 24
Finished Jul 17 05:43:54 PM PDT 24
Peak memory 213848 kb
Host smart-a4428d55-927d-465d-a7b9-38e2fb3a8daf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799760949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3799760949
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.330401308
Short name T485
Test name
Test status
Simulation time 24399891777 ps
CPU time 583.83 seconds
Started Jul 17 05:43:23 PM PDT 24
Finished Jul 17 05:53:08 PM PDT 24
Peak memory 3532556 kb
Host smart-2f9a7c38-b352-4163-bd65-af6c86147a8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330401308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.i2c_target_stress_all.330401308
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2251988434
Short name T544
Test name
Test status
Simulation time 7196600342 ps
CPU time 20.06 seconds
Started Jul 17 05:43:20 PM PDT 24
Finished Jul 17 05:43:41 PM PDT 24
Peak memory 238268 kb
Host smart-13828c41-8abe-4ee4-9b39-6d3a3ec20d04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251988434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2251988434
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.962128264
Short name T909
Test name
Test status
Simulation time 30998867745 ps
CPU time 34.72 seconds
Started Jul 17 05:43:17 PM PDT 24
Finished Jul 17 05:43:53 PM PDT 24
Peak memory 773548 kb
Host smart-c3474528-1cd1-4a69-b0e6-da3d7cf9a4a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962128264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_wr.962128264
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3460143636
Short name T964
Test name
Test status
Simulation time 1510894319 ps
CPU time 5.17 seconds
Started Jul 17 05:43:21 PM PDT 24
Finished Jul 17 05:43:27 PM PDT 24
Peak memory 264396 kb
Host smart-236ecec4-63a3-44c1-b98a-c4467b0a284d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460143636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3460143636
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1086433921
Short name T1467
Test name
Test status
Simulation time 1279342058 ps
CPU time 6.55 seconds
Started Jul 17 05:43:22 PM PDT 24
Finished Jul 17 05:43:30 PM PDT 24
Peak memory 222008 kb
Host smart-9e8dfac0-ca9f-4522-aa3b-ac0f85d4a7a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086433921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1086433921
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.1006643995
Short name T1273
Test name
Test status
Simulation time 75112391 ps
CPU time 1.69 seconds
Started Jul 17 05:47:16 PM PDT 24
Finished Jul 17 05:47:19 PM PDT 24
Peak memory 205616 kb
Host smart-cf493de1-e833-485c-b5a5-df36c63524af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006643995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.1006643995
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.1449383316
Short name T1373
Test name
Test status
Simulation time 43839862 ps
CPU time 0.63 seconds
Started Jul 17 05:43:41 PM PDT 24
Finished Jul 17 05:43:42 PM PDT 24
Peak memory 204736 kb
Host smart-d9b70138-3c6b-4683-bef5-12f38e7a07bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449383316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.1449383316
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3860835222
Short name T1042
Test name
Test status
Simulation time 68359434 ps
CPU time 1.5 seconds
Started Jul 17 05:47:27 PM PDT 24
Finished Jul 17 05:47:30 PM PDT 24
Peak memory 213760 kb
Host smart-fe8d95b6-6016-4316-8b51-0a7e13e37e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860835222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3860835222
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1662761349
Short name T1315
Test name
Test status
Simulation time 355084839 ps
CPU time 17.29 seconds
Started Jul 17 05:43:27 PM PDT 24
Finished Jul 17 05:43:45 PM PDT 24
Peak memory 272724 kb
Host smart-62eb5277-14b1-441c-8806-ec6c49624818
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662761349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1662761349
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3569134957
Short name T717
Test name
Test status
Simulation time 1934208210 ps
CPU time 52.36 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:44:23 PM PDT 24
Peak memory 554376 kb
Host smart-f78b9fe7-eae8-4e52-a2aa-ca87c9f1a524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569134957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3569134957
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2522703193
Short name T1064
Test name
Test status
Simulation time 2222436272 ps
CPU time 137.12 seconds
Started Jul 17 05:43:28 PM PDT 24
Finished Jul 17 05:45:46 PM PDT 24
Peak memory 602664 kb
Host smart-54c11bef-89a1-4fa2-9121-b52b61af6c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522703193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2522703193
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1526807045
Short name T1066
Test name
Test status
Simulation time 109820462 ps
CPU time 1.03 seconds
Started Jul 17 05:43:28 PM PDT 24
Finished Jul 17 05:43:30 PM PDT 24
Peak memory 205256 kb
Host smart-27b46b94-3ced-4c70-b8ec-02bf8ec65b07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526807045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1526807045
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1001864983
Short name T1388
Test name
Test status
Simulation time 230705622 ps
CPU time 11.36 seconds
Started Jul 17 05:43:32 PM PDT 24
Finished Jul 17 05:43:44 PM PDT 24
Peak memory 205524 kb
Host smart-c091940b-b928-474a-a280-2f19cf28c077
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001864983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1001864983
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2385098754
Short name T1118
Test name
Test status
Simulation time 3683142155 ps
CPU time 258.42 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:47:49 PM PDT 24
Peak memory 1093720 kb
Host smart-9ba597b9-733d-40c2-9fc4-492737f12f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385098754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2385098754
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.3653894123
Short name T253
Test name
Test status
Simulation time 662046587 ps
CPU time 8.81 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 05:47:40 PM PDT 24
Peak memory 205520 kb
Host smart-8b324ce1-f95e-4f18-9a64-94d64a557ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653894123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3653894123
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.3181824431
Short name T1490
Test name
Test status
Simulation time 40429760 ps
CPU time 0.62 seconds
Started Jul 17 05:43:32 PM PDT 24
Finished Jul 17 05:43:33 PM PDT 24
Peak memory 205220 kb
Host smart-180d8eed-bd93-4f6b-8955-0cded831fa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181824431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3181824431
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.212724498
Short name T237
Test name
Test status
Simulation time 27699687471 ps
CPU time 180.96 seconds
Started Jul 17 05:43:32 PM PDT 24
Finished Jul 17 05:46:34 PM PDT 24
Peak memory 205528 kb
Host smart-95a82779-3b6d-4ac2-8d89-665cea9fc8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212724498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.212724498
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.2575062736
Short name T994
Test name
Test status
Simulation time 470817551 ps
CPU time 1.1 seconds
Started Jul 17 05:43:32 PM PDT 24
Finished Jul 17 05:43:34 PM PDT 24
Peak memory 213580 kb
Host smart-d44172c4-7b88-4a70-8e2e-0be76770b9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575062736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.2575062736
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.966194634
Short name T938
Test name
Test status
Simulation time 1045300784 ps
CPU time 19.76 seconds
Started Jul 17 05:43:35 PM PDT 24
Finished Jul 17 05:43:55 PM PDT 24
Peak memory 334748 kb
Host smart-d988700b-c822-4252-9050-c578bdcefb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966194634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.966194634
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2993033951
Short name T940
Test name
Test status
Simulation time 3741180306 ps
CPU time 13.89 seconds
Started Jul 17 05:43:28 PM PDT 24
Finished Jul 17 05:43:43 PM PDT 24
Peak memory 230772 kb
Host smart-d1fc54b8-75b7-48a2-825a-80a606dfc070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993033951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2993033951
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2881755837
Short name T1372
Test name
Test status
Simulation time 4443902178 ps
CPU time 5.81 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 05:47:37 PM PDT 24
Peak memory 213896 kb
Host smart-4325fd4e-283a-46b5-85c8-d55da3cc8e1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881755837 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2881755837
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2876691256
Short name T885
Test name
Test status
Simulation time 319988797 ps
CPU time 0.96 seconds
Started Jul 17 05:43:41 PM PDT 24
Finished Jul 17 05:43:43 PM PDT 24
Peak memory 213672 kb
Host smart-e263c2dc-06cc-4175-a9e5-caf89adbc4b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876691256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2876691256
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3574401491
Short name T558
Test name
Test status
Simulation time 205922060 ps
CPU time 1.22 seconds
Started Jul 17 05:43:40 PM PDT 24
Finished Jul 17 05:43:42 PM PDT 24
Peak memory 205460 kb
Host smart-6bd95594-bc97-4f62-a09a-57775dce4d1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574401491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3574401491
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.3246579509
Short name T1281
Test name
Test status
Simulation time 331079960 ps
CPU time 1.98 seconds
Started Jul 17 05:47:27 PM PDT 24
Finished Jul 17 05:47:31 PM PDT 24
Peak memory 205428 kb
Host smart-3561582e-e002-44dc-98d0-ca45bf25513f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246579509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.3246579509
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.318938422
Short name T1627
Test name
Test status
Simulation time 40146133 ps
CPU time 0.72 seconds
Started Jul 17 05:43:40 PM PDT 24
Finished Jul 17 05:43:41 PM PDT 24
Peak memory 205380 kb
Host smart-944e43fd-c660-4a10-8e3f-de1c30cdb8cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318938422 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.318938422
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.3726358409
Short name T1609
Test name
Test status
Simulation time 1352482567 ps
CPU time 2.11 seconds
Started Jul 17 05:46:26 PM PDT 24
Finished Jul 17 05:46:29 PM PDT 24
Peak memory 213856 kb
Host smart-21722195-8d95-447c-b643-58cbbdba62e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726358409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.3726358409
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1716741678
Short name T312
Test name
Test status
Simulation time 2909758636 ps
CPU time 4.77 seconds
Started Jul 17 05:46:29 PM PDT 24
Finished Jul 17 05:46:35 PM PDT 24
Peak memory 214388 kb
Host smart-b62dfb6a-5315-4e1e-b890-15149ba613b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716741678 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1716741678
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.4050021202
Short name T1300
Test name
Test status
Simulation time 23974384632 ps
CPU time 217.71 seconds
Started Jul 17 05:46:29 PM PDT 24
Finished Jul 17 05:50:08 PM PDT 24
Peak memory 2891328 kb
Host smart-69b75f49-7b7b-4b00-91fc-2897b838401b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050021202 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4050021202
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.3143200301
Short name T1239
Test name
Test status
Simulation time 608744969 ps
CPU time 3 seconds
Started Jul 17 05:43:39 PM PDT 24
Finished Jul 17 05:43:44 PM PDT 24
Peak memory 213832 kb
Host smart-916dbc55-ebf6-4d57-bf3c-e5190bc42d2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143200301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.3143200301
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.431086302
Short name T463
Test name
Test status
Simulation time 494129376 ps
CPU time 2.66 seconds
Started Jul 17 05:43:44 PM PDT 24
Finished Jul 17 05:43:47 PM PDT 24
Peak memory 205628 kb
Host smart-9443b8e1-7919-4177-a26b-5dd1c9f9b509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431086302 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.431086302
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_txstretch.1011370452
Short name T46
Test name
Test status
Simulation time 254301076 ps
CPU time 1.47 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:51 PM PDT 24
Peak memory 222300 kb
Host smart-06f30ed9-4ac7-4d75-aa02-354ce910c784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011370452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_nack_txstretch.1011370452
Directory /workspace/17.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/17.i2c_target_perf.3166808120
Short name T967
Test name
Test status
Simulation time 3645065785 ps
CPU time 6.57 seconds
Started Jul 17 05:43:38 PM PDT 24
Finished Jul 17 05:43:46 PM PDT 24
Peak memory 222128 kb
Host smart-d77d6418-49d5-4efc-b35a-a84ab5f30e69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166808120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.3166808120
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.3371687878
Short name T1453
Test name
Test status
Simulation time 501292075 ps
CPU time 2.45 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 05:47:34 PM PDT 24
Peak memory 205412 kb
Host smart-9af983b4-408e-4741-9bbe-b59e5b274633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371687878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_smbus_maxlen.3371687878
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.1419086852
Short name T1557
Test name
Test status
Simulation time 55021957254 ps
CPU time 1578.68 seconds
Started Jul 17 05:43:39 PM PDT 24
Finished Jul 17 06:09:59 PM PDT 24
Peak memory 6688960 kb
Host smart-3be110bc-5a79-480a-993d-22569c07e4f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419086852 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.1419086852
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.4129837458
Short name T1718
Test name
Test status
Simulation time 1533832611 ps
CPU time 34.81 seconds
Started Jul 17 05:43:27 PM PDT 24
Finished Jul 17 05:44:03 PM PDT 24
Peak memory 213840 kb
Host smart-09cfdf1c-0e2e-4ad4-a828-1c3f9d93e28b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129837458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.4129837458
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.999177506
Short name T1216
Test name
Test status
Simulation time 59883173852 ps
CPU time 2422.73 seconds
Started Jul 17 05:43:31 PM PDT 24
Finished Jul 17 06:23:55 PM PDT 24
Peak memory 9976056 kb
Host smart-e9910748-0903-4a1b-af1c-c2677c5c5815
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999177506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.999177506
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.787395684
Short name T1157
Test name
Test status
Simulation time 3501998349 ps
CPU time 15.27 seconds
Started Jul 17 05:43:29 PM PDT 24
Finished Jul 17 05:43:45 PM PDT 24
Peak memory 261896 kb
Host smart-a1f3b340-4e9d-49db-ab09-263556b58137
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787395684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_t
arget_stretch.787395684
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.752168526
Short name T1444
Test name
Test status
Simulation time 1270636274 ps
CPU time 7.13 seconds
Started Jul 17 05:43:35 PM PDT 24
Finished Jul 17 05:43:42 PM PDT 24
Peak memory 230156 kb
Host smart-1774f5dd-c623-4b03-8c68-cd2fd187a3f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752168526 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.752168526
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.2611643939
Short name T542
Test name
Test status
Simulation time 214798475 ps
CPU time 3.48 seconds
Started Jul 17 05:43:39 PM PDT 24
Finished Jul 17 05:43:44 PM PDT 24
Peak memory 205656 kb
Host smart-4dab136a-16d4-4bdd-9a2e-60ab83d6ee67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611643939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2611643939
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3949302918
Short name T379
Test name
Test status
Simulation time 17418717 ps
CPU time 0.63 seconds
Started Jul 17 05:43:51 PM PDT 24
Finished Jul 17 05:43:52 PM PDT 24
Peak memory 204868 kb
Host smart-6070095e-a0e1-46a6-8f61-bfa13d010502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949302918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3949302918
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.168078844
Short name T616
Test name
Test status
Simulation time 248691204 ps
CPU time 9.49 seconds
Started Jul 17 05:46:14 PM PDT 24
Finished Jul 17 05:46:24 PM PDT 24
Peak memory 235068 kb
Host smart-6fb2edf2-6de4-495f-b4c2-779549c7cd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168078844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.168078844
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3295915453
Short name T314
Test name
Test status
Simulation time 1344653432 ps
CPU time 7.63 seconds
Started Jul 17 05:43:38 PM PDT 24
Finished Jul 17 05:43:46 PM PDT 24
Peak memory 275208 kb
Host smart-46791605-f7c9-4691-978d-df731a21a60e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295915453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3295915453
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1373116658
Short name T1578
Test name
Test status
Simulation time 12064874322 ps
CPU time 105.46 seconds
Started Jul 17 05:43:41 PM PDT 24
Finished Jul 17 05:45:27 PM PDT 24
Peak memory 730708 kb
Host smart-33f4b6fd-5d1b-4c40-815b-d24861d291f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373116658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1373116658
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.600262169
Short name T622
Test name
Test status
Simulation time 6818920287 ps
CPU time 50.17 seconds
Started Jul 17 05:43:39 PM PDT 24
Finished Jul 17 05:44:31 PM PDT 24
Peak memory 530560 kb
Host smart-3811a5e7-8c2d-4766-b808-1617948b450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600262169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.600262169
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2632426779
Short name T1651
Test name
Test status
Simulation time 550226195 ps
CPU time 1.26 seconds
Started Jul 17 05:43:41 PM PDT 24
Finished Jul 17 05:43:43 PM PDT 24
Peak memory 205392 kb
Host smart-d7518498-a4e3-4200-a0af-a7e815cb9b8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632426779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2632426779
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2479914354
Short name T1009
Test name
Test status
Simulation time 389457870 ps
CPU time 10.74 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:59 PM PDT 24
Peak memory 242544 kb
Host smart-3a94a23f-4658-41e2-b6ac-13560ae16fa6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479914354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2479914354
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2371212974
Short name T820
Test name
Test status
Simulation time 10281317359 ps
CPU time 215.83 seconds
Started Jul 17 05:46:53 PM PDT 24
Finished Jul 17 05:50:31 PM PDT 24
Peak memory 1025704 kb
Host smart-92879606-64df-4083-916b-37cefa3e4efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371212974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2371212974
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_override.826946320
Short name T1122
Test name
Test status
Simulation time 27696356 ps
CPU time 0.65 seconds
Started Jul 17 05:43:44 PM PDT 24
Finished Jul 17 05:43:45 PM PDT 24
Peak memory 205220 kb
Host smart-4e33f2fd-9feb-46be-a54a-ceff6e5d0e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826946320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.826946320
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.2902435467
Short name T1624
Test name
Test status
Simulation time 12933438856 ps
CPU time 180.76 seconds
Started Jul 17 05:47:09 PM PDT 24
Finished Jul 17 05:50:11 PM PDT 24
Peak memory 821244 kb
Host smart-d257da47-d2dc-4867-a692-09169b0f1cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902435467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2902435467
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.1079645902
Short name T917
Test name
Test status
Simulation time 658111254 ps
CPU time 2.33 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:52 PM PDT 24
Peak memory 205424 kb
Host smart-023d759a-13b8-4f8f-b575-911335cd0458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079645902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.1079645902
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2784053050
Short name T510
Test name
Test status
Simulation time 1440232230 ps
CPU time 66.1 seconds
Started Jul 17 05:43:40 PM PDT 24
Finished Jul 17 05:44:47 PM PDT 24
Peak memory 313632 kb
Host smart-d4fb71fe-08c4-409c-ae41-4c84db3ae135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784053050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2784053050
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.2718213792
Short name T787
Test name
Test status
Simulation time 2847944352 ps
CPU time 34.73 seconds
Started Jul 17 05:43:40 PM PDT 24
Finished Jul 17 05:44:15 PM PDT 24
Peak memory 214740 kb
Host smart-7daee3fa-ffe4-4eec-83e9-b7f82a79c093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718213792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.2718213792
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.769246203
Short name T911
Test name
Test status
Simulation time 708307597 ps
CPU time 4 seconds
Started Jul 17 05:43:48 PM PDT 24
Finished Jul 17 05:43:53 PM PDT 24
Peak memory 213848 kb
Host smart-d1d93bab-c930-42eb-bd0b-4ab04c2c7d42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769246203 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.769246203
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1563049002
Short name T658
Test name
Test status
Simulation time 155980658 ps
CPU time 1.13 seconds
Started Jul 17 05:43:50 PM PDT 24
Finished Jul 17 05:43:52 PM PDT 24
Peak memory 205416 kb
Host smart-30f4b38e-b62e-4592-9da8-1feff2e0bb15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563049002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1563049002
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2930355610
Short name T1016
Test name
Test status
Simulation time 819452922 ps
CPU time 1.86 seconds
Started Jul 17 05:43:51 PM PDT 24
Finished Jul 17 05:43:54 PM PDT 24
Peak memory 208436 kb
Host smart-c84e2797-e238-4529-a041-0de7da1c37d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930355610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2930355610
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.1481520110
Short name T742
Test name
Test status
Simulation time 863041237 ps
CPU time 2.47 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 205644 kb
Host smart-c7fba056-bf4d-480a-8c38-22f5c28e0ad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481520110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.1481520110
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.4100552454
Short name T1053
Test name
Test status
Simulation time 588283373 ps
CPU time 1.27 seconds
Started Jul 17 05:43:51 PM PDT 24
Finished Jul 17 05:43:54 PM PDT 24
Peak memory 205424 kb
Host smart-b99749bb-ac89-4d59-8774-9ae89ec41e35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100552454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.4100552454
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3347698463
Short name T731
Test name
Test status
Simulation time 3857224808 ps
CPU time 4.98 seconds
Started Jul 17 05:43:53 PM PDT 24
Finished Jul 17 05:43:59 PM PDT 24
Peak memory 213904 kb
Host smart-a631dead-a159-431e-abec-f9d376e8e2b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347698463 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3347698463
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.1629453306
Short name T1202
Test name
Test status
Simulation time 3928501541 ps
CPU time 2.58 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:52 PM PDT 24
Peak memory 213840 kb
Host smart-899ebb00-4c2b-425f-bf72-32e3a4ad16f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629453306 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1629453306
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.1561336936
Short name T154
Test name
Test status
Simulation time 2264115862 ps
CPU time 3.06 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:48 PM PDT 24
Peak memory 213932 kb
Host smart-82b625a4-bdb5-4bcf-8905-6fedaab4d75a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561336936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.1561336936
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.4266500179
Short name T434
Test name
Test status
Simulation time 2246619818 ps
CPU time 2.9 seconds
Started Jul 17 05:43:52 PM PDT 24
Finished Jul 17 05:43:56 PM PDT 24
Peak memory 205692 kb
Host smart-6cc338f5-4ab8-4a38-a34c-28b5f634b116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266500179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.4266500179
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.3914701889
Short name T672
Test name
Test status
Simulation time 865486040 ps
CPU time 6.4 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 221972 kb
Host smart-dfe11805-3522-4ff3-960c-5b17eb969551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914701889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.3914701889
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.4050740283
Short name T392
Test name
Test status
Simulation time 516678861 ps
CPU time 2.44 seconds
Started Jul 17 05:43:54 PM PDT 24
Finished Jul 17 05:43:58 PM PDT 24
Peak memory 205416 kb
Host smart-33d1edf0-26dd-4526-9171-959437cb2947
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050740283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_smbus_maxlen.4050740283
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.704899905
Short name T708
Test name
Test status
Simulation time 885245595 ps
CPU time 26.53 seconds
Started Jul 17 05:46:14 PM PDT 24
Finished Jul 17 05:46:41 PM PDT 24
Peak memory 213848 kb
Host smart-6e7f7825-1da1-4c3b-95d3-b8c7c894ca91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704899905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.704899905
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.2129346711
Short name T789
Test name
Test status
Simulation time 61618501208 ps
CPU time 2229.25 seconds
Started Jul 17 05:43:52 PM PDT 24
Finished Jul 17 06:21:03 PM PDT 24
Peak memory 8423132 kb
Host smart-d2c4953c-f5f4-4c55-b679-a280100b4807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129346711 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.2129346711
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2408344345
Short name T299
Test name
Test status
Simulation time 4808550064 ps
CPU time 53.28 seconds
Started Jul 17 05:43:51 PM PDT 24
Finished Jul 17 05:44:45 PM PDT 24
Peak memory 214568 kb
Host smart-950b101f-b7b7-41a9-b33d-0ff1f7161b51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408344345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2408344345
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.2627080386
Short name T565
Test name
Test status
Simulation time 34966860486 ps
CPU time 31.77 seconds
Started Jul 17 05:43:49 PM PDT 24
Finished Jul 17 05:44:22 PM PDT 24
Peak memory 690820 kb
Host smart-807ff371-d2d0-441a-97ec-96ff8162c1cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627080386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.2627080386
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1777674393
Short name T1128
Test name
Test status
Simulation time 3767575618 ps
CPU time 35.91 seconds
Started Jul 17 05:43:52 PM PDT 24
Finished Jul 17 05:44:29 PM PDT 24
Peak memory 374824 kb
Host smart-0f8ded6d-b49c-4640-8b1b-524a0ab850dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777674393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1777674393
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1661069769
Short name T1314
Test name
Test status
Simulation time 1564892843 ps
CPU time 7.48 seconds
Started Jul 17 05:47:26 PM PDT 24
Finished Jul 17 05:47:35 PM PDT 24
Peak memory 221996 kb
Host smart-73ef0d5d-0906-40a2-adea-6e7ff2a78c4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661069769 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1661069769
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.1866125575
Short name T1481
Test name
Test status
Simulation time 217888616 ps
CPU time 4.52 seconds
Started Jul 17 05:43:51 PM PDT 24
Finished Jul 17 05:43:57 PM PDT 24
Peak memory 207944 kb
Host smart-7341a045-e00d-4ad0-a85f-c60ee0e3d983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866125575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.1866125575
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.4053977459
Short name T470
Test name
Test status
Simulation time 48212850 ps
CPU time 0.66 seconds
Started Jul 17 05:44:16 PM PDT 24
Finished Jul 17 05:44:18 PM PDT 24
Peak memory 204944 kb
Host smart-fc28f7ee-52fb-4ec7-93de-381438614e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053977459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.4053977459
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.4176758493
Short name T795
Test name
Test status
Simulation time 195701212 ps
CPU time 7.46 seconds
Started Jul 17 05:46:26 PM PDT 24
Finished Jul 17 05:46:35 PM PDT 24
Peak memory 221992 kb
Host smart-e5864315-6a5d-49a7-bb0f-77bb96f7ded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176758493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.4176758493
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.2509424338
Short name T482
Test name
Test status
Simulation time 351230424 ps
CPU time 17.1 seconds
Started Jul 17 05:43:52 PM PDT 24
Finished Jul 17 05:44:10 PM PDT 24
Peak memory 276880 kb
Host smart-c7c9b769-5e9d-499d-8b3f-958df30d7f89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509424338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.2509424338
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3521083554
Short name T405
Test name
Test status
Simulation time 2311688445 ps
CPU time 89.03 seconds
Started Jul 17 05:43:53 PM PDT 24
Finished Jul 17 05:45:23 PM PDT 24
Peak memory 711928 kb
Host smart-88984b0a-78c1-455f-946e-a66c4ea053c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521083554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3521083554
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.971383194
Short name T1063
Test name
Test status
Simulation time 2604904426 ps
CPU time 67.77 seconds
Started Jul 17 05:43:51 PM PDT 24
Finished Jul 17 05:45:00 PM PDT 24
Peak memory 749928 kb
Host smart-74d7651e-943e-4e21-be60-b2efbfec5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971383194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.971383194
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1206247876
Short name T1190
Test name
Test status
Simulation time 282867739 ps
CPU time 1.15 seconds
Started Jul 17 05:43:54 PM PDT 24
Finished Jul 17 05:43:56 PM PDT 24
Peak memory 205228 kb
Host smart-1f16a40a-4ca6-405a-aaf3-b6a382d8a135
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206247876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1206247876
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3221223282
Short name T355
Test name
Test status
Simulation time 190831420 ps
CPU time 7.34 seconds
Started Jul 17 05:43:54 PM PDT 24
Finished Jul 17 05:44:02 PM PDT 24
Peak memory 205528 kb
Host smart-231b993e-2e72-4f63-81bd-b764b84b473b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221223282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3221223282
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1358961647
Short name T960
Test name
Test status
Simulation time 3421937415 ps
CPU time 215.42 seconds
Started Jul 17 05:43:53 PM PDT 24
Finished Jul 17 05:47:29 PM PDT 24
Peak memory 1019184 kb
Host smart-70ef10ad-3f43-476d-b4a7-ff8f5ae6ea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358961647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1358961647
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_override.3067745680
Short name T1060
Test name
Test status
Simulation time 29414530 ps
CPU time 0.73 seconds
Started Jul 17 05:43:51 PM PDT 24
Finished Jul 17 05:43:53 PM PDT 24
Peak memory 205212 kb
Host smart-f4fb7c0d-3e5a-4017-86b0-cd762e1cf01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067745680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3067745680
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.96251102
Short name T419
Test name
Test status
Simulation time 4989881956 ps
CPU time 68.95 seconds
Started Jul 17 05:44:00 PM PDT 24
Finished Jul 17 05:45:10 PM PDT 24
Peak memory 214540 kb
Host smart-6d0f2292-efa1-4cce-acf4-c5d8e1e1f2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96251102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.96251102
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.2264875071
Short name T963
Test name
Test status
Simulation time 2685961564 ps
CPU time 36.32 seconds
Started Jul 17 05:44:03 PM PDT 24
Finished Jul 17 05:44:40 PM PDT 24
Peak memory 205468 kb
Host smart-96c95b2a-c7fd-4116-abcf-86256ff1ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264875071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2264875071
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1453430147
Short name T643
Test name
Test status
Simulation time 3722997003 ps
CPU time 31.7 seconds
Started Jul 17 05:43:53 PM PDT 24
Finished Jul 17 05:44:26 PM PDT 24
Peak memory 304044 kb
Host smart-ff30bc59-a93b-4fe0-88f3-214a03459541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453430147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1453430147
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3224205954
Short name T132
Test name
Test status
Simulation time 71064023755 ps
CPU time 469.54 seconds
Started Jul 17 05:44:00 PM PDT 24
Finished Jul 17 05:51:51 PM PDT 24
Peak memory 2385072 kb
Host smart-724f5cde-d2b8-4267-83d4-78e09d5ce9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224205954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3224205954
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3398178725
Short name T123
Test name
Test status
Simulation time 713644415 ps
CPU time 31.92 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:48:19 PM PDT 24
Peak memory 213712 kb
Host smart-569c9f58-2de9-40f9-b5ce-f557b8dc4024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398178725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3398178725
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.965959699
Short name T303
Test name
Test status
Simulation time 5103821846 ps
CPU time 5.64 seconds
Started Jul 17 05:44:04 PM PDT 24
Finished Jul 17 05:44:10 PM PDT 24
Peak memory 213916 kb
Host smart-acb22e90-685e-402d-ac7e-ef2c82a45f1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965959699 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.965959699
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.4161665679
Short name T240
Test name
Test status
Simulation time 113655165 ps
CPU time 0.86 seconds
Started Jul 17 05:44:02 PM PDT 24
Finished Jul 17 05:44:04 PM PDT 24
Peak memory 205444 kb
Host smart-30f07a1f-ee8f-4a96-812a-7964e5f2ff7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161665679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.4161665679
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1667662436
Short name T933
Test name
Test status
Simulation time 635102394 ps
CPU time 1.27 seconds
Started Jul 17 05:44:04 PM PDT 24
Finished Jul 17 05:44:06 PM PDT 24
Peak memory 213804 kb
Host smart-9cc264ba-ad95-4f7b-a8ec-eedff3cf3dd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667662436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1667662436
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.1420017269
Short name T952
Test name
Test status
Simulation time 2087692476 ps
CPU time 3.19 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:49 PM PDT 24
Peak memory 205668 kb
Host smart-08c8683e-5585-4ec3-b83d-95690e71e843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420017269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.1420017269
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.1705453589
Short name T1378
Test name
Test status
Simulation time 599408789 ps
CPU time 1.27 seconds
Started Jul 17 05:44:04 PM PDT 24
Finished Jul 17 05:44:06 PM PDT 24
Peak memory 205456 kb
Host smart-5092b4cf-0e86-4bce-916b-78bb11c0285f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705453589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.1705453589
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.4097764879
Short name T1142
Test name
Test status
Simulation time 910302475 ps
CPU time 5.26 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:50 PM PDT 24
Peak memory 218980 kb
Host smart-c8d8d635-473c-4f4d-93da-c44e71a4005f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097764879 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.4097764879
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2803707810
Short name T1116
Test name
Test status
Simulation time 23675859816 ps
CPU time 79.73 seconds
Started Jul 17 05:44:01 PM PDT 24
Finished Jul 17 05:45:22 PM PDT 24
Peak memory 1101392 kb
Host smart-50893000-8405-4bca-8e57-a6dcd8b5d33e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803707810 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2803707810
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.1432079504
Short name T157
Test name
Test status
Simulation time 2072084628 ps
CPU time 2.64 seconds
Started Jul 17 05:47:37 PM PDT 24
Finished Jul 17 05:47:41 PM PDT 24
Peak memory 213860 kb
Host smart-6778f0d8-09be-4967-a40c-603371706e52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432079504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_nack_acqfull.1432079504
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.2537053594
Short name T1559
Test name
Test status
Simulation time 979183572 ps
CPU time 2.72 seconds
Started Jul 17 05:44:02 PM PDT 24
Finished Jul 17 05:44:06 PM PDT 24
Peak memory 205612 kb
Host smart-19141ef9-6572-47a0-b698-e1ebbfa0a407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537053594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.2537053594
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_txstretch.1014611658
Short name T736
Test name
Test status
Simulation time 485798160 ps
CPU time 1.52 seconds
Started Jul 17 05:44:04 PM PDT 24
Finished Jul 17 05:44:07 PM PDT 24
Peak memory 222396 kb
Host smart-b6a9bba1-bd8e-412c-87ae-da41aa74eefd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014611658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_nack_txstretch.1014611658
Directory /workspace/19.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/19.i2c_target_perf.3792268160
Short name T1280
Test name
Test status
Simulation time 5790305483 ps
CPU time 5.98 seconds
Started Jul 17 05:44:04 PM PDT 24
Finished Jul 17 05:44:11 PM PDT 24
Peak memory 216520 kb
Host smart-936b8a6c-8a55-40c5-959e-a79200e3d486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792268160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.3792268160
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.3034665442
Short name T1010
Test name
Test status
Simulation time 537614620 ps
CPU time 2.46 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:46:26 PM PDT 24
Peak memory 205448 kb
Host smart-473bd947-5169-4918-87ee-bf7d66823e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034665442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_smbus_maxlen.3034665442
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1576826295
Short name T1140
Test name
Test status
Simulation time 10462923928 ps
CPU time 26.94 seconds
Started Jul 17 05:44:03 PM PDT 24
Finished Jul 17 05:44:30 PM PDT 24
Peak memory 214100 kb
Host smart-006ee877-0135-4c3f-be2d-197277f968ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576826295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1576826295
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.2191884251
Short name T887
Test name
Test status
Simulation time 22735055453 ps
CPU time 100.56 seconds
Started Jul 17 05:44:01 PM PDT 24
Finished Jul 17 05:45:43 PM PDT 24
Peak memory 1043208 kb
Host smart-ee4c7b97-e709-4f06-9f6c-e44770b66bf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191884251 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.2191884251
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2899504278
Short name T531
Test name
Test status
Simulation time 1564766264 ps
CPU time 64.9 seconds
Started Jul 17 05:44:04 PM PDT 24
Finished Jul 17 05:45:10 PM PDT 24
Peak memory 217256 kb
Host smart-522fc7b7-b06f-43d1-8e8f-aa58e31940b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899504278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2899504278
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3723833937
Short name T1468
Test name
Test status
Simulation time 64668963647 ps
CPU time 384.39 seconds
Started Jul 17 05:44:01 PM PDT 24
Finished Jul 17 05:50:26 PM PDT 24
Peak memory 2793832 kb
Host smart-dc738fb7-1940-421e-83c7-746f259210e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723833937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3723833937
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.156034405
Short name T433
Test name
Test status
Simulation time 3139674239 ps
CPU time 155.44 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:50:22 PM PDT 24
Peak memory 885016 kb
Host smart-312561d8-9e1b-401f-a2d5-bde4d3a11807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156034405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_t
arget_stretch.156034405
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2034372570
Short name T865
Test name
Test status
Simulation time 1156070146 ps
CPU time 7.01 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:52 PM PDT 24
Peak memory 221996 kb
Host smart-e63bc062-d497-411d-aacc-39ee42f4f1ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034372570 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2034372570
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.4186733323
Short name T673
Test name
Test status
Simulation time 154203475 ps
CPU time 3.05 seconds
Started Jul 17 05:44:04 PM PDT 24
Finished Jul 17 05:44:08 PM PDT 24
Peak memory 205592 kb
Host smart-3b2144f1-48f1-4706-a168-079468f096b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186733323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.4186733323
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.198802206
Short name T576
Test name
Test status
Simulation time 81531586 ps
CPU time 0.6 seconds
Started Jul 17 05:39:58 PM PDT 24
Finished Jul 17 05:40:01 PM PDT 24
Peak memory 204812 kb
Host smart-f42e6e6f-34ad-4b8a-b265-6e2dacb225b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198802206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.198802206
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3373063472
Short name T1084
Test name
Test status
Simulation time 520144773 ps
CPU time 1.28 seconds
Started Jul 17 05:39:31 PM PDT 24
Finished Jul 17 05:39:33 PM PDT 24
Peak memory 217096 kb
Host smart-051aabec-52ea-4fbf-ad77-65f105c074c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373063472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3373063472
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.520106068
Short name T826
Test name
Test status
Simulation time 1680882546 ps
CPU time 9.9 seconds
Started Jul 17 05:45:49 PM PDT 24
Finished Jul 17 05:46:00 PM PDT 24
Peak memory 299792 kb
Host smart-d5649854-af9f-4c2c-ac01-4bf43c5bf684
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520106068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.520106068
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2340797856
Short name T1204
Test name
Test status
Simulation time 4293421876 ps
CPU time 89.23 seconds
Started Jul 17 05:39:31 PM PDT 24
Finished Jul 17 05:41:01 PM PDT 24
Peak memory 463508 kb
Host smart-0d810af5-acc0-48ea-b47b-f4b62d8932d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340797856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2340797856
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.465033346
Short name T1052
Test name
Test status
Simulation time 4914971724 ps
CPU time 179.71 seconds
Started Jul 17 05:45:41 PM PDT 24
Finished Jul 17 05:48:42 PM PDT 24
Peak memory 795492 kb
Host smart-1a5ea523-fba8-47ff-bb29-49c572b13021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465033346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.465033346
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.417912972
Short name T838
Test name
Test status
Simulation time 2142500678 ps
CPU time 1.27 seconds
Started Jul 17 05:39:30 PM PDT 24
Finished Jul 17 05:39:33 PM PDT 24
Peak memory 205428 kb
Host smart-c6430a31-6b2c-48c6-993c-8274c334600f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417912972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.417912972
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.258396170
Short name T1684
Test name
Test status
Simulation time 7782511188 ps
CPU time 70.65 seconds
Started Jul 17 05:39:30 PM PDT 24
Finished Jul 17 05:40:41 PM PDT 24
Peak memory 853592 kb
Host smart-d937b4bf-3d7b-4156-a7dd-188dfae003da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258396170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.258396170
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.4110977092
Short name T254
Test name
Test status
Simulation time 341264091 ps
CPU time 4.68 seconds
Started Jul 17 05:39:44 PM PDT 24
Finished Jul 17 05:39:49 PM PDT 24
Peak memory 205476 kb
Host smart-0aac174f-cd33-49ad-b49a-071016ddb341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110977092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.4110977092
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.3245603514
Short name T1521
Test name
Test status
Simulation time 109943098 ps
CPU time 0.72 seconds
Started Jul 17 05:40:57 PM PDT 24
Finished Jul 17 05:40:59 PM PDT 24
Peak memory 205204 kb
Host smart-e898b9f4-dfcb-4a99-8700-7ddecb586c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245603514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3245603514
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2671153515
Short name T1515
Test name
Test status
Simulation time 25475559888 ps
CPU time 880.71 seconds
Started Jul 17 05:46:59 PM PDT 24
Finished Jul 17 06:01:40 PM PDT 24
Peak memory 213740 kb
Host smart-5961a4a1-f9f4-4daf-b024-a28ed871ab01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671153515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2671153515
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.2525680273
Short name T918
Test name
Test status
Simulation time 875399816 ps
CPU time 2.59 seconds
Started Jul 17 05:39:31 PM PDT 24
Finished Jul 17 05:39:34 PM PDT 24
Peak memory 213568 kb
Host smart-c5567605-5737-4d83-a21f-65c85706bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525680273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2525680273
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.381646343
Short name T412
Test name
Test status
Simulation time 2443169737 ps
CPU time 53.15 seconds
Started Jul 17 05:40:56 PM PDT 24
Finished Jul 17 05:41:50 PM PDT 24
Peak memory 249248 kb
Host smart-ffe4aa44-03b9-4e64-a642-619f8f240e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381646343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.381646343
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.1642009768
Short name T530
Test name
Test status
Simulation time 877029014 ps
CPU time 15.42 seconds
Started Jul 17 05:45:41 PM PDT 24
Finished Jul 17 05:45:57 PM PDT 24
Peak memory 221732 kb
Host smart-5e7294bf-94ae-4054-9207-0ef24c505d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642009768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1642009768
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1904710516
Short name T182
Test name
Test status
Simulation time 127819712 ps
CPU time 0.94 seconds
Started Jul 17 05:40:39 PM PDT 24
Finished Jul 17 05:40:43 PM PDT 24
Peak memory 223976 kb
Host smart-7dc3405d-a573-4891-a86e-eea26c1d1831
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904710516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1904710516
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.553596967
Short name T846
Test name
Test status
Simulation time 5076681922 ps
CPU time 6.85 seconds
Started Jul 17 05:39:39 PM PDT 24
Finished Jul 17 05:39:47 PM PDT 24
Peak memory 222084 kb
Host smart-c0946b38-1b4d-46e3-aa1e-6ff4ecca06cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553596967 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.553596967
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3348945170
Short name T430
Test name
Test status
Simulation time 411368845 ps
CPU time 1.33 seconds
Started Jul 17 05:39:43 PM PDT 24
Finished Jul 17 05:39:45 PM PDT 24
Peak memory 205620 kb
Host smart-0f92f21b-0123-4c7f-b92f-5884e74e57c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348945170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3348945170
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1109188373
Short name T1370
Test name
Test status
Simulation time 154951182 ps
CPU time 1.01 seconds
Started Jul 17 05:39:42 PM PDT 24
Finished Jul 17 05:39:43 PM PDT 24
Peak memory 213660 kb
Host smart-0e45f3f7-323d-4d50-a28c-7888dfd56c0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109188373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1109188373
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.2478789585
Short name T1020
Test name
Test status
Simulation time 364813821 ps
CPU time 1.88 seconds
Started Jul 17 05:39:38 PM PDT 24
Finished Jul 17 05:39:41 PM PDT 24
Peak memory 205432 kb
Host smart-d49929bf-97e5-4f1b-bdda-f99acabc6da4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478789585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.2478789585
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.3457924592
Short name T1379
Test name
Test status
Simulation time 269351521 ps
CPU time 1.12 seconds
Started Jul 17 05:39:43 PM PDT 24
Finished Jul 17 05:39:45 PM PDT 24
Peak memory 205420 kb
Host smart-cde6420c-5fa1-4a16-975b-23f5f9fcab18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457924592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.3457924592
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.2269207064
Short name T1580
Test name
Test status
Simulation time 1382994241 ps
CPU time 2.83 seconds
Started Jul 17 05:39:38 PM PDT 24
Finished Jul 17 05:39:41 PM PDT 24
Peak memory 213792 kb
Host smart-58ac6824-b271-46b7-9938-d055f81dd0c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269207064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.2269207064
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2578718968
Short name T171
Test name
Test status
Simulation time 1494318693 ps
CPU time 8.72 seconds
Started Jul 17 05:39:31 PM PDT 24
Finished Jul 17 05:39:40 PM PDT 24
Peak memory 221388 kb
Host smart-6bc80b44-47fc-4127-804f-45f38d25ee39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578718968 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2578718968
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.1315950097
Short name T792
Test name
Test status
Simulation time 1430412240 ps
CPU time 2.04 seconds
Started Jul 17 05:39:30 PM PDT 24
Finished Jul 17 05:39:33 PM PDT 24
Peak memory 213876 kb
Host smart-a2f309e7-9226-4d71-8414-84f61298bc47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315950097 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.1315950097
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.3514629125
Short name T1086
Test name
Test status
Simulation time 1887341700 ps
CPU time 2.29 seconds
Started Jul 17 05:47:06 PM PDT 24
Finished Jul 17 05:47:10 PM PDT 24
Peak memory 205260 kb
Host smart-71339f0f-533c-4f0e-83cd-ffef3f89cc2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514629125 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.3514629125
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_txstretch.1248146945
Short name T1687
Test name
Test status
Simulation time 155323315 ps
CPU time 1.41 seconds
Started Jul 17 05:46:05 PM PDT 24
Finished Jul 17 05:46:07 PM PDT 24
Peak memory 222368 kb
Host smart-ed49e83d-71a8-4991-a83e-bd09d791fd24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248146945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_nack_txstretch.1248146945
Directory /workspace/2.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/2.i2c_target_perf.1716769024
Short name T679
Test name
Test status
Simulation time 2233243789 ps
CPU time 3.22 seconds
Started Jul 17 05:39:43 PM PDT 24
Finished Jul 17 05:39:47 PM PDT 24
Peak memory 213956 kb
Host smart-ff00aaac-aebe-4e3d-8f74-933fb2c1c25e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716769024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.1716769024
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.4256851437
Short name T1598
Test name
Test status
Simulation time 1021452814 ps
CPU time 2.23 seconds
Started Jul 17 05:39:36 PM PDT 24
Finished Jul 17 05:39:39 PM PDT 24
Peak memory 205628 kb
Host smart-85a04f6e-40fb-47cb-aabb-bc8d679ec39d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256851437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_smbus_maxlen.4256851437
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.2250846037
Short name T1642
Test name
Test status
Simulation time 627933000 ps
CPU time 18.58 seconds
Started Jul 17 05:39:29 PM PDT 24
Finished Jul 17 05:39:49 PM PDT 24
Peak memory 213788 kb
Host smart-e836642f-df71-4d5c-9adf-f818b1ca6672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250846037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.2250846037
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.3813975954
Short name T929
Test name
Test status
Simulation time 26041908737 ps
CPU time 115.97 seconds
Started Jul 17 05:39:38 PM PDT 24
Finished Jul 17 05:41:36 PM PDT 24
Peak memory 1175736 kb
Host smart-b39c8f2b-ede3-4111-9ad1-2e59abc4effa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813975954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.3813975954
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1084902301
Short name T1501
Test name
Test status
Simulation time 543105070 ps
CPU time 12.89 seconds
Started Jul 17 05:40:31 PM PDT 24
Finished Jul 17 05:40:44 PM PDT 24
Peak memory 205636 kb
Host smart-bc8862ad-eca2-4d2a-b85e-ea03f65bc055
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084902301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1084902301
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1845617222
Short name T385
Test name
Test status
Simulation time 55049754255 ps
CPU time 237.98 seconds
Started Jul 17 05:39:29 PM PDT 24
Finished Jul 17 05:43:28 PM PDT 24
Peak memory 2463732 kb
Host smart-5db7008b-e7dc-48a0-88db-f0fa9a713606
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845617222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1845617222
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.273711666
Short name T1375
Test name
Test status
Simulation time 3640594581 ps
CPU time 8.1 seconds
Started Jul 17 05:40:31 PM PDT 24
Finished Jul 17 05:40:40 PM PDT 24
Peak memory 225064 kb
Host smart-d49308c6-648c-4ae7-b792-6882af4b6ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273711666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.273711666
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2528045399
Short name T1237
Test name
Test status
Simulation time 1156117832 ps
CPU time 5.97 seconds
Started Jul 17 05:39:30 PM PDT 24
Finished Jul 17 05:39:37 PM PDT 24
Peak memory 221988 kb
Host smart-f5131d25-1b22-43c1-a53c-4e49a930854f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528045399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2528045399
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.2048342617
Short name T486
Test name
Test status
Simulation time 88046846 ps
CPU time 2.01 seconds
Started Jul 17 05:39:44 PM PDT 24
Finished Jul 17 05:39:46 PM PDT 24
Peak memory 205600 kb
Host smart-d44d397d-2b7e-4a28-a7e8-4658159c7d2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048342617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.2048342617
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3582340712
Short name T450
Test name
Test status
Simulation time 29258969 ps
CPU time 0.68 seconds
Started Jul 17 05:47:47 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 204684 kb
Host smart-584cbd8b-7f02-4cf5-8969-f36492dbd38e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582340712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3582340712
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2057899321
Short name T502
Test name
Test status
Simulation time 64853288 ps
CPU time 1.59 seconds
Started Jul 17 05:44:16 PM PDT 24
Finished Jul 17 05:44:19 PM PDT 24
Peak memory 213712 kb
Host smart-a4fa23b2-2381-413c-85a2-8fa68c339444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057899321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2057899321
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2559187038
Short name T1676
Test name
Test status
Simulation time 881813832 ps
CPU time 9.44 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:55 PM PDT 24
Peak memory 295472 kb
Host smart-4850af0d-aa8c-4f99-9d4f-cb1834766e48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559187038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2559187038
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3874802683
Short name T21
Test name
Test status
Simulation time 8768595440 ps
CPU time 49.36 seconds
Started Jul 17 05:44:15 PM PDT 24
Finished Jul 17 05:45:05 PM PDT 24
Peak memory 348992 kb
Host smart-414e305c-0c72-4eac-95bb-22ef2e058ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874802683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3874802683
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2246300103
Short name T1506
Test name
Test status
Simulation time 2476526489 ps
CPU time 55.33 seconds
Started Jul 17 05:44:25 PM PDT 24
Finished Jul 17 05:45:21 PM PDT 24
Peak memory 586256 kb
Host smart-1b0d6b03-a22e-432a-858b-8e5af8c2b6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246300103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2246300103
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2288855933
Short name T870
Test name
Test status
Simulation time 75761397 ps
CPU time 0.97 seconds
Started Jul 17 05:44:17 PM PDT 24
Finished Jul 17 05:44:20 PM PDT 24
Peak memory 205276 kb
Host smart-bb251894-0669-4b6a-8bae-0786673ce62b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288855933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2288855933
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1578038307
Short name T406
Test name
Test status
Simulation time 297572382 ps
CPU time 9.09 seconds
Started Jul 17 05:44:15 PM PDT 24
Finished Jul 17 05:44:26 PM PDT 24
Peak memory 205492 kb
Host smart-411fabb0-399b-4f4e-b131-1acfffa921d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578038307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1578038307
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.4261687749
Short name T1715
Test name
Test status
Simulation time 5924071368 ps
CPU time 167.99 seconds
Started Jul 17 05:44:16 PM PDT 24
Finished Jul 17 05:47:05 PM PDT 24
Peak memory 1533968 kb
Host smart-2518d3a1-81a8-477c-9f13-8aa982e79845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261687749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.4261687749
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.231139899
Short name T1591
Test name
Test status
Simulation time 655072192 ps
CPU time 13.13 seconds
Started Jul 17 05:44:18 PM PDT 24
Finished Jul 17 05:44:33 PM PDT 24
Peak memory 205536 kb
Host smart-83af340b-a185-4456-ab7f-2717b40a9009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231139899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.231139899
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_override.3625901077
Short name T1308
Test name
Test status
Simulation time 93959400 ps
CPU time 0.68 seconds
Started Jul 17 05:44:26 PM PDT 24
Finished Jul 17 05:44:27 PM PDT 24
Peak memory 205180 kb
Host smart-d0302456-983f-4c97-b54e-240410fbd275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625901077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3625901077
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1636045787
Short name T637
Test name
Test status
Simulation time 13486560203 ps
CPU time 53.9 seconds
Started Jul 17 05:47:12 PM PDT 24
Finished Jul 17 05:48:07 PM PDT 24
Peak memory 261952 kb
Host smart-2b89a3d9-0f4b-4a79-86f9-6f471dd5b39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636045787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1636045787
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.703549546
Short name T1164
Test name
Test status
Simulation time 437106218 ps
CPU time 4.88 seconds
Started Jul 17 05:44:17 PM PDT 24
Finished Jul 17 05:44:23 PM PDT 24
Peak memory 205428 kb
Host smart-be1a19ed-a95c-444c-8f80-da8ca0d3ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703549546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.703549546
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1690003597
Short name T1185
Test name
Test status
Simulation time 1527903594 ps
CPU time 56.71 seconds
Started Jul 17 05:44:12 PM PDT 24
Finished Jul 17 05:45:09 PM PDT 24
Peak memory 343216 kb
Host smart-9837fa8a-fb56-4aad-8d49-5fac28ce05b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690003597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1690003597
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.832205045
Short name T807
Test name
Test status
Simulation time 1133136921 ps
CPU time 10.05 seconds
Started Jul 17 05:44:18 PM PDT 24
Finished Jul 17 05:44:29 PM PDT 24
Peak memory 213708 kb
Host smart-4693b63d-7ff8-42f9-a6ee-8b55c14be35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832205045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.832205045
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.533730801
Short name T1277
Test name
Test status
Simulation time 931487011 ps
CPU time 4.99 seconds
Started Jul 17 05:44:21 PM PDT 24
Finished Jul 17 05:44:27 PM PDT 24
Peak memory 213904 kb
Host smart-cb35d1a5-cbc8-46bb-a85c-753c39bea8d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533730801 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.533730801
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.597477814
Short name T1706
Test name
Test status
Simulation time 415010474 ps
CPU time 1.37 seconds
Started Jul 17 05:47:20 PM PDT 24
Finished Jul 17 05:47:22 PM PDT 24
Peak memory 205604 kb
Host smart-defa554d-3087-4f44-b9c6-cc67764a9980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597477814 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.597477814
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.4005705670
Short name T1721
Test name
Test status
Simulation time 329388490 ps
CPU time 1.22 seconds
Started Jul 17 05:44:14 PM PDT 24
Finished Jul 17 05:44:16 PM PDT 24
Peak memory 205484 kb
Host smart-177c5375-bdb2-4607-b64d-e0d7d4bfca17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005705670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.4005705670
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.2783844991
Short name T652
Test name
Test status
Simulation time 646140736 ps
CPU time 1.26 seconds
Started Jul 17 05:44:15 PM PDT 24
Finished Jul 17 05:44:18 PM PDT 24
Peak memory 205404 kb
Host smart-a8ed7ae8-479e-4c79-a6ad-c52a5e67bc35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783844991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.2783844991
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.3531063429
Short name T1322
Test name
Test status
Simulation time 221785310 ps
CPU time 1.55 seconds
Started Jul 17 05:44:12 PM PDT 24
Finished Jul 17 05:44:14 PM PDT 24
Peak memory 205444 kb
Host smart-fbe73f00-2f9b-4862-ac42-0cd238abce37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531063429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.3531063429
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.4010924515
Short name T980
Test name
Test status
Simulation time 308961153 ps
CPU time 1.4 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:47:42 PM PDT 24
Peak memory 214920 kb
Host smart-11e75f95-3df2-4ed4-8afe-143ee88363fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010924515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.4010924515
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.757367507
Short name T324
Test name
Test status
Simulation time 1480600158 ps
CPU time 4.1 seconds
Started Jul 17 05:44:15 PM PDT 24
Finished Jul 17 05:44:19 PM PDT 24
Peak memory 221704 kb
Host smart-0eb50b74-9660-4101-8fcf-0a3964209343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757367507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.757367507
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2473989256
Short name T325
Test name
Test status
Simulation time 13825060900 ps
CPU time 28.5 seconds
Started Jul 17 05:44:16 PM PDT 24
Finished Jul 17 05:44:46 PM PDT 24
Peak memory 868972 kb
Host smart-6a41d2a4-86e2-44b1-8edc-4e0c07e84132
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473989256 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2473989256
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.1447676062
Short name T1485
Test name
Test status
Simulation time 536085388 ps
CPU time 2.84 seconds
Started Jul 17 05:44:21 PM PDT 24
Finished Jul 17 05:44:25 PM PDT 24
Peak memory 213832 kb
Host smart-d22f8768-6f7c-41ae-9216-3e5c962f804d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447676062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_nack_acqfull.1447676062
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.1800454677
Short name T857
Test name
Test status
Simulation time 506135461 ps
CPU time 2.45 seconds
Started Jul 17 05:44:21 PM PDT 24
Finished Jul 17 05:44:24 PM PDT 24
Peak memory 205628 kb
Host smart-94095b9b-5608-4250-85fe-cd5bab43e500
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800454677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.1800454677
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_txstretch.2579821557
Short name T163
Test name
Test status
Simulation time 2781220869 ps
CPU time 1.38 seconds
Started Jul 17 05:44:16 PM PDT 24
Finished Jul 17 05:44:19 PM PDT 24
Peak memory 222592 kb
Host smart-0d93c5a6-34a7-481c-9b2b-a0579a809d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579821557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_nack_txstretch.2579821557
Directory /workspace/20.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/20.i2c_target_perf.486867322
Short name T891
Test name
Test status
Simulation time 473874998 ps
CPU time 3.46 seconds
Started Jul 17 05:44:15 PM PDT 24
Finished Jul 17 05:44:20 PM PDT 24
Peak memory 213840 kb
Host smart-362a8e53-da7a-4e6d-b735-342579901e93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486867322 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_perf.486867322
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.2937443638
Short name T1343
Test name
Test status
Simulation time 556326682 ps
CPU time 2.48 seconds
Started Jul 17 05:44:18 PM PDT 24
Finished Jul 17 05:44:22 PM PDT 24
Peak memory 205400 kb
Host smart-0dfa772f-8cbc-4e2f-b843-5bb84ab50798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937443638 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_smbus_maxlen.2937443638
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1114307937
Short name T124
Test name
Test status
Simulation time 1681275198 ps
CPU time 12.92 seconds
Started Jul 17 05:44:15 PM PDT 24
Finished Jul 17 05:44:30 PM PDT 24
Peak memory 213828 kb
Host smart-502bd8f3-b752-40ca-93a9-8393174ce591
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114307937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1114307937
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2759335310
Short name T343
Test name
Test status
Simulation time 4597974486 ps
CPU time 40.92 seconds
Started Jul 17 05:44:18 PM PDT 24
Finished Jul 17 05:45:00 PM PDT 24
Peak memory 213980 kb
Host smart-4d6c8f6b-3117-4cea-9deb-5f7fb6006661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759335310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2759335310
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.1497543967
Short name T633
Test name
Test status
Simulation time 50671685110 ps
CPU time 1202.11 seconds
Started Jul 17 05:44:25 PM PDT 24
Finished Jul 17 06:04:28 PM PDT 24
Peak memory 7545372 kb
Host smart-52a0dac4-9b92-43b1-828a-43f1a1a79624
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497543967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.1497543967
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.1871913567
Short name T1266
Test name
Test status
Simulation time 2804502489 ps
CPU time 25 seconds
Started Jul 17 05:44:14 PM PDT 24
Finished Jul 17 05:44:40 PM PDT 24
Peak memory 553936 kb
Host smart-ba70c7e6-6888-4a70-bc19-4fb6431e4a1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871913567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.1871913567
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2468088684
Short name T1579
Test name
Test status
Simulation time 4813816097 ps
CPU time 6.74 seconds
Started Jul 17 05:47:17 PM PDT 24
Finished Jul 17 05:47:25 PM PDT 24
Peak memory 222036 kb
Host smart-d28095f4-676d-4a1c-a4ef-4deacc0f35d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468088684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2468088684
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.2587612759
Short name T646
Test name
Test status
Simulation time 129338142 ps
CPU time 2.72 seconds
Started Jul 17 05:44:15 PM PDT 24
Finished Jul 17 05:44:20 PM PDT 24
Peak memory 205612 kb
Host smart-16b3c557-b6ac-4cce-b50d-c8bc1869c216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587612759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.2587612759
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2224404698
Short name T847
Test name
Test status
Simulation time 36030397 ps
CPU time 0.6 seconds
Started Jul 17 05:46:42 PM PDT 24
Finished Jul 17 05:46:44 PM PDT 24
Peak memory 204812 kb
Host smart-49668b5a-4c9f-4d42-8ef2-dcc9cf24612a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224404698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2224404698
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2854906675
Short name T1612
Test name
Test status
Simulation time 344000892 ps
CPU time 6.35 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:46:30 PM PDT 24
Peak memory 280540 kb
Host smart-e8a8af5f-5acc-4a57-9686-70d8285f2ef4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854906675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2854906675
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1108617504
Short name T477
Test name
Test status
Simulation time 3570008511 ps
CPU time 77.1 seconds
Started Jul 17 05:44:30 PM PDT 24
Finished Jul 17 05:45:48 PM PDT 24
Peak memory 528100 kb
Host smart-d6b04090-74be-4705-8c89-d21f21d24bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108617504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1108617504
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2723170105
Short name T1151
Test name
Test status
Simulation time 10616621882 ps
CPU time 97.59 seconds
Started Jul 17 05:44:18 PM PDT 24
Finished Jul 17 05:45:57 PM PDT 24
Peak memory 870844 kb
Host smart-63140b96-3c3b-4f5c-8edb-6bc1962f9745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723170105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2723170105
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2601349055
Short name T1286
Test name
Test status
Simulation time 1386732780 ps
CPU time 1.09 seconds
Started Jul 17 05:44:31 PM PDT 24
Finished Jul 17 05:44:33 PM PDT 24
Peak memory 205404 kb
Host smart-1e546c54-4f05-4dc0-810b-a492df09d4e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601349055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2601349055
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2669197402
Short name T1694
Test name
Test status
Simulation time 8077028674 ps
CPU time 282.88 seconds
Started Jul 17 05:44:17 PM PDT 24
Finished Jul 17 05:49:01 PM PDT 24
Peak memory 1163352 kb
Host smart-a0937fe1-f14a-4866-9559-c1138fac11b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669197402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2669197402
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3664199086
Short name T1174
Test name
Test status
Simulation time 390088880 ps
CPU time 6.24 seconds
Started Jul 17 05:45:31 PM PDT 24
Finished Jul 17 05:45:38 PM PDT 24
Peak memory 205420 kb
Host smart-a5fbe3a8-15f4-4613-b928-b602db5d26ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664199086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3664199086
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.3746116080
Short name T1426
Test name
Test status
Simulation time 36244647 ps
CPU time 0.75 seconds
Started Jul 17 05:47:47 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 204976 kb
Host smart-d4e1065f-8096-4084-9ddf-9c8196546274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746116080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3746116080
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2207002602
Short name T1507
Test name
Test status
Simulation time 51868939883 ps
CPU time 3044.84 seconds
Started Jul 17 05:46:25 PM PDT 24
Finished Jul 17 06:37:11 PM PDT 24
Peak memory 4423444 kb
Host smart-dcbbc12d-4a4d-437a-9a4d-40607ff433f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207002602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2207002602
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.228933141
Short name T1299
Test name
Test status
Simulation time 235800129 ps
CPU time 10.27 seconds
Started Jul 17 05:44:31 PM PDT 24
Finished Jul 17 05:44:42 PM PDT 24
Peak memory 221620 kb
Host smart-4963e55f-8211-459d-a31c-068986e111c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228933141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.228933141
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3847237987
Short name T740
Test name
Test status
Simulation time 10324440338 ps
CPU time 23.04 seconds
Started Jul 17 05:44:15 PM PDT 24
Finished Jul 17 05:44:38 PM PDT 24
Peak memory 297952 kb
Host smart-56674d95-bed1-462a-a22b-113b1a64fd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847237987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3847237987
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1946355672
Short name T855
Test name
Test status
Simulation time 82891933157 ps
CPU time 2883.35 seconds
Started Jul 17 05:44:28 PM PDT 24
Finished Jul 17 06:32:33 PM PDT 24
Peak memory 5005824 kb
Host smart-f861537d-82bc-4dd1-9285-4eb5843deda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946355672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1946355672
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2275059138
Short name T1082
Test name
Test status
Simulation time 764359905 ps
CPU time 14.55 seconds
Started Jul 17 05:44:30 PM PDT 24
Finished Jul 17 05:44:45 PM PDT 24
Peak memory 221340 kb
Host smart-25f3ca77-d388-4b07-b7cc-40ebd1d282aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275059138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2275059138
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.227717820
Short name T1605
Test name
Test status
Simulation time 2801324270 ps
CPU time 5.73 seconds
Started Jul 17 05:46:25 PM PDT 24
Finished Jul 17 05:46:32 PM PDT 24
Peak memory 222136 kb
Host smart-8a3a7975-7405-42f6-8d5c-7675dae7b8f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227717820 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.227717820
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.94135750
Short name T1236
Test name
Test status
Simulation time 559848298 ps
CPU time 1.13 seconds
Started Jul 17 05:44:29 PM PDT 24
Finished Jul 17 05:44:31 PM PDT 24
Peak memory 205392 kb
Host smart-8be7dd15-933e-4816-a246-4fff2076b833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94135750 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_acq.94135750
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3291145487
Short name T100
Test name
Test status
Simulation time 579709580 ps
CPU time 1.24 seconds
Started Jul 17 05:44:28 PM PDT 24
Finished Jul 17 05:44:30 PM PDT 24
Peak memory 205464 kb
Host smart-c6994174-f266-418d-adee-1ec8482ed72c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291145487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3291145487
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.3633536192
Short name T269
Test name
Test status
Simulation time 759981544 ps
CPU time 2.35 seconds
Started Jul 17 05:44:29 PM PDT 24
Finished Jul 17 05:44:32 PM PDT 24
Peak memory 205624 kb
Host smart-6957b03f-35b0-4706-a3dc-ce7be961f2bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633536192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.3633536192
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2597184006
Short name T1196
Test name
Test status
Simulation time 2840889742 ps
CPU time 5.98 seconds
Started Jul 17 05:44:28 PM PDT 24
Finished Jul 17 05:44:35 PM PDT 24
Peak memory 222068 kb
Host smart-75ff9c45-42c5-4c14-abf4-213eee894639
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597184006 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2597184006
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1937064597
Short name T992
Test name
Test status
Simulation time 3937259626 ps
CPU time 9.18 seconds
Started Jul 17 05:44:30 PM PDT 24
Finished Jul 17 05:44:40 PM PDT 24
Peak memory 205768 kb
Host smart-f8e3cb57-4b46-4c43-bef4-adba0125082f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937064597 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1937064597
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.3336265089
Short name T1556
Test name
Test status
Simulation time 2082120760 ps
CPU time 3.09 seconds
Started Jul 17 05:44:32 PM PDT 24
Finished Jul 17 05:44:36 PM PDT 24
Peak memory 213772 kb
Host smart-01eb8139-6db2-4bb1-aef3-8df8f61ddd7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336265089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_acqfull.3336265089
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.3797664090
Short name T1561
Test name
Test status
Simulation time 544047221 ps
CPU time 2.52 seconds
Started Jul 17 05:44:30 PM PDT 24
Finished Jul 17 05:44:34 PM PDT 24
Peak memory 205612 kb
Host smart-40553fa8-ebcb-41ae-9daa-5073ca32a6c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797664090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.3797664090
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_txstretch.998074935
Short name T1319
Test name
Test status
Simulation time 277444248 ps
CPU time 1.55 seconds
Started Jul 17 05:44:28 PM PDT 24
Finished Jul 17 05:44:30 PM PDT 24
Peak memory 222272 kb
Host smart-838efc6c-8ecc-4dd5-803e-b44e27f5bbee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998074935 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_nack_txstretch.998074935
Directory /workspace/21.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/21.i2c_target_perf.3001708942
Short name T1693
Test name
Test status
Simulation time 2074391279 ps
CPU time 3.33 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 213724 kb
Host smart-5a46b70c-896c-4757-95f9-41dcbbbae939
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001708942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.3001708942
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.2433712008
Short name T1081
Test name
Test status
Simulation time 2411146250 ps
CPU time 2.56 seconds
Started Jul 17 05:44:33 PM PDT 24
Finished Jul 17 05:44:37 PM PDT 24
Peak memory 205504 kb
Host smart-50a969a4-9608-49b8-8929-5d48d8a432b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433712008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_smbus_maxlen.2433712008
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.2416430415
Short name T1636
Test name
Test status
Simulation time 808751758 ps
CPU time 25.89 seconds
Started Jul 17 05:44:28 PM PDT 24
Finished Jul 17 05:44:55 PM PDT 24
Peak memory 213824 kb
Host smart-3549f2c1-db01-4249-a85a-3738030aaea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416430415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.2416430415
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.3324866879
Short name T358
Test name
Test status
Simulation time 34399225683 ps
CPU time 177.92 seconds
Started Jul 17 05:47:12 PM PDT 24
Finished Jul 17 05:50:12 PM PDT 24
Peak memory 1083236 kb
Host smart-c5dffa5c-7756-4e2d-8ec3-ec782c399898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324866879 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_stress_all.3324866879
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1135591709
Short name T1374
Test name
Test status
Simulation time 1630182208 ps
CPU time 38.09 seconds
Started Jul 17 05:44:30 PM PDT 24
Finished Jul 17 05:45:09 PM PDT 24
Peak memory 213888 kb
Host smart-303a1520-ff14-4942-9a64-64e6c93724b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135591709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1135591709
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.2679132140
Short name T1522
Test name
Test status
Simulation time 57374217396 ps
CPU time 390.58 seconds
Started Jul 17 05:44:31 PM PDT 24
Finished Jul 17 05:51:03 PM PDT 24
Peak memory 3400536 kb
Host smart-ce013d8a-41de-4dd4-bf14-403929826b0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679132140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.2679132140
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.4098097942
Short name T1048
Test name
Test status
Simulation time 2187618060 ps
CPU time 45.93 seconds
Started Jul 17 05:46:43 PM PDT 24
Finished Jul 17 05:47:30 PM PDT 24
Peak memory 430160 kb
Host smart-97e602e7-0ff6-4c61-9f2c-bdab75c6aec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098097942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.4098097942
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3053989395
Short name T728
Test name
Test status
Simulation time 4422884026 ps
CPU time 6.75 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:53 PM PDT 24
Peak memory 219532 kb
Host smart-8a523fbb-50a3-4b54-9a95-096b35fe3929
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053989395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3053989395
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.3061475374
Short name T1093
Test name
Test status
Simulation time 113563337 ps
CPU time 2.6 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:47 PM PDT 24
Peak memory 205608 kb
Host smart-83f751ca-de69-4bc6-9153-9a74e8392d79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061475374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.3061475374
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2517501042
Short name T1563
Test name
Test status
Simulation time 40708566 ps
CPU time 0.62 seconds
Started Jul 17 05:44:45 PM PDT 24
Finished Jul 17 05:44:46 PM PDT 24
Peak memory 204712 kb
Host smart-63ba89d5-01bd-40cc-ba36-09f3cd730ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517501042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2517501042
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2800218382
Short name T508
Test name
Test status
Simulation time 110371878 ps
CPU time 3.31 seconds
Started Jul 17 05:44:43 PM PDT 24
Finished Jul 17 05:44:47 PM PDT 24
Peak memory 213740 kb
Host smart-11954de4-7ad5-4187-a324-ae21828cd260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800218382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2800218382
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.9747843
Short name T848
Test name
Test status
Simulation time 443207787 ps
CPU time 9.77 seconds
Started Jul 17 05:44:40 PM PDT 24
Finished Jul 17 05:44:51 PM PDT 24
Peak memory 303400 kb
Host smart-e96331f3-4d2e-42eb-9500-649038436816
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9747843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.9747843
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3202565537
Short name T464
Test name
Test status
Simulation time 2646415345 ps
CPU time 59.22 seconds
Started Jul 17 05:44:39 PM PDT 24
Finished Jul 17 05:45:41 PM PDT 24
Peak memory 424488 kb
Host smart-025aef1c-dc2c-476b-a7ac-0d2e9a40743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202565537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3202565537
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.210233699
Short name T1145
Test name
Test status
Simulation time 8843879442 ps
CPU time 108.15 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:49:36 PM PDT 24
Peak memory 578980 kb
Host smart-b128fc8d-5df4-44d4-aa20-e287aadfb80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210233699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.210233699
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3431543227
Short name T1610
Test name
Test status
Simulation time 85653108 ps
CPU time 0.91 seconds
Started Jul 17 05:47:12 PM PDT 24
Finished Jul 17 05:47:14 PM PDT 24
Peak memory 204956 kb
Host smart-aec5d070-1624-4338-87b7-ba98c14cc4f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431543227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3431543227
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2302042971
Short name T1430
Test name
Test status
Simulation time 147284071 ps
CPU time 6.96 seconds
Started Jul 17 05:44:38 PM PDT 24
Finished Jul 17 05:44:47 PM PDT 24
Peak memory 226288 kb
Host smart-a3b5453c-05a8-4f72-9e48-1888fb76980e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302042971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2302042971
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.684260269
Short name T584
Test name
Test status
Simulation time 4214130480 ps
CPU time 295.04 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:51:46 PM PDT 24
Peak memory 1212696 kb
Host smart-c7343ae1-0e72-424a-a990-d2264c369474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684260269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.684260269
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.71569219
Short name T1250
Test name
Test status
Simulation time 4157535127 ps
CPU time 12.43 seconds
Started Jul 17 05:47:48 PM PDT 24
Finished Jul 17 05:48:06 PM PDT 24
Peak memory 205616 kb
Host smart-0fbc4d81-f25a-4a6a-95a1-a674977c75de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71569219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.71569219
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3707667270
Short name T732
Test name
Test status
Simulation time 947652759 ps
CPU time 2.19 seconds
Started Jul 17 05:44:39 PM PDT 24
Finished Jul 17 05:44:43 PM PDT 24
Peak memory 221712 kb
Host smart-fdfcd835-47a1-4029-90ac-a852d704011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707667270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3707667270
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.3396492283
Short name T518
Test name
Test status
Simulation time 708543333 ps
CPU time 8.68 seconds
Started Jul 17 05:44:39 PM PDT 24
Finished Jul 17 05:44:49 PM PDT 24
Peak memory 238668 kb
Host smart-7c694992-5270-4d11-a4fb-4680248956ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396492283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3396492283
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1750645403
Short name T548
Test name
Test status
Simulation time 3194589654 ps
CPU time 74.14 seconds
Started Jul 17 05:44:30 PM PDT 24
Finished Jul 17 05:45:45 PM PDT 24
Peak memory 334880 kb
Host smart-6574d532-f772-40d7-8abf-785a2aaa7940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750645403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1750645403
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3757029180
Short name T367
Test name
Test status
Simulation time 890364003 ps
CPU time 17.22 seconds
Started Jul 17 05:44:40 PM PDT 24
Finished Jul 17 05:44:59 PM PDT 24
Peak memory 218496 kb
Host smart-cc549843-f743-4fa4-814c-2f3c313c0df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757029180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3757029180
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1292703057
Short name T465
Test name
Test status
Simulation time 16493102902 ps
CPU time 6.32 seconds
Started Jul 17 05:44:39 PM PDT 24
Finished Jul 17 05:44:47 PM PDT 24
Peak memory 217512 kb
Host smart-e4976602-e30f-4a36-be00-a22cebb23fe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292703057 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1292703057
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1905870861
Short name T624
Test name
Test status
Simulation time 200693293 ps
CPU time 0.92 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 205432 kb
Host smart-bcb1cdf8-9054-4608-9f81-e13bb47f9bae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905870861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1905870861
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.138811438
Short name T607
Test name
Test status
Simulation time 204964138 ps
CPU time 0.87 seconds
Started Jul 17 05:44:40 PM PDT 24
Finished Jul 17 05:44:42 PM PDT 24
Peak memory 205468 kb
Host smart-690916b6-9d31-4d82-8cee-32ad9e81efc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138811438 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.138811438
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1862634757
Short name T1686
Test name
Test status
Simulation time 1256860012 ps
CPU time 2.01 seconds
Started Jul 17 05:46:41 PM PDT 24
Finished Jul 17 05:46:43 PM PDT 24
Peak memory 205420 kb
Host smart-d04aa36a-ce0e-4f0a-b206-8ea05641f717
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862634757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1862634757
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.2865576541
Short name T1208
Test name
Test status
Simulation time 1389428980 ps
CPU time 1.67 seconds
Started Jul 17 05:46:05 PM PDT 24
Finished Jul 17 05:46:08 PM PDT 24
Peak memory 205472 kb
Host smart-a926911e-06ff-44a9-8b77-8165ac6afb8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865576541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.2865576541
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.1313526333
Short name T1463
Test name
Test status
Simulation time 297437976 ps
CPU time 2.29 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:48 PM PDT 24
Peak memory 214308 kb
Host smart-50a98c03-54e1-4d03-8b31-3a4c2827ac30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313526333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.1313526333
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1383675653
Short name T1500
Test name
Test status
Simulation time 526955145 ps
CPU time 3.07 seconds
Started Jul 17 05:44:40 PM PDT 24
Finished Jul 17 05:44:45 PM PDT 24
Peak memory 213884 kb
Host smart-3969d1e4-03bb-4eae-b21b-9acbdc008a17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383675653 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1383675653
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2927821734
Short name T737
Test name
Test status
Simulation time 23579956937 ps
CPU time 219.4 seconds
Started Jul 17 05:44:45 PM PDT 24
Finished Jul 17 05:48:25 PM PDT 24
Peak memory 2861524 kb
Host smart-c10ed1e7-99a0-428b-857e-b9ec61208e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927821734 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2927821734
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.3455951163
Short name T932
Test name
Test status
Simulation time 584773047 ps
CPU time 2.79 seconds
Started Jul 17 05:44:41 PM PDT 24
Finished Jul 17 05:44:45 PM PDT 24
Peak memory 213848 kb
Host smart-914a22bb-8756-4a2c-96d5-948c69896b33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455951163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.3455951163
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.694998425
Short name T476
Test name
Test status
Simulation time 535731233 ps
CPU time 2.53 seconds
Started Jul 17 05:44:42 PM PDT 24
Finished Jul 17 05:44:45 PM PDT 24
Peak memory 206172 kb
Host smart-48187a4a-f364-49e6-817e-546a26c7a9c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694998425 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.694998425
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_txstretch.2278334124
Short name T1695
Test name
Test status
Simulation time 581230459 ps
CPU time 1.35 seconds
Started Jul 17 05:44:38 PM PDT 24
Finished Jul 17 05:44:41 PM PDT 24
Peak memory 222164 kb
Host smart-fc1ccb9b-b8e4-4d89-a352-7a5dd0342386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278334124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_nack_txstretch.2278334124
Directory /workspace/22.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/22.i2c_target_perf.4110240653
Short name T880
Test name
Test status
Simulation time 767816986 ps
CPU time 5.07 seconds
Started Jul 17 05:44:39 PM PDT 24
Finished Jul 17 05:44:46 PM PDT 24
Peak memory 214124 kb
Host smart-859218e8-a58a-4680-8d9e-24fd610d3b4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110240653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.4110240653
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.1822689217
Short name T926
Test name
Test status
Simulation time 2323990989 ps
CPU time 2.34 seconds
Started Jul 17 05:44:41 PM PDT 24
Finished Jul 17 05:44:45 PM PDT 24
Peak memory 205472 kb
Host smart-489e008d-1efd-4e56-8e0f-07272a524167
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822689217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_smbus_maxlen.1822689217
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.2149699810
Short name T946
Test name
Test status
Simulation time 2339544440 ps
CPU time 16.48 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:48:03 PM PDT 24
Peak memory 213872 kb
Host smart-b9ca66c8-931d-4d62-9936-904dc7eb7447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149699810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.2149699810
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.2653199371
Short name T270
Test name
Test status
Simulation time 23345541964 ps
CPU time 729.46 seconds
Started Jul 17 05:44:43 PM PDT 24
Finished Jul 17 05:56:53 PM PDT 24
Peak memory 3771804 kb
Host smart-25b2847f-9267-4455-8541-5944627f8d28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653199371 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.2653199371
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1588249680
Short name T1282
Test name
Test status
Simulation time 3230505422 ps
CPU time 24.94 seconds
Started Jul 17 05:44:39 PM PDT 24
Finished Jul 17 05:45:06 PM PDT 24
Peak memory 238348 kb
Host smart-cc17f40a-ea16-4df8-b509-46942a6094b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588249680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1588249680
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.284744665
Short name T381
Test name
Test status
Simulation time 63527939357 ps
CPU time 540.84 seconds
Started Jul 17 05:44:38 PM PDT 24
Finished Jul 17 05:53:40 PM PDT 24
Peak memory 3820676 kb
Host smart-58999e7e-5848-4390-b6f9-42cbe9a1aafc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284744665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.284744665
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1698755127
Short name T1395
Test name
Test status
Simulation time 3075936177 ps
CPU time 147.09 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:50:14 PM PDT 24
Peak memory 819360 kb
Host smart-2b93c573-5afb-4fb9-ad26-99ed6fe89856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698755127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1698755127
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2543220154
Short name T1708
Test name
Test status
Simulation time 2154334747 ps
CPU time 6.08 seconds
Started Jul 17 05:44:41 PM PDT 24
Finished Jul 17 05:44:49 PM PDT 24
Peak memory 222092 kb
Host smart-82d1e3eb-59bd-4b8a-b13a-b89e23a40746
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543220154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2543220154
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.1021017794
Short name T319
Test name
Test status
Simulation time 520786846 ps
CPU time 6.73 seconds
Started Jul 17 05:44:41 PM PDT 24
Finished Jul 17 05:44:49 PM PDT 24
Peak memory 205592 kb
Host smart-c7e87c33-9a5c-4b36-bca0-18e916dee659
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021017794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1021017794
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.283604386
Short name T517
Test name
Test status
Simulation time 24575553 ps
CPU time 0.61 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:47:42 PM PDT 24
Peak memory 204724 kb
Host smart-51b21dcd-1bc0-47f3-9c8c-672cf19dce1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283604386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.283604386
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.3798103293
Short name T1187
Test name
Test status
Simulation time 566446309 ps
CPU time 7.15 seconds
Started Jul 17 05:44:57 PM PDT 24
Finished Jul 17 05:45:05 PM PDT 24
Peak memory 284012 kb
Host smart-b43720cb-3b33-4f95-8739-215b31fc2536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798103293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3798103293
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3955621090
Short name T1418
Test name
Test status
Simulation time 233003145 ps
CPU time 10.71 seconds
Started Jul 17 05:44:50 PM PDT 24
Finished Jul 17 05:45:01 PM PDT 24
Peak memory 232928 kb
Host smart-fbc5650a-c088-4c73-a48c-7dbd74e92dbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955621090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3955621090
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2508310894
Short name T153
Test name
Test status
Simulation time 12984270434 ps
CPU time 67.02 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:48:55 PM PDT 24
Peak memory 289296 kb
Host smart-21ef8395-3b4d-4319-a15c-0e569e214a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508310894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2508310894
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1065495289
Short name T747
Test name
Test status
Simulation time 5211205631 ps
CPU time 200.58 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:51:05 PM PDT 24
Peak memory 831812 kb
Host smart-b908d14c-f3b9-4f56-8bd9-b0714a6b77e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065495289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1065495289
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3205239275
Short name T1097
Test name
Test status
Simulation time 82307432 ps
CPU time 0.99 seconds
Started Jul 17 05:47:48 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 205224 kb
Host smart-aab7ce05-70e8-43d9-8c11-00fa1804681e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205239275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3205239275
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1949665658
Short name T591
Test name
Test status
Simulation time 706496822 ps
CPU time 3.93 seconds
Started Jul 17 05:46:13 PM PDT 24
Finished Jul 17 05:46:17 PM PDT 24
Peak memory 232860 kb
Host smart-ece37612-21fe-44d4-849d-92338fef5857
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949665658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1949665658
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2337795847
Short name T632
Test name
Test status
Simulation time 16691465641 ps
CPU time 335.31 seconds
Started Jul 17 05:44:52 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 1299680 kb
Host smart-d1bdae15-39cb-48e5-a2ab-b0c294b0a419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337795847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2337795847
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.988571725
Short name T257
Test name
Test status
Simulation time 1542570443 ps
CPU time 31.27 seconds
Started Jul 17 05:44:49 PM PDT 24
Finished Jul 17 05:45:21 PM PDT 24
Peak memory 205528 kb
Host smart-1ce7c788-532f-4b8f-bdbd-99f20d306b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988571725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.988571725
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.496380714
Short name T135
Test name
Test status
Simulation time 21252570 ps
CPU time 0.67 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:49 PM PDT 24
Peak memory 205204 kb
Host smart-1d63d120-b7f9-469c-8a21-ffad2ac36be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496380714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.496380714
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1592898724
Short name T573
Test name
Test status
Simulation time 2581079230 ps
CPU time 26.66 seconds
Started Jul 17 05:46:25 PM PDT 24
Finished Jul 17 05:46:53 PM PDT 24
Peak memory 227628 kb
Host smart-9bf20114-10a7-4b3f-be99-f002deaab96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592898724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1592898724
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.2895335774
Short name T1592
Test name
Test status
Simulation time 497546552 ps
CPU time 19.93 seconds
Started Jul 17 05:44:57 PM PDT 24
Finished Jul 17 05:45:18 PM PDT 24
Peak memory 205364 kb
Host smart-b2272055-8d3f-4ab5-a202-29a60233d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895335774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.2895335774
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1356668682
Short name T1056
Test name
Test status
Simulation time 7722827503 ps
CPU time 87.26 seconds
Started Jul 17 05:44:51 PM PDT 24
Finished Jul 17 05:46:19 PM PDT 24
Peak memory 428096 kb
Host smart-6c3e721e-ea5f-4dca-9871-d1814a4c0e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356668682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1356668682
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3102458669
Short name T340
Test name
Test status
Simulation time 3181696186 ps
CPU time 18.23 seconds
Started Jul 17 05:44:50 PM PDT 24
Finished Jul 17 05:45:09 PM PDT 24
Peak memory 221864 kb
Host smart-c7ce0246-08df-47f0-8b29-07960959f1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102458669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3102458669
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1837897313
Short name T1275
Test name
Test status
Simulation time 900576151 ps
CPU time 4.43 seconds
Started Jul 17 05:44:51 PM PDT 24
Finished Jul 17 05:44:56 PM PDT 24
Peak memory 213836 kb
Host smart-f93e814e-e4c0-437f-a7e2-c97bde78ca1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837897313 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1837897313
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.1995626586
Short name T322
Test name
Test status
Simulation time 219893364 ps
CPU time 0.81 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:50 PM PDT 24
Peak memory 205396 kb
Host smart-30ddd52d-9471-40f5-b479-d7afb2efd0b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995626586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.1995626586
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.2847665586
Short name T466
Test name
Test status
Simulation time 396444027 ps
CPU time 1.59 seconds
Started Jul 17 05:47:21 PM PDT 24
Finished Jul 17 05:47:24 PM PDT 24
Peak memory 210424 kb
Host smart-d2e20cad-bae4-45a4-9e6a-547993af5c68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847665586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.2847665586
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.1028681588
Short name T1663
Test name
Test status
Simulation time 875519917 ps
CPU time 1.52 seconds
Started Jul 17 05:44:50 PM PDT 24
Finished Jul 17 05:44:52 PM PDT 24
Peak memory 205448 kb
Host smart-44879c9b-a740-4409-9167-2efb90f62ddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028681588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.1028681588
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.1189900629
Short name T675
Test name
Test status
Simulation time 104327759 ps
CPU time 1.23 seconds
Started Jul 17 05:44:51 PM PDT 24
Finished Jul 17 05:44:53 PM PDT 24
Peak memory 205412 kb
Host smart-6f60a3ee-16e8-4e17-863f-52eba3e58bd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189900629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.1189900629
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.907438429
Short name T453
Test name
Test status
Simulation time 1213365531 ps
CPU time 7.21 seconds
Started Jul 17 05:44:51 PM PDT 24
Finished Jul 17 05:44:59 PM PDT 24
Peak memory 220148 kb
Host smart-9780f2df-1bba-449f-b98d-e314fc796684
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907438429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.907438429
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.671546307
Short name T308
Test name
Test status
Simulation time 2985598850 ps
CPU time 4.09 seconds
Started Jul 17 05:44:57 PM PDT 24
Finished Jul 17 05:45:02 PM PDT 24
Peak memory 205696 kb
Host smart-e86cde98-e331-4836-b1f5-45f29de1d0d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671546307 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.671546307
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.3441426402
Short name T1569
Test name
Test status
Simulation time 4337778643 ps
CPU time 2.99 seconds
Started Jul 17 05:47:48 PM PDT 24
Finished Jul 17 05:47:56 PM PDT 24
Peak memory 213888 kb
Host smart-de1cce2c-2b74-4220-9149-5173f37f9189
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441426402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_nack_acqfull.3441426402
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.1014242199
Short name T1034
Test name
Test status
Simulation time 3193653418 ps
CPU time 2.5 seconds
Started Jul 17 05:46:42 PM PDT 24
Finished Jul 17 05:46:45 PM PDT 24
Peak memory 205672 kb
Host smart-d2c60eb5-efd3-442c-8c0d-2b0c3bb46e72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014242199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.1014242199
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_txstretch.1097083201
Short name T1137
Test name
Test status
Simulation time 2489836265 ps
CPU time 1.61 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:50 PM PDT 24
Peak memory 222832 kb
Host smart-475e12a7-62bd-4702-878e-3996cda9208e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097083201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_nack_txstretch.1097083201
Directory /workspace/23.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/23.i2c_target_perf.73507261
Short name T326
Test name
Test status
Simulation time 6976692288 ps
CPU time 6.41 seconds
Started Jul 17 05:44:54 PM PDT 24
Finished Jul 17 05:45:01 PM PDT 24
Peak memory 230244 kb
Host smart-7dac37bd-d12c-4eab-812c-b8469989d157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73507261 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.i2c_target_perf.73507261
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.1675688044
Short name T886
Test name
Test status
Simulation time 1070455065 ps
CPU time 2.35 seconds
Started Jul 17 05:44:54 PM PDT 24
Finished Jul 17 05:44:57 PM PDT 24
Peak memory 205368 kb
Host smart-7d3f0da6-3e00-4d28-9c55-a80f0e5c8f83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675688044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_smbus_maxlen.1675688044
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.3654407249
Short name T1680
Test name
Test status
Simulation time 692356486 ps
CPU time 22.61 seconds
Started Jul 17 05:44:51 PM PDT 24
Finished Jul 17 05:45:15 PM PDT 24
Peak memory 213816 kb
Host smart-a73b3c8e-d5cb-43b9-a382-a486bb2e71c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654407249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.3654407249
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.2437989949
Short name T212
Test name
Test status
Simulation time 39050324327 ps
CPU time 928.85 seconds
Started Jul 17 05:47:48 PM PDT 24
Finished Jul 17 06:03:22 PM PDT 24
Peak memory 5739020 kb
Host smart-0bb7ec8b-8cd2-4140-b549-07551c7ba60a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437989949 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.2437989949
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1660259064
Short name T702
Test name
Test status
Simulation time 459364157 ps
CPU time 10.15 seconds
Started Jul 17 05:44:57 PM PDT 24
Finished Jul 17 05:45:07 PM PDT 24
Peak memory 205564 kb
Host smart-6a28dde6-8612-470d-89d4-19a49800f37b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660259064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1660259064
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2715460884
Short name T167
Test name
Test status
Simulation time 15133391583 ps
CPU time 3.93 seconds
Started Jul 17 05:44:50 PM PDT 24
Finished Jul 17 05:44:54 PM PDT 24
Peak memory 205652 kb
Host smart-90a201a4-2e29-4a41-9225-3545deef0e58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715460884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2715460884
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3992440718
Short name T525
Test name
Test status
Simulation time 1838928340 ps
CPU time 30.71 seconds
Started Jul 17 05:44:51 PM PDT 24
Finished Jul 17 05:45:22 PM PDT 24
Peak memory 348580 kb
Host smart-050a93f6-14da-40b9-90f5-01a7f926eead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992440718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3992440718
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3227871917
Short name T188
Test name
Test status
Simulation time 1375245131 ps
CPU time 7.84 seconds
Started Jul 17 05:44:51 PM PDT 24
Finished Jul 17 05:44:59 PM PDT 24
Peak memory 221828 kb
Host smart-f72e4d44-0ddc-4a5f-8452-1b62f15a3d07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227871917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3227871917
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.278650575
Short name T532
Test name
Test status
Simulation time 105225763 ps
CPU time 2.29 seconds
Started Jul 17 05:44:56 PM PDT 24
Finished Jul 17 05:44:59 PM PDT 24
Peak memory 205668 kb
Host smart-c9176507-e878-46b8-b9a4-6f78fa5b4c75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278650575 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.278650575
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.47323912
Short name T504
Test name
Test status
Simulation time 23994368 ps
CPU time 0.62 seconds
Started Jul 17 05:45:22 PM PDT 24
Finished Jul 17 05:45:24 PM PDT 24
Peak memory 204792 kb
Host smart-0a09d9b1-0850-4452-9860-473b786e6893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47323912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.47323912
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2998680984
Short name T27
Test name
Test status
Simulation time 215744360 ps
CPU time 1.81 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:49 PM PDT 24
Peak memory 213748 kb
Host smart-c405898f-734f-4418-a990-a9d91ec1a60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998680984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2998680984
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.196162498
Short name T879
Test name
Test status
Simulation time 1600590838 ps
CPU time 4.07 seconds
Started Jul 17 05:45:04 PM PDT 24
Finished Jul 17 05:45:09 PM PDT 24
Peak memory 232480 kb
Host smart-d9683510-67f6-4d8b-80f3-bce0facddc86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196162498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.196162498
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.3737392351
Short name T556
Test name
Test status
Simulation time 3630719669 ps
CPU time 96.44 seconds
Started Jul 17 05:45:04 PM PDT 24
Finished Jul 17 05:46:41 PM PDT 24
Peak memory 491084 kb
Host smart-2b42a07a-17b7-4e3f-8872-e9364d25347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737392351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.3737392351
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1282569544
Short name T678
Test name
Test status
Simulation time 1318395626 ps
CPU time 41.91 seconds
Started Jul 17 05:45:03 PM PDT 24
Finished Jul 17 05:45:46 PM PDT 24
Peak memory 520812 kb
Host smart-80bbff58-a39c-4170-a795-9e3c354202bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282569544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1282569544
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1487349343
Short name T683
Test name
Test status
Simulation time 808110369 ps
CPU time 0.84 seconds
Started Jul 17 05:45:03 PM PDT 24
Finished Jul 17 05:45:05 PM PDT 24
Peak memory 205188 kb
Host smart-a7516497-806d-4764-b4cd-dc8e27565836
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487349343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1487349343
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3448366303
Short name T984
Test name
Test status
Simulation time 1953512266 ps
CPU time 3.07 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:47:44 PM PDT 24
Peak memory 205468 kb
Host smart-0a134e06-8ac9-4fe3-b05d-5fad9db07ea9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448366303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3448366303
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1590990940
Short name T33
Test name
Test status
Simulation time 18464380089 ps
CPU time 116.49 seconds
Started Jul 17 05:45:04 PM PDT 24
Finished Jul 17 05:47:01 PM PDT 24
Peak memory 1187452 kb
Host smart-ca317935-4f9c-41bf-9832-59be3256c695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590990940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1590990940
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2736570346
Short name T1283
Test name
Test status
Simulation time 3998817334 ps
CPU time 3.73 seconds
Started Jul 17 05:45:22 PM PDT 24
Finished Jul 17 05:45:27 PM PDT 24
Peak memory 205616 kb
Host smart-5c4999c9-a9f0-4fad-ae5b-e40a7be2206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736570346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2736570346
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.2616350291
Short name T514
Test name
Test status
Simulation time 42308748 ps
CPU time 0.66 seconds
Started Jul 17 05:45:06 PM PDT 24
Finished Jul 17 05:45:07 PM PDT 24
Peak memory 205236 kb
Host smart-4a730147-e9be-4c37-b696-2bd88c800e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616350291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2616350291
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3822622935
Short name T1400
Test name
Test status
Simulation time 3345398191 ps
CPU time 19.45 seconds
Started Jul 17 05:45:04 PM PDT 24
Finished Jul 17 05:45:24 PM PDT 24
Peak memory 224048 kb
Host smart-2e257e98-1e38-45c2-90df-7d41bcac3a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822622935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3822622935
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.1355354311
Short name T1058
Test name
Test status
Simulation time 121864327 ps
CPU time 1.75 seconds
Started Jul 17 05:46:22 PM PDT 24
Finished Jul 17 05:46:25 PM PDT 24
Peak memory 214288 kb
Host smart-8d76e3c6-de47-4c29-b697-f3713a5c21cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355354311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.1355354311
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2188629985
Short name T767
Test name
Test status
Simulation time 3525761033 ps
CPU time 34.85 seconds
Started Jul 17 05:45:04 PM PDT 24
Finished Jul 17 05:45:40 PM PDT 24
Peak memory 431740 kb
Host smart-c6676765-75aa-4f24-b3b2-1350666c45cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188629985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2188629985
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.2791381557
Short name T818
Test name
Test status
Simulation time 627530826 ps
CPU time 10.34 seconds
Started Jul 17 05:47:09 PM PDT 24
Finished Jul 17 05:47:21 PM PDT 24
Peak memory 220308 kb
Host smart-bb74e20d-868f-4286-b098-ca80ade958b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791381557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2791381557
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3891280137
Short name T621
Test name
Test status
Simulation time 1000770976 ps
CPU time 4.57 seconds
Started Jul 17 05:45:21 PM PDT 24
Finished Jul 17 05:45:27 PM PDT 24
Peak memory 213940 kb
Host smart-adcf2c39-be4a-4beb-85b8-daf5d9506ec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891280137 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3891280137
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1126029654
Short name T323
Test name
Test status
Simulation time 315691944 ps
CPU time 1.21 seconds
Started Jul 17 05:45:21 PM PDT 24
Finished Jul 17 05:45:23 PM PDT 24
Peak memory 205644 kb
Host smart-a157bd7e-256b-434f-97c3-6b1f4e3501bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126029654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1126029654
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3423905770
Short name T1006
Test name
Test status
Simulation time 787875661 ps
CPU time 1.06 seconds
Started Jul 17 05:45:20 PM PDT 24
Finished Jul 17 05:45:22 PM PDT 24
Peak memory 205588 kb
Host smart-16740ec2-f927-40a9-82df-0a75fc30fcd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423905770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3423905770
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.2297966266
Short name T1146
Test name
Test status
Simulation time 1469980325 ps
CPU time 2.06 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 205420 kb
Host smart-e47b703d-6b88-40a0-a42e-ae8be1755ed9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297966266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.2297966266
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.610740371
Short name T1055
Test name
Test status
Simulation time 309698051 ps
CPU time 1.53 seconds
Started Jul 17 05:45:25 PM PDT 24
Finished Jul 17 05:45:27 PM PDT 24
Peak memory 205452 kb
Host smart-43e891a2-306a-44b0-b094-14b863b6aa2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610740371 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.610740371
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2585565310
Short name T1222
Test name
Test status
Simulation time 4418169510 ps
CPU time 6.85 seconds
Started Jul 17 05:45:03 PM PDT 24
Finished Jul 17 05:45:10 PM PDT 24
Peak memory 222120 kb
Host smart-58a0ded7-bafc-4578-8c8b-6282a9531b58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585565310 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2585565310
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.3185705200
Short name T1326
Test name
Test status
Simulation time 7443411791 ps
CPU time 88.75 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 1948064 kb
Host smart-33212280-87cd-4f84-9386-6b5e5edd5cfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185705200 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.3185705200
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.168795209
Short name T1618
Test name
Test status
Simulation time 6412552697 ps
CPU time 2.8 seconds
Started Jul 17 05:45:22 PM PDT 24
Finished Jul 17 05:45:26 PM PDT 24
Peak memory 213956 kb
Host smart-f2d6611b-f53c-419d-a7d3-56b1e95940ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168795209 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_nack_acqfull.168795209
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.3399958688
Short name T1191
Test name
Test status
Simulation time 522766970 ps
CPU time 2.62 seconds
Started Jul 17 05:45:25 PM PDT 24
Finished Jul 17 05:45:29 PM PDT 24
Peak memory 205732 kb
Host smart-957012b7-dfd1-4622-a178-8682bc7b6427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399958688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.3399958688
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_txstretch.404571326
Short name T1337
Test name
Test status
Simulation time 857267101 ps
CPU time 1.47 seconds
Started Jul 17 05:45:20 PM PDT 24
Finished Jul 17 05:45:23 PM PDT 24
Peak memory 222252 kb
Host smart-e79b75a3-e4ee-481a-b595-3f09456608f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404571326 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_nack_txstretch.404571326
Directory /workspace/24.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/24.i2c_target_perf.948951864
Short name T480
Test name
Test status
Simulation time 1446516270 ps
CPU time 5.18 seconds
Started Jul 17 05:45:22 PM PDT 24
Finished Jul 17 05:45:28 PM PDT 24
Peak memory 213748 kb
Host smart-6cb24eed-d53b-4bf3-b167-f2fd018cb5fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948951864 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_perf.948951864
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.759033866
Short name T1689
Test name
Test status
Simulation time 1793017682 ps
CPU time 2.06 seconds
Started Jul 17 05:45:23 PM PDT 24
Finished Jul 17 05:45:26 PM PDT 24
Peak memory 205432 kb
Host smart-3bf836d3-975d-477f-9822-a55e677d459c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759033866 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_smbus_maxlen.759033866
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.1608697381
Short name T351
Test name
Test status
Simulation time 2462711381 ps
CPU time 9.63 seconds
Started Jul 17 05:45:05 PM PDT 24
Finished Jul 17 05:45:15 PM PDT 24
Peak memory 213840 kb
Host smart-f53e4968-947a-4d1a-a453-df753215f4ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608697381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.1608697381
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.2102886437
Short name T1241
Test name
Test status
Simulation time 33073554595 ps
CPU time 843.05 seconds
Started Jul 17 05:47:21 PM PDT 24
Finished Jul 17 06:01:25 PM PDT 24
Peak memory 3446196 kb
Host smart-927ea858-03cd-4d70-972e-9051dedc371e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102886437 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.2102886437
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.4135610567
Short name T971
Test name
Test status
Simulation time 643737214 ps
CPU time 10.71 seconds
Started Jul 17 05:45:04 PM PDT 24
Finished Jul 17 05:45:16 PM PDT 24
Peak memory 216192 kb
Host smart-cdb2e130-33cc-4814-a54d-da1eee9ca778
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135610567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.4135610567
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1985394889
Short name T1091
Test name
Test status
Simulation time 62055404027 ps
CPU time 284.22 seconds
Started Jul 17 05:45:01 PM PDT 24
Finished Jul 17 05:49:46 PM PDT 24
Peak memory 2646880 kb
Host smart-d61d29db-975b-4d25-b295-204d4a6e95cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985394889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1985394889
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.3381284652
Short name T1607
Test name
Test status
Simulation time 6796403243 ps
CPU time 8.44 seconds
Started Jul 17 05:45:18 PM PDT 24
Finished Jul 17 05:45:28 PM PDT 24
Peak memory 231588 kb
Host smart-d9aecc03-5deb-48ff-80b3-3783d34bf7db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381284652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.3381284652
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.4130292611
Short name T892
Test name
Test status
Simulation time 124333983 ps
CPU time 2.73 seconds
Started Jul 17 05:45:25 PM PDT 24
Finished Jul 17 05:45:29 PM PDT 24
Peak memory 205616 kb
Host smart-fff23bad-c864-4ca7-810e-e7673a3d42af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130292611 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.4130292611
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.4008159667
Short name T352
Test name
Test status
Simulation time 16420895 ps
CPU time 0.66 seconds
Started Jul 17 05:45:30 PM PDT 24
Finished Jul 17 05:45:32 PM PDT 24
Peak memory 204784 kb
Host smart-c102441d-0909-4fd7-83a6-90058155e282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008159667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.4008159667
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3621348352
Short name T1144
Test name
Test status
Simulation time 118387011 ps
CPU time 1.56 seconds
Started Jul 17 05:47:15 PM PDT 24
Finished Jul 17 05:47:19 PM PDT 24
Peak memory 213796 kb
Host smart-240b029b-e200-4721-8fcb-cd46ac1085d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621348352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3621348352
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2290059248
Short name T1172
Test name
Test status
Simulation time 593487792 ps
CPU time 2.69 seconds
Started Jul 17 05:47:23 PM PDT 24
Finished Jul 17 05:47:27 PM PDT 24
Peak memory 224840 kb
Host smart-b19e6c52-e913-493b-9c1b-bda83974dc6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290059248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2290059248
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.612203210
Short name T1003
Test name
Test status
Simulation time 12112197119 ps
CPU time 102.41 seconds
Started Jul 17 05:45:22 PM PDT 24
Finished Jul 17 05:47:06 PM PDT 24
Peak memory 751764 kb
Host smart-f5f48392-4704-42f3-901c-ca6491285f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612203210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.612203210
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2384327397
Short name T1454
Test name
Test status
Simulation time 4462597304 ps
CPU time 176.52 seconds
Started Jul 17 05:47:16 PM PDT 24
Finished Jul 17 05:50:14 PM PDT 24
Peak memory 751964 kb
Host smart-34393b09-728e-471d-9f73-4a207c3eaa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384327397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2384327397
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.114966916
Short name T1061
Test name
Test status
Simulation time 394960744 ps
CPU time 1.04 seconds
Started Jul 17 05:45:21 PM PDT 24
Finished Jul 17 05:45:24 PM PDT 24
Peak memory 205256 kb
Host smart-3320c33a-4fca-431e-9b77-15070dede5e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114966916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fm
t.114966916
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.517602277
Short name T1215
Test name
Test status
Simulation time 565619819 ps
CPU time 3.13 seconds
Started Jul 17 05:45:20 PM PDT 24
Finished Jul 17 05:45:25 PM PDT 24
Peak memory 205704 kb
Host smart-1692551e-c8e8-4692-80a1-a55243627dea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517602277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
517602277
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1863884296
Short name T1492
Test name
Test status
Simulation time 4398405750 ps
CPU time 100.07 seconds
Started Jul 17 05:45:19 PM PDT 24
Finished Jul 17 05:47:00 PM PDT 24
Peak memory 1219820 kb
Host smart-9dc847ec-f922-4aef-9713-da69d4b14489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863884296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1863884296
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1154842021
Short name T1699
Test name
Test status
Simulation time 1258439492 ps
CPU time 4.83 seconds
Started Jul 17 05:45:34 PM PDT 24
Finished Jul 17 05:45:39 PM PDT 24
Peak memory 205516 kb
Host smart-fc18d363-344b-479c-8e24-3400509550ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154842021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1154842021
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_override.3446484986
Short name T7
Test name
Test status
Simulation time 26928898 ps
CPU time 0.68 seconds
Started Jul 17 05:45:22 PM PDT 24
Finished Jul 17 05:45:24 PM PDT 24
Peak memory 205168 kb
Host smart-eb4c7e23-242d-4942-b5d6-19ae9138aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446484986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3446484986
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1292853934
Short name T934
Test name
Test status
Simulation time 76098054269 ps
CPU time 345.13 seconds
Started Jul 17 05:45:22 PM PDT 24
Finished Jul 17 05:51:09 PM PDT 24
Peak memory 205536 kb
Host smart-e84b65e9-3e6a-45a7-83da-b1b0f30b4938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292853934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1292853934
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.704771052
Short name T721
Test name
Test status
Simulation time 2550493757 ps
CPU time 34.48 seconds
Started Jul 17 05:45:19 PM PDT 24
Finished Jul 17 05:45:55 PM PDT 24
Peak memory 206112 kb
Host smart-972ffafb-5638-4977-bf98-cbd70a482276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704771052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.704771052
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2400820736
Short name T662
Test name
Test status
Simulation time 1785476786 ps
CPU time 37.16 seconds
Started Jul 17 05:47:15 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 430052 kb
Host smart-e3a1025a-9b5d-421f-baa4-dbe58610577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400820736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2400820736
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.3078915109
Short name T126
Test name
Test status
Simulation time 20578656317 ps
CPU time 551.3 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:56:57 PM PDT 24
Peak memory 2161908 kb
Host smart-f7c0c2fe-49b3-4b18-9fd8-adce87d01040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078915109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.3078915109
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1364830063
Short name T825
Test name
Test status
Simulation time 2999198150 ps
CPU time 25.95 seconds
Started Jul 17 05:45:22 PM PDT 24
Finished Jul 17 05:45:49 PM PDT 24
Peak memory 213744 kb
Host smart-1a152f0a-6b72-48bf-a09a-d13c07584398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364830063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1364830063
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2240133040
Short name T729
Test name
Test status
Simulation time 1382954505 ps
CPU time 6.4 seconds
Started Jul 17 05:47:46 PM PDT 24
Finished Jul 17 05:47:59 PM PDT 24
Peak memory 213832 kb
Host smart-841dfd33-cf54-4fee-bc0b-2137ae11b74c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240133040 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2240133040
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.4032470044
Short name T438
Test name
Test status
Simulation time 256566688 ps
CPU time 0.82 seconds
Started Jul 17 05:47:46 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 205380 kb
Host smart-6c05eaa8-10de-48a8-858f-3581f03977c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032470044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.4032470044
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3014545472
Short name T1392
Test name
Test status
Simulation time 798799991 ps
CPU time 1.45 seconds
Started Jul 17 05:45:33 PM PDT 24
Finished Jul 17 05:45:35 PM PDT 24
Peak memory 205600 kb
Host smart-4e5a3634-2058-4320-bb83-2bfaf1f4e14f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014545472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3014545472
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.2002546228
Short name T725
Test name
Test status
Simulation time 265676824 ps
CPU time 1.74 seconds
Started Jul 17 05:47:46 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 205424 kb
Host smart-e52b4462-0a38-4f07-b7a7-772934240700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002546228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.2002546228
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.2841062973
Short name T1536
Test name
Test status
Simulation time 126712883 ps
CPU time 1.26 seconds
Started Jul 17 05:45:30 PM PDT 24
Finished Jul 17 05:45:32 PM PDT 24
Peak memory 205472 kb
Host smart-484d95e9-7d7f-4111-a8ca-f72a18910b6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841062973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.2841062973
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2490032972
Short name T90
Test name
Test status
Simulation time 278293891 ps
CPU time 2.15 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:48 PM PDT 24
Peak memory 214232 kb
Host smart-4cea468e-ab3b-4ad0-86e0-c7f4f4b16dc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490032972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2490032972
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.482963742
Short name T806
Test name
Test status
Simulation time 1351204016 ps
CPU time 5.85 seconds
Started Jul 17 05:45:32 PM PDT 24
Finished Jul 17 05:45:39 PM PDT 24
Peak memory 213808 kb
Host smart-6b3b98e6-a93e-4e33-b582-2609d3803d80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482963742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.482963742
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2247377792
Short name T1183
Test name
Test status
Simulation time 16073719741 ps
CPU time 32.78 seconds
Started Jul 17 05:45:34 PM PDT 24
Finished Jul 17 05:46:08 PM PDT 24
Peak memory 924544 kb
Host smart-e9cad658-4e22-4111-9097-e9bea0cdd021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247377792 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2247377792
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.2547732305
Short name T1047
Test name
Test status
Simulation time 727199577 ps
CPU time 2.8 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:47:43 PM PDT 24
Peak memory 213768 kb
Host smart-121f1e03-1808-4bff-b2c9-117fc7df8bfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547732305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.2547732305
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.3211846954
Short name T1044
Test name
Test status
Simulation time 746771476 ps
CPU time 2.39 seconds
Started Jul 17 05:46:41 PM PDT 24
Finished Jul 17 05:46:44 PM PDT 24
Peak memory 205608 kb
Host smart-370b5d3d-3ef4-44f4-b0db-de968bddb236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211846954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.3211846954
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_txstretch.3571550948
Short name T1731
Test name
Test status
Simulation time 257427340 ps
CPU time 1.39 seconds
Started Jul 17 05:45:31 PM PDT 24
Finished Jul 17 05:45:33 PM PDT 24
Peak memory 222336 kb
Host smart-f848d58e-1f86-4907-924e-ad4d05f6087a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571550948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_nack_txstretch.3571550948
Directory /workspace/25.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/25.i2c_target_perf.2152590964
Short name T610
Test name
Test status
Simulation time 998825639 ps
CPU time 7.54 seconds
Started Jul 17 05:45:38 PM PDT 24
Finished Jul 17 05:45:46 PM PDT 24
Peak memory 221020 kb
Host smart-c19bd961-21b5-4f23-8a89-9ef5b2685083
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152590964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.2152590964
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.1051459753
Short name T4
Test name
Test status
Simulation time 460316277 ps
CPU time 2.16 seconds
Started Jul 17 05:45:32 PM PDT 24
Finished Jul 17 05:45:35 PM PDT 24
Peak memory 205412 kb
Host smart-ae4afb44-4357-468d-b144-32d3f370cc98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051459753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_smbus_maxlen.1051459753
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.3245475157
Short name T1271
Test name
Test status
Simulation time 3020615107 ps
CPU time 39.25 seconds
Started Jul 17 05:45:25 PM PDT 24
Finished Jul 17 05:46:05 PM PDT 24
Peak memory 213912 kb
Host smart-d4ec78ad-0e13-4956-ba27-d5df1e02ea6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245475157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.3245475157
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.3302137176
Short name T733
Test name
Test status
Simulation time 49613670236 ps
CPU time 2338.68 seconds
Started Jul 17 05:47:46 PM PDT 24
Finished Jul 17 06:26:52 PM PDT 24
Peak memory 11466520 kb
Host smart-8a653350-f717-4422-a238-760451353226
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302137176 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.3302137176
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1702155175
Short name T1007
Test name
Test status
Simulation time 1573164241 ps
CPU time 7.87 seconds
Started Jul 17 05:47:16 PM PDT 24
Finished Jul 17 05:47:25 PM PDT 24
Peak memory 214972 kb
Host smart-86f46830-82b4-40d1-9fc0-e81929986ad8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702155175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1702155175
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2627362612
Short name T187
Test name
Test status
Simulation time 63489955218 ps
CPU time 869.3 seconds
Started Jul 17 05:45:20 PM PDT 24
Finished Jul 17 05:59:51 PM PDT 24
Peak memory 5683420 kb
Host smart-009d477a-08cb-41d5-94ad-e3d7a3c100e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627362612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2627362612
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1809431251
Short name T1013
Test name
Test status
Simulation time 3033616604 ps
CPU time 31.85 seconds
Started Jul 17 05:45:31 PM PDT 24
Finished Jul 17 05:46:04 PM PDT 24
Peak memory 624052 kb
Host smart-fae2e607-d689-462b-902c-432a57702fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809431251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1809431251
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3700093263
Short name T890
Test name
Test status
Simulation time 1461765814 ps
CPU time 7.17 seconds
Started Jul 17 05:45:38 PM PDT 24
Finished Jul 17 05:45:45 PM PDT 24
Peak memory 219200 kb
Host smart-eaa5cfc8-aa77-4464-a2fe-d4c6d83581d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700093263 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3700093263
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.2534160663
Short name T1511
Test name
Test status
Simulation time 137729633 ps
CPU time 3.13 seconds
Started Jul 17 05:45:34 PM PDT 24
Finished Jul 17 05:45:38 PM PDT 24
Peak memory 205604 kb
Host smart-e0540f55-5d89-40f0-9c74-53e50dc239be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534160663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2534160663
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1996362923
Short name T988
Test name
Test status
Simulation time 22016031 ps
CPU time 0.63 seconds
Started Jul 17 05:45:43 PM PDT 24
Finished Jul 17 05:45:44 PM PDT 24
Peak memory 204704 kb
Host smart-f34108e9-3b4d-4681-a426-a14c5f2fface
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996362923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1996362923
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.178765182
Short name T1069
Test name
Test status
Simulation time 495732082 ps
CPU time 26.37 seconds
Started Jul 17 05:45:37 PM PDT 24
Finished Jul 17 05:46:04 PM PDT 24
Peak memory 295768 kb
Host smart-334ba3cc-79a9-45e0-9b7e-be2692089f84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178765182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.178765182
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.999262607
Short name T519
Test name
Test status
Simulation time 14002024419 ps
CPU time 182.51 seconds
Started Jul 17 05:47:47 PM PDT 24
Finished Jul 17 05:50:55 PM PDT 24
Peak memory 544492 kb
Host smart-7be6f6c1-0442-411b-a3eb-610aa8acb06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999262607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.999262607
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2907553674
Short name T541
Test name
Test status
Simulation time 5439606555 ps
CPU time 89.41 seconds
Started Jul 17 05:45:33 PM PDT 24
Finished Jul 17 05:47:04 PM PDT 24
Peak memory 848904 kb
Host smart-2d7f015d-a30f-4951-9887-5d7d3237d081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907553674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2907553674
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.382011522
Short name T478
Test name
Test status
Simulation time 222482904 ps
CPU time 1.13 seconds
Started Jul 17 05:45:33 PM PDT 24
Finished Jul 17 05:45:35 PM PDT 24
Peak memory 205596 kb
Host smart-3274d2ae-e178-4098-9cd2-8a99d61098c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382011522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.382011522
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.474176772
Short name T189
Test name
Test status
Simulation time 525214698 ps
CPU time 7.41 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:47:47 PM PDT 24
Peak memory 205428 kb
Host smart-feeeffce-10f8-4f72-a4c2-b47189b98898
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474176772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.
474176772
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1059389522
Short name T1205
Test name
Test status
Simulation time 20188964400 ps
CPU time 126.44 seconds
Started Jul 17 05:47:46 PM PDT 24
Finished Jul 17 05:49:59 PM PDT 24
Peak memory 1381988 kb
Host smart-2f262ab5-7f4d-4380-934f-36f5085fa3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059389522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1059389522
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3404944684
Short name T1404
Test name
Test status
Simulation time 256476242 ps
CPU time 3.26 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:54 PM PDT 24
Peak memory 205540 kb
Host smart-11df0b0b-06f2-404a-806a-85d1af29e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404944684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3404944684
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_override.4255246859
Short name T831
Test name
Test status
Simulation time 84050213 ps
CPU time 0.67 seconds
Started Jul 17 05:45:30 PM PDT 24
Finished Jul 17 05:45:31 PM PDT 24
Peak memory 205132 kb
Host smart-4a039a05-8978-4c59-93e4-6572b3af749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255246859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.4255246859
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2495964593
Short name T1123
Test name
Test status
Simulation time 3118512950 ps
CPU time 18.88 seconds
Started Jul 17 05:45:31 PM PDT 24
Finished Jul 17 05:45:51 PM PDT 24
Peak memory 232096 kb
Host smart-ab3e115c-69a8-4492-8abc-df4fe516f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495964593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2495964593
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.4042553275
Short name T804
Test name
Test status
Simulation time 103434663 ps
CPU time 2.02 seconds
Started Jul 17 05:45:31 PM PDT 24
Finished Jul 17 05:45:34 PM PDT 24
Peak memory 226820 kb
Host smart-2e512246-38b5-4fd4-bcba-f88a990c64e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042553275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.4042553275
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1762840161
Short name T1643
Test name
Test status
Simulation time 3128617345 ps
CPU time 38.21 seconds
Started Jul 17 05:45:29 PM PDT 24
Finished Jul 17 05:46:08 PM PDT 24
Peak memory 466424 kb
Host smart-5eb691de-4612-43c9-8ed9-44e0f4d518bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762840161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1762840161
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.1367754613
Short name T693
Test name
Test status
Simulation time 576051613 ps
CPU time 8.71 seconds
Started Jul 17 05:45:34 PM PDT 24
Finished Jul 17 05:45:43 PM PDT 24
Peak memory 217480 kb
Host smart-23601882-6398-4a6d-85ab-b349b248f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367754613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1367754613
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2502144500
Short name T774
Test name
Test status
Simulation time 1713120304 ps
CPU time 4.24 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:55 PM PDT 24
Peak memory 217328 kb
Host smart-c464d3c6-b527-4d3d-94ad-c21fef36e729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502144500 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2502144500
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2944780483
Short name T1546
Test name
Test status
Simulation time 231579136 ps
CPU time 0.99 seconds
Started Jul 17 05:45:41 PM PDT 24
Finished Jul 17 05:45:42 PM PDT 24
Peak memory 205416 kb
Host smart-de53ca46-a658-4997-8186-c9095fc4cd5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944780483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2944780483
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.551753219
Short name T85
Test name
Test status
Simulation time 411518456 ps
CPU time 1.11 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:47 PM PDT 24
Peak memory 205600 kb
Host smart-f5154536-0da4-4989-b59d-b91fbce67f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551753219 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.551753219
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.513935272
Short name T1750
Test name
Test status
Simulation time 797131768 ps
CPU time 2.41 seconds
Started Jul 17 05:45:42 PM PDT 24
Finished Jul 17 05:45:46 PM PDT 24
Peak memory 205624 kb
Host smart-91375096-592a-42c2-a508-972aefd5c47c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513935272 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.513935272
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.3135427431
Short name T1210
Test name
Test status
Simulation time 165222847 ps
CPU time 1.34 seconds
Started Jul 17 05:45:41 PM PDT 24
Finished Jul 17 05:45:43 PM PDT 24
Peak memory 205480 kb
Host smart-a8cec9b4-bdf3-4186-94e6-6a3e0483101c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135427431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.3135427431
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.537906097
Short name T543
Test name
Test status
Simulation time 144582081 ps
CPU time 1.42 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:50 PM PDT 24
Peak memory 213796 kb
Host smart-91926ee7-9700-49e6-b7f0-09987f0a35fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537906097 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_hrst.537906097
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1283294533
Short name T802
Test name
Test status
Simulation time 634727268 ps
CPU time 3.64 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 213828 kb
Host smart-8bca44d9-a289-4e96-bbee-6ea338a7edc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283294533 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1283294533
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.4048422269
Short name T1479
Test name
Test status
Simulation time 15625080989 ps
CPU time 174.31 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:50:44 PM PDT 24
Peak memory 2136120 kb
Host smart-339f3e50-a1ce-4e3a-859c-83e0b80957f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048422269 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.4048422269
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.270041128
Short name T1279
Test name
Test status
Simulation time 2209126618 ps
CPU time 3.04 seconds
Started Jul 17 05:45:43 PM PDT 24
Finished Jul 17 05:45:47 PM PDT 24
Peak memory 213824 kb
Host smart-73aa8b31-d9e3-46ac-a94f-2bf2b749dc4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270041128 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_nack_acqfull.270041128
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.4273191475
Short name T70
Test name
Test status
Simulation time 1868228829 ps
CPU time 2.52 seconds
Started Jul 17 05:45:41 PM PDT 24
Finished Jul 17 05:45:45 PM PDT 24
Peak memory 205632 kb
Host smart-970fd9f7-1a2a-41a1-95ff-0f353fb3d74c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273191475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.4273191475
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_txstretch.318399383
Short name T738
Test name
Test status
Simulation time 486738299 ps
CPU time 1.45 seconds
Started Jul 17 05:45:42 PM PDT 24
Finished Jul 17 05:45:44 PM PDT 24
Peak memory 222072 kb
Host smart-3256d8ff-ae6c-4c3b-befa-fedb915505f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318399383 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_nack_txstretch.318399383
Directory /workspace/26.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/26.i2c_target_perf.1842839594
Short name T694
Test name
Test status
Simulation time 2019490268 ps
CPU time 3.73 seconds
Started Jul 17 05:45:42 PM PDT 24
Finished Jul 17 05:45:47 PM PDT 24
Peak memory 221052 kb
Host smart-9c8d0ad8-34e8-473f-ba55-b40e2fe916a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842839594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.1842839594
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.1967182603
Short name T1331
Test name
Test status
Simulation time 471589454 ps
CPU time 2.16 seconds
Started Jul 17 05:45:42 PM PDT 24
Finished Jul 17 05:45:45 PM PDT 24
Peak memory 205332 kb
Host smart-62f544f4-4fe8-4b70-9f73-e46fda266d56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967182603 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.1967182603
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.320405254
Short name T1504
Test name
Test status
Simulation time 834546826 ps
CPU time 13.39 seconds
Started Jul 17 05:46:45 PM PDT 24
Finished Jul 17 05:46:59 PM PDT 24
Peak memory 214092 kb
Host smart-434a3639-99ec-4b32-a382-f5d07abdf702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320405254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.320405254
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.3207567486
Short name T559
Test name
Test status
Simulation time 10480713150 ps
CPU time 73.1 seconds
Started Jul 17 05:45:41 PM PDT 24
Finished Jul 17 05:46:55 PM PDT 24
Peak memory 876220 kb
Host smart-54af6c3d-8ea5-40de-827c-f22bc7b99bb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207567486 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.3207567486
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2676687392
Short name T469
Test name
Test status
Simulation time 6064439230 ps
CPU time 23.7 seconds
Started Jul 17 05:45:45 PM PDT 24
Finished Jul 17 05:46:09 PM PDT 24
Peak memory 238260 kb
Host smart-641b90e3-3f91-4534-a14e-4f74a604fb51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676687392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2676687392
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1105318730
Short name T1099
Test name
Test status
Simulation time 73256188914 ps
CPU time 87.94 seconds
Started Jul 17 05:45:30 PM PDT 24
Finished Jul 17 05:46:59 PM PDT 24
Peak memory 1048808 kb
Host smart-b49521ae-c693-49d3-82d3-e82474a94a23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105318730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1105318730
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.727503282
Short name T271
Test name
Test status
Simulation time 2871228512 ps
CPU time 55.62 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:48:43 PM PDT 24
Peak memory 471592 kb
Host smart-b18faefd-de1d-4fc8-a2ba-f75b85e1c2b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727503282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_t
arget_stretch.727503282
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.4243337104
Short name T827
Test name
Test status
Simulation time 1147102720 ps
CPU time 6.92 seconds
Started Jul 17 05:45:46 PM PDT 24
Finished Jul 17 05:45:54 PM PDT 24
Peak memory 221928 kb
Host smart-725fbd60-d635-408e-a6a9-dd914b92e783
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243337104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.4243337104
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.1994193254
Short name T603
Test name
Test status
Simulation time 303226115 ps
CPU time 4.02 seconds
Started Jul 17 05:45:41 PM PDT 24
Finished Jul 17 05:45:46 PM PDT 24
Peak memory 205596 kb
Host smart-da4e358e-8f13-42c6-9896-58fee435a681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994193254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.1994193254
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.1513016289
Short name T1124
Test name
Test status
Simulation time 36717271 ps
CPU time 0.62 seconds
Started Jul 17 05:46:04 PM PDT 24
Finished Jul 17 05:46:06 PM PDT 24
Peak memory 204832 kb
Host smart-8c24b4bc-9822-42d3-b064-07cac57c3411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513016289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1513016289
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.4191136811
Short name T650
Test name
Test status
Simulation time 371524054 ps
CPU time 2.76 seconds
Started Jul 17 05:45:53 PM PDT 24
Finished Jul 17 05:45:57 PM PDT 24
Peak memory 214772 kb
Host smart-dae84167-2729-445b-b3e7-c1388267e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191136811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.4191136811
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1580859945
Short name T1025
Test name
Test status
Simulation time 789972226 ps
CPU time 19.49 seconds
Started Jul 17 05:45:53 PM PDT 24
Finished Jul 17 05:46:13 PM PDT 24
Peak memory 273360 kb
Host smart-968ab101-bb0d-4724-a68a-bc63dac13bfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580859945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1580859945
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1479919186
Short name T588
Test name
Test status
Simulation time 2978342785 ps
CPU time 194.01 seconds
Started Jul 17 05:45:52 PM PDT 24
Finished Jul 17 05:49:06 PM PDT 24
Peak memory 588284 kb
Host smart-a3d04862-5598-41e1-9a19-a0db478c96bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479919186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1479919186
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.4159716624
Short name T1
Test name
Test status
Simulation time 10122411936 ps
CPU time 60.39 seconds
Started Jul 17 05:45:55 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 681952 kb
Host smart-9d2a7257-829c-4048-bbc5-b1d99102889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159716624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.4159716624
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3738995483
Short name T422
Test name
Test status
Simulation time 396947603 ps
CPU time 1.06 seconds
Started Jul 17 05:46:05 PM PDT 24
Finished Jul 17 05:46:07 PM PDT 24
Peak memory 205208 kb
Host smart-eaa025a9-9dc3-4cc2-9176-06483996c5f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738995483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3738995483
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3198376408
Short name T1380
Test name
Test status
Simulation time 186790080 ps
CPU time 10.75 seconds
Started Jul 17 05:45:55 PM PDT 24
Finished Jul 17 05:46:07 PM PDT 24
Peak memory 240804 kb
Host smart-86009afe-9290-4f00-93ce-384686ad93b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198376408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3198376408
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.954094040
Short name T1178
Test name
Test status
Simulation time 21787243761 ps
CPU time 352.38 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:53:41 PM PDT 24
Peak memory 1342864 kb
Host smart-5f609c6d-ac14-4d71-b115-a33beace03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954094040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.954094040
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2838070812
Short name T497
Test name
Test status
Simulation time 486615821 ps
CPU time 3.3 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:53 PM PDT 24
Peak memory 205564 kb
Host smart-61bfbd99-5c66-419a-86a4-c0deb957dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838070812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2838070812
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1425852716
Short name T1662
Test name
Test status
Simulation time 156784868 ps
CPU time 5.49 seconds
Started Jul 17 05:46:03 PM PDT 24
Finished Jul 17 05:46:09 PM PDT 24
Peak memory 224216 kb
Host smart-ea9a56b6-afc1-496e-95c5-b3e24aab1cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425852716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1425852716
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.241735450
Short name T1242
Test name
Test status
Simulation time 90747490 ps
CPU time 0.68 seconds
Started Jul 17 05:45:40 PM PDT 24
Finished Jul 17 05:45:42 PM PDT 24
Peak memory 205184 kb
Host smart-a05c5754-d07b-4974-ab6f-f246e9ca39f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241735450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.241735450
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.2620832647
Short name T1333
Test name
Test status
Simulation time 79679768 ps
CPU time 1.4 seconds
Started Jul 17 05:45:53 PM PDT 24
Finished Jul 17 05:45:55 PM PDT 24
Peak memory 205448 kb
Host smart-4e70dde2-832e-41d2-814a-32913e2e31d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620832647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2620832647
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2694377804
Short name T1340
Test name
Test status
Simulation time 2743151484 ps
CPU time 24.64 seconds
Started Jul 17 05:45:45 PM PDT 24
Finished Jul 17 05:46:11 PM PDT 24
Peak memory 343108 kb
Host smart-aaef7b31-2075-430a-9000-cc8a4d22a4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694377804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2694377804
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.784952281
Short name T274
Test name
Test status
Simulation time 16966078073 ps
CPU time 256.51 seconds
Started Jul 17 05:45:51 PM PDT 24
Finished Jul 17 05:50:09 PM PDT 24
Peak memory 1018300 kb
Host smart-3be74112-3e08-4636-ba6e-2c928d2f7291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784952281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.784952281
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2934014878
Short name T1295
Test name
Test status
Simulation time 1067861634 ps
CPU time 8.93 seconds
Started Jul 17 05:45:51 PM PDT 24
Finished Jul 17 05:46:01 PM PDT 24
Peak memory 213660 kb
Host smart-57666b75-4865-4179-be5e-f9ff58b4e503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934014878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2934014878
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2034599879
Short name T951
Test name
Test status
Simulation time 10916496769 ps
CPU time 4.13 seconds
Started Jul 17 05:46:03 PM PDT 24
Finished Jul 17 05:46:08 PM PDT 24
Peak memory 219136 kb
Host smart-77f51baa-ffb3-42de-ae1d-b7e77292cad6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034599879 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2034599879
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1075314531
Short name T765
Test name
Test status
Simulation time 234784729 ps
CPU time 0.87 seconds
Started Jul 17 05:45:50 PM PDT 24
Finished Jul 17 05:45:52 PM PDT 24
Peak memory 205428 kb
Host smart-73a44495-968f-4c12-b308-65ce5775f3da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075314531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1075314531
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3393231085
Short name T674
Test name
Test status
Simulation time 1476924253 ps
CPU time 1.74 seconds
Started Jul 17 05:45:51 PM PDT 24
Finished Jul 17 05:45:54 PM PDT 24
Peak memory 208112 kb
Host smart-30917de3-9146-4939-ae08-0e9a090df584
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393231085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3393231085
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2677157927
Short name T395
Test name
Test status
Simulation time 1010185045 ps
CPU time 2.48 seconds
Started Jul 17 05:46:00 PM PDT 24
Finished Jul 17 05:46:03 PM PDT 24
Peak memory 205656 kb
Host smart-80f727b9-9997-4ea3-996f-bd859dcaa861
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677157927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2677157927
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.168222974
Short name T1738
Test name
Test status
Simulation time 594597346 ps
CPU time 1.49 seconds
Started Jul 17 05:46:05 PM PDT 24
Finished Jul 17 05:46:08 PM PDT 24
Peak memory 205460 kb
Host smart-1ef0a184-1ed3-49fa-bb30-ccdc993dbff3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168222974 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.168222974
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.390477392
Short name T829
Test name
Test status
Simulation time 1150679082 ps
CPU time 6.23 seconds
Started Jul 17 05:45:52 PM PDT 24
Finished Jul 17 05:45:59 PM PDT 24
Peak memory 229648 kb
Host smart-12f1b026-801f-411b-81bb-bb4e1a20835c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390477392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.390477392
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.801844825
Short name T1452
Test name
Test status
Simulation time 14664349663 ps
CPU time 149.1 seconds
Started Jul 17 05:45:52 PM PDT 24
Finished Jul 17 05:48:22 PM PDT 24
Peak memory 2033168 kb
Host smart-23708c3c-8728-4eb3-8210-63e2f9aadfb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801844825 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.801844825
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.521855168
Short name T564
Test name
Test status
Simulation time 513612834 ps
CPU time 2.69 seconds
Started Jul 17 05:46:04 PM PDT 24
Finished Jul 17 05:46:07 PM PDT 24
Peak memory 213812 kb
Host smart-230b69bc-d624-4de3-b74d-7e7379c21f2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521855168 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_nack_acqfull.521855168
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.2780669115
Short name T835
Test name
Test status
Simulation time 919983186 ps
CPU time 2.61 seconds
Started Jul 17 05:46:04 PM PDT 24
Finished Jul 17 05:46:08 PM PDT 24
Peak memory 205636 kb
Host smart-9fbe8f4b-65db-4bb1-acad-5b5f7968b965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780669115 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.2780669115
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_txstretch.2414841588
Short name T599
Test name
Test status
Simulation time 150538547 ps
CPU time 1.56 seconds
Started Jul 17 05:46:04 PM PDT 24
Finished Jul 17 05:46:06 PM PDT 24
Peak memory 222448 kb
Host smart-b3c166ec-6700-4a4a-82e7-089cdff58bfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414841588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_nack_txstretch.2414841588
Directory /workspace/27.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/27.i2c_target_perf.1706195102
Short name T288
Test name
Test status
Simulation time 1590969036 ps
CPU time 4.17 seconds
Started Jul 17 05:45:53 PM PDT 24
Finished Jul 17 05:45:58 PM PDT 24
Peak memory 216460 kb
Host smart-84327b63-285f-4061-b3c2-75e1203d7d44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706195102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.1706195102
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.1481910546
Short name T1255
Test name
Test status
Simulation time 561934067 ps
CPU time 2.42 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:50 PM PDT 24
Peak memory 205404 kb
Host smart-d7409e54-7e1c-4ec6-8e09-f8c2b0536f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481910546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_smbus_maxlen.1481910546
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.4039049751
Short name T1498
Test name
Test status
Simulation time 4713306023 ps
CPU time 37.53 seconds
Started Jul 17 05:45:55 PM PDT 24
Finished Jul 17 05:46:33 PM PDT 24
Peak memory 213924 kb
Host smart-b4c8c527-681a-43c4-9481-9519da5bd10b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039049751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.4039049751
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.1907676490
Short name T1227
Test name
Test status
Simulation time 40766083613 ps
CPU time 1692.46 seconds
Started Jul 17 05:45:55 PM PDT 24
Finished Jul 17 06:14:08 PM PDT 24
Peak memory 6695960 kb
Host smart-d9b12f81-f9d2-47a2-9df8-d129b2ddeb75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907676490 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.1907676490
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1786491093
Short name T262
Test name
Test status
Simulation time 5197811866 ps
CPU time 20.25 seconds
Started Jul 17 05:45:55 PM PDT 24
Finished Jul 17 05:46:16 PM PDT 24
Peak memory 235004 kb
Host smart-4bb7d1bf-c04e-4f86-a4ef-71c767ff48b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786491093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1786491093
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1773576561
Short name T1154
Test name
Test status
Simulation time 21395967499 ps
CPU time 10.99 seconds
Started Jul 17 05:45:56 PM PDT 24
Finished Jul 17 05:46:08 PM PDT 24
Peak memory 205672 kb
Host smart-6253e857-d7a7-42b2-b985-48735d7bf0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773576561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1773576561
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3254051936
Short name T1102
Test name
Test status
Simulation time 1679388042 ps
CPU time 14.33 seconds
Started Jul 17 05:45:50 PM PDT 24
Finished Jul 17 05:46:06 PM PDT 24
Peak memory 564304 kb
Host smart-85cef19c-9e89-458e-80f0-d04193b0312b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254051936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3254051936
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3803969859
Short name T1121
Test name
Test status
Simulation time 7246767730 ps
CPU time 6.57 seconds
Started Jul 17 05:46:02 PM PDT 24
Finished Jul 17 05:46:09 PM PDT 24
Peak memory 222020 kb
Host smart-e136998e-1d0e-4af9-bdc8-c9d8391100a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803969859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3803969859
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.921271651
Short name T1269
Test name
Test status
Simulation time 168723908 ps
CPU time 3.07 seconds
Started Jul 17 05:46:05 PM PDT 24
Finished Jul 17 05:46:09 PM PDT 24
Peak memory 206756 kb
Host smart-1baf17d5-ffa3-47a8-99c4-986324649865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921271651 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.921271651
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2283463781
Short name T1303
Test name
Test status
Simulation time 17985930 ps
CPU time 0.62 seconds
Started Jul 17 05:46:17 PM PDT 24
Finished Jul 17 05:46:18 PM PDT 24
Peak memory 204784 kb
Host smart-7502ddec-1915-41f7-9d6d-2157049df50a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283463781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2283463781
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2609363803
Short name T685
Test name
Test status
Simulation time 588077822 ps
CPU time 4.36 seconds
Started Jul 17 05:47:38 PM PDT 24
Finished Jul 17 05:47:43 PM PDT 24
Peak memory 244168 kb
Host smart-69e6aadf-cd91-46dc-8b37-b6000399aacf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609363803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2609363803
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.595178999
Short name T1413
Test name
Test status
Simulation time 9915523357 ps
CPU time 138.1 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:48:37 PM PDT 24
Peak memory 429352 kb
Host smart-6ed5513e-2933-4d72-8a3c-85453b7efe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595178999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.595178999
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1539717759
Short name T1312
Test name
Test status
Simulation time 14059589991 ps
CPU time 78.2 seconds
Started Jul 17 05:46:42 PM PDT 24
Finished Jul 17 05:48:01 PM PDT 24
Peak memory 767320 kb
Host smart-b1171350-1710-4fab-969d-f449ec87c77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539717759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1539717759
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.1653563991
Short name T1509
Test name
Test status
Simulation time 1495032741 ps
CPU time 0.97 seconds
Started Jul 17 05:46:05 PM PDT 24
Finished Jul 17 05:46:07 PM PDT 24
Peak memory 205416 kb
Host smart-78abd571-ae9b-425b-baec-0ece56434dcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653563991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.1653563991
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.3841874761
Short name T681
Test name
Test status
Simulation time 180050337 ps
CPU time 4.58 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:47:46 PM PDT 24
Peak memory 236108 kb
Host smart-42c211cb-8c31-4b83-862b-8068613f9e85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841874761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.3841874761
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1055418654
Short name T116
Test name
Test status
Simulation time 6420599967 ps
CPU time 82.33 seconds
Started Jul 17 05:46:06 PM PDT 24
Finished Jul 17 05:47:29 PM PDT 24
Peak memory 1036752 kb
Host smart-a7004c00-d6a8-48e4-a242-7d22646e3e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055418654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1055418654
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2893658771
Short name T1101
Test name
Test status
Simulation time 493654340 ps
CPU time 7.78 seconds
Started Jul 17 05:46:16 PM PDT 24
Finished Jul 17 05:46:25 PM PDT 24
Peak memory 205348 kb
Host smart-f19344bc-0251-4f05-beda-f51d2d864297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893658771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2893658771
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2740487570
Short name T76
Test name
Test status
Simulation time 156783777 ps
CPU time 1.37 seconds
Started Jul 17 05:46:16 PM PDT 24
Finished Jul 17 05:46:18 PM PDT 24
Peak memory 213572 kb
Host smart-3935c5ee-be5d-45e3-891c-e072a967ce06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740487570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2740487570
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1580138333
Short name T1562
Test name
Test status
Simulation time 25630294 ps
CPU time 0.67 seconds
Started Jul 17 05:46:06 PM PDT 24
Finished Jul 17 05:46:07 PM PDT 24
Peak memory 205248 kb
Host smart-a8aaad9b-63e9-4865-a0a2-dc81aca1a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580138333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1580138333
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2899136849
Short name T526
Test name
Test status
Simulation time 11282378625 ps
CPU time 15.13 seconds
Started Jul 17 05:46:14 PM PDT 24
Finished Jul 17 05:46:30 PM PDT 24
Peak memory 285852 kb
Host smart-d56f4b01-bc9c-46ae-86c0-1b589aef348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899136849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2899136849
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.1813860749
Short name T1700
Test name
Test status
Simulation time 6089027548 ps
CPU time 17.34 seconds
Started Jul 17 05:46:14 PM PDT 24
Finished Jul 17 05:46:32 PM PDT 24
Peak memory 205500 kb
Host smart-85c0016e-c514-4289-add0-518b59407549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813860749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.1813860749
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2045655557
Short name T606
Test name
Test status
Simulation time 4702454209 ps
CPU time 17.32 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:48:06 PM PDT 24
Peak memory 294872 kb
Host smart-f34cae21-160f-4cce-b5fa-576d8c439ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045655557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2045655557
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1236292105
Short name T1414
Test name
Test status
Simulation time 735817440 ps
CPU time 6.08 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:46:26 PM PDT 24
Peak memory 221544 kb
Host smart-d41b229f-c5a7-4fff-acdb-09977ee5f654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236292105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1236292105
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.2594406585
Short name T1225
Test name
Test status
Simulation time 888701893 ps
CPU time 4.05 seconds
Started Jul 17 05:46:15 PM PDT 24
Finished Jul 17 05:46:20 PM PDT 24
Peak memory 218428 kb
Host smart-93a56828-f99b-48d3-b37d-2790191f340e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594406585 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.2594406585
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.566107597
Short name T883
Test name
Test status
Simulation time 235860702 ps
CPU time 1.67 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:46:21 PM PDT 24
Peak memory 205624 kb
Host smart-f41644f3-c03c-40b3-9bd0-8ccf98fbc6b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566107597 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.566107597
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.871840301
Short name T710
Test name
Test status
Simulation time 119863143 ps
CPU time 0.91 seconds
Started Jul 17 05:47:23 PM PDT 24
Finished Jul 17 05:47:26 PM PDT 24
Peak memory 205452 kb
Host smart-ec8af19f-fd91-46e1-9a78-0039660b673a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871840301 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.871840301
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.521879030
Short name T1654
Test name
Test status
Simulation time 1700810171 ps
CPU time 2.73 seconds
Started Jul 17 05:46:13 PM PDT 24
Finished Jul 17 05:46:17 PM PDT 24
Peak memory 205604 kb
Host smart-ee33d2f9-3280-480b-a7a9-5c4620f95843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521879030 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.521879030
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.150183593
Short name T1752
Test name
Test status
Simulation time 144367567 ps
CPU time 1.6 seconds
Started Jul 17 05:46:16 PM PDT 24
Finished Jul 17 05:46:18 PM PDT 24
Peak memory 205632 kb
Host smart-df9815aa-f253-4ed8-b0a3-bd0848ab40c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150183593 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.150183593
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1116247490
Short name T1383
Test name
Test status
Simulation time 782971154 ps
CPU time 1.94 seconds
Started Jul 17 05:46:17 PM PDT 24
Finished Jul 17 05:46:20 PM PDT 24
Peak memory 213828 kb
Host smart-63a23c4d-fab9-4b89-a781-ef47c452163d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116247490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1116247490
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1308423950
Short name T894
Test name
Test status
Simulation time 2906007190 ps
CPU time 3.53 seconds
Started Jul 17 05:46:16 PM PDT 24
Finished Jul 17 05:46:20 PM PDT 24
Peak memory 213860 kb
Host smart-12dc4885-9f96-4717-a1ef-0c631389e676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308423950 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1308423950
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.829464042
Short name T639
Test name
Test status
Simulation time 27499267318 ps
CPU time 731.11 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:58:30 PM PDT 24
Peak memory 6187876 kb
Host smart-f1be9f6a-6930-4162-b56e-0fc68b853009
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829464042 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.829464042
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.659434742
Short name T785
Test name
Test status
Simulation time 1911831342 ps
CPU time 2.66 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:46:27 PM PDT 24
Peak memory 213868 kb
Host smart-72fe1bcb-a06e-41bf-92e3-22823bdb6dda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659434742 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_nack_acqfull.659434742
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.1138916161
Short name T1012
Test name
Test status
Simulation time 4232942401 ps
CPU time 2.6 seconds
Started Jul 17 05:46:14 PM PDT 24
Finished Jul 17 05:46:18 PM PDT 24
Peak memory 205828 kb
Host smart-f51614d8-4249-4c51-b607-7a6f71380407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138916161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.1138916161
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_txstretch.3061159996
Short name T977
Test name
Test status
Simulation time 136441270 ps
CPU time 1.36 seconds
Started Jul 17 05:46:17 PM PDT 24
Finished Jul 17 05:46:19 PM PDT 24
Peak memory 222116 kb
Host smart-c1526d52-0475-4f7e-b333-bea6c1a575ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061159996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_nack_txstretch.3061159996
Directory /workspace/28.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/28.i2c_target_perf.737250333
Short name T1595
Test name
Test status
Simulation time 588522903 ps
CPU time 4.47 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:58 PM PDT 24
Peak memory 222004 kb
Host smart-12992f10-079c-4b4f-a989-c144fae7d2c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737250333 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_perf.737250333
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.1933039371
Short name T1407
Test name
Test status
Simulation time 860099371 ps
CPU time 2.07 seconds
Started Jul 17 05:46:17 PM PDT 24
Finished Jul 17 05:46:20 PM PDT 24
Peak memory 205428 kb
Host smart-23ea2631-3f3e-4ac7-a064-3be6f0fc471e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933039371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_smbus_maxlen.1933039371
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.982827392
Short name T836
Test name
Test status
Simulation time 1288520658 ps
CPU time 18.46 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:46:38 PM PDT 24
Peak memory 213836 kb
Host smart-0849b12a-c2d2-4fc0-b742-5fbc734483b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982827392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_smoke.982827392
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.784307414
Short name T1149
Test name
Test status
Simulation time 45959734470 ps
CPU time 406.17 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:53:06 PM PDT 24
Peak memory 2828536 kb
Host smart-edd93a5d-7118-4f82-a75d-46f3b4280eba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784307414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_target_stress_all.784307414
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2741467866
Short name T989
Test name
Test status
Simulation time 5992089577 ps
CPU time 28.07 seconds
Started Jul 17 05:46:14 PM PDT 24
Finished Jul 17 05:46:43 PM PDT 24
Peak memory 230176 kb
Host smart-37665d43-d5e8-4ef8-a7b8-660109ba6b87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741467866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2741467866
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.593179542
Short name T574
Test name
Test status
Simulation time 59757180851 ps
CPU time 2192.13 seconds
Started Jul 17 05:47:15 PM PDT 24
Finished Jul 17 06:23:49 PM PDT 24
Peak memory 10210940 kb
Host smart-468f92c5-8cca-463f-9de0-412f99b94f7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593179542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_wr.593179542
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.894977314
Short name T1560
Test name
Test status
Simulation time 5434506556 ps
CPU time 18.94 seconds
Started Jul 17 05:46:15 PM PDT 24
Finished Jul 17 05:46:34 PM PDT 24
Peak memory 491516 kb
Host smart-15cd9632-305c-4509-868e-2f24b46e0d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894977314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t
arget_stretch.894977314
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.628046898
Short name T755
Test name
Test status
Simulation time 4840345466 ps
CPU time 7.78 seconds
Started Jul 17 05:46:17 PM PDT 24
Finished Jul 17 05:46:26 PM PDT 24
Peak memory 221960 kb
Host smart-0c3969d2-b5c6-4d56-a387-f43c5d94c3c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628046898 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.628046898
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.1210393524
Short name T1748
Test name
Test status
Simulation time 97229758 ps
CPU time 2.15 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:52 PM PDT 24
Peak memory 205608 kb
Host smart-8852b7d9-2112-4d8d-94bf-d158961ade8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210393524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1210393524
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.812388201
Short name T568
Test name
Test status
Simulation time 18648384 ps
CPU time 0.65 seconds
Started Jul 17 05:46:51 PM PDT 24
Finished Jul 17 05:46:52 PM PDT 24
Peak memory 204784 kb
Host smart-f0c90a94-32a5-4d11-87c3-7f62d2b89a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812388201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.812388201
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3271130367
Short name T773
Test name
Test status
Simulation time 541552358 ps
CPU time 3.93 seconds
Started Jul 17 05:46:37 PM PDT 24
Finished Jul 17 05:46:42 PM PDT 24
Peak memory 242344 kb
Host smart-e44eb68a-7c61-42cc-bca0-763dea54408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271130367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3271130367
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1951418078
Short name T759
Test name
Test status
Simulation time 4622055677 ps
CPU time 6.7 seconds
Started Jul 17 05:46:37 PM PDT 24
Finished Jul 17 05:46:44 PM PDT 24
Peak memory 264092 kb
Host smart-e1dc76bc-38a6-4655-af43-0930e708f159
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951418078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1951418078
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1478236217
Short name T512
Test name
Test status
Simulation time 4938792982 ps
CPU time 76.75 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 618616 kb
Host smart-4ec6573f-fb15-47fd-a4c7-79e27a738da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478236217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1478236217
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1787636939
Short name T421
Test name
Test status
Simulation time 1802015861 ps
CPU time 129.54 seconds
Started Jul 17 05:46:44 PM PDT 24
Finished Jul 17 05:48:55 PM PDT 24
Peak memory 645728 kb
Host smart-df51ba7e-3ae0-4727-b78c-001a5a9df1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787636939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1787636939
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1038979839
Short name T1153
Test name
Test status
Simulation time 114363051 ps
CPU time 1.08 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:48 PM PDT 24
Peak memory 205224 kb
Host smart-8faf8a5e-0b27-4102-b63d-56c1f83e524d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038979839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1038979839
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.1957283659
Short name T1169
Test name
Test status
Simulation time 1947251587 ps
CPU time 8.37 seconds
Started Jul 17 05:46:38 PM PDT 24
Finished Jul 17 05:46:47 PM PDT 24
Peak memory 205436 kb
Host smart-4f9f6b00-49a1-4957-a584-e925ce333b16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957283659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.1957283659
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1335250817
Short name T523
Test name
Test status
Simulation time 16064100819 ps
CPU time 282.5 seconds
Started Jul 17 05:46:37 PM PDT 24
Finished Jul 17 05:51:20 PM PDT 24
Peak memory 1206772 kb
Host smart-c974f2b4-fe6d-410a-b511-c641035e3894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335250817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1335250817
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.1502302030
Short name T265
Test name
Test status
Simulation time 1565628506 ps
CPU time 31.08 seconds
Started Jul 17 05:46:37 PM PDT 24
Finished Jul 17 05:47:09 PM PDT 24
Peak memory 205464 kb
Host smart-66decdfa-91f9-4f22-804d-7f55dcc31f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502302030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1502302030
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2632393616
Short name T12
Test name
Test status
Simulation time 89634471 ps
CPU time 2.98 seconds
Started Jul 17 05:46:37 PM PDT 24
Finished Jul 17 05:46:41 PM PDT 24
Peak memory 217640 kb
Host smart-101e313a-8782-455a-9929-b1628c09f5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632393616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2632393616
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.809460945
Short name T1665
Test name
Test status
Simulation time 26433212 ps
CPU time 0.69 seconds
Started Jul 17 05:47:16 PM PDT 24
Finished Jul 17 05:47:18 PM PDT 24
Peak memory 205180 kb
Host smart-626ad736-dac5-4ffd-8a15-f6bf14abe0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809460945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.809460945
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.309930413
Short name T687
Test name
Test status
Simulation time 27887944273 ps
CPU time 1029.62 seconds
Started Jul 17 05:46:36 PM PDT 24
Finished Jul 17 06:03:46 PM PDT 24
Peak memory 330004 kb
Host smart-cf67adc6-e04c-451a-9221-2b8a43525409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309930413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.309930413
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.2026434055
Short name T1161
Test name
Test status
Simulation time 24296938756 ps
CPU time 2319.52 seconds
Started Jul 17 05:46:36 PM PDT 24
Finished Jul 17 06:25:17 PM PDT 24
Peak memory 2511524 kb
Host smart-a13b2c02-dfbe-4624-8a6f-e4fa78930cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026434055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.2026434055
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1705220589
Short name T1051
Test name
Test status
Simulation time 2106538988 ps
CPU time 16.56 seconds
Started Jul 17 05:46:16 PM PDT 24
Finished Jul 17 05:46:33 PM PDT 24
Peak memory 270392 kb
Host smart-d608d9b8-3ce4-45c8-9cfd-98c247980141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705220589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1705220589
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3603486621
Short name T1409
Test name
Test status
Simulation time 26198317546 ps
CPU time 689.92 seconds
Started Jul 17 05:46:38 PM PDT 24
Finished Jul 17 05:58:09 PM PDT 24
Peak memory 2290756 kb
Host smart-4e0185f2-df00-4cb7-8098-e760846b5756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603486621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3603486621
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2526879807
Short name T1552
Test name
Test status
Simulation time 521758399 ps
CPU time 7.73 seconds
Started Jul 17 05:47:26 PM PDT 24
Finished Jul 17 05:47:35 PM PDT 24
Peak memory 221824 kb
Host smart-522ed933-4ae2-441d-96cd-90a4a18b2a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526879807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2526879807
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2852717959
Short name T912
Test name
Test status
Simulation time 2038686323 ps
CPU time 5.95 seconds
Started Jul 17 05:46:39 PM PDT 24
Finished Jul 17 05:46:46 PM PDT 24
Peak memory 213788 kb
Host smart-6a98cb0a-0b34-4237-9557-7a83587f2db1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852717959 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2852717959
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.919379381
Short name T1495
Test name
Test status
Simulation time 286563991 ps
CPU time 1.13 seconds
Started Jul 17 05:47:25 PM PDT 24
Finished Jul 17 05:47:27 PM PDT 24
Peak memory 213680 kb
Host smart-4878e179-7e66-46da-90b6-3169220cbe6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919379381 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.919379381
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.2766243572
Short name T1136
Test name
Test status
Simulation time 400596946 ps
CPU time 1.03 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:52 PM PDT 24
Peak memory 205480 kb
Host smart-167031a4-bdcc-47fc-9357-4017c37bb35c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766243572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.2766243572
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.651798767
Short name T696
Test name
Test status
Simulation time 907937525 ps
CPU time 2.72 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 205652 kb
Host smart-1ba7adce-2634-4639-b74a-ddb554ef6778
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651798767 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.651798767
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2831188650
Short name T561
Test name
Test status
Simulation time 83410921 ps
CPU time 0.96 seconds
Started Jul 17 05:46:35 PM PDT 24
Finished Jul 17 05:46:37 PM PDT 24
Peak memory 205416 kb
Host smart-b58b0601-41fc-4097-8451-08f8c25afcc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831188650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2831188650
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3065441649
Short name T176
Test name
Test status
Simulation time 1101944155 ps
CPU time 2.14 seconds
Started Jul 17 05:46:37 PM PDT 24
Finished Jul 17 05:46:40 PM PDT 24
Peak memory 214064 kb
Host smart-0ff6fa71-c0e8-4ebf-aca7-520eed2d4455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065441649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3065441649
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1033601574
Short name T479
Test name
Test status
Simulation time 904200799 ps
CPU time 5.34 seconds
Started Jul 17 05:46:37 PM PDT 24
Finished Jul 17 05:46:43 PM PDT 24
Peak memory 221896 kb
Host smart-2f8c58ce-30ca-4b68-9f58-a0fc4b852c25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033601574 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1033601574
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.905712192
Short name T1226
Test name
Test status
Simulation time 6454001815 ps
CPU time 10.32 seconds
Started Jul 17 05:46:38 PM PDT 24
Finished Jul 17 05:46:49 PM PDT 24
Peak memory 482964 kb
Host smart-cd9775a7-7f6b-41fc-ab96-353a1d301c5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905712192 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.905712192
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.19962154
Short name T147
Test name
Test status
Simulation time 1893977665 ps
CPU time 2.61 seconds
Started Jul 17 05:46:39 PM PDT 24
Finished Jul 17 05:46:43 PM PDT 24
Peak memory 213840 kb
Host smart-68ba3451-9f0f-4116-b0ce-dc5bad05bb68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19962154 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_target_nack_acqfull.19962154
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.3842976097
Short name T920
Test name
Test status
Simulation time 544794676 ps
CPU time 2.55 seconds
Started Jul 17 05:46:50 PM PDT 24
Finished Jul 17 05:46:54 PM PDT 24
Peak memory 205532 kb
Host smart-5b07b35d-d6e6-4d38-9c2a-7d5a47481667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842976097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.3842976097
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.4180761589
Short name T745
Test name
Test status
Simulation time 1048939767 ps
CPU time 7.28 seconds
Started Jul 17 05:46:37 PM PDT 24
Finished Jul 17 05:46:45 PM PDT 24
Peak memory 221488 kb
Host smart-9a61d362-1705-414f-88c0-0b8e925f6f3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180761589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.4180761589
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.3412448177
Short name T410
Test name
Test status
Simulation time 522339431 ps
CPU time 2.33 seconds
Started Jul 17 05:47:38 PM PDT 24
Finished Jul 17 05:47:41 PM PDT 24
Peak memory 205436 kb
Host smart-5fe4f2e5-20d8-478c-861a-6372c006d2e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412448177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.3412448177
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.1583067622
Short name T81
Test name
Test status
Simulation time 769945764 ps
CPU time 22.91 seconds
Started Jul 17 05:47:35 PM PDT 24
Finished Jul 17 05:47:59 PM PDT 24
Peak memory 214040 kb
Host smart-dfdb7878-b6d4-4479-928e-46b831b2f98a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583067622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.1583067622
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.943793424
Short name T1348
Test name
Test status
Simulation time 9458320221 ps
CPU time 46.92 seconds
Started Jul 17 05:46:40 PM PDT 24
Finished Jul 17 05:47:28 PM PDT 24
Peak memory 298496 kb
Host smart-818499b4-e82d-41f8-a115-361a649a8474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943793424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_target_stress_all.943793424
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3725536832
Short name T261
Test name
Test status
Simulation time 2167090661 ps
CPU time 24.18 seconds
Started Jul 17 05:46:39 PM PDT 24
Finished Jul 17 05:47:04 PM PDT 24
Peak memory 213856 kb
Host smart-b4e78c00-1918-4f4c-bae6-61ce69cb2456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725536832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3725536832
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2093073161
Short name T69
Test name
Test status
Simulation time 66241827349 ps
CPU time 166.52 seconds
Started Jul 17 05:47:25 PM PDT 24
Finished Jul 17 05:50:13 PM PDT 24
Peak memory 1722004 kb
Host smart-6a3215cb-7fa4-4327-be53-e5dbde0018b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093073161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2093073161
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.10437440
Short name T547
Test name
Test status
Simulation time 4484517468 ps
CPU time 57.66 seconds
Started Jul 17 05:46:38 PM PDT 24
Finished Jul 17 05:47:37 PM PDT 24
Peak memory 503016 kb
Host smart-f72f2cb3-7273-4341-8601-c6adb86f64e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_stretch.10437440
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1265295387
Short name T1360
Test name
Test status
Simulation time 1159692324 ps
CPU time 6.54 seconds
Started Jul 17 05:46:35 PM PDT 24
Finished Jul 17 05:46:42 PM PDT 24
Peak memory 222044 kb
Host smart-5712d76c-3879-4693-9ed9-a1bb086be875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265295387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1265295387
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.1356438139
Short name T1523
Test name
Test status
Simulation time 127483880 ps
CPU time 2.64 seconds
Started Jul 17 05:47:15 PM PDT 24
Finished Jul 17 05:47:19 PM PDT 24
Peak memory 205572 kb
Host smart-fd621eb2-a001-4f60-a89c-ca422c65b8e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356438139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.1356438139
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.4229268275
Short name T10
Test name
Test status
Simulation time 17479939 ps
CPU time 0.58 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:17 PM PDT 24
Peak memory 204868 kb
Host smart-d79ebb4c-924f-4bed-8184-a37b0b9def9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229268275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4229268275
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1404143812
Short name T78
Test name
Test status
Simulation time 133222913 ps
CPU time 1.14 seconds
Started Jul 17 05:41:55 PM PDT 24
Finished Jul 17 05:41:57 PM PDT 24
Peak memory 205568 kb
Host smart-fd948c56-cbbc-444c-a06b-5a7300fbe104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404143812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1404143812
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.3658618543
Short name T978
Test name
Test status
Simulation time 326270771 ps
CPU time 5.94 seconds
Started Jul 17 05:40:56 PM PDT 24
Finished Jul 17 05:41:03 PM PDT 24
Peak memory 263148 kb
Host smart-320d59bc-436b-49c8-b5c7-bb15da6b34b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658618543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.3658618543
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2352201558
Short name T1076
Test name
Test status
Simulation time 8382932428 ps
CPU time 129.38 seconds
Started Jul 17 05:39:59 PM PDT 24
Finished Jul 17 05:42:10 PM PDT 24
Peak memory 507448 kb
Host smart-49bac5a0-d727-40bb-9b40-df77b8240cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352201558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2352201558
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1917874338
Short name T1278
Test name
Test status
Simulation time 3215448757 ps
CPU time 103.09 seconds
Started Jul 17 05:40:00 PM PDT 24
Finished Jul 17 05:41:44 PM PDT 24
Peak memory 517484 kb
Host smart-7e3c110f-ffc3-40f0-8b4c-61f2aaad1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917874338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1917874338
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2225049694
Short name T954
Test name
Test status
Simulation time 289647602 ps
CPU time 1.16 seconds
Started Jul 17 05:39:58 PM PDT 24
Finished Jul 17 05:40:01 PM PDT 24
Peak memory 205172 kb
Host smart-45bd8556-b028-4a07-98c8-b7f5adb4ac3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225049694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2225049694
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1397880644
Short name T875
Test name
Test status
Simulation time 611440828 ps
CPU time 7.76 seconds
Started Jul 17 05:39:59 PM PDT 24
Finished Jul 17 05:40:08 PM PDT 24
Peak memory 205556 kb
Host smart-18e129eb-79bb-439f-a4cb-e12ada9a83d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397880644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1397880644
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.4018032455
Short name T119
Test name
Test status
Simulation time 16056207371 ps
CPU time 90.94 seconds
Started Jul 17 05:39:59 PM PDT 24
Finished Jul 17 05:41:32 PM PDT 24
Peak memory 1169100 kb
Host smart-723be576-5be5-44d7-ac19-187301ae11da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018032455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.4018032455
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2990704868
Short name T1606
Test name
Test status
Simulation time 183412570 ps
CPU time 2.55 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:18 PM PDT 24
Peak memory 205472 kb
Host smart-b570b035-01e5-4491-a7fd-01d6e75527c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990704868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2990704868
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_override.3834911706
Short name T441
Test name
Test status
Simulation time 48097395 ps
CPU time 0.75 seconds
Started Jul 17 05:39:57 PM PDT 24
Finished Jul 17 05:39:59 PM PDT 24
Peak memory 205224 kb
Host smart-83e76566-0de7-494e-8194-99322f0d88fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834911706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3834911706
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3582269391
Short name T805
Test name
Test status
Simulation time 7347198678 ps
CPU time 145.53 seconds
Started Jul 17 05:40:30 PM PDT 24
Finished Jul 17 05:42:57 PM PDT 24
Peak memory 308164 kb
Host smart-2d88adf5-bc62-4ea6-833d-66ea6c7e4a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582269391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3582269391
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.2564436365
Short name T1384
Test name
Test status
Simulation time 80545052 ps
CPU time 1.37 seconds
Started Jul 17 05:39:59 PM PDT 24
Finished Jul 17 05:40:02 PM PDT 24
Peak memory 213624 kb
Host smart-98f5e5c9-ef5e-48ad-bed3-b4a9e319fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564436365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.2564436365
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1810373291
Short name T1539
Test name
Test status
Simulation time 1413654142 ps
CPU time 62.8 seconds
Started Jul 17 05:39:58 PM PDT 24
Finished Jul 17 05:41:02 PM PDT 24
Peak memory 327248 kb
Host smart-555a1819-62bd-43e4-b1fb-3a909319ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810373291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1810373291
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3127984888
Short name T975
Test name
Test status
Simulation time 9272376772 ps
CPU time 18.69 seconds
Started Jul 17 05:39:58 PM PDT 24
Finished Jul 17 05:40:19 PM PDT 24
Peak memory 221304 kb
Host smart-43763318-0df9-4958-bb66-3e61bdc6a321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127984888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3127984888
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3562585644
Short name T181
Test name
Test status
Simulation time 131974723 ps
CPU time 0.96 seconds
Started Jul 17 05:40:12 PM PDT 24
Finished Jul 17 05:40:13 PM PDT 24
Peak memory 224052 kb
Host smart-f6a9ce38-63f3-42cc-802c-4c9922179e3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562585644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3562585644
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.4226810527
Short name T63
Test name
Test status
Simulation time 1291257766 ps
CPU time 3.53 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:20 PM PDT 24
Peak memory 213936 kb
Host smart-14ff9be2-bd0e-4dbe-b85f-5af30f8dac57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226810527 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.4226810527
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2357455420
Short name T1742
Test name
Test status
Simulation time 328852267 ps
CPU time 0.85 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:16 PM PDT 24
Peak memory 205432 kb
Host smart-c7b11e04-330f-48c3-8af2-0631e905fd65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357455420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2357455420
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.4248947334
Short name T1132
Test name
Test status
Simulation time 348920994 ps
CPU time 2.15 seconds
Started Jul 17 05:40:15 PM PDT 24
Finished Jul 17 05:40:19 PM PDT 24
Peak memory 215740 kb
Host smart-e121aab0-a7f8-4ba5-8163-87693a3c5ba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248947334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.4248947334
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.4116762226
Short name T615
Test name
Test status
Simulation time 3759312661 ps
CPU time 2.69 seconds
Started Jul 17 05:40:13 PM PDT 24
Finished Jul 17 05:40:17 PM PDT 24
Peak memory 205756 kb
Host smart-a1fefddc-5a9b-4d27-ae26-a5be7413a357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116762226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.4116762226
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.746950126
Short name T74
Test name
Test status
Simulation time 163048050 ps
CPU time 0.97 seconds
Started Jul 17 05:40:12 PM PDT 24
Finished Jul 17 05:40:13 PM PDT 24
Peak memory 205420 kb
Host smart-727fb9f5-283a-4bec-b452-9e0d87245f17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746950126 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.746950126
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.4227539947
Short name T1229
Test name
Test status
Simulation time 691049693 ps
CPU time 2.77 seconds
Started Jul 17 05:41:00 PM PDT 24
Finished Jul 17 05:41:04 PM PDT 24
Peak memory 217220 kb
Host smart-8add2c59-5219-499e-b577-650b4e612d2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227539947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.4227539947
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.4057871467
Short name T1614
Test name
Test status
Simulation time 3687415220 ps
CPU time 9.25 seconds
Started Jul 17 05:39:58 PM PDT 24
Finished Jul 17 05:40:09 PM PDT 24
Peak memory 235208 kb
Host smart-478c72b6-a81f-4c1a-81ad-24c81161e81d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057871467 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.4057871467
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2006529533
Short name T318
Test name
Test status
Simulation time 7710022232 ps
CPU time 16.46 seconds
Started Jul 17 05:40:12 PM PDT 24
Finished Jul 17 05:40:30 PM PDT 24
Peak memory 260416 kb
Host smart-c46125b0-bc9b-4500-a848-f69c68b2c693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006529533 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2006529533
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.3888112119
Short name T1544
Test name
Test status
Simulation time 2334820927 ps
CPU time 2.94 seconds
Started Jul 17 05:40:13 PM PDT 24
Finished Jul 17 05:40:17 PM PDT 24
Peak memory 213920 kb
Host smart-5bec3e05-0f09-43a0-b30d-423ed75ae395
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888112119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_acqfull.3888112119
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.415965053
Short name T1294
Test name
Test status
Simulation time 567490150 ps
CPU time 2.73 seconds
Started Jul 17 05:40:13 PM PDT 24
Finished Jul 17 05:40:18 PM PDT 24
Peak memory 205648 kb
Host smart-d74b6a7b-7e1a-4439-9c8b-65e921194867
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415965053 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.415965053
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.1583614803
Short name T446
Test name
Test status
Simulation time 588060386 ps
CPU time 4.19 seconds
Started Jul 17 05:40:11 PM PDT 24
Finished Jul 17 05:40:16 PM PDT 24
Peak memory 213892 kb
Host smart-feff9c17-7627-4381-ab53-0a97e0b489ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583614803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.1583614803
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.2608073374
Short name T1111
Test name
Test status
Simulation time 2390228037 ps
CPU time 2.44 seconds
Started Jul 17 05:40:12 PM PDT 24
Finished Jul 17 05:40:15 PM PDT 24
Peak memory 205644 kb
Host smart-6b0070c1-9e85-4c19-8597-9814292502a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608073374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_smbus_maxlen.2608073374
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.4018430020
Short name T1737
Test name
Test status
Simulation time 6974999801 ps
CPU time 13.08 seconds
Started Jul 17 05:39:57 PM PDT 24
Finished Jul 17 05:40:12 PM PDT 24
Peak memory 213872 kb
Host smart-1c1e2ec4-f79a-41bb-aedf-fbe6a817d40a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018430020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.4018430020
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.2529879468
Short name T1346
Test name
Test status
Simulation time 45029342046 ps
CPU time 170.93 seconds
Started Jul 17 05:40:12 PM PDT 24
Finished Jul 17 05:43:04 PM PDT 24
Peak memory 1478792 kb
Host smart-0c40bd8b-b98f-43a6-9400-dd6b879fd4a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529879468 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.2529879468
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2889159393
Short name T900
Test name
Test status
Simulation time 7673257851 ps
CPU time 22.77 seconds
Started Jul 17 05:39:59 PM PDT 24
Finished Jul 17 05:40:23 PM PDT 24
Peak memory 233268 kb
Host smart-3c05a4d9-d564-4138-92ca-603e94ad08d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889159393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2889159393
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.702526002
Short name T53
Test name
Test status
Simulation time 25598478924 ps
CPU time 93.81 seconds
Started Jul 17 05:39:58 PM PDT 24
Finished Jul 17 05:41:33 PM PDT 24
Peak memory 1473788 kb
Host smart-1856c0ff-8622-4c0c-b770-0dad3bd789dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702526002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.702526002
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1204171504
Short name T1621
Test name
Test status
Simulation time 3582880702 ps
CPU time 184.44 seconds
Started Jul 17 05:39:58 PM PDT 24
Finished Jul 17 05:43:04 PM PDT 24
Peak memory 974592 kb
Host smart-89f1cbfa-9cb1-4564-843d-c00d8bd25b1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204171504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1204171504
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3640607776
Short name T1218
Test name
Test status
Simulation time 4150305721 ps
CPU time 6.71 seconds
Started Jul 17 05:40:46 PM PDT 24
Finished Jul 17 05:40:54 PM PDT 24
Peak memory 222032 kb
Host smart-000db815-bc73-42a3-a8fa-0854540cd0cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640607776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3640607776
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.2224181281
Short name T1264
Test name
Test status
Simulation time 163498612 ps
CPU time 3.66 seconds
Started Jul 17 05:40:11 PM PDT 24
Finished Jul 17 05:40:16 PM PDT 24
Peak memory 205608 kb
Host smart-308a3e24-0684-4dc8-83e1-00f36a3c9bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224181281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.2224181281
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2300649332
Short name T1588
Test name
Test status
Simulation time 23097278 ps
CPU time 0.62 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 204728 kb
Host smart-63219319-aa8c-4551-8117-0ebec428ecdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300649332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2300649332
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1061604042
Short name T1235
Test name
Test status
Simulation time 193583310 ps
CPU time 3.48 seconds
Started Jul 17 05:46:53 PM PDT 24
Finished Jul 17 05:46:57 PM PDT 24
Peak memory 235848 kb
Host smart-42e07f4a-b5ae-483d-b8e1-221c6e34eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061604042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1061604042
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.805261912
Short name T942
Test name
Test status
Simulation time 1607251597 ps
CPU time 21.21 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:48:06 PM PDT 24
Peak memory 288580 kb
Host smart-516bf41c-533a-40f8-8cf9-ddf61edef86a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805261912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empt
y.805261912
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.807345712
Short name T995
Test name
Test status
Simulation time 4361296062 ps
CPU time 46.98 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:43 PM PDT 24
Peak memory 334140 kb
Host smart-d9aa0a65-c921-4d78-a76a-57457cafd931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807345712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.807345712
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.604764304
Short name T487
Test name
Test status
Simulation time 15578820630 ps
CPU time 39.13 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:34 PM PDT 24
Peak memory 557236 kb
Host smart-d92f86e4-4920-4d1a-8bdd-0a37c2f84b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604764304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.604764304
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1577903320
Short name T1155
Test name
Test status
Simulation time 448057754 ps
CPU time 1.33 seconds
Started Jul 17 05:47:24 PM PDT 24
Finished Jul 17 05:47:27 PM PDT 24
Peak memory 205396 kb
Host smart-5073b996-51eb-43b6-b310-05628f616ec4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577903320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1577903320
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3912681777
Short name T1666
Test name
Test status
Simulation time 362282567 ps
CPU time 3.1 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 205520 kb
Host smart-f9f4074f-339e-4f15-ae19-f0fc0f2e5222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912681777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3912681777
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.46326435
Short name T958
Test name
Test status
Simulation time 31185240314 ps
CPU time 100.31 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:49:22 PM PDT 24
Peak memory 1219420 kb
Host smart-248aabf1-a5a5-4b05-a338-647835998d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46326435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.46326435
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2594011397
Short name T1376
Test name
Test status
Simulation time 1030247269 ps
CPU time 20.29 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:16 PM PDT 24
Peak memory 205544 kb
Host smart-3e2163e4-ccdd-4b58-bc12-e629859b48ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594011397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2594011397
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.433878602
Short name T1432
Test name
Test status
Simulation time 82954318 ps
CPU time 0.67 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:54 PM PDT 24
Peak memory 205192 kb
Host smart-e6152682-2847-407c-995b-22ab76cdbdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433878602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.433878602
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2602390918
Short name T659
Test name
Test status
Simulation time 413911572 ps
CPU time 2.19 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 223412 kb
Host smart-4bc63fc1-0723-4777-bafa-ed6f6a7c283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602390918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2602390918
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.1291117148
Short name T716
Test name
Test status
Simulation time 53017467 ps
CPU time 1.37 seconds
Started Jul 17 05:46:51 PM PDT 24
Finished Jul 17 05:46:54 PM PDT 24
Peak memory 223136 kb
Host smart-105a86f9-aa14-41f2-995b-cfdf55089543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291117148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1291117148
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.4019263584
Short name T1675
Test name
Test status
Simulation time 952915464 ps
CPU time 41.44 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:47:35 PM PDT 24
Peak memory 286680 kb
Host smart-1d3dac15-ecfb-47c5-bc9b-8c0170097819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019263584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.4019263584
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2775781599
Short name T345
Test name
Test status
Simulation time 3405329539 ps
CPU time 13.83 seconds
Started Jul 17 05:46:50 PM PDT 24
Finished Jul 17 05:47:05 PM PDT 24
Peak memory 221144 kb
Host smart-b46d5b32-9cb1-49ef-b6cc-a5388d9f4485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775781599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2775781599
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3647664286
Short name T927
Test name
Test status
Simulation time 958196117 ps
CPU time 4.73 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:58 PM PDT 24
Peak memory 216076 kb
Host smart-e514d26c-1d1c-498f-90e7-227ef8fcf84f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647664286 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3647664286
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.343580967
Short name T1441
Test name
Test status
Simulation time 151543639 ps
CPU time 0.97 seconds
Started Jul 17 05:46:53 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 205412 kb
Host smart-5e1a7fb0-56b1-4c35-955a-f3667bc9b527
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343580967 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.343580967
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.1761889766
Short name T1357
Test name
Test status
Simulation time 272418424 ps
CPU time 1.57 seconds
Started Jul 17 05:46:53 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 208136 kb
Host smart-348e46a2-6fd8-4603-a0a3-8a6c440607bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761889766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.1761889766
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.3976731401
Short name T1059
Test name
Test status
Simulation time 2430375483 ps
CPU time 2.35 seconds
Started Jul 17 05:47:15 PM PDT 24
Finished Jul 17 05:47:19 PM PDT 24
Peak memory 205704 kb
Host smart-e200347c-db2f-401d-9202-b1b5a2b1cceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976731401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.3976731401
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.2219770178
Short name T1040
Test name
Test status
Simulation time 640290906 ps
CPU time 1.57 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:55 PM PDT 24
Peak memory 205448 kb
Host smart-390c6915-2a6a-4fb5-93ce-768095fb5c41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219770178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.2219770178
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.157522486
Short name T614
Test name
Test status
Simulation time 424931251 ps
CPU time 2.39 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 213808 kb
Host smart-098cc2fd-2c4a-4589-9111-0bd43f75ef8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157522486 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_hrst.157522486
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.948087912
Short name T1692
Test name
Test status
Simulation time 3105526220 ps
CPU time 3.87 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:00 PM PDT 24
Peak memory 218500 kb
Host smart-e2cdb09b-a96c-4289-81d8-e10aeb45b378
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948087912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.948087912
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3964894532
Short name T59
Test name
Test status
Simulation time 15579543145 ps
CPU time 20.19 seconds
Started Jul 17 05:47:16 PM PDT 24
Finished Jul 17 05:47:37 PM PDT 24
Peak memory 502844 kb
Host smart-01562edf-6674-4e02-b895-50dd7a51040b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964894532 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3964894532
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.3421561005
Short name T620
Test name
Test status
Simulation time 1248111510 ps
CPU time 3.18 seconds
Started Jul 17 05:46:50 PM PDT 24
Finished Jul 17 05:46:54 PM PDT 24
Peak memory 213808 kb
Host smart-c47b359e-9586-4325-ab20-86b3cda59987
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421561005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_acqfull.3421561005
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.3200304194
Short name T1363
Test name
Test status
Simulation time 572996486 ps
CPU time 2.68 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 205816 kb
Host smart-7554e304-24ff-4976-8d1b-b1ab3d9b3c5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200304194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.3200304194
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.788461818
Short name T344
Test name
Test status
Simulation time 2719997649 ps
CPU time 4.87 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:47:48 PM PDT 24
Peak memory 216176 kb
Host smart-489b34f2-b2a3-4f2d-b11b-5d15552e201f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788461818 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_perf.788461818
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.3505360703
Short name T389
Test name
Test status
Simulation time 1903025672 ps
CPU time 2.17 seconds
Started Jul 17 05:46:49 PM PDT 24
Finished Jul 17 05:46:52 PM PDT 24
Peak memory 205420 kb
Host smart-8a35604c-a35e-45db-9851-f17d94168d95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505360703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_smbus_maxlen.3505360703
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2258793798
Short name T921
Test name
Test status
Simulation time 4412864341 ps
CPU time 16.25 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:12 PM PDT 24
Peak memory 213800 kb
Host smart-09e744cc-eaa1-4b83-a00e-95c8f0c54f0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258793798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2258793798
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.3815674081
Short name T1046
Test name
Test status
Simulation time 22966880024 ps
CPU time 34.98 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:31 PM PDT 24
Peak memory 264700 kb
Host smart-aa0c03a8-dfe7-405c-b733-dfe8ad64a754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815674081 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.3815674081
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.1318944038
Short name T1393
Test name
Test status
Simulation time 16400708351 ps
CPU time 18.39 seconds
Started Jul 17 05:47:15 PM PDT 24
Finished Jul 17 05:47:35 PM PDT 24
Peak memory 223576 kb
Host smart-dbfd6114-a81f-4c84-9577-108c513c3bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318944038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.1318944038
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.490154441
Short name T1622
Test name
Test status
Simulation time 56361328282 ps
CPU time 2172.88 seconds
Started Jul 17 05:46:50 PM PDT 24
Finished Jul 17 06:23:05 PM PDT 24
Peak memory 9247692 kb
Host smart-bd9113d6-e062-4770-8c4e-758f6bf45699
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490154441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_wr.490154441
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1521765240
Short name T871
Test name
Test status
Simulation time 3381476759 ps
CPU time 12.34 seconds
Started Jul 17 05:46:50 PM PDT 24
Finished Jul 17 05:47:04 PM PDT 24
Peak memory 346504 kb
Host smart-1895d061-5596-46a2-a446-d2df1208ee8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521765240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1521765240
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2485412138
Short name T864
Test name
Test status
Simulation time 2673348736 ps
CPU time 7.6 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:03 PM PDT 24
Peak memory 220840 kb
Host smart-284b54b7-8816-4f6c-951e-1d45b8041a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485412138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2485412138
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.3073543448
Short name T1659
Test name
Test status
Simulation time 121075260 ps
CPU time 2.01 seconds
Started Jul 17 05:47:24 PM PDT 24
Finished Jul 17 05:47:28 PM PDT 24
Peak memory 205612 kb
Host smart-afac20d3-6040-4591-be13-a6ae6652612f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073543448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.3073543448
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2262491946
Short name T630
Test name
Test status
Simulation time 18823928 ps
CPU time 0.63 seconds
Started Jul 17 05:47:04 PM PDT 24
Finished Jul 17 05:47:07 PM PDT 24
Peak memory 204816 kb
Host smart-48a6e403-b267-4625-af2a-aadb3811dc80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262491946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2262491946
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3630020915
Short name T1526
Test name
Test status
Simulation time 77157374 ps
CPU time 1.78 seconds
Started Jul 17 05:47:36 PM PDT 24
Finished Jul 17 05:47:39 PM PDT 24
Peak memory 213916 kb
Host smart-8794e4ba-6566-400c-afab-4c19b40bb909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630020915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3630020915
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1430316456
Short name T454
Test name
Test status
Simulation time 892110127 ps
CPU time 8.95 seconds
Started Jul 17 05:47:04 PM PDT 24
Finished Jul 17 05:47:14 PM PDT 24
Peak memory 286684 kb
Host smart-88afa200-df91-4680-88a5-02fac24eb23f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430316456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1430316456
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.548234505
Short name T151
Test name
Test status
Simulation time 6489902713 ps
CPU time 85.63 seconds
Started Jul 17 05:47:05 PM PDT 24
Finished Jul 17 05:48:32 PM PDT 24
Peak memory 215540 kb
Host smart-f031b700-ce05-4804-b5e6-079df966260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548234505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.548234505
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2473211706
Short name T689
Test name
Test status
Simulation time 8005044614 ps
CPU time 55.54 seconds
Started Jul 17 05:46:54 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 617360 kb
Host smart-a116d535-9b5c-40ac-8e14-e1507b47a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473211706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2473211706
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3157886197
Short name T1474
Test name
Test status
Simulation time 117145380 ps
CPU time 0.92 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:47:43 PM PDT 24
Peak memory 205172 kb
Host smart-0e5a7532-26c1-4ea9-9a68-402f555c7b48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157886197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3157886197
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2691370581
Short name T448
Test name
Test status
Simulation time 331442493 ps
CPU time 4.08 seconds
Started Jul 17 05:47:03 PM PDT 24
Finished Jul 17 05:47:09 PM PDT 24
Peak memory 205508 kb
Host smart-dc45f53c-35f1-4a5c-8c41-49e5e6632939
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691370581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2691370581
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.2241662751
Short name T919
Test name
Test status
Simulation time 20178869492 ps
CPU time 133.23 seconds
Started Jul 17 05:47:28 PM PDT 24
Finished Jul 17 05:49:44 PM PDT 24
Peak memory 1493292 kb
Host smart-03c0eb7d-e90b-465b-be24-e3bed9818c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241662751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.2241662751
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2845724664
Short name T1130
Test name
Test status
Simulation time 838742043 ps
CPU time 5.38 seconds
Started Jul 17 05:47:06 PM PDT 24
Finished Jul 17 05:47:13 PM PDT 24
Peak memory 205516 kb
Host smart-08b24f28-dc06-40db-9883-c32d0574e76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845724664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2845724664
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_override.2909567855
Short name T1751
Test name
Test status
Simulation time 18245730 ps
CPU time 0.65 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:47:41 PM PDT 24
Peak memory 205188 kb
Host smart-1e9829af-de60-4100-a11b-3c171afef43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909567855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2909567855
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3603967439
Short name T493
Test name
Test status
Simulation time 6424567661 ps
CPU time 81.38 seconds
Started Jul 17 05:47:03 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 205548 kb
Host smart-2a3b100c-d66c-4ee4-a76f-fc03dd7f2fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603967439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3603967439
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.2955787294
Short name T1301
Test name
Test status
Simulation time 223226865 ps
CPU time 3.55 seconds
Started Jul 17 05:47:01 PM PDT 24
Finished Jul 17 05:47:06 PM PDT 24
Peak memory 205440 kb
Host smart-2c4f6e35-fb91-45bb-b949-53c34cd159b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955787294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.2955787294
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2427492410
Short name T377
Test name
Test status
Simulation time 5405048762 ps
CPU time 68.9 seconds
Started Jul 17 05:46:53 PM PDT 24
Finished Jul 17 05:48:03 PM PDT 24
Peak memory 348044 kb
Host smart-e5bacf51-0d14-48bb-934c-ca2daf486586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427492410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2427492410
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.4242168859
Short name T117
Test name
Test status
Simulation time 40379152307 ps
CPU time 1858.48 seconds
Started Jul 17 05:47:02 PM PDT 24
Finished Jul 17 06:18:01 PM PDT 24
Peak memory 3015724 kb
Host smart-e2e2f41a-2699-46df-b729-0356a24ba474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242168859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.4242168859
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.833156324
Short name T1049
Test name
Test status
Simulation time 2535020984 ps
CPU time 11.71 seconds
Started Jul 17 05:47:05 PM PDT 24
Finished Jul 17 05:47:18 PM PDT 24
Peak memory 221924 kb
Host smart-39949036-8f1b-4ff8-8eea-623c4b438e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833156324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.833156324
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2086215978
Short name T1391
Test name
Test status
Simulation time 7179018544 ps
CPU time 6.06 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:57 PM PDT 24
Peak memory 210228 kb
Host smart-3d010719-c6a8-4794-960d-5c2391ceeba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086215978 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2086215978
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.357056685
Short name T1661
Test name
Test status
Simulation time 522921941 ps
CPU time 1.09 seconds
Started Jul 17 05:47:03 PM PDT 24
Finished Jul 17 05:47:06 PM PDT 24
Peak memory 205392 kb
Host smart-3da15679-56bc-473a-b6d8-dd13ff7d1ace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357056685 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_acq.357056685
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2981450620
Short name T317
Test name
Test status
Simulation time 466280247 ps
CPU time 1.16 seconds
Started Jul 17 05:47:02 PM PDT 24
Finished Jul 17 05:47:04 PM PDT 24
Peak memory 205400 kb
Host smart-9cf3cac4-e74b-49c1-822e-d8b9f2458a1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981450620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2981450620
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.139089122
Short name T1309
Test name
Test status
Simulation time 323069628 ps
CPU time 1.95 seconds
Started Jul 17 05:47:00 PM PDT 24
Finished Jul 17 05:47:03 PM PDT 24
Peak memory 205340 kb
Host smart-86dda907-1540-4009-a4bf-9fbac3a6634f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139089122 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.139089122
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.1898010111
Short name T1197
Test name
Test status
Simulation time 250843211 ps
CPU time 1.07 seconds
Started Jul 17 05:47:03 PM PDT 24
Finished Jul 17 05:47:05 PM PDT 24
Peak memory 205264 kb
Host smart-9930523e-2f88-40dd-99ce-84648d706dd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898010111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.1898010111
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.3783942609
Short name T397
Test name
Test status
Simulation time 218774879 ps
CPU time 1.49 seconds
Started Jul 17 05:47:23 PM PDT 24
Finished Jul 17 05:47:25 PM PDT 24
Peak memory 221972 kb
Host smart-03829904-7e2d-45f3-aff4-2ec954ad46bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783942609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.3783942609
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.981724337
Short name T1402
Test name
Test status
Simulation time 685316713 ps
CPU time 3.61 seconds
Started Jul 17 05:47:01 PM PDT 24
Finished Jul 17 05:47:05 PM PDT 24
Peak memory 217912 kb
Host smart-cf2fd544-108c-42e4-b067-2e76b1cdcf3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981724337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.981724337
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3156807728
Short name T801
Test name
Test status
Simulation time 27116275259 ps
CPU time 222.48 seconds
Started Jul 17 05:47:02 PM PDT 24
Finished Jul 17 05:50:45 PM PDT 24
Peak memory 2880436 kb
Host smart-fb379376-f469-43b5-b667-55381e1b8461
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156807728 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3156807728
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.3937884293
Short name T1317
Test name
Test status
Simulation time 816117392 ps
CPU time 2.62 seconds
Started Jul 17 05:47:02 PM PDT 24
Finished Jul 17 05:47:06 PM PDT 24
Peak memory 213772 kb
Host smart-8bf0ddf7-30d0-4b7c-822f-275d7c88be16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937884293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_nack_acqfull.3937884293
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.1696463160
Short name T60
Test name
Test status
Simulation time 493424428 ps
CPU time 2.73 seconds
Started Jul 17 05:47:04 PM PDT 24
Finished Jul 17 05:47:08 PM PDT 24
Peak memory 205632 kb
Host smart-c62580c2-d220-4649-93b4-f48fd165eef7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696463160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.1696463160
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_txstretch.457339259
Short name T1677
Test name
Test status
Simulation time 1953157452 ps
CPU time 1.6 seconds
Started Jul 17 05:47:03 PM PDT 24
Finished Jul 17 05:47:06 PM PDT 24
Peak memory 222216 kb
Host smart-f729f541-99c1-43b1-b412-65e381dd1ecf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457339259 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_nack_txstretch.457339259
Directory /workspace/31.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/31.i2c_target_perf.712735431
Short name T712
Test name
Test status
Simulation time 979851996 ps
CPU time 7.09 seconds
Started Jul 17 05:47:06 PM PDT 24
Finished Jul 17 05:47:14 PM PDT 24
Peak memory 220996 kb
Host smart-3131cffc-e9a9-4f85-ac05-e3283ec83dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712735431 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_perf.712735431
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.1047249275
Short name T429
Test name
Test status
Simulation time 1002106141 ps
CPU time 2.15 seconds
Started Jul 17 05:47:00 PM PDT 24
Finished Jul 17 05:47:02 PM PDT 24
Peak memory 205412 kb
Host smart-8bc6b649-42e1-4597-8b32-199f4a4b743c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047249275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.1047249275
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3725918682
Short name T1347
Test name
Test status
Simulation time 549081382 ps
CPU time 8.36 seconds
Started Jul 17 05:47:26 PM PDT 24
Finished Jul 17 05:47:36 PM PDT 24
Peak memory 213856 kb
Host smart-86035782-62d0-4a82-b1df-0d31fe6faea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725918682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3725918682
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.760370336
Short name T1728
Test name
Test status
Simulation time 43090191848 ps
CPU time 123.38 seconds
Started Jul 17 05:47:03 PM PDT 24
Finished Jul 17 05:49:07 PM PDT 24
Peak memory 847424 kb
Host smart-31336354-e3b7-44bf-b99c-8b874299ee01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760370336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.i2c_target_stress_all.760370336
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.3285272685
Short name T1100
Test name
Test status
Simulation time 413482038 ps
CPU time 17.77 seconds
Started Jul 17 05:47:04 PM PDT 24
Finished Jul 17 05:47:24 PM PDT 24
Peak memory 205596 kb
Host smart-643d462a-28b4-416b-bcf1-e9cd84276efa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285272685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.3285272685
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2117365738
Short name T748
Test name
Test status
Simulation time 57721005448 ps
CPU time 63.29 seconds
Started Jul 17 05:47:00 PM PDT 24
Finished Jul 17 05:48:03 PM PDT 24
Peak memory 930780 kb
Host smart-d9d13066-a026-4306-8d6f-a6c2a9ea2f31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117365738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2117365738
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.3392861636
Short name T1162
Test name
Test status
Simulation time 2904244583 ps
CPU time 2.4 seconds
Started Jul 17 05:47:04 PM PDT 24
Finished Jul 17 05:47:08 PM PDT 24
Peak memory 213888 kb
Host smart-263013dd-0dcc-47b0-99c0-fb3d0ddf44b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392861636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.3392861636
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2921716448
Short name T1540
Test name
Test status
Simulation time 7529750658 ps
CPU time 7.23 seconds
Started Jul 17 05:47:01 PM PDT 24
Finished Jul 17 05:47:08 PM PDT 24
Peak memory 232888 kb
Host smart-aa6eddd4-edcb-4807-8198-91452d962ecc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921716448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2921716448
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.2406037495
Short name T1735
Test name
Test status
Simulation time 427331469 ps
CPU time 5.92 seconds
Started Jul 17 05:47:01 PM PDT 24
Finished Jul 17 05:47:08 PM PDT 24
Peak memory 205632 kb
Host smart-3e4f8c92-d5e2-4a47-94da-c8ba0f01aa0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406037495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2406037495
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3832121810
Short name T555
Test name
Test status
Simulation time 39607881 ps
CPU time 0.69 seconds
Started Jul 17 05:47:18 PM PDT 24
Finished Jul 17 05:47:21 PM PDT 24
Peak memory 204832 kb
Host smart-84c338a9-eab1-466d-a1df-390777d741bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832121810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3832121810
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3701768026
Short name T1442
Test name
Test status
Simulation time 2742443584 ps
CPU time 19.65 seconds
Started Jul 17 05:47:19 PM PDT 24
Finished Jul 17 05:47:40 PM PDT 24
Peak memory 297764 kb
Host smart-1850c70e-1797-47f4-bfe0-3e45eb1cea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701768026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3701768026
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1988456258
Short name T1733
Test name
Test status
Simulation time 1269646796 ps
CPU time 16.84 seconds
Started Jul 17 05:47:23 PM PDT 24
Finished Jul 17 05:47:41 PM PDT 24
Peak memory 276652 kb
Host smart-fb71e74b-dd6c-4bf8-b8e5-c253745aa91a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988456258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1988456258
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2619448813
Short name T1359
Test name
Test status
Simulation time 1840841632 ps
CPU time 40.75 seconds
Started Jul 17 05:47:16 PM PDT 24
Finished Jul 17 05:47:58 PM PDT 24
Peak memory 321120 kb
Host smart-d2e44e58-574a-4b8f-a858-7b88d6c042fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619448813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2619448813
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2867219646
Short name T1486
Test name
Test status
Simulation time 2344976478 ps
CPU time 165.33 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:50:25 PM PDT 24
Peak memory 717428 kb
Host smart-a2cb6a08-237b-46d3-a813-d5ab9ceae049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867219646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2867219646
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.650017675
Short name T899
Test name
Test status
Simulation time 2900285344 ps
CPU time 5.16 seconds
Started Jul 17 05:47:36 PM PDT 24
Finished Jul 17 05:47:42 PM PDT 24
Peak memory 205540 kb
Host smart-39558e7c-da96-45c0-9342-bd1c33fae86e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650017675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
650017675
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1341917280
Short name T1338
Test name
Test status
Simulation time 8508104871 ps
CPU time 288.54 seconds
Started Jul 17 05:47:03 PM PDT 24
Finished Jul 17 05:51:52 PM PDT 24
Peak memory 1223656 kb
Host smart-ca7acdb6-672c-4c1b-900c-17d7d8cca16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341917280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1341917280
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.4074950839
Short name T256
Test name
Test status
Simulation time 1101854607 ps
CPU time 7.88 seconds
Started Jul 17 05:47:13 PM PDT 24
Finished Jul 17 05:47:22 PM PDT 24
Peak memory 205532 kb
Host smart-3eae0a34-e710-4970-900b-f3f33c52f534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074950839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.4074950839
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.1185648082
Short name T141
Test name
Test status
Simulation time 54635873 ps
CPU time 0.71 seconds
Started Jul 17 05:47:04 PM PDT 24
Finished Jul 17 05:47:07 PM PDT 24
Peak memory 205212 kb
Host smart-94b70cdb-803a-4c38-86e9-0f1cb70b9953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185648082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1185648082
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1435668609
Short name T586
Test name
Test status
Simulation time 30502350979 ps
CPU time 1668.58 seconds
Started Jul 17 05:47:24 PM PDT 24
Finished Jul 17 06:15:14 PM PDT 24
Peak memory 1001056 kb
Host smart-cb2a1aba-b12e-41b6-b65d-50e4234c083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435668609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1435668609
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.3585025779
Short name T832
Test name
Test status
Simulation time 23367197687 ps
CPU time 108.12 seconds
Started Jul 17 05:47:38 PM PDT 24
Finished Jul 17 05:49:27 PM PDT 24
Peak memory 205544 kb
Host smart-67601ef0-220c-4e48-95bb-da2c056a0aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585025779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.3585025779
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.264518957
Short name T941
Test name
Test status
Simulation time 3530821795 ps
CPU time 35.22 seconds
Started Jul 17 05:47:09 PM PDT 24
Finished Jul 17 05:47:46 PM PDT 24
Peak memory 350232 kb
Host smart-2974be01-620b-4c57-b36e-11e21a62301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264518957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.264518957
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.2199598822
Short name T235
Test name
Test status
Simulation time 29606919400 ps
CPU time 1715.32 seconds
Started Jul 17 05:47:15 PM PDT 24
Finished Jul 17 06:15:53 PM PDT 24
Peak memory 2760664 kb
Host smart-408bfdb2-87a8-48a2-a463-1236909c766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199598822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.2199598822
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3749696146
Short name T1512
Test name
Test status
Simulation time 722749066 ps
CPU time 15.44 seconds
Started Jul 17 05:47:13 PM PDT 24
Finished Jul 17 05:47:30 PM PDT 24
Peak memory 213660 kb
Host smart-04382700-0a7d-47b6-9894-492d5ed2663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749696146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3749696146
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.739742525
Short name T1510
Test name
Test status
Simulation time 1190677870 ps
CPU time 6.42 seconds
Started Jul 17 05:47:23 PM PDT 24
Finished Jul 17 05:47:31 PM PDT 24
Peak memory 222052 kb
Host smart-1bfaf307-5e56-4673-8a4a-f882c9b79e30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739742525 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.739742525
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.663035986
Short name T1496
Test name
Test status
Simulation time 1028118730 ps
CPU time 1.12 seconds
Started Jul 17 05:47:22 PM PDT 24
Finished Jul 17 05:47:24 PM PDT 24
Peak memory 205472 kb
Host smart-3816418c-76d0-4c09-9647-bde58627a5fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663035986 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.663035986
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1195737614
Short name T1696
Test name
Test status
Simulation time 1056749467 ps
CPU time 1.08 seconds
Started Jul 17 05:47:13 PM PDT 24
Finished Jul 17 05:47:16 PM PDT 24
Peak memory 205600 kb
Host smart-117b83a2-d998-429f-9b09-59553e5ae405
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195737614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1195737614
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.2000780050
Short name T1470
Test name
Test status
Simulation time 1070009997 ps
CPU time 2.66 seconds
Started Jul 17 05:47:37 PM PDT 24
Finished Jul 17 05:47:41 PM PDT 24
Peak memory 205648 kb
Host smart-a588f5a5-051f-47a8-b586-0ccd73c89c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000780050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.2000780050
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.3092492913
Short name T1152
Test name
Test status
Simulation time 235593593 ps
CPU time 1.31 seconds
Started Jul 17 05:47:16 PM PDT 24
Finished Jul 17 05:47:19 PM PDT 24
Peak memory 205444 kb
Host smart-c9c56b69-76bb-4060-a01c-c4419563a1b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092492913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.3092492913
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.1187800448
Short name T1134
Test name
Test status
Simulation time 442548125 ps
CPU time 1.8 seconds
Started Jul 17 05:47:11 PM PDT 24
Finished Jul 17 05:47:14 PM PDT 24
Peak memory 213832 kb
Host smart-bd0eab14-afe1-4584-b673-c0e5bb5187ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187800448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.1187800448
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2244237002
Short name T1408
Test name
Test status
Simulation time 1018022015 ps
CPU time 5.94 seconds
Started Jul 17 05:47:25 PM PDT 24
Finished Jul 17 05:47:33 PM PDT 24
Peak memory 218016 kb
Host smart-d40ca166-59e4-46f7-81af-cbab2e201775
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244237002 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2244237002
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2343816556
Short name T896
Test name
Test status
Simulation time 19380384295 ps
CPU time 17.03 seconds
Started Jul 17 05:47:19 PM PDT 24
Finished Jul 17 05:47:37 PM PDT 24
Peak memory 563224 kb
Host smart-d558989b-a434-4029-bbd2-a89e7a6d7563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343816556 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2343816556
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.4117388257
Short name T1525
Test name
Test status
Simulation time 584690923 ps
CPU time 3.01 seconds
Started Jul 17 05:47:18 PM PDT 24
Finished Jul 17 05:47:23 PM PDT 24
Peak memory 213848 kb
Host smart-e606412c-85cf-43ae-a694-0f2766f48ba4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117388257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_nack_acqfull.4117388257
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_txstretch.2913432494
Short name T500
Test name
Test status
Simulation time 286614958 ps
CPU time 1.3 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:48 PM PDT 24
Peak memory 222180 kb
Host smart-e532125e-1a9e-4887-bb64-d45d9ccbef1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913432494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_nack_txstretch.2913432494
Directory /workspace/32.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/32.i2c_target_perf.648432623
Short name T893
Test name
Test status
Simulation time 1082087594 ps
CPU time 4.04 seconds
Started Jul 17 05:47:17 PM PDT 24
Finished Jul 17 05:47:23 PM PDT 24
Peak memory 221772 kb
Host smart-37a12fb1-fcd1-4097-ba00-2e209bdf2fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648432623 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_perf.648432623
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.1016643493
Short name T549
Test name
Test status
Simulation time 490614431 ps
CPU time 2.29 seconds
Started Jul 17 05:47:28 PM PDT 24
Finished Jul 17 05:47:32 PM PDT 24
Peak memory 205332 kb
Host smart-6e6f1616-b882-4e7e-b9c1-bd18e12307b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016643493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_smbus_maxlen.1016643493
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2760837285
Short name T320
Test name
Test status
Simulation time 2584052696 ps
CPU time 20.19 seconds
Started Jul 17 05:47:25 PM PDT 24
Finished Jul 17 05:47:47 PM PDT 24
Peak memory 213876 kb
Host smart-7d63906d-6424-4112-acc7-0b1e77e9135b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760837285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2760837285
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.4156135967
Short name T557
Test name
Test status
Simulation time 48509180893 ps
CPU time 133.24 seconds
Started Jul 17 05:47:14 PM PDT 24
Finished Jul 17 05:49:29 PM PDT 24
Peak memory 951404 kb
Host smart-f2fa7a9d-7a25-4f09-9849-b1b19905f4c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156135967 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.4156135967
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3277470009
Short name T1001
Test name
Test status
Simulation time 1470789841 ps
CPU time 8.98 seconds
Started Jul 17 05:47:25 PM PDT 24
Finished Jul 17 05:47:35 PM PDT 24
Peak memory 205656 kb
Host smart-24ca9054-8b5f-45d1-b3b5-db5652eebf30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277470009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3277470009
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1740574692
Short name T321
Test name
Test status
Simulation time 8166422199 ps
CPU time 14.32 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:48:01 PM PDT 24
Peak memory 205636 kb
Host smart-2e2accfd-77db-4061-b7f4-bde836ead1fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740574692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1740574692
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1905774227
Short name T613
Test name
Test status
Simulation time 4709068888 ps
CPU time 51.62 seconds
Started Jul 17 05:47:37 PM PDT 24
Finished Jul 17 05:48:30 PM PDT 24
Peak memory 895200 kb
Host smart-60025a01-dffa-4357-8155-b149773ec62a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905774227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1905774227
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.731158959
Short name T1019
Test name
Test status
Simulation time 1558513698 ps
CPU time 7.58 seconds
Started Jul 17 05:47:15 PM PDT 24
Finished Jul 17 05:47:24 PM PDT 24
Peak memory 219764 kb
Host smart-0ffcc725-2691-454c-8698-61f8f983f0aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731158959 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.731158959
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.2117971211
Short name T987
Test name
Test status
Simulation time 199751239 ps
CPU time 2.63 seconds
Started Jul 17 05:47:25 PM PDT 24
Finished Jul 17 05:47:29 PM PDT 24
Peak memory 205616 kb
Host smart-eab03ffb-5885-4c16-a7f6-d514afffb2a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117971211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.2117971211
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.424088567
Short name T178
Test name
Test status
Simulation time 34627497 ps
CPU time 0.61 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 204708 kb
Host smart-8a96b477-1d9e-45e5-a3b9-62e2625e6210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424088567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.424088567
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.4007645588
Short name T1062
Test name
Test status
Simulation time 950759296 ps
CPU time 1.55 seconds
Started Jul 17 05:47:38 PM PDT 24
Finished Jul 17 05:47:41 PM PDT 24
Peak memory 213824 kb
Host smart-cabf135f-36b5-41ca-a48d-541a6fbb8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007645588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.4007645588
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1879299148
Short name T1571
Test name
Test status
Simulation time 113554636 ps
CPU time 2.17 seconds
Started Jul 17 05:47:36 PM PDT 24
Finished Jul 17 05:47:39 PM PDT 24
Peak memory 208536 kb
Host smart-86cdbc29-f4be-496a-a30e-28d863319260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879299148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1879299148
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3558992395
Short name T536
Test name
Test status
Simulation time 2668280720 ps
CPU time 75.83 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 489844 kb
Host smart-a7143e2d-ce01-4712-8cb8-9a054174c806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558992395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3558992395
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2475074629
Short name T667
Test name
Test status
Simulation time 4309824951 ps
CPU time 59.46 seconds
Started Jul 17 05:47:19 PM PDT 24
Finished Jul 17 05:48:20 PM PDT 24
Peak memory 652772 kb
Host smart-b99e32b2-9fc5-4bce-a610-76be2de962ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475074629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2475074629
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3618125843
Short name T34
Test name
Test status
Simulation time 272375751 ps
CPU time 0.81 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:47:52 PM PDT 24
Peak memory 205164 kb
Host smart-0673a983-4cd4-4f13-9ee3-8476af17d666
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618125843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.3618125843
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.65510063
Short name T350
Test name
Test status
Simulation time 194985517 ps
CPU time 10.65 seconds
Started Jul 17 05:47:30 PM PDT 24
Finished Jul 17 05:47:43 PM PDT 24
Peak memory 239324 kb
Host smart-37e14190-abc7-4a45-9055-7f579e6a006a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65510063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.65510063
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2969634178
Short name T118
Test name
Test status
Simulation time 38759067545 ps
CPU time 128.98 seconds
Started Jul 17 05:47:13 PM PDT 24
Finished Jul 17 05:49:23 PM PDT 24
Peak memory 1491880 kb
Host smart-27951d8b-9b82-4b44-a2af-8382cf427002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969634178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2969634178
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.19125950
Short name T249
Test name
Test status
Simulation time 1711782648 ps
CPU time 4.74 seconds
Started Jul 17 05:47:34 PM PDT 24
Finished Jul 17 05:47:40 PM PDT 24
Peak memory 205468 kb
Host smart-6c204bb5-32b4-44df-8c8a-8a0a4311373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19125950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.19125950
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.634792984
Short name T140
Test name
Test status
Simulation time 110936088 ps
CPU time 0.67 seconds
Started Jul 17 05:47:18 PM PDT 24
Finished Jul 17 05:47:21 PM PDT 24
Peak memory 205244 kb
Host smart-0b08bf9a-28a0-4481-99a1-ba343c1b0053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634792984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.634792984
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.176226569
Short name T1129
Test name
Test status
Simulation time 49413597566 ps
CPU time 186.94 seconds
Started Jul 17 05:47:30 PM PDT 24
Finished Jul 17 05:50:39 PM PDT 24
Peak memory 213772 kb
Host smart-a7d43737-4961-49fe-89ad-deda6e8d09e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176226569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.176226569
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.4021567019
Short name T1639
Test name
Test status
Simulation time 6803011775 ps
CPU time 26.47 seconds
Started Jul 17 05:47:27 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 205504 kb
Host smart-af5f6d0d-0c51-423e-b08b-b83f9da2b2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021567019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.4021567019
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3260575190
Short name T342
Test name
Test status
Simulation time 2862190442 ps
CPU time 63.98 seconds
Started Jul 17 05:47:14 PM PDT 24
Finished Jul 17 05:48:20 PM PDT 24
Peak memory 288524 kb
Host smart-a8970674-d6ee-4646-9794-994d699b7ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260575190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3260575190
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.860667163
Short name T950
Test name
Test status
Simulation time 2979359103 ps
CPU time 12.55 seconds
Started Jul 17 05:47:27 PM PDT 24
Finished Jul 17 05:47:41 PM PDT 24
Peak memory 216032 kb
Host smart-30d4b2b6-8116-44ba-b753-3eb428bc6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860667163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.860667163
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3190038129
Short name T1724
Test name
Test status
Simulation time 4651436454 ps
CPU time 6.53 seconds
Started Jul 17 05:47:27 PM PDT 24
Finished Jul 17 05:47:36 PM PDT 24
Peak memory 214328 kb
Host smart-bc83b700-80b0-40c3-a4a8-89aae08f59de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190038129 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3190038129
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.1460477324
Short name T98
Test name
Test status
Simulation time 491924958 ps
CPU time 1.14 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:47:42 PM PDT 24
Peak memory 205472 kb
Host smart-a7beeb7d-a38d-4065-b68a-686c157fab56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460477324 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.1460477324
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3931652522
Short name T1524
Test name
Test status
Simulation time 175763273 ps
CPU time 1.16 seconds
Started Jul 17 05:47:31 PM PDT 24
Finished Jul 17 05:47:33 PM PDT 24
Peak memory 205640 kb
Host smart-d6ac2040-f715-47d2-8487-d59a58d1b21d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931652522 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3931652522
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.4231689171
Short name T625
Test name
Test status
Simulation time 695265158 ps
CPU time 2.14 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 205440 kb
Host smart-873c1466-581e-414f-92e0-113ac7bce8e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231689171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.4231689171
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.2008657825
Short name T1656
Test name
Test status
Simulation time 173672750 ps
CPU time 1.26 seconds
Started Jul 17 05:47:33 PM PDT 24
Finished Jul 17 05:47:35 PM PDT 24
Peak memory 205428 kb
Host smart-1e2bea96-dbe6-4317-b47c-91111ad0a4f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008657825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.2008657825
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2743899308
Short name T1245
Test name
Test status
Simulation time 5676436709 ps
CPU time 7.76 seconds
Started Jul 17 05:47:27 PM PDT 24
Finished Jul 17 05:47:36 PM PDT 24
Peak memory 222016 kb
Host smart-d2213a80-0ca0-47f4-a389-65919ee5ef7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743899308 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2743899308
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.939286354
Short name T1516
Test name
Test status
Simulation time 6128433959 ps
CPU time 4.99 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:52 PM PDT 24
Peak memory 299312 kb
Host smart-9cfffdd1-77a9-4c13-bfc7-8239bc056702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939286354 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.939286354
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.3914971226
Short name T156
Test name
Test status
Simulation time 515968783 ps
CPU time 2.8 seconds
Started Jul 17 05:47:27 PM PDT 24
Finished Jul 17 05:47:32 PM PDT 24
Peak memory 213800 kb
Host smart-bdfb17da-f77f-4e46-9be3-65cc2da8d88f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914971226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.3914971226
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.127948053
Short name T1641
Test name
Test status
Simulation time 6691413237 ps
CPU time 2.76 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:47:44 PM PDT 24
Peak memory 205692 kb
Host smart-e7fe9d8e-8429-4e1f-8ad8-d272cd870f85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127948053 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.127948053
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.2209581838
Short name T939
Test name
Test status
Simulation time 1610384441 ps
CPU time 4.39 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 05:47:36 PM PDT 24
Peak memory 222072 kb
Host smart-a33895d3-ea3f-4c97-b9bc-8a8271a76db2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209581838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.2209581838
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.1901057417
Short name T1570
Test name
Test status
Simulation time 1225284971 ps
CPU time 2.38 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:49 PM PDT 24
Peak memory 205316 kb
Host smart-469d5f65-b990-47b5-92bc-b388a32b9d87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901057417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.1901057417
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3376509486
Short name T1471
Test name
Test status
Simulation time 1477673189 ps
CPU time 9.92 seconds
Started Jul 17 05:47:30 PM PDT 24
Finished Jul 17 05:47:42 PM PDT 24
Peak memory 213804 kb
Host smart-26aceace-a7a6-4e56-ad3c-c8a46f79e9a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376509486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3376509486
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.3450253670
Short name T997
Test name
Test status
Simulation time 34264966399 ps
CPU time 237.17 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 05:51:29 PM PDT 24
Peak memory 2331056 kb
Host smart-98adf314-3dd0-4107-87e4-5ae8bb91660c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450253670 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.3450253670
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3590405447
Short name T335
Test name
Test status
Simulation time 1462639917 ps
CPU time 29.22 seconds
Started Jul 17 05:47:28 PM PDT 24
Finished Jul 17 05:47:59 PM PDT 24
Peak memory 230324 kb
Host smart-cc9d55d4-1265-4be8-ab62-edead6e73b26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590405447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3590405447
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2781397759
Short name T1071
Test name
Test status
Simulation time 45561631202 ps
CPU time 104.95 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 1480188 kb
Host smart-abbe6bf2-4e6a-454f-a681-47bf7fb7b890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781397759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2781397759
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3332373954
Short name T592
Test name
Test status
Simulation time 3746339191 ps
CPU time 73.8 seconds
Started Jul 17 05:47:31 PM PDT 24
Finished Jul 17 05:48:46 PM PDT 24
Peak memory 977852 kb
Host smart-54e71147-2784-4a20-a182-abeeea7518dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332373954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3332373954
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2473171746
Short name T443
Test name
Test status
Simulation time 1288678683 ps
CPU time 7.17 seconds
Started Jul 17 05:47:32 PM PDT 24
Finished Jul 17 05:47:40 PM PDT 24
Peak memory 221980 kb
Host smart-2164e58d-169f-4c09-ab01-29e4df64b3e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473171746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2473171746
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.1754230425
Short name T1532
Test name
Test status
Simulation time 109164896 ps
CPU time 2.38 seconds
Started Jul 17 05:47:33 PM PDT 24
Finished Jul 17 05:47:36 PM PDT 24
Peak memory 205608 kb
Host smart-1a4c8698-1497-44bb-a35a-37385ddca7c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754230425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.1754230425
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3108756534
Short name T775
Test name
Test status
Simulation time 17616192 ps
CPU time 0.63 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 204736 kb
Host smart-7dc934bd-d4fb-4ea3-93aa-459d89d999e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108756534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3108756534
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3847650597
Short name T498
Test name
Test status
Simulation time 156796517 ps
CPU time 1.75 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:50 PM PDT 24
Peak memory 213768 kb
Host smart-2d1d7f10-d60a-4e1b-b7f7-177b703e9ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847650597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3847650597
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3931060180
Short name T125
Test name
Test status
Simulation time 1805954807 ps
CPU time 5.94 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 249840 kb
Host smart-c9e03c08-9784-4a18-8b28-f9b99b6692c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931060180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3931060180
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.766229387
Short name T1505
Test name
Test status
Simulation time 8420793816 ps
CPU time 46.76 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:48:33 PM PDT 24
Peak memory 288476 kb
Host smart-d28f10ec-af9b-4fe9-a43a-d17fb766a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766229387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.766229387
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.140920780
Short name T1565
Test name
Test status
Simulation time 10628957030 ps
CPU time 92.26 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:49:22 PM PDT 24
Peak memory 844848 kb
Host smart-12e62932-78ef-4ade-9317-642c396964bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140920780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.140920780
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2073212053
Short name T241
Test name
Test status
Simulation time 365222564 ps
CPU time 1.07 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:47:52 PM PDT 24
Peak memory 205424 kb
Host smart-5cf25c41-ff84-4111-aa05-bb4f4cb759a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073212053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2073212053
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3991759581
Short name T545
Test name
Test status
Simulation time 654397500 ps
CPU time 4.76 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:47:56 PM PDT 24
Peak memory 233392 kb
Host smart-aefd67a2-e714-48e4-9ab5-6d32f07ae20e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991759581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3991759581
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3725800766
Short name T1461
Test name
Test status
Simulation time 16605122528 ps
CPU time 120.33 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:49:44 PM PDT 24
Peak memory 1217664 kb
Host smart-dfd15ad8-a9b8-462f-ab0b-ea4623656ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725800766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3725800766
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.3627172200
Short name T22
Test name
Test status
Simulation time 856535744 ps
CPU time 5.45 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:47:58 PM PDT 24
Peak memory 205480 kb
Host smart-a2ee97a4-cfe5-471c-a1e4-75f335a9daac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627172200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3627172200
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.1622281517
Short name T905
Test name
Test status
Simulation time 139751587 ps
CPU time 0.71 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:48 PM PDT 24
Peak memory 205132 kb
Host smart-7eb8246d-9a8f-4dc4-9fb9-69f20ce0040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622281517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1622281517
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.634026825
Short name T1679
Test name
Test status
Simulation time 6338354438 ps
CPU time 5.84 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:55 PM PDT 24
Peak memory 235964 kb
Host smart-fd5da5ed-c024-49cc-a545-907357de43d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634026825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.634026825
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.166091983
Short name T236
Test name
Test status
Simulation time 280342579 ps
CPU time 2.79 seconds
Started Jul 17 05:47:46 PM PDT 24
Finished Jul 17 05:47:56 PM PDT 24
Peak memory 205504 kb
Host smart-7e914109-7990-4e1f-8bfa-c2b26f300789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166091983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.166091983
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3670634683
Short name T1258
Test name
Test status
Simulation time 2633561653 ps
CPU time 62.12 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:48:54 PM PDT 24
Peak memory 307156 kb
Host smart-84a1ca63-25de-4e68-ab54-a3f09dc33b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670634683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3670634683
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.3234709456
Short name T131
Test name
Test status
Simulation time 48793815753 ps
CPU time 353.43 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:53:42 PM PDT 24
Peak memory 1636096 kb
Host smart-f3603e0f-d41a-4833-9384-54309d8ed6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234709456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.3234709456
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.834434166
Short name T279
Test name
Test status
Simulation time 2032805894 ps
CPU time 9.68 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 213904 kb
Host smart-c223675e-5e32-4948-8f7d-b57219b8f5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834434166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.834434166
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.727148268
Short name T1173
Test name
Test status
Simulation time 3051800515 ps
CPU time 4.38 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:47:55 PM PDT 24
Peak memory 214136 kb
Host smart-cfa6a5a2-532d-49fe-9507-0e91f8cb01ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727148268 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.727148268
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.379055872
Short name T1045
Test name
Test status
Simulation time 124613982 ps
CPU time 0.93 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:47:53 PM PDT 24
Peak memory 205444 kb
Host smart-c6bf61ce-5395-46fe-ba61-d54d6682f5ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379055872 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.379055872
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.4166673075
Short name T407
Test name
Test status
Simulation time 136178582 ps
CPU time 0.99 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:47:53 PM PDT 24
Peak memory 205472 kb
Host smart-cde74dfc-07a9-40fe-8d59-f7c1bab8768c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166673075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.4166673075
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.3129708392
Short name T1311
Test name
Test status
Simulation time 2082984297 ps
CPU time 2.73 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:47:46 PM PDT 24
Peak memory 205668 kb
Host smart-df76c2e5-5535-4aba-9f8a-6d73b129d8aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129708392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.3129708392
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.1079617175
Short name T1177
Test name
Test status
Simulation time 166779894 ps
CPU time 1.34 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:47:52 PM PDT 24
Peak memory 205452 kb
Host smart-a8c147a9-5910-43fb-9250-228888da4c68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079617175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1079617175
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3185777174
Short name T1139
Test name
Test status
Simulation time 305321199 ps
CPU time 2.12 seconds
Started Jul 17 05:47:49 PM PDT 24
Finished Jul 17 05:47:56 PM PDT 24
Peak memory 221248 kb
Host smart-18662f8d-0ae1-4dee-ba00-b2dfe6307064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185777174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3185777174
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1509337658
Short name T1030
Test name
Test status
Simulation time 5172240983 ps
CPU time 6.85 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:56 PM PDT 24
Peak memory 222092 kb
Host smart-7b08abea-1123-45ad-9bd4-805786fa8758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509337658 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1509337658
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.3416438838
Short name T349
Test name
Test status
Simulation time 10367472666 ps
CPU time 46.08 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:48:38 PM PDT 24
Peak memory 925800 kb
Host smart-caf8e2d7-d9f4-4771-ad0e-af463525e78b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416438838 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.3416438838
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.3396466410
Short name T66
Test name
Test status
Simulation time 440516707 ps
CPU time 2.72 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:47:55 PM PDT 24
Peak memory 213852 kb
Host smart-4b18710e-3468-4010-b360-590457e57243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396466410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.3396466410
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.2654996234
Short name T833
Test name
Test status
Simulation time 433394213 ps
CPU time 2.5 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 205640 kb
Host smart-2414fe7a-76e0-4643-89f2-cd88407595eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654996234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.2654996234
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_txstretch.2499450640
Short name T623
Test name
Test status
Simulation time 172622617 ps
CPU time 1.45 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:47:53 PM PDT 24
Peak memory 222236 kb
Host smart-031a6898-9f0e-49bd-825f-f544e2fecffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499450640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_nack_txstretch.2499450640
Directory /workspace/34.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/34.i2c_target_perf.1847114795
Short name T1424
Test name
Test status
Simulation time 9090870068 ps
CPU time 4.5 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:55 PM PDT 24
Peak memory 222100 kb
Host smart-3be0a271-c806-4bfa-9195-7780f59ae805
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847114795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.1847114795
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.171209142
Short name T570
Test name
Test status
Simulation time 1025925035 ps
CPU time 2.23 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 205444 kb
Host smart-9c2303aa-c666-447f-b02e-16de1d8b95e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171209142 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_smbus_maxlen.171209142
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.4239161930
Short name T1554
Test name
Test status
Simulation time 2118756202 ps
CPU time 14.88 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:48:06 PM PDT 24
Peak memory 213820 kb
Host smart-cf353cbb-3cc2-4c30-912a-8a564776ebe4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239161930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.4239161930
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.3858626561
Short name T1448
Test name
Test status
Simulation time 43514556006 ps
CPU time 27.54 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:48:10 PM PDT 24
Peak memory 234280 kb
Host smart-c356a755-21e2-40a0-a894-65deb0f08d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858626561 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.3858626561
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1526643052
Short name T1377
Test name
Test status
Simulation time 7463986257 ps
CPU time 39 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:48:30 PM PDT 24
Peak memory 231156 kb
Host smart-356ca10f-4398-49a2-95b8-adcf455c2e7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526643052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1526643052
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.1755994572
Short name T1259
Test name
Test status
Simulation time 50815228758 ps
CPU time 1441.07 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 06:11:44 PM PDT 24
Peak memory 7647864 kb
Host smart-5bcea528-f822-4ccc-9c23-c0b11ae15da2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755994572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.1755994572
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.4132919367
Short name T842
Test name
Test status
Simulation time 3877819101 ps
CPU time 10.77 seconds
Started Jul 17 05:47:45 PM PDT 24
Finished Jul 17 05:48:03 PM PDT 24
Peak memory 254232 kb
Host smart-8889484f-0165-4768-90bf-01f3a7cf4c34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132919367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.4132919367
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2806219439
Short name T760
Test name
Test status
Simulation time 1139506104 ps
CPU time 6.6 seconds
Started Jul 17 05:47:44 PM PDT 24
Finished Jul 17 05:47:58 PM PDT 24
Peak memory 218004 kb
Host smart-930141f3-9bf4-43c8-8ca7-e71799087ce4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806219439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2806219439
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.105001642
Short name T1703
Test name
Test status
Simulation time 89625976 ps
CPU time 1.74 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:51 PM PDT 24
Peak memory 205616 kb
Host smart-0d65ebf7-fbe5-4555-af1e-42d0b285e57a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105001642 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.105001642
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.183546263
Short name T1182
Test name
Test status
Simulation time 17613249 ps
CPU time 0.63 seconds
Started Jul 17 05:47:56 PM PDT 24
Finished Jul 17 05:47:58 PM PDT 24
Peak memory 204744 kb
Host smart-b3b6b88c-7173-4b51-8370-8dab6827e465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183546263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.183546263
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1283939346
Short name T1228
Test name
Test status
Simulation time 1338783444 ps
CPU time 1.46 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 05:48:01 PM PDT 24
Peak memory 213804 kb
Host smart-478922bf-bc8f-4209-a15f-0c400aef45f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283939346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1283939346
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.532205902
Short name T629
Test name
Test status
Simulation time 2542555937 ps
CPU time 22.86 seconds
Started Jul 17 05:47:40 PM PDT 24
Finished Jul 17 05:48:06 PM PDT 24
Peak memory 301032 kb
Host smart-0a617b9b-d801-43f0-94e0-264c4235294f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532205902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empt
y.532205902
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3055659290
Short name T40
Test name
Test status
Simulation time 2774403663 ps
CPU time 87.54 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:49:14 PM PDT 24
Peak memory 310600 kb
Host smart-09d0cbfa-35c4-453e-a073-84c090b5d0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055659290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3055659290
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.988240106
Short name T1127
Test name
Test status
Simulation time 6078996638 ps
CPU time 29.32 seconds
Started Jul 17 05:47:39 PM PDT 24
Finished Jul 17 05:48:10 PM PDT 24
Peak memory 309884 kb
Host smart-7a2a09b4-3e55-4958-aa13-90342a634303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988240106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.988240106
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.6827066
Short name T36
Test name
Test status
Simulation time 160208916 ps
CPU time 1.08 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:52 PM PDT 24
Peak memory 205272 kb
Host smart-6c7c2466-171e-4dc6-81ec-dec5e42eb889
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6827066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.6827066
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.46846842
Short name T660
Test name
Test status
Simulation time 381908667 ps
CPU time 3.06 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:47:54 PM PDT 24
Peak memory 222544 kb
Host smart-ba2f8b2a-9bec-4e0f-bacc-efd6bcf5cb74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46846842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.46846842
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1581906253
Short name T1527
Test name
Test status
Simulation time 6835501591 ps
CPU time 94.22 seconds
Started Jul 17 05:47:42 PM PDT 24
Finished Jul 17 05:49:22 PM PDT 24
Peak memory 1022956 kb
Host smart-77c36379-d774-4834-894f-6aca96eed4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581906253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1581906253
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2328472665
Short name T669
Test name
Test status
Simulation time 994452260 ps
CPU time 3.47 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:48:00 PM PDT 24
Peak memory 205524 kb
Host smart-8096b227-2e56-4d01-a8cd-f03fb022a624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328472665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2328472665
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.1019082353
Short name T365
Test name
Test status
Simulation time 44548356 ps
CPU time 0.64 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:47:45 PM PDT 24
Peak memory 205220 kb
Host smart-3d52b249-624d-461d-94b9-726d469ebeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019082353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1019082353
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2147948652
Short name T1341
Test name
Test status
Simulation time 28080876336 ps
CPU time 83.71 seconds
Started Jul 17 05:47:53 PM PDT 24
Finished Jul 17 05:49:19 PM PDT 24
Peak memory 299936 kb
Host smart-7d95ed2e-b7f8-4a5b-985a-3c92272dbe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147948652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2147948652
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.2156725631
Short name T1131
Test name
Test status
Simulation time 176303681 ps
CPU time 8.23 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:48:05 PM PDT 24
Peak memory 224088 kb
Host smart-2c0b279d-a56a-43f9-b535-cca5b840c0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156725631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2156725631
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.4159546119
Short name T636
Test name
Test status
Simulation time 2159564284 ps
CPU time 33.96 seconds
Started Jul 17 05:47:41 PM PDT 24
Finished Jul 17 05:48:20 PM PDT 24
Peak memory 412624 kb
Host smart-9f365970-696b-4f43-b4c3-36646351d432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159546119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.4159546119
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1369851983
Short name T414
Test name
Test status
Simulation time 36019535312 ps
CPU time 1164.29 seconds
Started Jul 17 05:47:56 PM PDT 24
Finished Jul 17 06:07:22 PM PDT 24
Peak memory 2538460 kb
Host smart-c6934319-0517-40ae-a3f8-e0a93773a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369851983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1369851983
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.4138975965
Short name T1744
Test name
Test status
Simulation time 11108563010 ps
CPU time 10.56 seconds
Started Jul 17 05:47:54 PM PDT 24
Finished Jul 17 05:48:06 PM PDT 24
Peak memory 221500 kb
Host smart-9c8277e3-43a8-4a41-9c4d-e47832bb8830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138975965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.4138975965
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3056219845
Short name T811
Test name
Test status
Simulation time 2851709528 ps
CPU time 3.96 seconds
Started Jul 17 05:47:54 PM PDT 24
Finished Jul 17 05:48:00 PM PDT 24
Peak memory 213856 kb
Host smart-12cc460b-daa5-40d2-8365-a2d9993582ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056219845 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3056219845
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1914885088
Short name T150
Test name
Test status
Simulation time 212337972 ps
CPU time 1.2 seconds
Started Jul 17 05:47:56 PM PDT 24
Finished Jul 17 05:47:59 PM PDT 24
Peak memory 205452 kb
Host smart-8bba1b15-a87d-4b00-8aef-12600892a2df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914885088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1914885088
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3064886148
Short name T734
Test name
Test status
Simulation time 2763581299 ps
CPU time 1.41 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:47:58 PM PDT 24
Peak memory 210016 kb
Host smart-178fa460-ef1d-41b1-84de-78740bc5779a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064886148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3064886148
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.402470750
Short name T1528
Test name
Test status
Simulation time 590729159 ps
CPU time 3.11 seconds
Started Jul 17 05:48:00 PM PDT 24
Finished Jul 17 05:48:05 PM PDT 24
Peak memory 205616 kb
Host smart-48cd7678-0e6c-49da-b5fa-6e1705aed0d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402470750 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.402470750
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.1314937864
Short name T577
Test name
Test status
Simulation time 274067356 ps
CPU time 1.48 seconds
Started Jul 17 05:47:59 PM PDT 24
Finished Jul 17 05:48:02 PM PDT 24
Peak memory 205460 kb
Host smart-feff3632-19ba-4bb1-aa2d-5ba6806763aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314937864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.1314937864
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2411182847
Short name T339
Test name
Test status
Simulation time 996389285 ps
CPU time 4.62 seconds
Started Jul 17 05:47:52 PM PDT 24
Finished Jul 17 05:47:59 PM PDT 24
Peak memory 214244 kb
Host smart-5fc68dd4-3f15-46c2-8489-4e7ae29be38c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411182847 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2411182847
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2393685063
Short name T1425
Test name
Test status
Simulation time 19969383506 ps
CPU time 136.74 seconds
Started Jul 17 05:47:58 PM PDT 24
Finished Jul 17 05:50:17 PM PDT 24
Peak memory 2284868 kb
Host smart-f4927d28-1ae3-4258-858e-8dcfb510acd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393685063 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2393685063
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.3301821742
Short name T1364
Test name
Test status
Simulation time 1884189905 ps
CPU time 2.73 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 05:48:01 PM PDT 24
Peak memory 213844 kb
Host smart-f54228b5-9f1a-48d6-8624-2d413d0d9050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301821742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_nack_acqfull.3301821742
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.3278960974
Short name T739
Test name
Test status
Simulation time 482317733 ps
CPU time 2.55 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:48:00 PM PDT 24
Peak memory 205916 kb
Host smart-4e2d01df-7533-44f4-80d8-5681dec698cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278960974 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.3278960974
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_txstretch.1931854649
Short name T1576
Test name
Test status
Simulation time 283940845 ps
CPU time 1.41 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:47:58 PM PDT 24
Peak memory 222196 kb
Host smart-b25c9520-a02e-4d6f-9ed0-0bdc7bf60e04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931854649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_nack_txstretch.1931854649
Directory /workspace/35.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/35.i2c_target_perf.172701709
Short name T1211
Test name
Test status
Simulation time 3605473264 ps
CPU time 4.31 seconds
Started Jul 17 05:48:00 PM PDT 24
Finished Jul 17 05:48:05 PM PDT 24
Peak memory 214764 kb
Host smart-8194a655-7dd6-42a5-9bad-622a7c65f036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172701709 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_perf.172701709
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.4082630960
Short name T1405
Test name
Test status
Simulation time 567835731 ps
CPU time 2.43 seconds
Started Jul 17 05:47:53 PM PDT 24
Finished Jul 17 05:47:57 PM PDT 24
Peak memory 205424 kb
Host smart-f25a4591-5eaf-4ef1-b97d-adec4612b419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082630960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_smbus_maxlen.4082630960
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2198993743
Short name T1717
Test name
Test status
Simulation time 1398587636 ps
CPU time 21.78 seconds
Started Jul 17 05:47:56 PM PDT 24
Finished Jul 17 05:48:20 PM PDT 24
Peak memory 213812 kb
Host smart-218d460a-44b0-4d92-ae93-01a95cfebdad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198993743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2198993743
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.3486342941
Short name T374
Test name
Test status
Simulation time 33723527919 ps
CPU time 178.65 seconds
Started Jul 17 05:48:01 PM PDT 24
Finished Jul 17 05:51:01 PM PDT 24
Peak memory 1101756 kb
Host smart-9da9b630-9425-47f2-96f2-3db6be832249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486342941 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.3486342941
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3864587214
Short name T1709
Test name
Test status
Simulation time 28282315052 ps
CPU time 27 seconds
Started Jul 17 05:48:01 PM PDT 24
Finished Jul 17 05:48:30 PM PDT 24
Peak memory 230184 kb
Host smart-81fc59b6-06c7-4a3a-9117-f8603e7b8ede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864587214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3864587214
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.292049622
Short name T979
Test name
Test status
Simulation time 68359487593 ps
CPU time 3493.48 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 06:46:13 PM PDT 24
Peak memory 12007916 kb
Host smart-1a34a119-572b-4df5-99c2-757ea1e42c23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292049622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_wr.292049622
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2863376977
Short name T959
Test name
Test status
Simulation time 1697168771 ps
CPU time 8.07 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:48:05 PM PDT 24
Peak memory 232760 kb
Host smart-f5407ed4-a442-4b06-9242-f669526e054b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863376977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2863376977
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2248315878
Short name T657
Test name
Test status
Simulation time 112175815 ps
CPU time 2.5 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:47:59 PM PDT 24
Peak memory 206232 kb
Host smart-1c1a5fac-aa4a-47c6-9ee5-b4ef93508e68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248315878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2248315878
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.718806899
Short name T293
Test name
Test status
Simulation time 30867235 ps
CPU time 0.62 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:08 PM PDT 24
Peak memory 204760 kb
Host smart-6a660c7d-af6c-4a28-996f-fc17f0f6cc6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718806899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.718806899
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3892613141
Short name T1419
Test name
Test status
Simulation time 244472488 ps
CPU time 1.8 seconds
Started Jul 17 05:47:56 PM PDT 24
Finished Jul 17 05:48:00 PM PDT 24
Peak memory 213744 kb
Host smart-0948776d-263f-4d3e-9192-46fe3deb00e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892613141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3892613141
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.392433192
Short name T388
Test name
Test status
Simulation time 1369325521 ps
CPU time 4.1 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 05:48:03 PM PDT 24
Peak memory 242220 kb
Host smart-6d85437b-b840-490a-8d24-6e3365f10c02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392433192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.392433192
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.1401551913
Short name T619
Test name
Test status
Simulation time 1860012672 ps
CPU time 117.75 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:49:54 PM PDT 24
Peak memory 536996 kb
Host smart-c9dc5e70-53ca-46fd-80d8-8359f8e3e7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401551913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1401551913
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.608151320
Short name T1023
Test name
Test status
Simulation time 4245088864 ps
CPU time 50.3 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 05:48:49 PM PDT 24
Peak memory 444412 kb
Host smart-cc099f88-5fe1-4204-a20f-de5acb21dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608151320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.608151320
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1492127071
Short name T1356
Test name
Test status
Simulation time 138331041 ps
CPU time 1.32 seconds
Started Jul 17 05:47:59 PM PDT 24
Finished Jul 17 05:48:02 PM PDT 24
Peak memory 205396 kb
Host smart-5f978792-bc34-4a21-aafc-7cd7dd38ddb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492127071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1492127071
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2448068877
Short name T777
Test name
Test status
Simulation time 346619266 ps
CPU time 9.24 seconds
Started Jul 17 05:47:58 PM PDT 24
Finished Jul 17 05:48:09 PM PDT 24
Peak memory 205440 kb
Host smart-feb45c22-194b-4216-acc1-795a05dc776e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448068877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2448068877
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.3409004556
Short name T1247
Test name
Test status
Simulation time 36896609784 ps
CPU time 317.09 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 05:53:16 PM PDT 24
Peak memory 1276332 kb
Host smart-a24cad31-fb02-4edd-9e5e-e59dc0bd67b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409004556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.3409004556
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1590091085
Short name T246
Test name
Test status
Simulation time 2094802788 ps
CPU time 9.27 seconds
Started Jul 17 05:48:10 PM PDT 24
Finished Jul 17 05:48:20 PM PDT 24
Peak memory 205508 kb
Host smart-a4ebcd97-e7f8-40bf-9f14-aa8aea8df33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590091085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1590091085
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.754345379
Short name T1305
Test name
Test status
Simulation time 34124024 ps
CPU time 0.64 seconds
Started Jul 17 05:47:58 PM PDT 24
Finished Jul 17 05:48:01 PM PDT 24
Peak memory 205184 kb
Host smart-f972592b-8e22-4826-ac83-bcedecba900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754345379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.754345379
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.4241621985
Short name T152
Test name
Test status
Simulation time 3218195626 ps
CPU time 19.18 seconds
Started Jul 17 05:48:01 PM PDT 24
Finished Jul 17 05:48:22 PM PDT 24
Peak memory 399944 kb
Host smart-31cab7b4-5bfa-4197-a935-38e4e9c47820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241621985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.4241621985
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.1255639065
Short name T1112
Test name
Test status
Simulation time 134647358 ps
CPU time 1.42 seconds
Started Jul 17 05:47:53 PM PDT 24
Finished Jul 17 05:47:56 PM PDT 24
Peak memory 213992 kb
Host smart-bfdbf721-2573-470e-9bae-06db35684a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255639065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.1255639065
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2497273487
Short name T1125
Test name
Test status
Simulation time 995952324 ps
CPU time 14.44 seconds
Started Jul 17 05:47:56 PM PDT 24
Finished Jul 17 05:48:12 PM PDT 24
Peak memory 254180 kb
Host smart-d3a8ea2d-1901-4e3d-b0a9-ef15818bd9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497273487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2497273487
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2345986491
Short name T130
Test name
Test status
Simulation time 42543828663 ps
CPU time 425.21 seconds
Started Jul 17 05:48:01 PM PDT 24
Finished Jul 17 05:55:08 PM PDT 24
Peak memory 2059516 kb
Host smart-bdf50ece-3ef8-4e94-a64b-fc3b5b399009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345986491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2345986491
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3168002289
Short name T1594
Test name
Test status
Simulation time 898177371 ps
CPU time 19.19 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:48:15 PM PDT 24
Peak memory 213704 kb
Host smart-af34ea97-e911-4dd5-a897-57a473e9aa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168002289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3168002289
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.746830241
Short name T1582
Test name
Test status
Simulation time 10961234522 ps
CPU time 5.53 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:13 PM PDT 24
Peak memory 219740 kb
Host smart-908d5df0-309b-4e69-8df2-210eebe291b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746830241 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.746830241
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2645761792
Short name T1620
Test name
Test status
Simulation time 181429119 ps
CPU time 1.01 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 05:48:00 PM PDT 24
Peak memory 205480 kb
Host smart-52b665fe-7404-418d-87ee-edc936f7a0a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645761792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2645761792
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.4050068219
Short name T460
Test name
Test status
Simulation time 239898233 ps
CPU time 1.1 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 05:48:00 PM PDT 24
Peak memory 213760 kb
Host smart-ee2bfb42-0369-423c-9d5a-fde17851a131
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050068219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.4050068219
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.2789471005
Short name T535
Test name
Test status
Simulation time 2468991811 ps
CPU time 2.27 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:10 PM PDT 24
Peak memory 205656 kb
Host smart-0ade5003-64f8-40a1-a249-0c3f847be1db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789471005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.2789471005
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.1356572957
Short name T1316
Test name
Test status
Simulation time 147714107 ps
CPU time 1.21 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:09 PM PDT 24
Peak memory 205452 kb
Host smart-30a03f4e-d03c-4565-a91b-d756167d556e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356572957 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.1356572957
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.1265105699
Short name T665
Test name
Test status
Simulation time 394407645 ps
CPU time 1.75 seconds
Started Jul 17 05:48:09 PM PDT 24
Finished Jul 17 05:48:12 PM PDT 24
Peak memory 213808 kb
Host smart-c9647077-d22c-4e5e-8f24-dea6c796156c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265105699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.1265105699
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3828372983
Short name T1369
Test name
Test status
Simulation time 4091899823 ps
CPU time 6.12 seconds
Started Jul 17 05:47:58 PM PDT 24
Finished Jul 17 05:48:07 PM PDT 24
Peak memory 213904 kb
Host smart-7872b9c6-0d53-44ec-8680-7ab3d88f09a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828372983 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3828372983
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.102971113
Short name T461
Test name
Test status
Simulation time 23264568563 ps
CPU time 77.29 seconds
Started Jul 17 05:47:55 PM PDT 24
Finished Jul 17 05:49:14 PM PDT 24
Peak memory 1041572 kb
Host smart-90489c0d-55f5-4f3a-8f71-2dc6f754fcee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102971113 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.102971113
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.951294188
Short name T1087
Test name
Test status
Simulation time 1225182928 ps
CPU time 3.08 seconds
Started Jul 17 05:48:07 PM PDT 24
Finished Jul 17 05:48:12 PM PDT 24
Peak memory 213848 kb
Host smart-2842e5b3-0f0a-466a-8531-540a14d95234
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951294188 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_nack_acqfull.951294188
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.4034538409
Short name T878
Test name
Test status
Simulation time 994991044 ps
CPU time 2.36 seconds
Started Jul 17 05:48:09 PM PDT 24
Finished Jul 17 05:48:13 PM PDT 24
Peak memory 205644 kb
Host smart-8b1d172f-5b40-4e9d-897d-6edd2e8e5f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034538409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.4034538409
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.2724099815
Short name T382
Test name
Test status
Simulation time 3609201676 ps
CPU time 5.08 seconds
Started Jul 17 05:47:56 PM PDT 24
Finished Jul 17 05:48:03 PM PDT 24
Peak memory 219576 kb
Host smart-51b50e26-a7f2-4f70-9b6d-e0475dd5dd5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724099815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.2724099815
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.1617214357
Short name T1597
Test name
Test status
Simulation time 2195764023 ps
CPU time 2.14 seconds
Started Jul 17 05:48:08 PM PDT 24
Finished Jul 17 05:48:11 PM PDT 24
Peak memory 205656 kb
Host smart-b80fca3f-5a65-47f2-9ef8-fe84b4e6baec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617214357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.1617214357
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3574667414
Short name T1450
Test name
Test status
Simulation time 882716548 ps
CPU time 13.45 seconds
Started Jul 17 05:47:58 PM PDT 24
Finished Jul 17 05:48:14 PM PDT 24
Peak memory 213824 kb
Host smart-9d058081-77ba-4c1d-b4a9-8a15e30ab4c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574667414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3574667414
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.817184508
Short name T1458
Test name
Test status
Simulation time 32791615215 ps
CPU time 1355 seconds
Started Jul 17 05:47:58 PM PDT 24
Finished Jul 17 06:10:35 PM PDT 24
Peak memory 7098696 kb
Host smart-161b8c42-6ffe-4607-b336-ead24c17956b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817184508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.i2c_target_stress_all.817184508
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1122622931
Short name T552
Test name
Test status
Simulation time 2536115378 ps
CPU time 32.02 seconds
Started Jul 17 05:47:57 PM PDT 24
Finished Jul 17 05:48:31 PM PDT 24
Peak memory 238876 kb
Host smart-a6bef348-436c-4f9a-a100-cdade2f5cc84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122622931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1122622931
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2811255301
Short name T1701
Test name
Test status
Simulation time 29470307399 ps
CPU time 87.06 seconds
Started Jul 17 05:47:56 PM PDT 24
Finished Jul 17 05:49:25 PM PDT 24
Peak memory 1444672 kb
Host smart-ee1a607e-7a75-4cac-aeaa-9443519cbe35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811255301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2811255301
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.4112249493
Short name T839
Test name
Test status
Simulation time 1578740918 ps
CPU time 8 seconds
Started Jul 17 05:48:00 PM PDT 24
Finished Jul 17 05:48:10 PM PDT 24
Peak memory 222028 kb
Host smart-3e19db17-1be9-4f8d-8eb2-458a96012452
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112249493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.4112249493
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.200291738
Short name T790
Test name
Test status
Simulation time 658920565 ps
CPU time 8.47 seconds
Started Jul 17 05:48:07 PM PDT 24
Finished Jul 17 05:48:17 PM PDT 24
Peak memory 205572 kb
Host smart-d3c80b17-61fb-4fb6-a6af-865e81304d47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200291738 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.200291738
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3891475946
Short name T425
Test name
Test status
Simulation time 15835166 ps
CPU time 0.61 seconds
Started Jul 17 05:48:17 PM PDT 24
Finished Jul 17 05:48:19 PM PDT 24
Peak memory 204872 kb
Host smart-83ed3b3a-a9eb-474c-bccb-5f7d6506b8cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891475946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3891475946
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3322109048
Short name T925
Test name
Test status
Simulation time 157264208 ps
CPU time 1.25 seconds
Started Jul 17 05:48:16 PM PDT 24
Finished Jul 17 05:48:18 PM PDT 24
Peak memory 213740 kb
Host smart-ac8b8c96-0768-4f20-a30d-e19dda4fd60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322109048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3322109048
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3197192959
Short name T641
Test name
Test status
Simulation time 2454194817 ps
CPU time 7.58 seconds
Started Jul 17 05:48:08 PM PDT 24
Finished Jul 17 05:48:17 PM PDT 24
Peak memory 279248 kb
Host smart-8226a7c8-1b99-4b80-8a6d-bb0c8177f0fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197192959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3197192959
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1642838543
Short name T1342
Test name
Test status
Simulation time 2689624905 ps
CPU time 55.39 seconds
Started Jul 17 05:48:09 PM PDT 24
Finished Jul 17 05:49:06 PM PDT 24
Peak memory 358864 kb
Host smart-e7f48537-e3b4-45de-bb6e-0b7b8c2b00bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642838543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1642838543
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.749211441
Short name T1596
Test name
Test status
Simulation time 5050531071 ps
CPU time 89 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:49:37 PM PDT 24
Peak memory 812656 kb
Host smart-ddd13efd-1f3f-49b8-9200-c459844a4831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749211441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.749211441
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.542500935
Short name T862
Test name
Test status
Simulation time 2376071564 ps
CPU time 1.33 seconds
Started Jul 17 05:48:10 PM PDT 24
Finished Jul 17 05:48:13 PM PDT 24
Peak memory 205268 kb
Host smart-5a5b1ea0-f552-40d2-8a28-7b76875defca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542500935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.542500935
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.606607616
Short name T1199
Test name
Test status
Simulation time 819897498 ps
CPU time 10.22 seconds
Started Jul 17 05:48:15 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 205496 kb
Host smart-b7221175-82f0-40e6-abfb-4a96d842fb22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606607616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
606607616
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.271633309
Short name T113
Test name
Test status
Simulation time 12289566731 ps
CPU time 68.53 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 940076 kb
Host smart-f8546200-87bc-4160-968e-64b77504794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271633309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.271633309
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.1334796753
Short name T376
Test name
Test status
Simulation time 360573966 ps
CPU time 15.08 seconds
Started Jul 17 05:48:09 PM PDT 24
Finished Jul 17 05:48:25 PM PDT 24
Peak memory 205556 kb
Host smart-9c458d72-1f1c-452c-b946-6cb4552d102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334796753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1334796753
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.131524621
Short name T11
Test name
Test status
Simulation time 142458381 ps
CPU time 1.15 seconds
Started Jul 17 05:48:09 PM PDT 24
Finished Jul 17 05:48:12 PM PDT 24
Peak memory 213692 kb
Host smart-0f41b7c4-6e8f-4d44-b6e4-4bdfb0e041c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131524621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.131524621
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2766125403
Short name T872
Test name
Test status
Simulation time 90307606 ps
CPU time 0.67 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:08 PM PDT 24
Peak memory 205236 kb
Host smart-09e9a1ff-7eb6-4468-915e-e94d689604a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766125403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2766125403
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3293638477
Short name T511
Test name
Test status
Simulation time 73613386434 ps
CPU time 657.99 seconds
Started Jul 17 05:48:07 PM PDT 24
Finished Jul 17 05:59:07 PM PDT 24
Peak memory 213776 kb
Host smart-f2102c75-ef38-45d5-a300-9dbd0048e0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293638477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3293638477
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.3024826328
Short name T993
Test name
Test status
Simulation time 234002473 ps
CPU time 3.2 seconds
Started Jul 17 05:48:09 PM PDT 24
Finished Jul 17 05:48:14 PM PDT 24
Peak memory 205452 kb
Host smart-f2d92296-f81c-49f3-a9b2-ec68062ce384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024826328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.3024826328
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3919615645
Short name T638
Test name
Test status
Simulation time 1013374257 ps
CPU time 15.16 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:23 PM PDT 24
Peak memory 283724 kb
Host smart-f4954372-9125-43cb-a939-f9b21508cab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919615645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3919615645
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.677885546
Short name T273
Test name
Test status
Simulation time 28860933853 ps
CPU time 573.36 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:57:41 PM PDT 24
Peak memory 1092008 kb
Host smart-8ba3c06b-8fc2-4ea0-9291-69edbc9a0dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677885546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.677885546
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.2160986455
Short name T1251
Test name
Test status
Simulation time 1108066528 ps
CPU time 24.87 seconds
Started Jul 17 05:48:07 PM PDT 24
Finished Jul 17 05:48:34 PM PDT 24
Peak memory 212824 kb
Host smart-5578a1c5-9e3d-4b78-9125-32e5d7ba9201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160986455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.2160986455
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1327891069
Short name T582
Test name
Test status
Simulation time 1967200939 ps
CPU time 5.22 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:13 PM PDT 24
Peak memory 215412 kb
Host smart-96674997-78b8-4f6d-83c8-36209f1f36fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327891069 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1327891069
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1191660636
Short name T286
Test name
Test status
Simulation time 232962111 ps
CPU time 1.36 seconds
Started Jul 17 05:48:08 PM PDT 24
Finished Jul 17 05:48:11 PM PDT 24
Peak memory 205608 kb
Host smart-7ecae158-d301-44cd-ad5b-af6960a29e33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191660636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1191660636
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.63395628
Short name T474
Test name
Test status
Simulation time 392549697 ps
CPU time 1.11 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:09 PM PDT 24
Peak memory 205440 kb
Host smart-800fdd1e-27f1-4463-b1b9-79cd641ae4c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63395628 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_fifo_reset_tx.63395628
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.1679380282
Short name T1745
Test name
Test status
Simulation time 1335374545 ps
CPU time 2.23 seconds
Started Jul 17 05:48:15 PM PDT 24
Finished Jul 17 05:48:18 PM PDT 24
Peak memory 205632 kb
Host smart-691fec41-a9cd-467a-99df-d76676566f06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679380282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.1679380282
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.1001331399
Short name T42
Test name
Test status
Simulation time 473648383 ps
CPU time 1.28 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:48:25 PM PDT 24
Peak memory 205492 kb
Host smart-3bf7243b-12df-4ac0-9f9c-42496b2e120d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001331399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.1001331399
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.994779175
Short name T763
Test name
Test status
Simulation time 4754417436 ps
CPU time 2.35 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:10 PM PDT 24
Peak memory 216652 kb
Host smart-6d7661ad-b3a4-4512-a65c-844139e61c61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994779175 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_hrst.994779175
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1963668915
Short name T95
Test name
Test status
Simulation time 1567027055 ps
CPU time 4.81 seconds
Started Jul 17 05:48:07 PM PDT 24
Finished Jul 17 05:48:14 PM PDT 24
Peak memory 213220 kb
Host smart-600857f0-2fc9-45ff-b9c0-ead38de4e165
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963668915 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1963668915
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3443488038
Short name T1449
Test name
Test status
Simulation time 10251440346 ps
CPU time 51.22 seconds
Started Jul 17 05:48:03 PM PDT 24
Finished Jul 17 05:48:55 PM PDT 24
Peak memory 972204 kb
Host smart-edf03ce9-9eba-4f32-8094-4ba7d46f1004
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443488038 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3443488038
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.1535179960
Short name T534
Test name
Test status
Simulation time 483978484 ps
CPU time 2.79 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 213880 kb
Host smart-5ebdcaea-31d7-48bc-9467-7459e303dbac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535179960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.1535179960
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.642427886
Short name T628
Test name
Test status
Simulation time 440342814 ps
CPU time 2.44 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:48:23 PM PDT 24
Peak memory 205600 kb
Host smart-5f89229c-3c87-4bf3-80ae-f1305bf9a853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642427886 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.642427886
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_txstretch.2059382583
Short name T161
Test name
Test status
Simulation time 451277049 ps
CPU time 1.28 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:48:21 PM PDT 24
Peak memory 222324 kb
Host smart-4742bf4d-3923-4bdd-bcf2-e066b0855579
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059382583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_nack_txstretch.2059382583
Directory /workspace/37.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/37.i2c_target_perf.507646391
Short name T416
Test name
Test status
Simulation time 3410014152 ps
CPU time 6.16 seconds
Started Jul 17 05:48:05 PM PDT 24
Finished Jul 17 05:48:13 PM PDT 24
Peak memory 213964 kb
Host smart-7581c0f3-c469-4172-904e-469cb250bbf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507646391 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_perf.507646391
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.64888914
Short name T709
Test name
Test status
Simulation time 412036600 ps
CPU time 2.2 seconds
Started Jul 17 05:48:17 PM PDT 24
Finished Jul 17 05:48:20 PM PDT 24
Peak memory 205332 kb
Host smart-47a4b9a9-a109-4a2e-bb04-d03019e195a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64888914 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_target_smbus_maxlen.64888914
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2978405033
Short name T291
Test name
Test status
Simulation time 2335830969 ps
CPU time 38.92 seconds
Started Jul 17 05:48:08 PM PDT 24
Finished Jul 17 05:48:49 PM PDT 24
Peak memory 213904 kb
Host smart-a9ed6d08-34bb-47a9-8a59-03d5dadd6e52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978405033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2978405033
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.1834483405
Short name T91
Test name
Test status
Simulation time 41580303257 ps
CPU time 1407 seconds
Started Jul 17 05:48:15 PM PDT 24
Finished Jul 17 06:11:43 PM PDT 24
Peak memory 6539740 kb
Host smart-07f81d44-e5e5-4170-a1a2-3c51c2f10bd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834483405 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.1834483405
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1557394122
Short name T1070
Test name
Test status
Simulation time 1872128167 ps
CPU time 17.57 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 208344 kb
Host smart-85fe65ea-358f-452c-bdbc-db23dfcf898a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557394122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1557394122
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.4222098197
Short name T754
Test name
Test status
Simulation time 11118646292 ps
CPU time 2.85 seconds
Started Jul 17 05:48:07 PM PDT 24
Finished Jul 17 05:48:11 PM PDT 24
Peak memory 205720 kb
Host smart-190d77ff-1a2b-43ba-984a-6d0c2075f074
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222098197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.4222098197
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1892958273
Short name T55
Test name
Test status
Simulation time 460863341 ps
CPU time 4.09 seconds
Started Jul 17 05:48:06 PM PDT 24
Finished Jul 17 05:48:12 PM PDT 24
Peak memory 215276 kb
Host smart-4dd0d53d-15a3-41dc-b206-132bc0d0d59b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892958273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1892958273
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3629222330
Short name T294
Test name
Test status
Simulation time 2431210180 ps
CPU time 7.12 seconds
Started Jul 17 05:48:16 PM PDT 24
Finished Jul 17 05:48:24 PM PDT 24
Peak memory 221988 kb
Host smart-c1564e2d-c84c-4dd6-9f22-1cde1444245b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629222330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3629222330
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.2444516089
Short name T528
Test name
Test status
Simulation time 56941964 ps
CPU time 1.35 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:48:25 PM PDT 24
Peak memory 205612 kb
Host smart-1e001baf-fc9f-43c7-b87f-79ad9a3115b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444516089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.2444516089
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1025381589
Short name T768
Test name
Test status
Simulation time 16535502 ps
CPU time 0.66 seconds
Started Jul 17 05:48:20 PM PDT 24
Finished Jul 17 05:48:23 PM PDT 24
Peak memory 204692 kb
Host smart-eaa07a63-40ec-49c2-aee4-5c8ed9bc5e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025381589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1025381589
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.1433097494
Short name T1734
Test name
Test status
Simulation time 242939815 ps
CPU time 1.85 seconds
Started Jul 17 05:48:20 PM PDT 24
Finished Jul 17 05:48:24 PM PDT 24
Peak memory 221724 kb
Host smart-64ec9412-0706-482e-bf3e-1ed0ae5a6b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433097494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1433097494
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.545105188
Short name T1083
Test name
Test status
Simulation time 1467440196 ps
CPU time 19.38 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:48:41 PM PDT 24
Peak memory 283836 kb
Host smart-6137b04f-396b-4b51-a917-480926e87eea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545105188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.545105188
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.837187650
Short name T803
Test name
Test status
Simulation time 10536024129 ps
CPU time 76.67 seconds
Started Jul 17 05:48:23 PM PDT 24
Finished Jul 17 05:49:41 PM PDT 24
Peak memory 501208 kb
Host smart-f9a0b7c2-ca7e-46de-b429-07e4fd12afee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837187650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.837187650
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.280573277
Short name T1433
Test name
Test status
Simulation time 1937969754 ps
CPU time 65.35 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:49:27 PM PDT 24
Peak memory 675016 kb
Host smart-98335bd6-9754-4e50-8042-b3f7d9efdfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280573277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.280573277
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.2518760590
Short name T348
Test name
Test status
Simulation time 462398485 ps
CPU time 3.07 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:48:24 PM PDT 24
Peak memory 205520 kb
Host smart-2ad006e6-1831-4e40-bf9d-2fc73e354e7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518760590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.2518760590
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1307225874
Short name T353
Test name
Test status
Simulation time 14678582760 ps
CPU time 221.74 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:52:02 PM PDT 24
Peak memory 1007420 kb
Host smart-7f672e4e-0ee4-4ff5-a8f8-0b4edfb3f367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307225874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1307225874
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.59870509
Short name T1683
Test name
Test status
Simulation time 685758930 ps
CPU time 4.62 seconds
Started Jul 17 05:48:14 PM PDT 24
Finished Jul 17 05:48:20 PM PDT 24
Peak memory 205476 kb
Host smart-52c25098-f414-4003-a164-7acf4b1c88b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59870509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.59870509
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_override.2881027575
Short name T142
Test name
Test status
Simulation time 31111829 ps
CPU time 0.71 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:48:21 PM PDT 24
Peak memory 205180 kb
Host smart-6e0ad29b-a365-496b-b0e8-63e281c61f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881027575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2881027575
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1465007568
Short name T185
Test name
Test status
Simulation time 48498608172 ps
CPU time 684.81 seconds
Started Jul 17 05:48:17 PM PDT 24
Finished Jul 17 05:59:43 PM PDT 24
Peak memory 906304 kb
Host smart-c93beb44-947e-4cff-b026-ae1e3b463a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465007568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1465007568
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.1901124385
Short name T301
Test name
Test status
Simulation time 96242965 ps
CPU time 1.86 seconds
Started Jul 17 05:48:22 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 205484 kb
Host smart-c2a351df-7932-4a12-aecc-ae30d5ac832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901124385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.1901124385
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.222310358
Short name T1600
Test name
Test status
Simulation time 29077366206 ps
CPU time 32.39 seconds
Started Jul 17 05:48:17 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 328484 kb
Host smart-516b6a03-3f0e-4d24-98e6-d1010c452b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222310358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.222310358
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3503602767
Short name T635
Test name
Test status
Simulation time 981271118 ps
CPU time 15.1 seconds
Started Jul 17 05:48:22 PM PDT 24
Finished Jul 17 05:48:39 PM PDT 24
Peak memory 221844 kb
Host smart-733eadc5-0015-4086-b6e6-4253f8f1325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503602767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3503602767
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3305661211
Short name T1616
Test name
Test status
Simulation time 763815050 ps
CPU time 4.03 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:48:27 PM PDT 24
Peak memory 219060 kb
Host smart-9cf2d1ba-75ff-4377-b439-3a7b29d8cbd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305661211 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3305661211
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1733205503
Short name T1719
Test name
Test status
Simulation time 128276723 ps
CPU time 0.97 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:48:22 PM PDT 24
Peak memory 205436 kb
Host smart-49f65031-6ebb-44a0-ad3c-d3d64256378b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733205503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1733205503
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3580411009
Short name T1574
Test name
Test status
Simulation time 141663156 ps
CPU time 0.98 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:48:25 PM PDT 24
Peak memory 205476 kb
Host smart-dad88d55-547e-4859-a1d5-dfcbb0437892
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580411009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3580411009
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.451738992
Short name T627
Test name
Test status
Simulation time 1851873801 ps
CPU time 2.78 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:48:22 PM PDT 24
Peak memory 205604 kb
Host smart-1699731e-fdfc-4ccb-9f27-9f5f8c4c04fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451738992 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.451738992
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.225631138
Short name T1224
Test name
Test status
Simulation time 508280229 ps
CPU time 1.13 seconds
Started Jul 17 05:48:22 PM PDT 24
Finished Jul 17 05:48:25 PM PDT 24
Peak memory 205488 kb
Host smart-2220b1d4-8c01-4dc6-b0f4-19af15821056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225631138 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.225631138
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3885381536
Short name T398
Test name
Test status
Simulation time 344692310 ps
CPU time 2.04 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:48:21 PM PDT 24
Peak memory 213852 kb
Host smart-6955539f-beac-4a9c-b016-c525a1e3878d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885381536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3885381536
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3614721594
Short name T1284
Test name
Test status
Simulation time 7758783871 ps
CPU time 8.98 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:48:28 PM PDT 24
Peak memory 221880 kb
Host smart-3de1e4d0-cbc1-4cbb-9011-d047e1a3e3de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614721594 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3614721594
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1029247551
Short name T583
Test name
Test status
Simulation time 22114108745 ps
CPU time 38.97 seconds
Started Jul 17 05:48:20 PM PDT 24
Finished Jul 17 05:49:01 PM PDT 24
Peak memory 655860 kb
Host smart-90c1f98d-9cb2-4a4a-8d8b-716465d05d27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029247551 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1029247551
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.536727523
Short name T159
Test name
Test status
Simulation time 438655448 ps
CPU time 2.83 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:48:22 PM PDT 24
Peak memory 213844 kb
Host smart-d65a64f7-99f7-46f1-bc4d-f99db7237e9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536727523 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_nack_acqfull.536727523
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.1775167163
Short name T1603
Test name
Test status
Simulation time 1094775730 ps
CPU time 2.56 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 205632 kb
Host smart-1f4009e6-b565-4fbf-a998-11356945e885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775167163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.1775167163
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_txstretch.586215560
Short name T1437
Test name
Test status
Simulation time 134430668 ps
CPU time 1.4 seconds
Started Jul 17 05:48:23 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 222224 kb
Host smart-9ed47a59-97eb-469a-bea7-0c7a66d9f440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586215560 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_nack_txstretch.586215560
Directory /workspace/38.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/38.i2c_target_perf.532000032
Short name T611
Test name
Test status
Simulation time 2465099798 ps
CPU time 4.84 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:48:29 PM PDT 24
Peak memory 221276 kb
Host smart-2c21832c-5dd1-485e-a4b6-19013b6fe208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532000032 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_perf.532000032
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.43038558
Short name T1549
Test name
Test status
Simulation time 504302728 ps
CPU time 2.26 seconds
Started Jul 17 05:48:23 PM PDT 24
Finished Jul 17 05:48:27 PM PDT 24
Peak memory 205400 kb
Host smart-ae6e76f0-7aaa-47e6-9198-1d9c2c223b10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43038558 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_smbus_maxlen.43038558
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2816714856
Short name T1115
Test name
Test status
Simulation time 819042323 ps
CPU time 10.54 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:48:32 PM PDT 24
Peak memory 213852 kb
Host smart-a5a28204-b138-4dc2-8885-6d3498560ef7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816714856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2816714856
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3345156750
Short name T666
Test name
Test status
Simulation time 3178274846 ps
CPU time 19.47 seconds
Started Jul 17 05:48:20 PM PDT 24
Finished Jul 17 05:48:42 PM PDT 24
Peak memory 230192 kb
Host smart-1251802b-fd07-4d19-a4cc-b64d204e8879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345156750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3345156750
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.3354137260
Short name T1307
Test name
Test status
Simulation time 34644008748 ps
CPU time 62.03 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:49:24 PM PDT 24
Peak memory 1133768 kb
Host smart-c79b6b71-1d4e-4ffa-bcf2-83f21c3e55f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354137260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.3354137260
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.48242218
Short name T700
Test name
Test status
Simulation time 2605531819 ps
CPU time 7.36 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:48:29 PM PDT 24
Peak memory 303068 kb
Host smart-ecac14cd-dc53-4c31-81b9-ad46597f4c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48242218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_stretch.48242218
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.4199816029
Short name T949
Test name
Test status
Simulation time 4477760021 ps
CPU time 6.57 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 214012 kb
Host smart-10945908-fd47-4ae3-97d6-548d05bebafe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199816029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.4199816029
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1684575328
Short name T771
Test name
Test status
Simulation time 14725139 ps
CPU time 0.64 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:41 PM PDT 24
Peak memory 204648 kb
Host smart-4c1255d2-4f7f-42cb-a8ab-667f504005ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684575328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1684575328
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.143201947
Short name T780
Test name
Test status
Simulation time 259127266 ps
CPU time 1.45 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:40 PM PDT 24
Peak memory 213740 kb
Host smart-0e45a838-8e70-40d2-9d60-08017e39837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143201947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.143201947
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2841012721
Short name T866
Test name
Test status
Simulation time 208532981 ps
CPU time 4.47 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:48:27 PM PDT 24
Peak memory 244040 kb
Host smart-85edc161-a27f-47e3-b1d9-074e2469a10f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841012721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2841012721
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3588301212
Short name T906
Test name
Test status
Simulation time 8947959750 ps
CPU time 66.01 seconds
Started Jul 17 05:48:17 PM PDT 24
Finished Jul 17 05:49:24 PM PDT 24
Peak memory 389656 kb
Host smart-5897a3ef-e95c-43ce-b073-9f4deca8e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588301212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3588301212
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1579736765
Short name T1434
Test name
Test status
Simulation time 2435330744 ps
CPU time 196.01 seconds
Started Jul 17 05:48:21 PM PDT 24
Finished Jul 17 05:51:39 PM PDT 24
Peak memory 812276 kb
Host smart-7b74bd18-2149-4fe5-bf3c-0de8a537f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579736765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1579736765
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.411529642
Short name T1714
Test name
Test status
Simulation time 146273468 ps
CPU time 0.95 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:48:22 PM PDT 24
Peak memory 205252 kb
Host smart-863443e0-f57b-4b68-baf5-4227c069bf20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411529642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.411529642
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1646718324
Short name T663
Test name
Test status
Simulation time 261040486 ps
CPU time 7.56 seconds
Started Jul 17 05:48:18 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 259816 kb
Host smart-3f84dbf6-bdc9-4b09-9432-a51db518d822
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646718324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1646718324
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.903296741
Short name T120
Test name
Test status
Simulation time 17633456761 ps
CPU time 111.7 seconds
Started Jul 17 05:48:20 PM PDT 24
Finished Jul 17 05:50:14 PM PDT 24
Peak memory 1307580 kb
Host smart-8da3ee77-56d1-45d2-b662-634c9809eb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903296741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.903296741
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2032568170
Short name T822
Test name
Test status
Simulation time 341131210 ps
CPU time 3.74 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:43 PM PDT 24
Peak memory 205536 kb
Host smart-51c8fff3-44eb-452a-822c-19eb5215acb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032568170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2032568170
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3312200993
Short name T1649
Test name
Test status
Simulation time 583258371 ps
CPU time 2.2 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:48:43 PM PDT 24
Peak memory 213712 kb
Host smart-a990e7e8-c868-4562-bd06-c5e3c272fe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312200993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3312200993
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2778306452
Short name T1175
Test name
Test status
Simulation time 140612727 ps
CPU time 0.71 seconds
Started Jul 17 05:48:23 PM PDT 24
Finished Jul 17 05:48:26 PM PDT 24
Peak memory 205152 kb
Host smart-157d9f93-c4bd-4447-b9dc-b49263377e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778306452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2778306452
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1376350342
Short name T996
Test name
Test status
Simulation time 12261349162 ps
CPU time 122.32 seconds
Started Jul 17 05:48:23 PM PDT 24
Finished Jul 17 05:50:27 PM PDT 24
Peak memory 205544 kb
Host smart-c9c1ba8b-26de-48f9-84d9-951aaa5680ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376350342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1376350342
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.1975050906
Short name T810
Test name
Test status
Simulation time 6178331789 ps
CPU time 34.93 seconds
Started Jul 17 05:48:19 PM PDT 24
Finished Jul 17 05:48:57 PM PDT 24
Peak memory 573252 kb
Host smart-be150c96-520a-42d8-a689-51bb618b3a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975050906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.1975050906
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1371031368
Short name T1415
Test name
Test status
Simulation time 5229354646 ps
CPU time 20.16 seconds
Started Jul 17 05:48:20 PM PDT 24
Finished Jul 17 05:48:43 PM PDT 24
Peak memory 338020 kb
Host smart-890fda79-a1ae-4097-b636-4cf383fc0e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371031368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1371031368
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.799105073
Short name T127
Test name
Test status
Simulation time 5802927333 ps
CPU time 97.51 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:50:16 PM PDT 24
Peak memory 522472 kb
Host smart-a72c0f35-97dd-49b5-ad4a-5dfd4631f528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799105073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.799105073
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1637456084
Short name T192
Test name
Test status
Simulation time 3126062994 ps
CPU time 14.4 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:54 PM PDT 24
Peak memory 221936 kb
Host smart-6bfc24a4-aadc-4eaa-810a-2d2b3670d532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637456084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1637456084
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.437356025
Short name T431
Test name
Test status
Simulation time 4787640891 ps
CPU time 6.12 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:45 PM PDT 24
Peak memory 222072 kb
Host smart-5c290ff9-cc8f-4257-bf93-73a87de58fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437356025 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.437356025
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1286875548
Short name T1041
Test name
Test status
Simulation time 639171880 ps
CPU time 0.96 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:41 PM PDT 24
Peak memory 205448 kb
Host smart-d062fe4b-3362-4c33-800f-72cb0ab91beb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286875548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1286875548
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2153503086
Short name T313
Test name
Test status
Simulation time 919434999 ps
CPU time 1.41 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:48:43 PM PDT 24
Peak memory 205620 kb
Host smart-096c92b6-447e-40cb-bd1c-d4c573653627
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153503086 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2153503086
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.3855933231
Short name T503
Test name
Test status
Simulation time 1778107789 ps
CPU time 2.49 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:42 PM PDT 24
Peak memory 205568 kb
Host smart-95b0b141-2630-4ec4-b643-19a1971441ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855933231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.3855933231
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.1725107139
Short name T164
Test name
Test status
Simulation time 165422521 ps
CPU time 1.33 seconds
Started Jul 17 05:48:43 PM PDT 24
Finished Jul 17 05:48:46 PM PDT 24
Peak memory 205432 kb
Host smart-64bdcb9d-8cd4-4fd5-bc03-240e63b46b20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725107139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.1725107139
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2897516064
Short name T72
Test name
Test status
Simulation time 824259938 ps
CPU time 5.13 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:45 PM PDT 24
Peak memory 219500 kb
Host smart-3bf88fb8-74d2-467f-afb2-db793e06821a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897516064 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2897516064
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2037858531
Short name T447
Test name
Test status
Simulation time 13683413982 ps
CPU time 15.46 seconds
Started Jul 17 05:48:36 PM PDT 24
Finished Jul 17 05:48:53 PM PDT 24
Peak memory 407804 kb
Host smart-fedba126-dd9a-4e37-9c34-56cbedb61382
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037858531 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2037858531
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.3220941691
Short name T1626
Test name
Test status
Simulation time 919482358 ps
CPU time 2.54 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:42 PM PDT 24
Peak memory 213888 kb
Host smart-d749ca05-1d29-4aa0-8547-749092f58945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220941691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_nack_acqfull.3220941691
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.1611127357
Short name T1200
Test name
Test status
Simulation time 695896547 ps
CPU time 2.79 seconds
Started Jul 17 05:48:35 PM PDT 24
Finished Jul 17 05:48:38 PM PDT 24
Peak memory 205628 kb
Host smart-595df031-9ab8-4216-9481-5f3cc71db34b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611127357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.1611127357
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_txstretch.828147025
Short name T1568
Test name
Test status
Simulation time 877400746 ps
CPU time 1.33 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:41 PM PDT 24
Peak memory 222288 kb
Host smart-52dc8714-acfe-402f-8e0d-ea66a09bee3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828147025 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_nack_txstretch.828147025
Directory /workspace/39.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/39.i2c_target_perf.349161632
Short name T1287
Test name
Test status
Simulation time 2268498937 ps
CPU time 4.28 seconds
Started Jul 17 05:48:39 PM PDT 24
Finished Jul 17 05:48:46 PM PDT 24
Peak memory 213872 kb
Host smart-e6bb8443-470c-4013-9ba6-2ad4272759b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349161632 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_perf.349161632
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.677741341
Short name T661
Test name
Test status
Simulation time 559325960 ps
CPU time 2.62 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:48:45 PM PDT 24
Peak memory 205312 kb
Host smart-602720fa-d7e7-4c8c-acb4-6c28be63ec34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677741341 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_smbus_maxlen.677741341
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1986529761
Short name T1690
Test name
Test status
Simulation time 10765846875 ps
CPU time 20.28 seconds
Started Jul 17 05:48:35 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 213856 kb
Host smart-139afc5c-ebde-44e2-9b57-b067f4430e87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986529761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1986529761
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.1333588387
Short name T338
Test name
Test status
Simulation time 74184535087 ps
CPU time 302.69 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:53:43 PM PDT 24
Peak memory 2952876 kb
Host smart-a8c7c75f-ba33-40a4-ac07-d6b147f772cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333588387 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.1333588387
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.713755499
Short name T369
Test name
Test status
Simulation time 1826863269 ps
CPU time 29.17 seconds
Started Jul 17 05:48:36 PM PDT 24
Finished Jul 17 05:49:07 PM PDT 24
Peak memory 231148 kb
Host smart-b1c19264-2cfe-4322-b199-ecd4832fcf49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713755499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.713755499
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.1256289820
Short name T1390
Test name
Test status
Simulation time 8370009435 ps
CPU time 3.38 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:44 PM PDT 24
Peak memory 205708 kb
Host smart-ed2c2353-b859-46e0-8208-938fd935f713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256289820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.1256289820
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3410522216
Short name T794
Test name
Test status
Simulation time 3043862527 ps
CPU time 23.36 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:49:02 PM PDT 24
Peak memory 538260 kb
Host smart-33a65262-6df3-4d7c-b072-ae15508c3d00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410522216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3410522216
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2345206989
Short name T444
Test name
Test status
Simulation time 2960851448 ps
CPU time 7.94 seconds
Started Jul 17 05:48:36 PM PDT 24
Finished Jul 17 05:48:46 PM PDT 24
Peak memory 222040 kb
Host smart-9eb1b48d-a9ae-40f4-a368-c7069c38c660
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345206989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2345206989
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.3586744556
Short name T520
Test name
Test status
Simulation time 459215069 ps
CPU time 4.21 seconds
Started Jul 17 05:48:39 PM PDT 24
Finished Jul 17 05:48:46 PM PDT 24
Peak memory 213760 kb
Host smart-8a5f4b71-57ce-4d3b-95cf-d80a5986fe09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586744556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.3586744556
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2484799086
Short name T1306
Test name
Test status
Simulation time 24614762 ps
CPU time 0.59 seconds
Started Jul 17 05:40:22 PM PDT 24
Finished Jul 17 05:40:23 PM PDT 24
Peak memory 204816 kb
Host smart-eb2d7471-9c58-499e-814a-d9e71e98c993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484799086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2484799086
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.822064641
Short name T494
Test name
Test status
Simulation time 203763061 ps
CPU time 1.25 seconds
Started Jul 17 05:40:13 PM PDT 24
Finished Jul 17 05:40:15 PM PDT 24
Peak memory 213772 kb
Host smart-54eda6b4-1d9d-4551-bc90-9adc048a41fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822064641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.822064641
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1994188097
Short name T877
Test name
Test status
Simulation time 446105885 ps
CPU time 9.22 seconds
Started Jul 17 05:40:13 PM PDT 24
Finished Jul 17 05:40:23 PM PDT 24
Peak memory 300536 kb
Host smart-09075ab6-6621-4939-9b15-099fe8b64312
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994188097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.1994188097
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.114478846
Short name T330
Test name
Test status
Simulation time 7565669322 ps
CPU time 123.16 seconds
Started Jul 17 05:40:15 PM PDT 24
Finished Jul 17 05:42:19 PM PDT 24
Peak memory 663196 kb
Host smart-0a9afc64-4121-4c5c-ba83-0bdb391d4c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114478846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.114478846
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1978078625
Short name T974
Test name
Test status
Simulation time 3986405679 ps
CPU time 140.51 seconds
Started Jul 17 05:40:11 PM PDT 24
Finished Jul 17 05:42:32 PM PDT 24
Peak memory 650800 kb
Host smart-c47e8bcf-9520-47d5-aec4-683a82286726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978078625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1978078625
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2181279153
Short name T575
Test name
Test status
Simulation time 105970064 ps
CPU time 0.94 seconds
Started Jul 17 05:41:00 PM PDT 24
Finished Jul 17 05:41:02 PM PDT 24
Peak memory 204788 kb
Host smart-03f2224e-7c13-4489-997b-753839270ea2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181279153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2181279153
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.607029338
Short name T1669
Test name
Test status
Simulation time 536399847 ps
CPU time 2.95 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:19 PM PDT 24
Peak memory 205460 kb
Host smart-0cac708a-7628-4bef-bf0c-21c160c153dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607029338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.607029338
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.591309854
Short name T1253
Test name
Test status
Simulation time 13525131384 ps
CPU time 77.27 seconds
Started Jul 17 05:40:13 PM PDT 24
Finished Jul 17 05:41:31 PM PDT 24
Peak memory 1048488 kb
Host smart-2c7fc95f-df8b-42d3-933a-0361d98434d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591309854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.591309854
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.148885647
Short name T943
Test name
Test status
Simulation time 790501812 ps
CPU time 3.58 seconds
Started Jul 17 05:45:24 PM PDT 24
Finished Jul 17 05:45:29 PM PDT 24
Peak memory 205532 kb
Host smart-86a1f85b-3d04-40ff-a5f8-75d35277fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148885647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.148885647
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.2289302641
Short name T1629
Test name
Test status
Simulation time 188053096 ps
CPU time 1.41 seconds
Started Jul 17 05:40:24 PM PDT 24
Finished Jul 17 05:40:26 PM PDT 24
Peak memory 213648 kb
Host smart-52e2043e-b489-4062-8271-c28dad835eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289302641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2289302641
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.1275318319
Short name T982
Test name
Test status
Simulation time 48431473 ps
CPU time 0.73 seconds
Started Jul 17 05:40:12 PM PDT 24
Finished Jul 17 05:40:14 PM PDT 24
Peak memory 205152 kb
Host smart-84dc8037-fbb1-4b01-a981-c446e832502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275318319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1275318319
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2281731555
Short name T1078
Test name
Test status
Simulation time 54653005793 ps
CPU time 2482.74 seconds
Started Jul 17 05:45:06 PM PDT 24
Finished Jul 17 06:26:30 PM PDT 24
Peak memory 4009148 kb
Host smart-2ea635f9-9765-4e8d-b136-32d506fab2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281731555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2281731555
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.3307612974
Short name T965
Test name
Test status
Simulation time 24271079499 ps
CPU time 291.59 seconds
Started Jul 17 05:40:59 PM PDT 24
Finished Jul 17 05:45:51 PM PDT 24
Peak memory 205556 kb
Host smart-6febebf4-febe-4a21-a9c0-3ed486e03e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307612974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.3307612974
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.4111843069
Short name T945
Test name
Test status
Simulation time 4466748981 ps
CPU time 49.31 seconds
Started Jul 17 05:42:21 PM PDT 24
Finished Jul 17 05:43:11 PM PDT 24
Peak memory 305404 kb
Host smart-ff237542-8345-4390-8da9-e17928632bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111843069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.4111843069
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.4227591859
Short name T784
Test name
Test status
Simulation time 1545436922 ps
CPU time 7.02 seconds
Started Jul 17 05:40:56 PM PDT 24
Finished Jul 17 05:41:04 PM PDT 24
Peak memory 213764 kb
Host smart-fa557999-3f41-4b1e-ab5a-7373ff84bfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227591859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.4227591859
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.192857511
Short name T183
Test name
Test status
Simulation time 275495162 ps
CPU time 0.85 seconds
Started Jul 17 05:40:30 PM PDT 24
Finished Jul 17 05:40:32 PM PDT 24
Peak memory 223844 kb
Host smart-3535f28a-a0b3-4b67-935f-1a7fc05370a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192857511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.192857511
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1434366200
Short name T455
Test name
Test status
Simulation time 2575897380 ps
CPU time 5.02 seconds
Started Jul 17 05:41:54 PM PDT 24
Finished Jul 17 05:41:59 PM PDT 24
Peak memory 213968 kb
Host smart-c32017e1-efa9-4dae-8fff-87198ca136eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434366200 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1434366200
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.203892485
Short name T165
Test name
Test status
Simulation time 932911077 ps
CPU time 1.88 seconds
Started Jul 17 05:45:32 PM PDT 24
Finished Jul 17 05:45:35 PM PDT 24
Peak memory 213052 kb
Host smart-bde451c6-edf9-4130-8db1-aa763aa1ecd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203892485 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.203892485
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2971365941
Short name T645
Test name
Test status
Simulation time 472665399 ps
CPU time 1.17 seconds
Started Jul 17 05:42:03 PM PDT 24
Finished Jul 17 05:42:05 PM PDT 24
Peak memory 205624 kb
Host smart-b47bacdb-aff7-4b64-b0ef-a557c57f6830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971365941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2971365941
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.2259897208
Short name T143
Test name
Test status
Simulation time 369817066 ps
CPU time 2.23 seconds
Started Jul 17 05:42:17 PM PDT 24
Finished Jul 17 05:42:20 PM PDT 24
Peak memory 205604 kb
Host smart-9b604482-d6e9-4991-ac98-1df31884b849
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259897208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.2259897208
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.2962869496
Short name T1150
Test name
Test status
Simulation time 852155837 ps
CPU time 1.26 seconds
Started Jul 17 05:40:28 PM PDT 24
Finished Jul 17 05:40:30 PM PDT 24
Peak memory 205368 kb
Host smart-9b7ed3c2-f213-4d28-9f5b-6f68eeff669c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962869496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.2962869496
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3235236804
Short name T289
Test name
Test status
Simulation time 5545151907 ps
CPU time 6.02 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:22 PM PDT 24
Peak memory 222084 kb
Host smart-b389e04f-ab64-4655-95d5-764f97050d96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235236804 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3235236804
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.614671863
Short name T360
Test name
Test status
Simulation time 4942762443 ps
CPU time 4.41 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:20 PM PDT 24
Peak memory 205704 kb
Host smart-2e9189be-ed81-4668-b1de-bed5ec4ac48e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614671863 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.614671863
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.1839473345
Short name T1465
Test name
Test status
Simulation time 515743395 ps
CPU time 3.08 seconds
Started Jul 17 05:40:28 PM PDT 24
Finished Jul 17 05:40:32 PM PDT 24
Peak memory 213748 kb
Host smart-3469de98-1815-4563-9440-2ca7cbc0142e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839473345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.1839473345
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.756427877
Short name T1417
Test name
Test status
Simulation time 2065858800 ps
CPU time 2.8 seconds
Started Jul 17 05:43:44 PM PDT 24
Finished Jul 17 05:43:47 PM PDT 24
Peak memory 205616 kb
Host smart-6a0b9363-9537-4e13-8697-e37e4f05f7b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756427877 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.756427877
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_txstretch.3068229629
Short name T281
Test name
Test status
Simulation time 143502309 ps
CPU time 1.44 seconds
Started Jul 17 05:41:13 PM PDT 24
Finished Jul 17 05:41:15 PM PDT 24
Peak memory 222500 kb
Host smart-682c4c0a-70a9-4059-9b00-ba49bf16d153
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068229629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_nack_txstretch.3068229629
Directory /workspace/4.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/4.i2c_target_perf.2385161729
Short name T730
Test name
Test status
Simulation time 735446710 ps
CPU time 5.58 seconds
Started Jul 17 05:41:13 PM PDT 24
Finished Jul 17 05:41:19 PM PDT 24
Peak memory 222048 kb
Host smart-b9736bbf-d4ae-4f9e-a0f1-c707f4d71f1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385161729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.2385161729
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.4218447399
Short name T357
Test name
Test status
Simulation time 2121007668 ps
CPU time 2.47 seconds
Started Jul 17 05:40:25 PM PDT 24
Finished Jul 17 05:40:29 PM PDT 24
Peak memory 205440 kb
Host smart-5bb3707f-c777-4745-a6b2-3bba2e9c3f79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218447399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_smbus_maxlen.4218447399
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2066799180
Short name T1198
Test name
Test status
Simulation time 913578396 ps
CPU time 13.03 seconds
Started Jul 17 05:40:12 PM PDT 24
Finished Jul 17 05:40:27 PM PDT 24
Peak memory 213880 kb
Host smart-e4a70857-ec87-4997-9bf5-1df1b7e94b49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066799180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2066799180
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.2608342545
Short name T719
Test name
Test status
Simulation time 5867113179 ps
CPU time 26.27 seconds
Started Jul 17 05:40:21 PM PDT 24
Finished Jul 17 05:40:48 PM PDT 24
Peak memory 254820 kb
Host smart-efb56138-5986-40f4-b79d-f0ad8e6a9919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608342545 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.2608342545
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.2473344950
Short name T612
Test name
Test status
Simulation time 4116037828 ps
CPU time 21.58 seconds
Started Jul 17 05:40:10 PM PDT 24
Finished Jul 17 05:40:33 PM PDT 24
Peak memory 224408 kb
Host smart-66eef9ec-0c90-42e0-b35d-6301ce8fa889
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473344950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.2473344950
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3485586433
Short name T1725
Test name
Test status
Simulation time 34947650028 ps
CPU time 54.65 seconds
Started Jul 17 05:40:10 PM PDT 24
Finished Jul 17 05:41:06 PM PDT 24
Peak memory 1005624 kb
Host smart-b3267fc9-32e8-4a91-ac5c-204bc26639fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485586433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3485586433
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2143744116
Short name T697
Test name
Test status
Simulation time 351788883 ps
CPU time 2.43 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:17 PM PDT 24
Peak memory 214684 kb
Host smart-d33271e7-a634-4a9a-8cff-153740c6e31b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143744116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2143744116
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2220312742
Short name T432
Test name
Test status
Simulation time 1095383715 ps
CPU time 5.92 seconds
Started Jul 17 05:40:14 PM PDT 24
Finished Jul 17 05:40:21 PM PDT 24
Peak memory 221988 kb
Host smart-ac876d94-3beb-4c0e-8d6c-6fc072c76fdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220312742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2220312742
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.2607914536
Short name T1716
Test name
Test status
Simulation time 114131071 ps
CPU time 2.44 seconds
Started Jul 17 05:43:44 PM PDT 24
Finished Jul 17 05:43:47 PM PDT 24
Peak memory 205612 kb
Host smart-e778fe1b-6060-47e7-88a6-502a48393095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607914536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.2607914536
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3445195318
Short name T600
Test name
Test status
Simulation time 40864651 ps
CPU time 0.64 seconds
Started Jul 17 05:48:47 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 204780 kb
Host smart-ee7b6325-028d-437d-9e85-404c15f1a3ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445195318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3445195318
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.642148274
Short name T359
Test name
Test status
Simulation time 751006092 ps
CPU time 1.93 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:48:43 PM PDT 24
Peak memory 219176 kb
Host smart-62385926-f6f2-4892-9063-d81f46f77cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642148274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.642148274
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.127379277
Short name T684
Test name
Test status
Simulation time 784771660 ps
CPU time 4.58 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:48:46 PM PDT 24
Peak memory 240340 kb
Host smart-e9f4a792-d57f-484f-a56c-e0101cff3cfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127379277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empt
y.127379277
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.3874327669
Short name T155
Test name
Test status
Simulation time 2038975412 ps
CPU time 144.97 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:51:06 PM PDT 24
Peak memory 695032 kb
Host smart-84290bc3-df55-41fa-95ae-d4ba4ae605f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874327669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3874327669
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3826047767
Short name T435
Test name
Test status
Simulation time 5906082329 ps
CPU time 47.96 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:49:29 PM PDT 24
Peak memory 558964 kb
Host smart-c9187d2d-bd21-4313-90fb-575ef8d07583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826047767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3826047767
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.2761112533
Short name T1382
Test name
Test status
Simulation time 90919999 ps
CPU time 1.01 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:40 PM PDT 24
Peak memory 205252 kb
Host smart-2beda03b-4036-45e1-80d8-426755dcfa88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761112533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.2761112533
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.566130953
Short name T553
Test name
Test status
Simulation time 306265738 ps
CPU time 9.11 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 233536 kb
Host smart-12d7abe5-7dc3-4df7-9a10-6f0c06cda170
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566130953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
566130953
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1524067682
Short name T1653
Test name
Test status
Simulation time 166923245 ps
CPU time 2.41 seconds
Started Jul 17 05:48:53 PM PDT 24
Finished Jul 17 05:48:58 PM PDT 24
Peak memory 205524 kb
Host smart-8f4cce09-1be0-4faf-9f90-5d0ec97bd607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524067682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1524067682
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.504435740
Short name T858
Test name
Test status
Simulation time 351353046 ps
CPU time 1.46 seconds
Started Jul 17 05:48:48 PM PDT 24
Finished Jul 17 05:48:51 PM PDT 24
Peak memory 215456 kb
Host smart-f30608d5-3f6b-4c50-b5e8-070d6d718dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504435740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.504435740
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.174277880
Short name T354
Test name
Test status
Simulation time 17694411 ps
CPU time 0.68 seconds
Started Jul 17 05:48:39 PM PDT 24
Finished Jul 17 05:48:43 PM PDT 24
Peak memory 205208 kb
Host smart-c87d3fd9-ba9f-4a38-b03a-6d9ca6bba5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174277880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.174277880
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1661941359
Short name T1493
Test name
Test status
Simulation time 18742863351 ps
CPU time 188.53 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:51:49 PM PDT 24
Peak memory 205728 kb
Host smart-93070ac7-111f-4ecb-9a1f-382b111e0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661941359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1661941359
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.1892488353
Short name T1028
Test name
Test status
Simulation time 24579901392 ps
CPU time 60.82 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:49:40 PM PDT 24
Peak memory 205596 kb
Host smart-e1941234-0d20-47ee-b953-33ab3f0e6f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892488353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.1892488353
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1827781628
Short name T585
Test name
Test status
Simulation time 7980513179 ps
CPU time 26.17 seconds
Started Jul 17 05:48:34 PM PDT 24
Finished Jul 17 05:49:00 PM PDT 24
Peak memory 302832 kb
Host smart-59d9e09f-53f3-4474-a005-472176dd8480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827781628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1827781628
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.346955171
Short name T1567
Test name
Test status
Simulation time 3970322645 ps
CPU time 43.19 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:49:24 PM PDT 24
Peak memory 213772 kb
Host smart-6aa62eaa-cb95-41c4-ac76-8b72ff06015f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346955171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.346955171
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1728761474
Short name T64
Test name
Test status
Simulation time 652213215 ps
CPU time 3.1 seconds
Started Jul 17 05:48:50 PM PDT 24
Finished Jul 17 05:48:55 PM PDT 24
Peak memory 222020 kb
Host smart-baa96ecf-3b37-4087-8cb1-6098def46e49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728761474 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1728761474
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2695235253
Short name T1332
Test name
Test status
Simulation time 223485192 ps
CPU time 1.33 seconds
Started Jul 17 05:48:34 PM PDT 24
Finished Jul 17 05:48:36 PM PDT 24
Peak memory 205852 kb
Host smart-da511904-4fb1-4858-b489-e883d72604e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695235253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2695235253
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2479896062
Short name T420
Test name
Test status
Simulation time 227821127 ps
CPU time 1.42 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:41 PM PDT 24
Peak memory 213828 kb
Host smart-19ab4b5e-d816-419a-828e-6a3fba192f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479896062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2479896062
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.389373305
Short name T1050
Test name
Test status
Simulation time 557458800 ps
CPU time 2.88 seconds
Started Jul 17 05:48:50 PM PDT 24
Finished Jul 17 05:48:54 PM PDT 24
Peak memory 205592 kb
Host smart-4dd3866f-96c5-43cd-b851-fb88603d61fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389373305 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.389373305
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.2699454648
Short name T821
Test name
Test status
Simulation time 480783650 ps
CPU time 1.49 seconds
Started Jul 17 05:48:50 PM PDT 24
Finished Jul 17 05:48:53 PM PDT 24
Peak memory 205456 kb
Host smart-45199d1c-c4c7-47c8-9538-ea9a174f2df9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699454648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.2699454648
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.64618938
Short name T1088
Test name
Test status
Simulation time 1688233206 ps
CPU time 4.9 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:48:46 PM PDT 24
Peak memory 221976 kb
Host smart-ce9995cd-a5a2-460a-9fd4-6dd3b16a73ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64618938 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.64618938
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.2209513732
Short name T1538
Test name
Test status
Simulation time 17915051876 ps
CPU time 99.67 seconds
Started Jul 17 05:48:36 PM PDT 24
Finished Jul 17 05:50:17 PM PDT 24
Peak memory 1508788 kb
Host smart-a4465737-2f17-4cc7-ae0b-4362c8791066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209513732 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.2209513732
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.555501558
Short name T52
Test name
Test status
Simulation time 1969877513 ps
CPU time 2.81 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 213820 kb
Host smart-a3f9912f-8755-4216-b9f7-124c9a67857e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555501558 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_nack_acqfull.555501558
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.1896166025
Short name T1065
Test name
Test status
Simulation time 1210849764 ps
CPU time 2.29 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 205660 kb
Host smart-1a953fba-95e5-4a90-8925-9fceb2b94b73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896166025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.1896166025
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_txstretch.2581610628
Short name T1739
Test name
Test status
Simulation time 159207836 ps
CPU time 1.48 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:49:01 PM PDT 24
Peak memory 222408 kb
Host smart-6140a5b9-df08-4457-a5a0-5c1f4c56c5c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581610628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_nack_txstretch.2581610628
Directory /workspace/40.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/40.i2c_target_perf.2213557423
Short name T1170
Test name
Test status
Simulation time 733391671 ps
CPU time 5.51 seconds
Started Jul 17 05:48:39 PM PDT 24
Finished Jul 17 05:48:48 PM PDT 24
Peak memory 213804 kb
Host smart-bb54cf8a-e994-4606-855d-db5a00b82375
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213557423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.2213557423
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.3222655624
Short name T92
Test name
Test status
Simulation time 1324667812 ps
CPU time 2.07 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 205424 kb
Host smart-4e94b2d0-4265-429f-a226-4d20da48b1bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222655624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.3222655624
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.280204004
Short name T715
Test name
Test status
Simulation time 3420424383 ps
CPU time 9.71 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 213852 kb
Host smart-8c745fc6-e62a-4a2f-bc5c-9531b4539611
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280204004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.280204004
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.1284957245
Short name T937
Test name
Test status
Simulation time 5242951409 ps
CPU time 33.43 seconds
Started Jul 17 05:48:37 PM PDT 24
Finished Jul 17 05:49:14 PM PDT 24
Peak memory 284844 kb
Host smart-a220a56d-771d-42ba-9dd0-33e5cf791e5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284957245 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.1284957245
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.535001468
Short name T1460
Test name
Test status
Simulation time 2630308412 ps
CPU time 19.8 seconds
Started Jul 17 05:48:35 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 230212 kb
Host smart-4f40beac-98f5-4141-8aba-3c9a60802a3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535001468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_rd.535001468
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.1358695829
Short name T863
Test name
Test status
Simulation time 27694142967 ps
CPU time 59.43 seconds
Started Jul 17 05:48:38 PM PDT 24
Finished Jul 17 05:49:41 PM PDT 24
Peak memory 1087460 kb
Host smart-355ba488-9727-4a99-a169-111493f851e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358695829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.1358695829
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.687573876
Short name T1367
Test name
Test status
Simulation time 613329338 ps
CPU time 1.99 seconds
Started Jul 17 05:48:36 PM PDT 24
Finished Jul 17 05:48:40 PM PDT 24
Peak memory 213768 kb
Host smart-2e0cd40f-89d0-4aab-abcb-ce152fe76069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687573876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.687573876
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3846037500
Short name T1261
Test name
Test status
Simulation time 1764136191 ps
CPU time 7.35 seconds
Started Jul 17 05:48:36 PM PDT 24
Finished Jul 17 05:48:45 PM PDT 24
Peak memory 230088 kb
Host smart-70a077e3-0419-4ca8-9445-d69224f3c87f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846037500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3846037500
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.3237315241
Short name T793
Test name
Test status
Simulation time 75417125 ps
CPU time 1.38 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:49 PM PDT 24
Peak memory 205620 kb
Host smart-e5b023d7-6df0-4add-a1f1-5117b8728886
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237315241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.3237315241
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2705288889
Short name T1411
Test name
Test status
Simulation time 18637150 ps
CPU time 0.63 seconds
Started Jul 17 05:48:49 PM PDT 24
Finished Jul 17 05:48:51 PM PDT 24
Peak memory 204788 kb
Host smart-5b06777d-489c-43be-8820-80810ff47d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705288889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2705288889
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1578578280
Short name T1270
Test name
Test status
Simulation time 271875409 ps
CPU time 9.75 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:58 PM PDT 24
Peak memory 249972 kb
Host smart-c4cfd784-e1ed-43fc-8a7f-b9c225d2fa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578578280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1578578280
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3402252488
Short name T596
Test name
Test status
Simulation time 631776587 ps
CPU time 3.13 seconds
Started Jul 17 05:48:53 PM PDT 24
Finished Jul 17 05:48:58 PM PDT 24
Peak memory 214716 kb
Host smart-da5f0144-5a53-48f5-8a59-7997dc290ef3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402252488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3402252488
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1957473827
Short name T458
Test name
Test status
Simulation time 7845707801 ps
CPU time 49.81 seconds
Started Jul 17 05:48:45 PM PDT 24
Finished Jul 17 05:49:37 PM PDT 24
Peak memory 213828 kb
Host smart-0e49f9f0-0e57-45d6-9435-5854329ce43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957473827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1957473827
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.697151628
Short name T428
Test name
Test status
Simulation time 16384928115 ps
CPU time 79.41 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:50:18 PM PDT 24
Peak memory 820076 kb
Host smart-1d00dc66-8d90-4fab-b5ad-e39330c352ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697151628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.697151628
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3489434072
Short name T1428
Test name
Test status
Simulation time 78552045 ps
CPU time 0.93 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:49 PM PDT 24
Peak memory 205168 kb
Host smart-d4ca00ea-43d5-4b23-8173-956bdb7c90ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489434072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3489434072
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.653518079
Short name T749
Test name
Test status
Simulation time 143458449 ps
CPU time 7.64 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 227704 kb
Host smart-c5a24994-0f18-4b5a-bacd-e7ec325581df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653518079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
653518079
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.553884053
Short name T1213
Test name
Test status
Simulation time 10098204636 ps
CPU time 332.29 seconds
Started Jul 17 05:48:45 PM PDT 24
Finished Jul 17 05:54:19 PM PDT 24
Peak memory 1280844 kb
Host smart-990fb141-9314-4d0d-b562-110de2c5a688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553884053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.553884053
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3910534031
Short name T492
Test name
Test status
Simulation time 2086741391 ps
CPU time 10.45 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:49:10 PM PDT 24
Peak memory 205504 kb
Host smart-c57f8219-e415-4ebd-9c0d-cce44abc261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910534031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3910534031
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.2477327678
Short name T1697
Test name
Test status
Simulation time 27705756 ps
CPU time 0.72 seconds
Started Jul 17 05:48:47 PM PDT 24
Finished Jul 17 05:48:50 PM PDT 24
Peak memory 205172 kb
Host smart-4f3bafa3-bb1e-490c-8608-807825a59937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477327678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2477327678
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3182532636
Short name T1477
Test name
Test status
Simulation time 6218472613 ps
CPU time 43.52 seconds
Started Jul 17 05:48:50 PM PDT 24
Finished Jul 17 05:49:35 PM PDT 24
Peak memory 238968 kb
Host smart-1d5a3026-a1d2-49ed-84f5-64682b3cc454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182532636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3182532636
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.153456147
Short name T1611
Test name
Test status
Simulation time 93804559 ps
CPU time 2.17 seconds
Started Jul 17 05:48:53 PM PDT 24
Finished Jul 17 05:48:58 PM PDT 24
Peak memory 214264 kb
Host smart-204e00d3-235c-4e36-93da-f534f0bdbd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153456147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.153456147
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.4153462634
Short name T998
Test name
Test status
Simulation time 2064291652 ps
CPU time 91.57 seconds
Started Jul 17 05:48:48 PM PDT 24
Finished Jul 17 05:50:21 PM PDT 24
Peak memory 334072 kb
Host smart-3e5e1456-f73c-42e8-9ed4-838f27d364d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153462634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.4153462634
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1882938282
Short name T1221
Test name
Test status
Simulation time 1123876076 ps
CPU time 8.28 seconds
Started Jul 17 05:48:55 PM PDT 24
Finished Jul 17 05:49:06 PM PDT 24
Peak memory 216592 kb
Host smart-687064ff-76e9-4d10-b776-1d9ffaa3a526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882938282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1882938282
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2170271230
Short name T1159
Test name
Test status
Simulation time 1171222004 ps
CPU time 3.59 seconds
Started Jul 17 05:48:54 PM PDT 24
Finished Jul 17 05:49:00 PM PDT 24
Peak memory 213840 kb
Host smart-25207422-e89a-4738-99c2-a11fa4f3f1b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170271230 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2170271230
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1624880303
Short name T691
Test name
Test status
Simulation time 162636771 ps
CPU time 1.15 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:01 PM PDT 24
Peak memory 205448 kb
Host smart-d107b4c9-2f8f-4c63-a557-c9b2415d3ecb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624880303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1624880303
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3152992565
Short name T677
Test name
Test status
Simulation time 456301403 ps
CPU time 0.87 seconds
Started Jul 17 05:48:53 PM PDT 24
Finished Jul 17 05:48:55 PM PDT 24
Peak memory 205388 kb
Host smart-800ef083-cac3-4e0e-b806-850e4afa7a3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152992565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3152992565
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.3281751516
Short name T1329
Test name
Test status
Simulation time 2896823885 ps
CPU time 2.65 seconds
Started Jul 17 05:48:48 PM PDT 24
Finished Jul 17 05:48:53 PM PDT 24
Peak memory 205644 kb
Host smart-5712333f-3a8b-4292-bf17-2d0d763c24ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281751516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.3281751516
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.664775687
Short name T442
Test name
Test status
Simulation time 1413737399 ps
CPU time 1.53 seconds
Started Jul 17 05:48:45 PM PDT 24
Finished Jul 17 05:48:49 PM PDT 24
Peak memory 205468 kb
Host smart-d6045eb5-b8a8-43b6-a271-aac999ded978
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664775687 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.664775687
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1834550343
Short name T972
Test name
Test status
Simulation time 1150915847 ps
CPU time 2.22 seconds
Started Jul 17 05:48:43 PM PDT 24
Finished Jul 17 05:48:46 PM PDT 24
Peak memory 215784 kb
Host smart-cba9b03c-cad7-4a32-b004-a7830b01ac9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834550343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1834550343
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3563359181
Short name T1640
Test name
Test status
Simulation time 974377681 ps
CPU time 5.48 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:49:04 PM PDT 24
Peak memory 217920 kb
Host smart-fa7700b5-2bd4-4375-8f77-285c96f0ea1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563359181 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3563359181
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.593016252
Short name T1387
Test name
Test status
Simulation time 8278157762 ps
CPU time 5.85 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:53 PM PDT 24
Peak memory 205596 kb
Host smart-216c5f4a-8471-4956-b2e6-150030a856df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593016252 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.593016252
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.4017823974
Short name T51
Test name
Test status
Simulation time 1272061157 ps
CPU time 2.44 seconds
Started Jul 17 05:48:53 PM PDT 24
Finished Jul 17 05:48:57 PM PDT 24
Peak memory 213764 kb
Host smart-824d8251-3499-413d-a586-551fdc7e20f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017823974 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_acqfull.4017823974
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.837736069
Short name T1435
Test name
Test status
Simulation time 553582461 ps
CPU time 2.45 seconds
Started Jul 17 05:48:52 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 205580 kb
Host smart-e13c4607-5ac1-4b78-9d68-ed3bb685225b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837736069 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.837736069
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.2773715245
Short name T297
Test name
Test status
Simulation time 703625338 ps
CPU time 4.85 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:49:04 PM PDT 24
Peak memory 213332 kb
Host smart-5e5434e4-f85d-4e22-9a7f-6cb531e074a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773715245 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.2773715245
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.3688032713
Short name T703
Test name
Test status
Simulation time 435225552 ps
CPU time 2.1 seconds
Started Jul 17 05:48:47 PM PDT 24
Finished Jul 17 05:48:51 PM PDT 24
Peak memory 205380 kb
Host smart-e27c4f7b-a30e-4ad4-8dd4-7ea9aadbf516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688032713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.3688032713
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.855905373
Short name T490
Test name
Test status
Simulation time 2205780761 ps
CPU time 7.88 seconds
Started Jul 17 05:48:49 PM PDT 24
Finished Jul 17 05:48:59 PM PDT 24
Peak memory 213892 kb
Host smart-6425b2c1-42b3-42ad-acf2-ff91bd2edca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855905373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.855905373
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.3346223081
Short name T283
Test name
Test status
Simulation time 29657683203 ps
CPU time 345.32 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:54:33 PM PDT 24
Peak memory 2093680 kb
Host smart-fa516383-defe-41e7-a88b-a880b0f13d59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346223081 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.3346223081
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3302289037
Short name T634
Test name
Test status
Simulation time 1062459851 ps
CPU time 18.33 seconds
Started Jul 17 05:48:54 PM PDT 24
Finished Jul 17 05:49:14 PM PDT 24
Peak memory 221896 kb
Host smart-fb649166-5ee0-44a8-9a96-fccb96540e9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302289037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3302289037
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.489009387
Short name T1365
Test name
Test status
Simulation time 63466056968 ps
CPU time 1679.75 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 06:16:58 PM PDT 24
Peak memory 8664100 kb
Host smart-984c562f-b394-4a75-ae66-a71fcf72884b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489009387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.489009387
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1424250685
Short name T1499
Test name
Test status
Simulation time 3208417484 ps
CPU time 6.81 seconds
Started Jul 17 05:48:48 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 221412 kb
Host smart-b5ec462c-4678-459b-bb5b-0da7cf999446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424250685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1424250685
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.4155840731
Short name T569
Test name
Test status
Simulation time 147008496 ps
CPU time 2.52 seconds
Started Jul 17 05:48:45 PM PDT 24
Finished Jul 17 05:48:49 PM PDT 24
Peak memory 205600 kb
Host smart-38c016a9-9cb5-4013-9c61-ad723a14173b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155840731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.4155840731
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.774358153
Short name T1209
Test name
Test status
Simulation time 21990819 ps
CPU time 0.6 seconds
Started Jul 17 05:48:52 PM PDT 24
Finished Jul 17 05:48:54 PM PDT 24
Peak memory 204776 kb
Host smart-d6c081b7-89a0-4a0b-9390-58651920604b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774358153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.774358153
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2287531482
Short name T1147
Test name
Test status
Simulation time 719926201 ps
CPU time 1.74 seconds
Started Jul 17 05:48:59 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 214756 kb
Host smart-2493717e-58d1-4e3f-a2c4-9e0d2b4e0050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287531482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2287531482
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2501122231
Short name T1296
Test name
Test status
Simulation time 304415739 ps
CPU time 7.43 seconds
Started Jul 17 05:48:54 PM PDT 24
Finished Jul 17 05:49:03 PM PDT 24
Peak memory 271592 kb
Host smart-8a0d16a6-4d05-4c03-b8e0-1b8f1f903b0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501122231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2501122231
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1090240481
Short name T1722
Test name
Test status
Simulation time 14046854829 ps
CPU time 70.1 seconds
Started Jul 17 05:48:54 PM PDT 24
Finished Jul 17 05:50:06 PM PDT 24
Peak memory 548240 kb
Host smart-7649a3ba-9c56-4172-96d7-b33e07083271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090240481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1090240481
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.66113562
Short name T1171
Test name
Test status
Simulation time 6110735037 ps
CPU time 135.72 seconds
Started Jul 17 05:48:49 PM PDT 24
Finished Jul 17 05:51:07 PM PDT 24
Peak memory 649084 kb
Host smart-bdfadc6f-41af-473a-affc-d73dd6d0d1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66113562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.66113562
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1598857563
Short name T1631
Test name
Test status
Simulation time 196191551 ps
CPU time 0.96 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:48:59 PM PDT 24
Peak memory 205228 kb
Host smart-ab944b0d-03db-486b-9b13-9df0f24c7d94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598857563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1598857563
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.2924288239
Short name T587
Test name
Test status
Simulation time 209006156 ps
CPU time 4.18 seconds
Started Jul 17 05:48:41 PM PDT 24
Finished Jul 17 05:48:48 PM PDT 24
Peak memory 205492 kb
Host smart-0a04d0d8-e5ef-4a7c-9842-8d14ce13ac85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924288239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.2924288239
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2715725549
Short name T336
Test name
Test status
Simulation time 5452089064 ps
CPU time 156.76 seconds
Started Jul 17 05:48:45 PM PDT 24
Finished Jul 17 05:51:23 PM PDT 24
Peak memory 823316 kb
Host smart-7f39101d-38cc-458c-ad74-fc685a7ecd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715725549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2715725549
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_override.4183868713
Short name T956
Test name
Test status
Simulation time 40084728 ps
CPU time 0.74 seconds
Started Jul 17 05:48:53 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 204728 kb
Host smart-6a7a472e-465b-4b05-bb2c-d3652414ffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183868713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.4183868713
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.1987182462
Short name T39
Test name
Test status
Simulation time 24054929972 ps
CPU time 1754.49 seconds
Started Jul 17 05:48:54 PM PDT 24
Finished Jul 17 06:18:11 PM PDT 24
Peak memory 1290780 kb
Host smart-d66db62a-4b09-43d9-8c84-1ccfbafceb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987182462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.1987182462
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.804667014
Short name T1438
Test name
Test status
Simulation time 233456035 ps
CPU time 2.18 seconds
Started Jul 17 05:48:47 PM PDT 24
Finished Jul 17 05:48:51 PM PDT 24
Peak memory 221576 kb
Host smart-c0f1e1a9-c5c1-4465-9a19-6d9623971cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804667014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.804667014
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.850601899
Short name T852
Test name
Test status
Simulation time 1442186204 ps
CPU time 27.23 seconds
Started Jul 17 05:48:53 PM PDT 24
Finished Jul 17 05:49:23 PM PDT 24
Peak memory 304100 kb
Host smart-b69e9098-490e-46d4-8240-42f73b8d925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850601899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.850601899
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2430278165
Short name T814
Test name
Test status
Simulation time 856120271 ps
CPU time 12.92 seconds
Started Jul 17 05:48:50 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 238024 kb
Host smart-58b90d84-6761-4943-9ff5-88cb1d421067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430278165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2430278165
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2747243330
Short name T1456
Test name
Test status
Simulation time 2775533896 ps
CPU time 3.97 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 216828 kb
Host smart-8231840a-4b2f-49b6-a6aa-ab775fc002ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747243330 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2747243330
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.923311063
Short name T462
Test name
Test status
Simulation time 1473390998 ps
CPU time 0.96 seconds
Started Jul 17 05:48:50 PM PDT 24
Finished Jul 17 05:48:53 PM PDT 24
Peak memory 205456 kb
Host smart-5abb357f-d3b1-48e3-98f6-395a74686eae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923311063 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.923311063
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.2642560933
Short name T699
Test name
Test status
Simulation time 207165197 ps
CPU time 1.22 seconds
Started Jul 17 05:48:59 PM PDT 24
Finished Jul 17 05:49:04 PM PDT 24
Peak memory 205360 kb
Host smart-24946343-72e8-43f6-8904-cdd13f7a8f9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642560933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.2642560933
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.2320599269
Short name T966
Test name
Test status
Simulation time 319293688 ps
CPU time 1.97 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:03 PM PDT 24
Peak memory 205420 kb
Host smart-9c2ed0cd-1efc-438d-8e68-5dac5188c095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320599269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.2320599269
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.1643989274
Short name T1203
Test name
Test status
Simulation time 582265981 ps
CPU time 1.5 seconds
Started Jul 17 05:48:51 PM PDT 24
Finished Jul 17 05:48:54 PM PDT 24
Peak memory 205488 kb
Host smart-0260d5a0-2861-4558-a206-0703ea092950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643989274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.1643989274
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.584700989
Short name T1234
Test name
Test status
Simulation time 2776376079 ps
CPU time 4.37 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:06 PM PDT 24
Peak memory 214028 kb
Host smart-929df1ad-2f42-4415-8164-3034c097d641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584700989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.584700989
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1516175521
Short name T309
Test name
Test status
Simulation time 23694200037 ps
CPU time 88.84 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:50:30 PM PDT 24
Peak memory 1143376 kb
Host smart-05bde898-7ffc-4070-80bc-bfacec9f1e66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516175521 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1516175521
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.3245282901
Short name T1688
Test name
Test status
Simulation time 471072018 ps
CPU time 2.85 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:03 PM PDT 24
Peak memory 213832 kb
Host smart-21333c8c-985e-41fa-aee2-66c52ffb85b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245282901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.3245282901
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.323171730
Short name T1188
Test name
Test status
Simulation time 2312729850 ps
CPU time 2.95 seconds
Started Jul 17 05:48:54 PM PDT 24
Finished Jul 17 05:48:59 PM PDT 24
Peak memory 205684 kb
Host smart-5b6d234b-81e7-4497-b3b0-409d9b363107
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323171730 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.323171730
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.2563333288
Short name T1194
Test name
Test status
Simulation time 7943086994 ps
CPU time 7.04 seconds
Started Jul 17 05:48:46 PM PDT 24
Finished Jul 17 05:48:55 PM PDT 24
Peak memory 222088 kb
Host smart-0e0cf0aa-598d-42c7-80e2-d25ebc909819
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563333288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.2563333288
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.2085209340
Short name T1558
Test name
Test status
Simulation time 3417877873 ps
CPU time 2.5 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 205472 kb
Host smart-3c4b5884-0463-44b8-8c6a-9a90ba40ec72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085209340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_smbus_maxlen.2085209340
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1094828473
Short name T1037
Test name
Test status
Simulation time 3993533668 ps
CPU time 30.22 seconds
Started Jul 17 05:48:51 PM PDT 24
Finished Jul 17 05:49:23 PM PDT 24
Peak memory 213896 kb
Host smart-ef8af5c5-27a6-4128-92ff-a02424c88350
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094828473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1094828473
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.1176562510
Short name T239
Test name
Test status
Simulation time 84850062182 ps
CPU time 536.97 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:57:59 PM PDT 24
Peak memory 2524672 kb
Host smart-edfd6e42-2d03-4791-bb37-8825546534ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176562510 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.1176562510
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.609191419
Short name T1252
Test name
Test status
Simulation time 1575521988 ps
CPU time 4.88 seconds
Started Jul 17 05:48:50 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 205648 kb
Host smart-5c56222d-9d54-4603-9d04-b99743943146
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609191419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.609191419
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3723098903
Short name T68
Test name
Test status
Simulation time 44632836824 ps
CPU time 112.33 seconds
Started Jul 17 05:48:47 PM PDT 24
Finished Jul 17 05:50:41 PM PDT 24
Peak memory 1543280 kb
Host smart-7c298a2f-4c3a-427b-84a6-3401e47ae079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723098903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3723098903
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2631414266
Short name T1135
Test name
Test status
Simulation time 5114440619 ps
CPU time 42.2 seconds
Started Jul 17 05:48:51 PM PDT 24
Finished Jul 17 05:49:35 PM PDT 24
Peak memory 679044 kb
Host smart-5cded561-11e6-4c3e-b0c6-2fac20ba6861
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631414266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2631414266
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.760920080
Short name T1475
Test name
Test status
Simulation time 5714705394 ps
CPU time 7.72 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:09 PM PDT 24
Peak memory 233492 kb
Host smart-8b8919bd-e97c-470a-965e-28fe27f19856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760920080 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.760920080
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.580761467
Short name T539
Test name
Test status
Simulation time 102849870 ps
CPU time 2.26 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:04 PM PDT 24
Peak memory 205608 kb
Host smart-15f49bd0-a2ec-403a-be1b-934ebce65e80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580761467 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.580761467
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.322499209
Short name T1350
Test name
Test status
Simulation time 25240992 ps
CPU time 0.62 seconds
Started Jul 17 05:49:05 PM PDT 24
Finished Jul 17 05:49:09 PM PDT 24
Peak memory 204740 kb
Host smart-582bc22c-a613-4902-9458-f9a42fcaa1e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322499209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.322499209
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2219781890
Short name T1334
Test name
Test status
Simulation time 354587607 ps
CPU time 3.09 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 219580 kb
Host smart-2cda79ab-ba11-4ba7-ae98-72f498f4a44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219781890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2219781890
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3277717740
Short name T1537
Test name
Test status
Simulation time 669455361 ps
CPU time 17.87 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 277536 kb
Host smart-bb8f4d52-fec0-47ef-8325-a761dab126df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277717740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3277717740
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1167987113
Short name T26
Test name
Test status
Simulation time 20062343054 ps
CPU time 124.07 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:51:06 PM PDT 24
Peak memory 671536 kb
Host smart-bcdfe3ba-0191-497c-a3a5-3358d928182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167987113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1167987113
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2534352168
Short name T1711
Test name
Test status
Simulation time 9458752683 ps
CPU time 71.67 seconds
Started Jul 17 05:48:55 PM PDT 24
Finished Jul 17 05:50:10 PM PDT 24
Peak memory 725360 kb
Host smart-c21ecb21-864e-40c8-95d1-9c64283f49e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534352168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2534352168
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2917050391
Short name T796
Test name
Test status
Simulation time 247646363 ps
CPU time 1.2 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:49:00 PM PDT 24
Peak memory 205380 kb
Host smart-5742fc48-51cb-4c26-b1dc-11241d441bc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917050391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2917050391
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3108935785
Short name T1577
Test name
Test status
Simulation time 510546195 ps
CPU time 2.88 seconds
Started Jul 17 05:48:52 PM PDT 24
Finished Jul 17 05:48:56 PM PDT 24
Peak memory 205516 kb
Host smart-e18b3dac-5f58-4e68-a72c-879cd1b958bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108935785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3108935785
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2105590299
Short name T1489
Test name
Test status
Simulation time 2746440628 ps
CPU time 66.53 seconds
Started Jul 17 05:48:53 PM PDT 24
Finished Jul 17 05:50:01 PM PDT 24
Peak memory 813168 kb
Host smart-a07e0fa7-695f-40fe-992e-7378afbe38ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105590299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2105590299
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.693217804
Short name T1103
Test name
Test status
Simulation time 832814830 ps
CPU time 6.7 seconds
Started Jul 17 05:49:02 PM PDT 24
Finished Jul 17 05:49:11 PM PDT 24
Peak memory 205428 kb
Host smart-caca36c2-9d55-4897-a041-daea206280f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693217804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.693217804
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.4217795338
Short name T94
Test name
Test status
Simulation time 78737753 ps
CPU time 0.67 seconds
Started Jul 17 05:48:52 PM PDT 24
Finished Jul 17 05:48:54 PM PDT 24
Peak memory 205168 kb
Host smart-270af837-68f8-4928-8ea1-019ec5df5ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217795338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.4217795338
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2763130900
Short name T1590
Test name
Test status
Simulation time 857381958 ps
CPU time 17.98 seconds
Started Jul 17 05:48:59 PM PDT 24
Finished Jul 17 05:49:21 PM PDT 24
Peak memory 252976 kb
Host smart-b5516a2a-c316-49c1-a780-67926c336a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763130900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2763130900
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.1431000195
Short name T1645
Test name
Test status
Simulation time 140383216 ps
CPU time 2.58 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:03 PM PDT 24
Peak memory 225208 kb
Host smart-a69cabe6-eb15-4518-bebf-7881d0f9f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431000195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1431000195
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2323030618
Short name T1531
Test name
Test status
Simulation time 15157402280 ps
CPU time 44.33 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:45 PM PDT 24
Peak memory 490260 kb
Host smart-4f1738e4-39b7-4cdd-9315-fa6ceba71d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323030618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2323030618
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.572696853
Short name T656
Test name
Test status
Simulation time 1078834212 ps
CPU time 23.5 seconds
Started Jul 17 05:48:59 PM PDT 24
Finished Jul 17 05:49:26 PM PDT 24
Peak memory 213672 kb
Host smart-eaf45e36-ca4e-4395-ace6-68ed86dac8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572696853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.572696853
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3740106319
Short name T1412
Test name
Test status
Simulation time 1964417991 ps
CPU time 4.79 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:07 PM PDT 24
Peak memory 214268 kb
Host smart-90f8e3e4-3519-437e-ae99-b736d024ccfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740106319 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3740106319
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3050533585
Short name T640
Test name
Test status
Simulation time 292658905 ps
CPU time 0.87 seconds
Started Jul 17 05:48:54 PM PDT 24
Finished Jul 17 05:48:57 PM PDT 24
Peak memory 205444 kb
Host smart-930c9dfc-9921-4910-9c4e-3cc7d987aff5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050533585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3050533585
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.261941347
Short name T1223
Test name
Test status
Simulation time 598530040 ps
CPU time 1.35 seconds
Started Jul 17 05:49:04 PM PDT 24
Finished Jul 17 05:49:09 PM PDT 24
Peak memory 205664 kb
Host smart-aadbe099-f98a-4659-bdbe-446d79a8fdb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261941347 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.261941347
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.2755351089
Short name T861
Test name
Test status
Simulation time 534125488 ps
CPU time 3.33 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:06 PM PDT 24
Peak memory 213828 kb
Host smart-dca2c0ff-7552-4021-ac63-1aeb9bd857f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755351089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.2755351089
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.3353479872
Short name T1293
Test name
Test status
Simulation time 552013027 ps
CPU time 1.51 seconds
Started Jul 17 05:49:00 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 205392 kb
Host smart-6ad438b7-9374-4de5-a483-22540373e905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353479872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.3353479872
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3023547524
Short name T88
Test name
Test status
Simulation time 3304928171 ps
CPU time 5.06 seconds
Started Jul 17 05:49:05 PM PDT 24
Finished Jul 17 05:49:13 PM PDT 24
Peak memory 216584 kb
Host smart-a1876a81-f721-47f2-ac15-c975d7451d9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023547524 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3023547524
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3503012929
Short name T1678
Test name
Test status
Simulation time 17246814853 ps
CPU time 415.51 seconds
Started Jul 17 05:49:17 PM PDT 24
Finished Jul 17 05:56:16 PM PDT 24
Peak memory 3961872 kb
Host smart-6fab7f43-80e9-4e2d-a579-2da7bc0560e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503012929 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3503012929
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.669239006
Short name T579
Test name
Test status
Simulation time 2931572110 ps
CPU time 2.66 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 213852 kb
Host smart-8d904c51-0778-41a6-98f1-4d68a7a8ec23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669239006 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_nack_acqfull.669239006
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.2642107666
Short name T1094
Test name
Test status
Simulation time 1861792809 ps
CPU time 2.69 seconds
Started Jul 17 05:49:02 PM PDT 24
Finished Jul 17 05:49:07 PM PDT 24
Peak memory 205576 kb
Host smart-ce35f185-e22b-4046-9547-70d1a0b1f1f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642107666 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.2642107666
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_txstretch.221829330
Short name T166
Test name
Test status
Simulation time 502814378 ps
CPU time 1.31 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:49:01 PM PDT 24
Peak memory 222452 kb
Host smart-b8961814-8480-40d5-aba3-76382b1024e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221829330 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_nack_txstretch.221829330
Directory /workspace/43.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/43.i2c_target_perf.3336295881
Short name T618
Test name
Test status
Simulation time 3026545061 ps
CPU time 3.81 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 213876 kb
Host smart-c1139d42-9a38-43fd-b658-656c66f62e75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336295881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.3336295881
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.3293259262
Short name T2
Test name
Test status
Simulation time 953861865 ps
CPU time 2.1 seconds
Started Jul 17 05:49:16 PM PDT 24
Finished Jul 17 05:49:22 PM PDT 24
Peak memory 205360 kb
Host smart-c2e33612-8434-4e27-ba23-1c2bf106b000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293259262 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_smbus_maxlen.3293259262
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1027732626
Short name T1022
Test name
Test status
Simulation time 4052643827 ps
CPU time 15.98 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 213896 kb
Host smart-6b01fe32-0845-4611-ad52-57e60793c605
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027732626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1027732626
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.2079616302
Short name T735
Test name
Test status
Simulation time 36354497446 ps
CPU time 80.27 seconds
Started Jul 17 05:49:16 PM PDT 24
Finished Jul 17 05:50:41 PM PDT 24
Peak memory 1177936 kb
Host smart-1c5df2b6-7b9c-4541-b593-dcf7616b8b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079616302 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.2079616302
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.1218617127
Short name T331
Test name
Test status
Simulation time 1497360574 ps
CPU time 23.54 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:26 PM PDT 24
Peak memory 230924 kb
Host smart-81b37aa7-72b9-4789-b2b2-bf6f8b14dd72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218617127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.1218617127
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1958880829
Short name T704
Test name
Test status
Simulation time 28583003938 ps
CPU time 104.15 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:50:46 PM PDT 24
Peak memory 1700256 kb
Host smart-630593f3-8b0a-4e42-9a34-6f456d7c0e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958880829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1958880829
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1763093109
Short name T475
Test name
Test status
Simulation time 1876825596 ps
CPU time 12.97 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:15 PM PDT 24
Peak memory 398664 kb
Host smart-d75a9a8b-e6cb-4d35-a518-5d67ea23aaba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763093109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1763093109
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3504521847
Short name T1220
Test name
Test status
Simulation time 1281074749 ps
CPU time 7.24 seconds
Started Jul 17 05:48:59 PM PDT 24
Finished Jul 17 05:49:10 PM PDT 24
Peak memory 218732 kb
Host smart-134781c7-da2e-4de1-adb1-438958f56ff9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504521847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3504521847
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.4274749108
Short name T874
Test name
Test status
Simulation time 54121312 ps
CPU time 1.35 seconds
Started Jul 17 05:49:03 PM PDT 24
Finished Jul 17 05:49:07 PM PDT 24
Peak memory 205648 kb
Host smart-7ab2f3e7-0cc0-4b94-aa14-e37cd9c23f6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274749108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.4274749108
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1130734338
Short name T1231
Test name
Test status
Simulation time 16150251 ps
CPU time 0.62 seconds
Started Jul 17 05:49:13 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 204848 kb
Host smart-3b48bf45-067d-4bad-a7b1-373ef3da25bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130734338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1130734338
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.50904987
Short name T366
Test name
Test status
Simulation time 295744605 ps
CPU time 5.46 seconds
Started Jul 17 05:49:02 PM PDT 24
Finished Jul 17 05:49:11 PM PDT 24
Peak memory 254192 kb
Host smart-dffc5970-c7f3-4cf6-9074-1fd0f3db5e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50904987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.50904987
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.537008120
Short name T604
Test name
Test status
Simulation time 1595946667 ps
CPU time 6.08 seconds
Started Jul 17 05:48:59 PM PDT 24
Finished Jul 17 05:49:09 PM PDT 24
Peak memory 247548 kb
Host smart-3d5aed6c-fd9c-4cb8-96f4-14a89c68c0c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537008120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.537008120
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2618034728
Short name T1615
Test name
Test status
Simulation time 13601340700 ps
CPU time 85.4 seconds
Started Jul 17 05:49:02 PM PDT 24
Finished Jul 17 05:50:30 PM PDT 24
Peak memory 479248 kb
Host smart-8603b275-04a1-4e4f-af1d-f9a89fecd9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618034728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2618034728
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2124397521
Short name T452
Test name
Test status
Simulation time 8969243466 ps
CPU time 72.51 seconds
Started Jul 17 05:49:00 PM PDT 24
Finished Jul 17 05:50:16 PM PDT 24
Peak memory 722584 kb
Host smart-ee965a58-a18c-45b8-8ef4-c62d089706a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124397521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2124397521
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1118478324
Short name T243
Test name
Test status
Simulation time 349803189 ps
CPU time 0.9 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:03 PM PDT 24
Peak memory 205384 kb
Host smart-b9c363c7-fc76-42ca-8b97-fe34bdd4b1e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118478324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1118478324
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1028741714
Short name T1248
Test name
Test status
Simulation time 286461921 ps
CPU time 2.94 seconds
Started Jul 17 05:49:04 PM PDT 24
Finished Jul 17 05:49:10 PM PDT 24
Peak memory 205484 kb
Host smart-b287ee30-dfd9-4640-a413-d4f25264c7ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028741714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1028741714
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.572513868
Short name T378
Test name
Test status
Simulation time 5894475100 ps
CPU time 223.87 seconds
Started Jul 17 05:49:05 PM PDT 24
Finished Jul 17 05:52:52 PM PDT 24
Peak memory 1021316 kb
Host smart-b6984d19-d88f-4c30-95b9-9704437a8daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572513868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.572513868
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.4277237341
Short name T13
Test name
Test status
Simulation time 78452799 ps
CPU time 1.94 seconds
Started Jul 17 05:49:00 PM PDT 24
Finished Jul 17 05:49:05 PM PDT 24
Peak memory 205528 kb
Host smart-18857a2f-0a76-48c7-b0d9-6b56bc6cc03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277237341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.4277237341
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.529335870
Short name T96
Test name
Test status
Simulation time 19444379 ps
CPU time 0.67 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:01 PM PDT 24
Peak memory 204540 kb
Host smart-089ca60d-cffc-43b4-826f-4e28b4bc54ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529335870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.529335870
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2137062797
Short name T327
Test name
Test status
Simulation time 6557277139 ps
CPU time 30.85 seconds
Started Jul 17 05:49:05 PM PDT 24
Finished Jul 17 05:49:39 PM PDT 24
Peak memory 205568 kb
Host smart-3ca93603-7612-4654-a2ef-8d76798f0d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137062797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2137062797
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.1646391010
Short name T955
Test name
Test status
Simulation time 147633259 ps
CPU time 1.93 seconds
Started Jul 17 05:49:03 PM PDT 24
Finished Jul 17 05:49:08 PM PDT 24
Peak memory 223360 kb
Host smart-2af2f1e5-8e9c-496d-8f54-7e18b072e9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646391010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.1646391010
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3314762305
Short name T1533
Test name
Test status
Simulation time 8770340610 ps
CPU time 55.52 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:58 PM PDT 24
Peak memory 253824 kb
Host smart-dc40f618-e36e-4152-8d1b-900985e0ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314762305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3314762305
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.1539214450
Short name T25
Test name
Test status
Simulation time 29814677391 ps
CPU time 1506.84 seconds
Started Jul 17 05:48:59 PM PDT 24
Finished Jul 17 06:14:10 PM PDT 24
Peak memory 2342592 kb
Host smart-be69097b-0c85-4219-ba3a-3bfdb7742a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539214450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.1539214450
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1882766586
Short name T808
Test name
Test status
Simulation time 1528991260 ps
CPU time 12.35 seconds
Started Jul 17 05:49:03 PM PDT 24
Finished Jul 17 05:49:18 PM PDT 24
Peak memory 221260 kb
Host smart-36c78842-814a-445d-85b7-7c83ba611704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882766586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1882766586
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3397281966
Short name T1011
Test name
Test status
Simulation time 851907142 ps
CPU time 4.46 seconds
Started Jul 17 05:49:16 PM PDT 24
Finished Jul 17 05:49:25 PM PDT 24
Peak memory 218848 kb
Host smart-9aa14f57-4448-40e1-8fc5-ae36687359a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397281966 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3397281966
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.287009136
Short name T99
Test name
Test status
Simulation time 179682596 ps
CPU time 1.08 seconds
Started Jul 17 05:48:56 PM PDT 24
Finished Jul 17 05:48:59 PM PDT 24
Peak memory 205388 kb
Host smart-05a13474-fa5e-438a-8ec5-2174abbd1e5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287009136 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.287009136
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1960000053
Short name T1117
Test name
Test status
Simulation time 328396375 ps
CPU time 1.57 seconds
Started Jul 17 05:49:16 PM PDT 24
Finished Jul 17 05:49:21 PM PDT 24
Peak memory 205564 kb
Host smart-a2c12abf-3bd8-47c1-978b-435a471536b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960000053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1960000053
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.1924638172
Short name T1371
Test name
Test status
Simulation time 1959965636 ps
CPU time 2.67 seconds
Started Jul 17 05:49:16 PM PDT 24
Finished Jul 17 05:49:23 PM PDT 24
Peak memory 205588 kb
Host smart-62f2419e-d5d7-4816-b00f-1375c56791ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924638172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.1924638172
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.4262703684
Short name T1550
Test name
Test status
Simulation time 115094865 ps
CPU time 1.36 seconds
Started Jul 17 05:49:17 PM PDT 24
Finished Jul 17 05:49:22 PM PDT 24
Peak memory 205204 kb
Host smart-eb97b103-0eb6-400a-b010-6b8abeeb9aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262703684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.4262703684
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3664394063
Short name T174
Test name
Test status
Simulation time 713183065 ps
CPU time 1.52 seconds
Started Jul 17 05:49:16 PM PDT 24
Finished Jul 17 05:49:22 PM PDT 24
Peak memory 216476 kb
Host smart-94fa3511-9e4a-4f21-ba1a-fcde92031c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664394063 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3664394063
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1745098424
Short name T1573
Test name
Test status
Simulation time 9343489341 ps
CPU time 4.08 seconds
Started Jul 17 05:49:02 PM PDT 24
Finished Jul 17 05:49:09 PM PDT 24
Peak memory 216092 kb
Host smart-c7ccc03e-ae49-40a6-9a82-7b9f8501d990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745098424 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1745098424
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1471826246
Short name T1027
Test name
Test status
Simulation time 12476919917 ps
CPU time 42.5 seconds
Started Jul 17 05:48:58 PM PDT 24
Finished Jul 17 05:49:45 PM PDT 24
Peak memory 842428 kb
Host smart-e26b6785-8730-49f0-9520-95f7f67dd093
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471826246 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1471826246
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.1752988473
Short name T913
Test name
Test status
Simulation time 1866218003 ps
CPU time 2.6 seconds
Started Jul 17 05:49:10 PM PDT 24
Finished Jul 17 05:49:16 PM PDT 24
Peak memory 213824 kb
Host smart-ba2fb6a7-7191-4205-8c79-2d01604ea278
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752988473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_nack_acqfull.1752988473
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.1901929498
Short name T1420
Test name
Test status
Simulation time 1731467561 ps
CPU time 2.2 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:18 PM PDT 24
Peak memory 205636 kb
Host smart-33b7e602-1941-4569-bd5e-8635fc2a2cda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901929498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.1901929498
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.1446110061
Short name T341
Test name
Test status
Simulation time 1601924855 ps
CPU time 6.16 seconds
Started Jul 17 05:49:03 PM PDT 24
Finished Jul 17 05:49:12 PM PDT 24
Peak memory 210448 kb
Host smart-def09b15-2c22-4a75-a5b5-321cbc5fcde8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446110061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.1446110061
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.3195819160
Short name T550
Test name
Test status
Simulation time 541654538 ps
CPU time 2.35 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:18 PM PDT 24
Peak memory 205392 kb
Host smart-6da36546-c86b-4a65-8d71-54c19669d261
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195819160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_smbus_maxlen.3195819160
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3670836419
Short name T1265
Test name
Test status
Simulation time 3135607170 ps
CPU time 29.87 seconds
Started Jul 17 05:49:03 PM PDT 24
Finished Jul 17 05:49:36 PM PDT 24
Peak memory 213936 kb
Host smart-99838afc-7538-424d-8375-9d396a0d9cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670836419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3670836419
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.2183491087
Short name T1451
Test name
Test status
Simulation time 38727542985 ps
CPU time 95.08 seconds
Started Jul 17 05:49:00 PM PDT 24
Finished Jul 17 05:50:38 PM PDT 24
Peak memory 1035744 kb
Host smart-452fdce9-d67a-4655-8a52-9e75fe6bd244
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183491087 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_stress_all.2183491087
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.979091703
Short name T1729
Test name
Test status
Simulation time 1491769200 ps
CPU time 20.55 seconds
Started Jul 17 05:48:57 PM PDT 24
Finished Jul 17 05:49:22 PM PDT 24
Peak memory 235308 kb
Host smart-ec464703-118f-4d49-b924-92fa46d8521f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979091703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.979091703
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.905228459
Short name T680
Test name
Test status
Simulation time 47423908598 ps
CPU time 135.42 seconds
Started Jul 17 05:49:03 PM PDT 24
Finished Jul 17 05:51:22 PM PDT 24
Peak memory 1733140 kb
Host smart-d6add4cf-193d-4e95-8023-6cd8974d7d41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905228459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.905228459
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.4161108847
Short name T1038
Test name
Test status
Simulation time 6596310749 ps
CPU time 8.83 seconds
Started Jul 17 05:49:00 PM PDT 24
Finished Jul 17 05:49:12 PM PDT 24
Peak memory 230192 kb
Host smart-6102215e-13c9-4b14-8830-8e3dd2f600dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161108847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.4161108847
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3597360119
Short name T56
Test name
Test status
Simulation time 185135541 ps
CPU time 2.55 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:15 PM PDT 24
Peak memory 205644 kb
Host smart-252c15ed-6788-4749-b9b0-6bf64d38aa3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597360119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3597360119
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1219856178
Short name T387
Test name
Test status
Simulation time 18403328 ps
CPU time 0.67 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 204820 kb
Host smart-208091d8-92b7-429f-aaa4-6e6ed52f14b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219856178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1219856178
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.575991918
Short name T849
Test name
Test status
Simulation time 458560457 ps
CPU time 1.62 seconds
Started Jul 17 05:49:08 PM PDT 24
Finished Jul 17 05:49:13 PM PDT 24
Peak memory 217500 kb
Host smart-1f80b50c-efff-49c0-8860-d00c9ff7ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575991918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.575991918
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2317416302
Short name T1660
Test name
Test status
Simulation time 1028159961 ps
CPU time 12.74 seconds
Started Jul 17 05:49:10 PM PDT 24
Finished Jul 17 05:49:27 PM PDT 24
Peak memory 256044 kb
Host smart-2bfca33a-9632-4764-b1e1-536463c5084a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317416302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2317416302
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2073978257
Short name T563
Test name
Test status
Simulation time 2999367010 ps
CPU time 134.74 seconds
Started Jul 17 05:49:14 PM PDT 24
Finished Jul 17 05:51:33 PM PDT 24
Peak memory 842816 kb
Host smart-1a535d80-2008-4bc9-8cb1-df2b520c17e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073978257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2073978257
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3789008522
Short name T521
Test name
Test status
Simulation time 11751973068 ps
CPU time 174.77 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:52:07 PM PDT 24
Peak memory 724392 kb
Host smart-e93dc6fc-d560-47cc-97aa-7de2f734f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789008522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3789008522
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1302580460
Short name T1587
Test name
Test status
Simulation time 291315639 ps
CPU time 1.02 seconds
Started Jul 17 05:49:08 PM PDT 24
Finished Jul 17 05:49:13 PM PDT 24
Peak memory 205260 kb
Host smart-8b89fecf-9009-4a17-9ef5-c09efb12f75d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302580460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1302580460
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2041209058
Short name T1726
Test name
Test status
Simulation time 218493462 ps
CPU time 5.1 seconds
Started Jul 17 05:49:10 PM PDT 24
Finished Jul 17 05:49:19 PM PDT 24
Peak memory 205532 kb
Host smart-8f6ff790-dfff-4459-81bc-3ebc8714380e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041209058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2041209058
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2863633540
Short name T1219
Test name
Test status
Simulation time 11438646642 ps
CPU time 78.85 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:50:35 PM PDT 24
Peak memory 920632 kb
Host smart-3292825e-8a0c-4cdf-bfb8-fedc781cd235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863633540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2863633540
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1149836333
Short name T850
Test name
Test status
Simulation time 585351576 ps
CPU time 3.79 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:20 PM PDT 24
Peak memory 205512 kb
Host smart-7702cd64-3505-498b-8d72-7c3a081e4f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149836333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1149836333
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_override.3377223121
Short name T424
Test name
Test status
Simulation time 37576471 ps
CPU time 0.65 seconds
Started Jul 17 05:49:10 PM PDT 24
Finished Jul 17 05:49:15 PM PDT 24
Peak memory 205136 kb
Host smart-0a4f126f-10eb-46ee-ac69-fad9ffdb578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377223121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3377223121
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.4274401223
Short name T1256
Test name
Test status
Simulation time 6192359078 ps
CPU time 61.77 seconds
Started Jul 17 05:49:08 PM PDT 24
Finished Jul 17 05:50:13 PM PDT 24
Peak memory 214704 kb
Host smart-9ff5835c-ae4c-41d3-863c-14fa057cc928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274401223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.4274401223
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.77259515
Short name T1126
Test name
Test status
Simulation time 146327867 ps
CPU time 1.13 seconds
Started Jul 17 05:49:13 PM PDT 24
Finished Jul 17 05:49:18 PM PDT 24
Peak memory 213400 kb
Host smart-8b3e4e51-d2c2-4745-a953-288348827b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77259515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.77259515
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1511172385
Short name T705
Test name
Test status
Simulation time 4545828938 ps
CPU time 23.97 seconds
Started Jul 17 05:49:10 PM PDT 24
Finished Jul 17 05:49:38 PM PDT 24
Peak memory 333424 kb
Host smart-5377f693-60b9-45f3-a25b-92ac16784c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511172385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1511172385
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.3566256943
Short name T751
Test name
Test status
Simulation time 497633391 ps
CPU time 20.29 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:37 PM PDT 24
Peak memory 213660 kb
Host smart-c0c6bea3-81c1-4d1e-8364-f2c97a2ea681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566256943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3566256943
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2405791934
Short name T1163
Test name
Test status
Simulation time 1104835783 ps
CPU time 6.29 seconds
Started Jul 17 05:49:10 PM PDT 24
Finished Jul 17 05:49:20 PM PDT 24
Peak memory 221980 kb
Host smart-c9810691-cc56-4e47-bccf-dad8b1b4191a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405791934 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2405791934
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.432210136
Short name T869
Test name
Test status
Simulation time 337555208 ps
CPU time 1.25 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:14 PM PDT 24
Peak memory 213804 kb
Host smart-72a7bb92-52a5-41ea-9951-70ac7884d239
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432210136 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_acq.432210136
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3077207327
Short name T1133
Test name
Test status
Simulation time 211144125 ps
CPU time 1.41 seconds
Started Jul 17 05:49:08 PM PDT 24
Finished Jul 17 05:49:13 PM PDT 24
Peak memory 205584 kb
Host smart-274409b2-b72c-4be6-849c-1e0f2544d67b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077207327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3077207327
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.316047631
Short name T484
Test name
Test status
Simulation time 107930133 ps
CPU time 1 seconds
Started Jul 17 05:49:13 PM PDT 24
Finished Jul 17 05:49:18 PM PDT 24
Peak memory 205428 kb
Host smart-fa808862-72f2-4d77-8ce4-06e041307da3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316047631 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.316047631
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.1652694803
Short name T653
Test name
Test status
Simulation time 134974855 ps
CPU time 1.41 seconds
Started Jul 17 05:49:11 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 205396 kb
Host smart-aad4e548-6735-418d-b438-bc1df43158b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652694803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.1652694803
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.3811451860
Short name T567
Test name
Test status
Simulation time 799946556 ps
CPU time 2.14 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:15 PM PDT 24
Peak memory 213836 kb
Host smart-6c49ae08-1bd9-4939-be05-1658cc95e460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811451860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.3811451860
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2270707055
Short name T781
Test name
Test status
Simulation time 10932291871 ps
CPU time 6.69 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:20 PM PDT 24
Peak memory 220180 kb
Host smart-a0819be1-722e-47fc-8cc5-066b60f3ce23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270707055 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2270707055
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3856431220
Short name T540
Test name
Test status
Simulation time 15057211808 ps
CPU time 153.52 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:51:46 PM PDT 24
Peak memory 2018260 kb
Host smart-754f30f3-3134-4b78-a455-d670855f7e30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856431220 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3856431220
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.2781529230
Short name T87
Test name
Test status
Simulation time 1987719012 ps
CPU time 2.75 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:19 PM PDT 24
Peak memory 213788 kb
Host smart-ca3c26ec-ceea-40a2-ab78-cc3a4dfd6930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781529230 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_nack_acqfull.2781529230
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.3203828813
Short name T1457
Test name
Test status
Simulation time 2332248443 ps
CPU time 2.44 seconds
Started Jul 17 05:49:08 PM PDT 24
Finished Jul 17 05:49:14 PM PDT 24
Peak memory 205652 kb
Host smart-f1e85844-bf76-4026-b2ee-6d5548b80fb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203828813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.3203828813
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_txstretch.597761793
Short name T1244
Test name
Test status
Simulation time 153830236 ps
CPU time 1.38 seconds
Started Jul 17 05:49:13 PM PDT 24
Finished Jul 17 05:49:18 PM PDT 24
Peak memory 222284 kb
Host smart-1d65783c-2ec7-4ca1-9902-2791e205add9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597761793 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_nack_txstretch.597761793
Directory /workspace/45.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/45.i2c_target_perf.3150911590
Short name T1092
Test name
Test status
Simulation time 646020838 ps
CPU time 4.77 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:20 PM PDT 24
Peak memory 216108 kb
Host smart-9d792289-6517-4b13-99e4-11865494d14b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150911590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.3150911590
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.1477796964
Short name T722
Test name
Test status
Simulation time 1850608984 ps
CPU time 2.12 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:16 PM PDT 24
Peak memory 205368 kb
Host smart-3b32d525-6313-436f-b646-f04d6c74d352
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477796964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_smbus_maxlen.1477796964
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2633197905
Short name T649
Test name
Test status
Simulation time 826877861 ps
CPU time 8.82 seconds
Started Jul 17 05:49:20 PM PDT 24
Finished Jul 17 05:49:33 PM PDT 24
Peak memory 213704 kb
Host smart-a6b46f9a-2421-4c69-a630-be54155e9b4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633197905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2633197905
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.1108028775
Short name T284
Test name
Test status
Simulation time 33417045508 ps
CPU time 184.46 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:52:20 PM PDT 24
Peak memory 1289664 kb
Host smart-97870343-d713-4af2-b93f-1d0d3b235503
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108028775 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.1108028775
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.285735744
Short name T48
Test name
Test status
Simulation time 1552659779 ps
CPU time 28.38 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:41 PM PDT 24
Peak memory 230152 kb
Host smart-e3a93fda-093a-4e17-967a-8ae862ec777c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285735744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.285735744
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.1651443963
Short name T1564
Test name
Test status
Simulation time 42471089599 ps
CPU time 271.95 seconds
Started Jul 17 05:49:10 PM PDT 24
Finished Jul 17 05:53:46 PM PDT 24
Peak memory 2839524 kb
Host smart-d3816718-0b91-4356-a05e-59c30d010e81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651443963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.1651443963
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2755581745
Short name T1427
Test name
Test status
Simulation time 2252799088 ps
CPU time 10.45 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:23 PM PDT 24
Peak memory 321676 kb
Host smart-2fdbabe2-7dcd-4e2d-abac-542bf6db4898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755581745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2755581745
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3998561783
Short name T268
Test name
Test status
Simulation time 1229151330 ps
CPU time 6.36 seconds
Started Jul 17 05:49:08 PM PDT 24
Finished Jul 17 05:49:17 PM PDT 24
Peak memory 222108 kb
Host smart-333c30c9-7eba-4de7-b177-37e44f7d37d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998561783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3998561783
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3182294434
Short name T1075
Test name
Test status
Simulation time 23876598 ps
CPU time 0.63 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:49:28 PM PDT 24
Peak memory 204764 kb
Host smart-5fc6ee8b-c0cc-42e8-8063-186ec35d0951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182294434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3182294434
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.79326454
Short name T1156
Test name
Test status
Simulation time 256438440 ps
CPU time 1.6 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:18 PM PDT 24
Peak memory 217908 kb
Host smart-fd366f72-4ed3-4ddf-8003-23596a3755c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79326454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.79326454
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2021192027
Short name T307
Test name
Test status
Simulation time 2177116344 ps
CPU time 11.63 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:28 PM PDT 24
Peak memory 326848 kb
Host smart-8a1ec7d3-c0b5-45b7-a102-57f5f7c15181
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021192027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2021192027
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1498077169
Short name T594
Test name
Test status
Simulation time 2052332616 ps
CPU time 58.01 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:50:11 PM PDT 24
Peak memory 379444 kb
Host smart-7a59311c-ad2e-4212-8b15-7d61b55d41a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498077169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1498077169
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.4007115953
Short name T505
Test name
Test status
Simulation time 12402598482 ps
CPU time 48.69 seconds
Started Jul 17 05:49:13 PM PDT 24
Finished Jul 17 05:50:05 PM PDT 24
Peak memory 638536 kb
Host smart-7b3d588a-18b3-42b8-a885-7033d36c0abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007115953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.4007115953
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.4255915585
Short name T1105
Test name
Test status
Simulation time 524428215 ps
CPU time 1.45 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:14 PM PDT 24
Peak memory 205260 kb
Host smart-111d281f-75ad-4058-a36b-e3d225560dd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255915585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.4255915585
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.3458606288
Short name T1351
Test name
Test status
Simulation time 239902539 ps
CPU time 10.47 seconds
Started Jul 17 05:49:16 PM PDT 24
Finished Jul 17 05:49:30 PM PDT 24
Peak memory 242376 kb
Host smart-59a9385a-7591-45b5-9148-937248fac418
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458606288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.3458606288
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.3045767978
Short name T695
Test name
Test status
Simulation time 51803403188 ps
CPU time 290.19 seconds
Started Jul 17 05:49:14 PM PDT 24
Finished Jul 17 05:54:08 PM PDT 24
Peak memory 1211408 kb
Host smart-b94fe5e8-0092-4efc-8c4a-97e43fd1f144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045767978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3045767978
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1306033557
Short name T581
Test name
Test status
Simulation time 234793574 ps
CPU time 3.41 seconds
Started Jul 17 05:49:23 PM PDT 24
Finished Jul 17 05:49:31 PM PDT 24
Peak memory 205496 kb
Host smart-1247e287-afcf-478b-aca4-0b808e4de7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306033557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1306033557
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.2820736824
Short name T868
Test name
Test status
Simulation time 527079052 ps
CPU time 4.9 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:49:32 PM PDT 24
Peak memory 216704 kb
Host smart-5fc572d5-4a23-46eb-a824-67f24cc30b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820736824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.2820736824
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.642913074
Short name T1730
Test name
Test status
Simulation time 35409236 ps
CPU time 0.66 seconds
Started Jul 17 05:49:15 PM PDT 24
Finished Jul 17 05:49:19 PM PDT 24
Peak memory 205236 kb
Host smart-d8bed311-2dd1-4b48-8c42-36818f33f1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642913074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.642913074
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.361903481
Short name T1386
Test name
Test status
Simulation time 30807055982 ps
CPU time 1592.03 seconds
Started Jul 17 05:49:10 PM PDT 24
Finished Jul 17 06:15:46 PM PDT 24
Peak memory 537648 kb
Host smart-0b43551c-7bcb-4354-b219-6a7997d599bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361903481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.361903481
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.1625132648
Short name T578
Test name
Test status
Simulation time 2129047305 ps
CPU time 7.5 seconds
Started Jul 17 05:49:09 PM PDT 24
Finished Jul 17 05:49:20 PM PDT 24
Peak memory 253768 kb
Host smart-1584e8e4-2a3e-4eb4-a429-81a13e9afa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625132648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.1625132648
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2691632409
Short name T401
Test name
Test status
Simulation time 8533060818 ps
CPU time 117.72 seconds
Started Jul 17 05:49:08 PM PDT 24
Finished Jul 17 05:51:10 PM PDT 24
Peak memory 445148 kb
Host smart-46b9b3f3-8cef-40f3-ad1d-ff0dff1805ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691632409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2691632409
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2836135626
Short name T654
Test name
Test status
Simulation time 1521637702 ps
CPU time 18.41 seconds
Started Jul 17 05:49:12 PM PDT 24
Finished Jul 17 05:49:34 PM PDT 24
Peak memory 213772 kb
Host smart-71cee08e-c6a4-4b9a-b0d7-b73edc463a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836135626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2836135626
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2070406263
Short name T843
Test name
Test status
Simulation time 8305890559 ps
CPU time 3.87 seconds
Started Jul 17 05:49:24 PM PDT 24
Finished Jul 17 05:49:32 PM PDT 24
Peak memory 213936 kb
Host smart-0e2f1511-4e39-4640-af02-5d612ed559c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070406263 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2070406263
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3070008010
Short name T439
Test name
Test status
Simulation time 225012144 ps
CPU time 1.37 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:49:28 PM PDT 24
Peak memory 205452 kb
Host smart-c8b46ff8-06f5-44d4-abb4-325ee8205c3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070008010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3070008010
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.286435615
Short name T1520
Test name
Test status
Simulation time 146240154 ps
CPU time 1.1 seconds
Started Jul 17 05:49:25 PM PDT 24
Finished Jul 17 05:49:30 PM PDT 24
Peak memory 205412 kb
Host smart-0f354612-dea8-48e1-b7da-66631241926f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286435615 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.286435615
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.323793784
Short name T295
Test name
Test status
Simulation time 512049809 ps
CPU time 2.76 seconds
Started Jul 17 05:49:24 PM PDT 24
Finished Jul 17 05:49:31 PM PDT 24
Peak memory 205616 kb
Host smart-42551c07-286f-43bf-90cc-ce52c0d3ac9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323793784 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.323793784
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.959872822
Short name T451
Test name
Test status
Simulation time 575554346 ps
CPU time 1.48 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:49:28 PM PDT 24
Peak memory 205432 kb
Host smart-0fb2626d-7ee3-49b5-8f93-e4c78f5e090d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959872822 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.959872822
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3724686384
Short name T302
Test name
Test status
Simulation time 1229639591 ps
CPU time 6.87 seconds
Started Jul 17 05:49:23 PM PDT 24
Finished Jul 17 05:49:35 PM PDT 24
Peak memory 213856 kb
Host smart-37375e92-0c78-4ce4-a571-8f3307540f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724686384 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3724686384
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2649228209
Short name T524
Test name
Test status
Simulation time 19236983988 ps
CPU time 48.39 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:50:15 PM PDT 24
Peak memory 1049212 kb
Host smart-27398281-c17e-47be-ad3e-64331d3115d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649228209 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2649228209
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.1288555384
Short name T417
Test name
Test status
Simulation time 995118808 ps
CPU time 2.87 seconds
Started Jul 17 05:49:23 PM PDT 24
Finished Jul 17 05:49:30 PM PDT 24
Peak memory 213860 kb
Host smart-e2015ebb-bd9b-4551-b19e-ff92c7cdbc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288555384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_acqfull.1288555384
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.2314997424
Short name T873
Test name
Test status
Simulation time 816112910 ps
CPU time 2.23 seconds
Started Jul 17 05:49:24 PM PDT 24
Finished Jul 17 05:49:30 PM PDT 24
Peak memory 205632 kb
Host smart-09d3643d-dfe2-4fe8-ac54-9968d30c543f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314997424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.2314997424
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_txstretch.289839255
Short name T47
Test name
Test status
Simulation time 695837634 ps
CPU time 1.72 seconds
Started Jul 17 05:49:23 PM PDT 24
Finished Jul 17 05:49:29 PM PDT 24
Peak memory 222364 kb
Host smart-9047bfa6-cfb4-41d4-b351-ca0b28be7434
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289839255 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_nack_txstretch.289839255
Directory /workspace/46.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/46.i2c_target_perf.3120018981
Short name T408
Test name
Test status
Simulation time 2289426818 ps
CPU time 3.78 seconds
Started Jul 17 05:49:24 PM PDT 24
Finished Jul 17 05:49:32 PM PDT 24
Peak memory 222076 kb
Host smart-c2a367ef-de22-490c-8cde-76aaa39e2d21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120018981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.3120018981
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.2641004234
Short name T1423
Test name
Test status
Simulation time 553626662 ps
CPU time 2.61 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:49:30 PM PDT 24
Peak memory 205428 kb
Host smart-71d60b50-ab9d-4142-948f-08dcb802594f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641004234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_smbus_maxlen.2641004234
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2539747065
Short name T488
Test name
Test status
Simulation time 929484482 ps
CPU time 15.31 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:49:42 PM PDT 24
Peak memory 213860 kb
Host smart-a5973d80-0ad2-466f-8833-7165bc8b0ff4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539747065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2539747065
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.598352753
Short name T436
Test name
Test status
Simulation time 42129759575 ps
CPU time 116.49 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:51:23 PM PDT 24
Peak memory 1768512 kb
Host smart-2745bfd4-6f26-4386-89d3-b489d6727768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598352753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_target_stress_all.598352753
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.946465237
Short name T1584
Test name
Test status
Simulation time 2933716820 ps
CPU time 11.45 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:49:38 PM PDT 24
Peak memory 220048 kb
Host smart-49682fe1-f63f-458f-aab4-b4ede3c23b39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946465237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.946465237
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.2739256971
Short name T904
Test name
Test status
Simulation time 43370476304 ps
CPU time 100.52 seconds
Started Jul 17 05:49:23 PM PDT 24
Finished Jul 17 05:51:08 PM PDT 24
Peak memory 1489556 kb
Host smart-57ceb460-7ee9-481c-8533-8e76b8f98758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739256971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.2739256971
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1052714364
Short name T968
Test name
Test status
Simulation time 985597556 ps
CPU time 1.88 seconds
Started Jul 17 05:49:22 PM PDT 24
Finished Jul 17 05:49:29 PM PDT 24
Peak memory 240988 kb
Host smart-cc64d11b-48ba-4e67-9548-0568ac4a1a3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052714364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1052714364
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2808711795
Short name T1535
Test name
Test status
Simulation time 1221240292 ps
CPU time 7.23 seconds
Started Jul 17 05:49:23 PM PDT 24
Finished Jul 17 05:49:35 PM PDT 24
Peak memory 222044 kb
Host smart-a35446f5-bbc0-4e3b-aa28-c84bbacec34b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808711795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2808711795
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.2652469706
Short name T1039
Test name
Test status
Simulation time 788135182 ps
CPU time 9.63 seconds
Started Jul 17 05:49:24 PM PDT 24
Finished Jul 17 05:49:38 PM PDT 24
Peak memory 205524 kb
Host smart-863cd3ed-3321-431f-a46a-029a67eb8799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652469706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.2652469706
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2150879644
Short name T601
Test name
Test status
Simulation time 15511637 ps
CPU time 0.63 seconds
Started Jul 17 05:49:41 PM PDT 24
Finished Jul 17 05:49:46 PM PDT 24
Peak memory 204612 kb
Host smart-2e2889dc-c31e-43ba-ade4-5c64a57f76c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150879644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2150879644
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2688004017
Short name T1026
Test name
Test status
Simulation time 239411038 ps
CPU time 1.38 seconds
Started Jul 17 05:49:36 PM PDT 24
Finished Jul 17 05:49:38 PM PDT 24
Peak memory 213752 kb
Host smart-753b5778-0e1f-4782-a506-b8fad96335b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688004017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2688004017
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3536308047
Short name T1604
Test name
Test status
Simulation time 276552452 ps
CPU time 6 seconds
Started Jul 17 05:49:35 PM PDT 24
Finished Jul 17 05:49:41 PM PDT 24
Peak memory 253504 kb
Host smart-4a9c9b2d-78f4-4d03-874b-1ca7fd402bbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536308047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3536308047
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1548152922
Short name T743
Test name
Test status
Simulation time 6443377553 ps
CPU time 91.4 seconds
Started Jul 17 05:49:39 PM PDT 24
Finished Jul 17 05:51:14 PM PDT 24
Peak memory 679292 kb
Host smart-7fc00e57-1f1f-48c4-80fe-43fb58f710d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548152922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1548152922
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3472862561
Short name T1141
Test name
Test status
Simulation time 10298309927 ps
CPU time 93.85 seconds
Started Jul 17 05:49:36 PM PDT 24
Finished Jul 17 05:51:11 PM PDT 24
Peak memory 825456 kb
Host smart-c4a3ad86-1e12-4653-bd4b-da4fca9596b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472862561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3472862561
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1485004316
Short name T1104
Test name
Test status
Simulation time 1263478847 ps
CPU time 1.07 seconds
Started Jul 17 05:49:39 PM PDT 24
Finished Jul 17 05:49:44 PM PDT 24
Peak memory 205264 kb
Host smart-a165d304-28e1-4443-a825-76e02491fd7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485004316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1485004316
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1782013694
Short name T411
Test name
Test status
Simulation time 573609477 ps
CPU time 3.48 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:44 PM PDT 24
Peak memory 228440 kb
Host smart-3ddebf2e-8811-402b-9e77-512c95198759
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782013694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1782013694
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1192761702
Short name T1158
Test name
Test status
Simulation time 51738962891 ps
CPU time 451.02 seconds
Started Jul 17 05:53:40 PM PDT 24
Finished Jul 17 06:01:12 PM PDT 24
Peak memory 1527968 kb
Host smart-8e6ec182-82ea-4dcd-85a0-988a12fa0907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192761702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1192761702
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2783661218
Short name T1344
Test name
Test status
Simulation time 362009276 ps
CPU time 14.16 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:55 PM PDT 24
Peak memory 205536 kb
Host smart-79d80830-f8a1-4904-9fa6-792383736096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783661218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2783661218
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.2354072158
Short name T139
Test name
Test status
Simulation time 57780618 ps
CPU time 0.65 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:42 PM PDT 24
Peak memory 205212 kb
Host smart-7eb2b376-10a2-4d44-a38e-db7ef1610264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354072158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2354072158
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1765544267
Short name T1057
Test name
Test status
Simulation time 73296911693 ps
CPU time 1337.07 seconds
Started Jul 17 05:49:34 PM PDT 24
Finished Jul 17 06:11:51 PM PDT 24
Peak memory 1286380 kb
Host smart-f0e9df27-d10f-47c0-b3f0-07a752c13d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765544267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1765544267
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.3093483956
Short name T1206
Test name
Test status
Simulation time 284704382 ps
CPU time 1.15 seconds
Started Jul 17 05:49:41 PM PDT 24
Finished Jul 17 05:49:46 PM PDT 24
Peak memory 213688 kb
Host smart-24120041-ff14-44a1-863b-a624481962ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093483956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.3093483956
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3568829997
Short name T1067
Test name
Test status
Simulation time 1795545505 ps
CPU time 31.33 seconds
Started Jul 17 05:49:33 PM PDT 24
Finished Jul 17 05:50:05 PM PDT 24
Peak memory 366432 kb
Host smart-5a4fadd8-0696-4a9d-87e1-ce357605f00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568829997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3568829997
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3836220653
Short name T1575
Test name
Test status
Simulation time 3428556336 ps
CPU time 15.42 seconds
Started Jul 17 05:49:34 PM PDT 24
Finished Jul 17 05:49:50 PM PDT 24
Peak memory 221976 kb
Host smart-3f7c0ea3-c7ef-4be4-aba3-638fe77c8986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836220653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3836220653
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.736009940
Short name T948
Test name
Test status
Simulation time 1795756233 ps
CPU time 5.08 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:45 PM PDT 24
Peak memory 220512 kb
Host smart-09774bcd-044c-4f44-956f-066d8f26f651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736009940 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.736009940
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2029322373
Short name T489
Test name
Test status
Simulation time 727235658 ps
CPU time 1.48 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:49:47 PM PDT 24
Peak memory 205504 kb
Host smart-131f67df-0a70-4242-b1c6-7387f2aa8f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029322373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2029322373
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.421686125
Short name T1324
Test name
Test status
Simulation time 368823070 ps
CPU time 1.41 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:43 PM PDT 24
Peak memory 209232 kb
Host smart-9560cedc-f0ad-4ae1-ad4d-5edc02008e1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421686125 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.421686125
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.4198556035
Short name T496
Test name
Test status
Simulation time 1419748703 ps
CPU time 2.12 seconds
Started Jul 17 05:49:41 PM PDT 24
Finished Jul 17 05:49:47 PM PDT 24
Peak memory 205280 kb
Host smart-e282c36a-d5e1-4b90-b592-770dd74e7631
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198556035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.4198556035
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.2504386879
Short name T73
Test name
Test status
Simulation time 311384493 ps
CPU time 1.53 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:44 PM PDT 24
Peak memory 205412 kb
Host smart-c625512b-7a08-4659-a238-025a1551b4cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504386879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.2504386879
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.177802434
Short name T413
Test name
Test status
Simulation time 1354467301 ps
CPU time 2.15 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:44 PM PDT 24
Peak memory 205800 kb
Host smart-a718bb06-5e9f-4247-91e4-20bc0a95c190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177802434 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.177802434
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1907643439
Short name T1262
Test name
Test status
Simulation time 1617754063 ps
CPU time 4.96 seconds
Started Jul 17 05:49:41 PM PDT 24
Finished Jul 17 05:49:50 PM PDT 24
Peak memory 222008 kb
Host smart-bfcd686d-7331-437a-a783-e3e7c7d4849c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907643439 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1907643439
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1159778156
Short name T1288
Test name
Test status
Simulation time 2872055313 ps
CPU time 6.13 seconds
Started Jul 17 05:49:36 PM PDT 24
Finished Jul 17 05:49:43 PM PDT 24
Peak memory 205848 kb
Host smart-cb0c7665-0f0f-42e9-89a7-e3ac18c3f08c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159778156 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1159778156
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.924034235
Short name T67
Test name
Test status
Simulation time 7446598175 ps
CPU time 2.79 seconds
Started Jul 17 05:49:37 PM PDT 24
Finished Jul 17 05:49:42 PM PDT 24
Peak memory 213884 kb
Host smart-b047d6b8-7d2a-4632-a601-c3419c53d9f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924034235 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_nack_acqfull.924034235
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.2266037455
Short name T1586
Test name
Test status
Simulation time 544172893 ps
CPU time 2.61 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:42 PM PDT 24
Peak memory 205628 kb
Host smart-c6b4dd12-96c5-4a81-bf69-0ba6cbbafe56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266037455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.2266037455
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.333090939
Short name T537
Test name
Test status
Simulation time 8792778710 ps
CPU time 4.52 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:46 PM PDT 24
Peak memory 217912 kb
Host smart-33fefa97-4852-44db-91e4-83092abd4524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333090939 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_perf.333090939
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.3624409976
Short name T361
Test name
Test status
Simulation time 469972045 ps
CPU time 2.34 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:44 PM PDT 24
Peak memory 205468 kb
Host smart-bbdb007b-cb9a-422e-9cfe-4de3aaabd2c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624409976 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_smbus_maxlen.3624409976
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2037596269
Short name T1008
Test name
Test status
Simulation time 855352012 ps
CPU time 12.27 seconds
Started Jul 17 05:49:37 PM PDT 24
Finished Jul 17 05:49:50 PM PDT 24
Peak memory 213856 kb
Host smart-7f4ca9f5-e152-4dd0-9f7d-25cf2d8fa118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037596269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2037596269
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.2354392700
Short name T1361
Test name
Test status
Simulation time 43852921496 ps
CPU time 1256.56 seconds
Started Jul 17 05:49:39 PM PDT 24
Finished Jul 17 06:10:40 PM PDT 24
Peak memory 7001584 kb
Host smart-04302c81-541d-42a7-a6c0-513a5b0a3433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354392700 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.2354392700
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1194719553
Short name T791
Test name
Test status
Simulation time 6816093339 ps
CPU time 11.7 seconds
Started Jul 17 05:49:37 PM PDT 24
Finished Jul 17 05:49:51 PM PDT 24
Peak memory 217476 kb
Host smart-0141f88f-49f2-4861-8249-5e108f7a9c60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194719553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1194719553
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.434257370
Short name T1593
Test name
Test status
Simulation time 21376664072 ps
CPU time 43.77 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 350580 kb
Host smart-0c5851cd-4839-49b5-9d1d-d4c77ba5e5c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434257370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.434257370
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.734906705
Short name T1313
Test name
Test status
Simulation time 5179181164 ps
CPU time 7.31 seconds
Started Jul 17 05:49:39 PM PDT 24
Finished Jul 17 05:49:51 PM PDT 24
Peak memory 230292 kb
Host smart-8fdb2439-bdbe-4bf3-a362-e48d2b3b0a02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734906705 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_timeout.734906705
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.3275427714
Short name T285
Test name
Test status
Simulation time 85449305 ps
CPU time 1.96 seconds
Started Jul 17 05:49:37 PM PDT 24
Finished Jul 17 05:49:41 PM PDT 24
Peak memory 205628 kb
Host smart-8f7bb581-43d5-486e-bc48-b3f083b0a561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275427714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.3275427714
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3523112347
Short name T1403
Test name
Test status
Simulation time 51337525 ps
CPU time 0.67 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:00 PM PDT 24
Peak memory 204780 kb
Host smart-98d914c1-d919-46b7-81ce-1d112b68c8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523112347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3523112347
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2135579240
Short name T19
Test name
Test status
Simulation time 434059298 ps
CPU time 1.87 seconds
Started Jul 17 05:49:39 PM PDT 24
Finished Jul 17 05:49:45 PM PDT 24
Peak memory 213716 kb
Host smart-f2fb5b13-739b-4cc4-b0af-3f7d2ad27c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135579240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2135579240
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.133103553
Short name T1035
Test name
Test status
Simulation time 1777775805 ps
CPU time 4 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:45 PM PDT 24
Peak memory 221264 kb
Host smart-071951c7-83b1-4cab-87fb-d1fb1d1b0271
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133103553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.133103553
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2627620091
Short name T1349
Test name
Test status
Simulation time 9532381166 ps
CPU time 111.16 seconds
Started Jul 17 05:49:37 PM PDT 24
Finished Jul 17 05:51:29 PM PDT 24
Peak memory 666752 kb
Host smart-7e5133d5-9847-4c55-a2ee-a0577be15ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627620091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2627620091
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2076645327
Short name T741
Test name
Test status
Simulation time 2489012510 ps
CPU time 40.41 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:50:21 PM PDT 24
Peak memory 521176 kb
Host smart-050e51ff-65b6-490c-adbc-c3285bb52ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076645327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2076645327
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2408059416
Short name T626
Test name
Test status
Simulation time 192852919 ps
CPU time 1.03 seconds
Started Jul 17 05:49:37 PM PDT 24
Finished Jul 17 05:49:40 PM PDT 24
Peak memory 205272 kb
Host smart-14da3967-b266-4d64-b1da-723c8713c6f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408059416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2408059416
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3202738844
Short name T238
Test name
Test status
Simulation time 597517215 ps
CPU time 3.63 seconds
Started Jul 17 05:49:39 PM PDT 24
Finished Jul 17 05:49:47 PM PDT 24
Peak memory 205528 kb
Host smart-de793f53-d8ce-4482-ae2b-d25128f0e923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202738844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3202738844
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1274645693
Short name T903
Test name
Test status
Simulation time 4872909521 ps
CPU time 134.46 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:51:59 PM PDT 24
Peak memory 1308620 kb
Host smart-bb9c1684-e9ba-4f78-a0b8-eb59ddb4997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274645693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1274645693
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3072486582
Short name T969
Test name
Test status
Simulation time 336211111 ps
CPU time 5.04 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:49:50 PM PDT 24
Peak memory 205720 kb
Host smart-ddbcf65d-2932-4954-8b45-0496638a338b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072486582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3072486582
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_override.4076873403
Short name T1285
Test name
Test status
Simulation time 88856309 ps
CPU time 0.7 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:41 PM PDT 24
Peak memory 205172 kb
Host smart-5d2f7026-93d4-4fcd-a71c-3dc5aa5565d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076873403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.4076873403
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2819824831
Short name T1033
Test name
Test status
Simulation time 27841358104 ps
CPU time 502.46 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:58:03 PM PDT 24
Peak memory 215136 kb
Host smart-e82458a9-b29a-420a-b738-c17cf79c6d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819824831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2819824831
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.1747689001
Short name T961
Test name
Test status
Simulation time 189547337 ps
CPU time 1.4 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:49:46 PM PDT 24
Peak memory 229000 kb
Host smart-9427fc3a-7f39-4d4a-8161-0501c245d459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747689001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.1747689001
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.845003142
Short name T473
Test name
Test status
Simulation time 2236228717 ps
CPU time 34.9 seconds
Started Jul 17 05:49:35 PM PDT 24
Finished Jul 17 05:50:10 PM PDT 24
Peak memory 404756 kb
Host smart-222e3eab-8df0-45c5-92ba-cbe8278c2afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845003142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.845003142
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3187381494
Short name T1339
Test name
Test status
Simulation time 847681658 ps
CPU time 38.02 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:50:19 PM PDT 24
Peak memory 213752 kb
Host smart-b88cd0e4-9171-46c3-b1e6-0d58982eb30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187381494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3187381494
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2827518243
Short name T690
Test name
Test status
Simulation time 598600145 ps
CPU time 3.47 seconds
Started Jul 17 05:49:41 PM PDT 24
Finished Jul 17 05:49:49 PM PDT 24
Peak memory 214032 kb
Host smart-2badf93d-84e0-49bf-814d-d6c86f050c66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827518243 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2827518243
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.4061323336
Short name T1004
Test name
Test status
Simulation time 280810207 ps
CPU time 1.62 seconds
Started Jul 17 05:49:39 PM PDT 24
Finished Jul 17 05:49:46 PM PDT 24
Peak memory 205632 kb
Host smart-8ad0d52f-0236-4071-887e-f3c7d053220b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061323336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.4061323336
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1444094423
Short name T84
Test name
Test status
Simulation time 1647914415 ps
CPU time 1.44 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:49:46 PM PDT 24
Peak memory 213888 kb
Host smart-478040cf-5459-4ff3-8225-345b1aa39c84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444094423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1444094423
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.1337137389
Short name T332
Test name
Test status
Simulation time 405919735 ps
CPU time 2.37 seconds
Started Jul 17 05:49:52 PM PDT 24
Finished Jul 17 05:49:55 PM PDT 24
Peak memory 205664 kb
Host smart-3c185d61-2831-4151-a2bc-6263de997cf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337137389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.1337137389
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.3318991584
Short name T1195
Test name
Test status
Simulation time 64926572 ps
CPU time 0.9 seconds
Started Jul 17 05:49:52 PM PDT 24
Finished Jul 17 05:49:54 PM PDT 24
Peak memory 205384 kb
Host smart-243cd894-853e-4456-95d9-d3922bc82b51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318991584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.3318991584
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1077597781
Short name T860
Test name
Test status
Simulation time 830815466 ps
CPU time 4.38 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:46 PM PDT 24
Peak memory 222008 kb
Host smart-a0806e9f-25dd-4ebe-b3e8-7fc618a54544
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077597781 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1077597781
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.832800148
Short name T1320
Test name
Test status
Simulation time 14579522988 ps
CPU time 80.1 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:51:05 PM PDT 24
Peak memory 1252692 kb
Host smart-b8cc44d9-a36b-4741-b80f-9bbc91b37d47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832800148 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.832800148
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.3979161914
Short name T924
Test name
Test status
Simulation time 578947851 ps
CPU time 2.95 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:00 PM PDT 24
Peak memory 213848 kb
Host smart-632fffce-a844-4506-9690-e9b63bdca510
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979161914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_acqfull.3979161914
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.425927317
Short name T1310
Test name
Test status
Simulation time 667018081 ps
CPU time 2.81 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:02 PM PDT 24
Peak memory 205616 kb
Host smart-05321c04-fa20-4ede-be01-359cc91619c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425927317 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.425927317
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_txstretch.4012428094
Short name T499
Test name
Test status
Simulation time 496889524 ps
CPU time 1.64 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:49:59 PM PDT 24
Peak memory 222548 kb
Host smart-1a907ceb-cbb7-4f96-8226-475d434d358e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012428094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_nack_txstretch.4012428094
Directory /workspace/48.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/48.i2c_target_perf.1718497881
Short name T720
Test name
Test status
Simulation time 3116241146 ps
CPU time 6.53 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:49:51 PM PDT 24
Peak memory 230488 kb
Host smart-7125d639-0a6a-409c-979c-ee2b93c60fbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718497881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.1718497881
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.3096761518
Short name T394
Test name
Test status
Simulation time 868930152 ps
CPU time 2.18 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:02 PM PDT 24
Peak memory 205452 kb
Host smart-a157d7ec-3f70-48a7-8c41-106e4925301a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096761518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_smbus_maxlen.3096761518
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1583456474
Short name T93
Test name
Test status
Simulation time 2342974859 ps
CPU time 15.04 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:49:56 PM PDT 24
Peak memory 209556 kb
Host smart-75ea661a-118f-4c3d-8299-66a2539b2d11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583456474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1583456474
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.243826870
Short name T1617
Test name
Test status
Simulation time 7856180256 ps
CPU time 46.65 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:50:31 PM PDT 24
Peak memory 287652 kb
Host smart-36036a2a-1133-42d4-bfec-3c6027d17730
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243826870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_target_stress_all.243826870
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3180607877
Short name T538
Test name
Test status
Simulation time 2830439737 ps
CPU time 23.69 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:50:04 PM PDT 24
Peak memory 238184 kb
Host smart-17a85ad8-9064-44fc-ab89-c5a6a73c3070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180607877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3180607877
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.547823030
Short name T1108
Test name
Test status
Simulation time 31929795313 ps
CPU time 181.75 seconds
Started Jul 17 05:49:38 PM PDT 24
Finished Jul 17 05:52:43 PM PDT 24
Peak memory 2399964 kb
Host smart-15116239-5d54-4da7-a5a0-e1a8b014dd30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547823030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_wr.547823030
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1459848273
Short name T617
Test name
Test status
Simulation time 1912907116 ps
CPU time 13.49 seconds
Started Jul 17 05:49:36 PM PDT 24
Finished Jul 17 05:49:50 PM PDT 24
Peak memory 250316 kb
Host smart-38693789-fa52-4ba0-a1df-432cb6b3affe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459848273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1459848273
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2544052070
Short name T1704
Test name
Test status
Simulation time 1261831230 ps
CPU time 6.53 seconds
Started Jul 17 05:49:40 PM PDT 24
Finished Jul 17 05:49:51 PM PDT 24
Peak memory 221988 kb
Host smart-f1370f4e-018f-4cf7-8b27-1d9b2ae850e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544052070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2544052070
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.400496406
Short name T515
Test name
Test status
Simulation time 83459356 ps
CPU time 1.81 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:49:58 PM PDT 24
Peak memory 205616 kb
Host smart-89050a6f-80bc-4b1a-8bd2-e20a6a73601d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400496406 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.400496406
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4182902934
Short name T122
Test name
Test status
Simulation time 36595726 ps
CPU time 0.67 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:00 PM PDT 24
Peak memory 204772 kb
Host smart-eac3dad5-a3c7-4e2c-b1a5-5a8714b4fc2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182902934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4182902934
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2778661287
Short name T18
Test name
Test status
Simulation time 72358586 ps
CPU time 1.3 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:49:56 PM PDT 24
Peak memory 213764 kb
Host smart-251c6cad-fed7-4a59-9088-ad1c314a6adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778661287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2778661287
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.4133542162
Short name T859
Test name
Test status
Simulation time 1282565551 ps
CPU time 4.71 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:03 PM PDT 24
Peak memory 255008 kb
Host smart-679ef874-9b7b-4a7b-b1fe-477d7645404f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133542162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.4133542162
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1922560037
Short name T901
Test name
Test status
Simulation time 9937539734 ps
CPU time 58.97 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:58 PM PDT 24
Peak memory 291640 kb
Host smart-6cf87b80-4589-4b6d-a154-e1bbf3521d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922560037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1922560037
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3676754734
Short name T602
Test name
Test status
Simulation time 11249694569 ps
CPU time 54.58 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:50:49 PM PDT 24
Peak memory 657692 kb
Host smart-5cdf17bb-2e99-4565-87de-6f6642bc73c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676754734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3676754734
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.4205365444
Short name T935
Test name
Test status
Simulation time 577779693 ps
CPU time 1.21 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:00 PM PDT 24
Peak memory 205224 kb
Host smart-4d2c6544-bcb4-4369-a680-50fc154ed15d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205365444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.4205365444
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.4192826808
Short name T1439
Test name
Test status
Simulation time 838995033 ps
CPU time 12.44 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:12 PM PDT 24
Peak memory 247528 kb
Host smart-b9d0703d-6559-403a-86df-c9091cd6ebb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192826808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.4192826808
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.326818297
Short name T1335
Test name
Test status
Simulation time 3755952817 ps
CPU time 91.4 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:51:28 PM PDT 24
Peak memory 1109532 kb
Host smart-a31dd3af-8de2-4ab9-84d9-56a02759c7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326818297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.326818297
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.912915998
Short name T1443
Test name
Test status
Simulation time 658325338 ps
CPU time 13.63 seconds
Started Jul 17 05:49:50 PM PDT 24
Finished Jul 17 05:50:05 PM PDT 24
Peak memory 205464 kb
Host smart-21364c99-f5f6-40b4-a74b-16358b903944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912915998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.912915998
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.2143164629
Short name T77
Test name
Test status
Simulation time 109129852 ps
CPU time 2 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:49:57 PM PDT 24
Peak memory 213696 kb
Host smart-2296b31c-b272-4e0d-bbf5-7078cd4690c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143164629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2143164629
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.4048999258
Short name T609
Test name
Test status
Simulation time 17910298 ps
CPU time 0.67 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:49:57 PM PDT 24
Peak memory 205208 kb
Host smart-48c2062f-4cb1-48dd-935f-250b4bb34e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048999258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.4048999258
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.584313978
Short name T15
Test name
Test status
Simulation time 5146237954 ps
CPU time 130.43 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:52:04 PM PDT 24
Peak memory 526396 kb
Host smart-594e30a3-e86a-4fbb-8173-32693f048483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584313978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.584313978
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.3661985045
Short name T305
Test name
Test status
Simulation time 158868572 ps
CPU time 2.34 seconds
Started Jul 17 05:49:52 PM PDT 24
Finished Jul 17 05:49:55 PM PDT 24
Peak memory 205468 kb
Host smart-538ca138-f877-42a2-8595-e752c179d36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661985045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3661985045
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.606576029
Short name T881
Test name
Test status
Simulation time 9524028627 ps
CPU time 37.72 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:50:32 PM PDT 24
Peak memory 415364 kb
Host smart-1dda1b2c-a263-4092-89bb-389a915bf2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606576029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.606576029
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.398810352
Short name T551
Test name
Test status
Simulation time 6709156733 ps
CPU time 29.57 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:28 PM PDT 24
Peak memory 213832 kb
Host smart-79f408d0-ae06-4621-b6fe-912d61b79390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398810352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.398810352
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2694755593
Short name T467
Test name
Test status
Simulation time 1942367193 ps
CPU time 5.32 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:04 PM PDT 24
Peak memory 213776 kb
Host smart-8736cf6e-e3d5-417d-92bf-4561f059759a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694755593 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2694755593
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2430926790
Short name T146
Test name
Test status
Simulation time 504681515 ps
CPU time 1.11 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:49:58 PM PDT 24
Peak memory 205468 kb
Host smart-da600f68-0746-44d2-adc1-080ef6fd4247
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430926790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2430926790
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2528030813
Short name T779
Test name
Test status
Simulation time 187712402 ps
CPU time 0.91 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:49:56 PM PDT 24
Peak memory 205468 kb
Host smart-bd45fe45-d406-40ea-88e9-b429662b0398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528030813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2528030813
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.2011880747
Short name T373
Test name
Test status
Simulation time 887919953 ps
CPU time 2.4 seconds
Started Jul 17 05:49:52 PM PDT 24
Finished Jul 17 05:49:55 PM PDT 24
Peak memory 205640 kb
Host smart-2b8689ad-817d-4618-b169-fc120d8de8fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011880747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.2011880747
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.3319613493
Short name T1749
Test name
Test status
Simulation time 284678437 ps
CPU time 1.65 seconds
Started Jul 17 05:49:57 PM PDT 24
Finished Jul 17 05:50:02 PM PDT 24
Peak memory 205416 kb
Host smart-e9ffec87-aea4-499c-b64b-e527e1cc434c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319613493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.3319613493
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2796705127
Short name T175
Test name
Test status
Simulation time 1353922297 ps
CPU time 3.02 seconds
Started Jul 17 05:49:56 PM PDT 24
Finished Jul 17 05:50:02 PM PDT 24
Peak memory 213908 kb
Host smart-c1ff2e4e-497c-408c-9b6e-534c0496818b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796705127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2796705127
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.807834060
Short name T1192
Test name
Test status
Simulation time 817229340 ps
CPU time 5.16 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:04 PM PDT 24
Peak memory 218844 kb
Host smart-47cf48bf-a7e5-4c37-8ff4-738f22097070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807834060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.807834060
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2291420641
Short name T823
Test name
Test status
Simulation time 10207058467 ps
CPU time 54.23 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:52 PM PDT 24
Peak memory 1441236 kb
Host smart-e1739235-cc0e-46d7-a082-affd7c71adad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291420641 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2291420641
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.1498247461
Short name T158
Test name
Test status
Simulation time 725757975 ps
CPU time 2.81 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:01 PM PDT 24
Peak memory 213828 kb
Host smart-4d94f906-a9a4-469d-88cc-0874c47bf9dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498247461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_nack_acqfull.1498247461
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.3537209105
Short name T1472
Test name
Test status
Simulation time 1675813381 ps
CPU time 2.24 seconds
Started Jul 17 05:49:52 PM PDT 24
Finished Jul 17 05:49:56 PM PDT 24
Peak memory 205584 kb
Host smart-f897146f-80d1-497c-a6f7-91cbdaec09e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537209105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.3537209105
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_txstretch.4152597549
Short name T1712
Test name
Test status
Simulation time 1570811077 ps
CPU time 1.5 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:49:58 PM PDT 24
Peak memory 222244 kb
Host smart-2b018e19-4501-4393-9e94-faed53ca2b40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152597549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_nack_txstretch.4152597549
Directory /workspace/49.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/49.i2c_target_perf.702745406
Short name T1355
Test name
Test status
Simulation time 2869499429 ps
CPU time 4.7 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:01 PM PDT 24
Peak memory 221960 kb
Host smart-ed7367a2-4c1b-4440-ad46-f6d52299b38b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702745406 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_perf.702745406
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.1607287096
Short name T522
Test name
Test status
Simulation time 1540799123 ps
CPU time 2.01 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:49:58 PM PDT 24
Peak memory 205436 kb
Host smart-430c657f-251a-4995-83ff-d5c2b8235d76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607287096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.1607287096
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.817163559
Short name T688
Test name
Test status
Simulation time 3305569618 ps
CPU time 15.52 seconds
Started Jul 17 05:49:53 PM PDT 24
Finished Jul 17 05:50:10 PM PDT 24
Peak memory 213912 kb
Host smart-02eb86e6-98b0-4117-9bfb-a8b54926aef9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817163559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.817163559
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.3225448409
Short name T566
Test name
Test status
Simulation time 35588647752 ps
CPU time 1176.19 seconds
Started Jul 17 05:49:57 PM PDT 24
Finished Jul 17 06:09:37 PM PDT 24
Peak memory 5918452 kb
Host smart-109859f4-2b83-47cf-b75e-7bf1e8d5f78f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225448409 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_stress_all.3225448409
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2943394510
Short name T1668
Test name
Test status
Simulation time 1699791478 ps
CPU time 32.07 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:50:29 PM PDT 24
Peak memory 231704 kb
Host smart-635b5a60-1678-41c7-b5af-9cfc1335c02f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943394510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2943394510
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.61705053
Short name T757
Test name
Test status
Simulation time 26426400326 ps
CPU time 21.72 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:20 PM PDT 24
Peak memory 453264 kb
Host smart-8c918ce9-649c-4813-b6b5-2ce386d73771
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61705053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stress_wr.61705053
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2460433059
Short name T876
Test name
Test status
Simulation time 3779573029 ps
CPU time 8.49 seconds
Started Jul 17 05:49:52 PM PDT 24
Finished Jul 17 05:50:01 PM PDT 24
Peak memory 312596 kb
Host smart-eb32f1a2-d8d2-4790-9707-0e121c36c04c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460433059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2460433059
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.99004321
Short name T1238
Test name
Test status
Simulation time 5122819497 ps
CPU time 6.78 seconds
Started Jul 17 05:49:55 PM PDT 24
Finished Jul 17 05:50:05 PM PDT 24
Peak memory 230224 kb
Host smart-53722179-3621-4df9-bb76-dbba4ab28ca7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99004321 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_timeout.99004321
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.2548404475
Short name T844
Test name
Test status
Simulation time 186614943 ps
CPU time 2.4 seconds
Started Jul 17 05:49:54 PM PDT 24
Finished Jul 17 05:49:58 PM PDT 24
Peak memory 205608 kb
Host smart-e53967c4-09e7-4c21-811b-0409218ec37b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548404475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.2548404475
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3496491159
Short name T1698
Test name
Test status
Simulation time 18779349 ps
CPU time 0.63 seconds
Started Jul 17 05:40:50 PM PDT 24
Finished Jul 17 05:40:52 PM PDT 24
Peak memory 204880 kb
Host smart-efc2c483-4334-4d4a-a413-e640a2c21614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496491159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3496491159
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.908650766
Short name T28
Test name
Test status
Simulation time 152368287 ps
CPU time 2.11 seconds
Started Jul 17 05:47:21 PM PDT 24
Finished Jul 17 05:47:24 PM PDT 24
Peak memory 213708 kb
Host smart-f36d1a30-cdcd-4b85-a148-df96b863d459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908650766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.908650766
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1824217496
Short name T390
Test name
Test status
Simulation time 250400009 ps
CPU time 5.43 seconds
Started Jul 17 05:40:23 PM PDT 24
Finished Jul 17 05:40:30 PM PDT 24
Peak memory 255596 kb
Host smart-02479fde-903f-4dc4-b162-92699b823eef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824217496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1824217496
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3170868065
Short name T590
Test name
Test status
Simulation time 6906473032 ps
CPU time 128.11 seconds
Started Jul 17 05:40:25 PM PDT 24
Finished Jul 17 05:42:34 PM PDT 24
Peak memory 409816 kb
Host smart-d4c2a1f1-56cf-419d-bf2c-79194d6e1a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170868065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3170868065
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3995744489
Short name T1534
Test name
Test status
Simulation time 1781441257 ps
CPU time 45.56 seconds
Started Jul 17 05:40:25 PM PDT 24
Finished Jul 17 05:41:12 PM PDT 24
Peak memory 581968 kb
Host smart-65ca3de3-b23e-475a-abd4-73fde5ece197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995744489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3995744489
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1857640484
Short name T242
Test name
Test status
Simulation time 461599570 ps
CPU time 1.16 seconds
Started Jul 17 05:40:28 PM PDT 24
Finished Jul 17 05:40:30 PM PDT 24
Peak memory 205200 kb
Host smart-6a6e925f-c007-4a13-9a89-6a4072e3fca7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857640484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1857640484
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.645903361
Short name T1705
Test name
Test status
Simulation time 119117925 ps
CPU time 6.1 seconds
Started Jul 17 05:47:29 PM PDT 24
Finished Jul 17 05:47:38 PM PDT 24
Peak memory 205476 kb
Host smart-074e9d25-4cf0-4d10-8d98-34015a4f84f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645903361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.645903361
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1719953558
Short name T121
Test name
Test status
Simulation time 3728326736 ps
CPU time 84.67 seconds
Started Jul 17 05:40:23 PM PDT 24
Finished Jul 17 05:41:48 PM PDT 24
Peak memory 1108008 kb
Host smart-3a3c6bc0-b280-4cc0-b6d1-588d9457234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719953558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1719953558
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.4247425451
Short name T23
Test name
Test status
Simulation time 521375775 ps
CPU time 21.51 seconds
Started Jul 17 05:43:59 PM PDT 24
Finished Jul 17 05:44:21 PM PDT 24
Peak memory 205488 kb
Host smart-3d7f6ddf-1cba-4937-9268-82b2bfdd2db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247425451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.4247425451
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_override.442942965
Short name T1181
Test name
Test status
Simulation time 43151970 ps
CPU time 0.67 seconds
Started Jul 17 05:40:23 PM PDT 24
Finished Jul 17 05:40:24 PM PDT 24
Peak memory 205452 kb
Host smart-a755100c-c29e-41fb-843f-9d1f994da3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442942965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.442942965
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3203977564
Short name T560
Test name
Test status
Simulation time 73329068667 ps
CPU time 2826.63 seconds
Started Jul 17 05:40:25 PM PDT 24
Finished Jul 17 06:27:33 PM PDT 24
Peak memory 205580 kb
Host smart-825f24b0-31d5-44e8-88f1-cee7896f07e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203977564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3203977564
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.3585619247
Short name T981
Test name
Test status
Simulation time 498415813 ps
CPU time 19.71 seconds
Started Jul 17 05:42:21 PM PDT 24
Finished Jul 17 05:42:41 PM PDT 24
Peak memory 205372 kb
Host smart-d8a1d41e-dd24-4b5e-bf64-07092bb0f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585619247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.3585619247
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3866399730
Short name T471
Test name
Test status
Simulation time 1546551856 ps
CPU time 22.68 seconds
Started Jul 17 05:40:24 PM PDT 24
Finished Jul 17 05:40:48 PM PDT 24
Peak memory 294704 kb
Host smart-2ab9861a-d271-491b-b5a7-e59fa2f2e089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866399730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3866399730
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.516146592
Short name T129
Test name
Test status
Simulation time 8653995642 ps
CPU time 210.63 seconds
Started Jul 17 05:40:23 PM PDT 24
Finished Jul 17 05:43:55 PM PDT 24
Peak memory 836452 kb
Host smart-083cd28a-dfeb-4f98-a60f-71959a4b4333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516146592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.516146592
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2771545564
Short name T368
Test name
Test status
Simulation time 1164050725 ps
CPU time 26.93 seconds
Started Jul 17 05:42:03 PM PDT 24
Finished Jul 17 05:42:31 PM PDT 24
Peak memory 213672 kb
Host smart-65d10ebc-719e-46ad-bb19-874b8235a3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771545564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2771545564
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1445861368
Short name T190
Test name
Test status
Simulation time 2875687016 ps
CPU time 4.77 seconds
Started Jul 17 05:40:38 PM PDT 24
Finished Jul 17 05:40:45 PM PDT 24
Peak memory 221532 kb
Host smart-5049f13d-aabb-4d21-85b4-28dc1d31a46f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445861368 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1445861368
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.4166057605
Short name T752
Test name
Test status
Simulation time 489984725 ps
CPU time 1.19 seconds
Started Jul 17 05:40:38 PM PDT 24
Finished Jul 17 05:40:42 PM PDT 24
Peak memory 205380 kb
Host smart-5ca0a817-7785-44dd-8ac3-20ba3aa26f2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166057605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.4166057605
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3496479467
Short name T43
Test name
Test status
Simulation time 971143921 ps
CPU time 1.25 seconds
Started Jul 17 05:40:43 PM PDT 24
Finished Jul 17 05:40:45 PM PDT 24
Peak memory 205404 kb
Host smart-d6308554-32ec-49af-9f7d-a0e144ab9a9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496479467 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3496479467
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.2208912752
Short name T1217
Test name
Test status
Simulation time 1425247598 ps
CPU time 2.74 seconds
Started Jul 17 05:41:29 PM PDT 24
Finished Jul 17 05:41:32 PM PDT 24
Peak memory 205596 kb
Host smart-cfe810c7-244e-459f-9b24-4f4dcb5bff13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208912752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.2208912752
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.3227750307
Short name T1502
Test name
Test status
Simulation time 459506185 ps
CPU time 1.34 seconds
Started Jul 17 05:40:40 PM PDT 24
Finished Jul 17 05:40:43 PM PDT 24
Peak memory 205444 kb
Host smart-26a40011-4037-4f28-a24c-682212bf5111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227750307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.3227750307
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.438237234
Short name T1366
Test name
Test status
Simulation time 2934071367 ps
CPU time 4.92 seconds
Started Jul 17 05:40:42 PM PDT 24
Finished Jul 17 05:40:48 PM PDT 24
Peak memory 221488 kb
Host smart-24133005-3dcf-456a-aca3-a9d0d94da8e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438237234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.438237234
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.4174639977
Short name T889
Test name
Test status
Simulation time 1415463990 ps
CPU time 2.01 seconds
Started Jul 17 05:45:24 PM PDT 24
Finished Jul 17 05:45:27 PM PDT 24
Peak memory 205636 kb
Host smart-7a2775d2-102e-4def-b6cc-f7341c895704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174639977 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.4174639977
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.2876618446
Short name T1321
Test name
Test status
Simulation time 4166368451 ps
CPU time 3.24 seconds
Started Jul 17 05:42:16 PM PDT 24
Finished Jul 17 05:42:20 PM PDT 24
Peak memory 213932 kb
Host smart-7a9d6f46-73fd-444d-926e-569e6290a7f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876618446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_nack_acqfull.2876618446
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.1914856371
Short name T1710
Test name
Test status
Simulation time 1311739270 ps
CPU time 2.58 seconds
Started Jul 17 05:47:22 PM PDT 24
Finished Jul 17 05:47:26 PM PDT 24
Peak memory 205616 kb
Host smart-d16b9499-8990-4a13-9bfd-e97f08143e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914856371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.1914856371
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.3180299596
Short name T310
Test name
Test status
Simulation time 529254466 ps
CPU time 4.02 seconds
Started Jul 17 05:40:46 PM PDT 24
Finished Jul 17 05:40:51 PM PDT 24
Peak memory 219440 kb
Host smart-a21db992-d655-44c7-a7f9-ffaa049933de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180299596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.3180299596
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.833873206
Short name T1399
Test name
Test status
Simulation time 2319913404 ps
CPU time 2.33 seconds
Started Jul 17 05:40:43 PM PDT 24
Finished Jul 17 05:40:47 PM PDT 24
Peak memory 205424 kb
Host smart-e9332733-52b3-4126-8c25-79ce674c818a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833873206 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_smbus_maxlen.833873206
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2373257734
Short name T769
Test name
Test status
Simulation time 1082860484 ps
CPU time 7.49 seconds
Started Jul 17 05:41:28 PM PDT 24
Finished Jul 17 05:41:36 PM PDT 24
Peak memory 213852 kb
Host smart-ac31b8a9-3e0e-4459-9d99-b245d0e5bf7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373257734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2373257734
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.1928503086
Short name T1727
Test name
Test status
Simulation time 52661555346 ps
CPU time 134.4 seconds
Started Jul 17 05:40:37 PM PDT 24
Finished Jul 17 05:42:53 PM PDT 24
Peak memory 1731584 kb
Host smart-307e40b0-b49e-4e34-a0d4-3090235ff9ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928503086 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.1928503086
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.1896431060
Short name T1628
Test name
Test status
Simulation time 901946262 ps
CPU time 16.61 seconds
Started Jul 17 05:41:29 PM PDT 24
Finished Jul 17 05:41:46 PM PDT 24
Peak memory 220428 kb
Host smart-810037ae-3e1e-4564-ab20-3b5f89f82773
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896431060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.1896431060
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2769681029
Short name T1583
Test name
Test status
Simulation time 30401756258 ps
CPU time 36.97 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 769708 kb
Host smart-9cd16a4a-fd43-4b4c-8344-ab1b5a63abb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769681029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2769681029
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3714265190
Short name T655
Test name
Test status
Simulation time 443664000 ps
CPU time 2.25 seconds
Started Jul 17 05:47:06 PM PDT 24
Finished Jul 17 05:47:10 PM PDT 24
Peak memory 218540 kb
Host smart-648bf97e-eb60-42b5-a7e3-82cce0d391ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714265190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3714265190
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.40424139
Short name T1664
Test name
Test status
Simulation time 5720578030 ps
CPU time 7.56 seconds
Started Jul 17 05:40:38 PM PDT 24
Finished Jul 17 05:40:47 PM PDT 24
Peak memory 230272 kb
Host smart-1ff4483b-723e-4375-88fc-28b1d89bd9f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40424139 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_timeout.40424139
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.2189633239
Short name T57
Test name
Test status
Simulation time 516704717 ps
CPU time 6.69 seconds
Started Jul 17 05:40:38 PM PDT 24
Finished Jul 17 05:40:47 PM PDT 24
Peak memory 205608 kb
Host smart-3b141a5a-eea0-4faa-9c4b-ddbac1e14538
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189633239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.2189633239
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2596646668
Short name T1336
Test name
Test status
Simulation time 33004400 ps
CPU time 0.66 seconds
Started Jul 17 05:41:02 PM PDT 24
Finished Jul 17 05:41:04 PM PDT 24
Peak memory 204908 kb
Host smart-e33e3cec-f7c6-4b4b-b1b3-e4c735ba47e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596646668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2596646668
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1822814102
Short name T17
Test name
Test status
Simulation time 68513393 ps
CPU time 1.19 seconds
Started Jul 17 05:40:49 PM PDT 24
Finished Jul 17 05:40:52 PM PDT 24
Peak memory 213708 kb
Host smart-908002ac-5aeb-4291-b930-99b7daebe8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822814102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1822814102
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2668933854
Short name T41
Test name
Test status
Simulation time 1732454954 ps
CPU time 7.88 seconds
Started Jul 17 05:40:56 PM PDT 24
Finished Jul 17 05:41:05 PM PDT 24
Peak memory 301068 kb
Host smart-7c5de201-c657-4988-813f-e1768a8b5c88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668933854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2668933854
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3039119545
Short name T1671
Test name
Test status
Simulation time 1927914171 ps
CPU time 59.55 seconds
Started Jul 17 05:40:50 PM PDT 24
Finished Jul 17 05:41:51 PM PDT 24
Peak memory 423784 kb
Host smart-e56e5560-cd82-4140-b1be-7df9b5d667a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039119545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3039119545
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1921058069
Short name T372
Test name
Test status
Simulation time 5737719621 ps
CPU time 44.17 seconds
Started Jul 17 05:43:58 PM PDT 24
Finished Jul 17 05:44:43 PM PDT 24
Peak memory 538972 kb
Host smart-e9333aee-0d04-4dba-b879-b4f3f2ad6c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921058069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1921058069
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.278896426
Short name T931
Test name
Test status
Simulation time 201629142 ps
CPU time 1.05 seconds
Started Jul 17 05:40:51 PM PDT 24
Finished Jul 17 05:40:53 PM PDT 24
Peak memory 205244 kb
Host smart-962a1dad-8375-4f12-80e1-80066151ce7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278896426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.278896426
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1319240372
Short name T1184
Test name
Test status
Simulation time 658421309 ps
CPU time 4.09 seconds
Started Jul 17 05:40:53 PM PDT 24
Finished Jul 17 05:40:58 PM PDT 24
Peak memory 205552 kb
Host smart-3dc736b0-4121-412d-9ba5-b3549cda8d75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319240372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1319240372
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2399988367
Short name T172
Test name
Test status
Simulation time 30459797147 ps
CPU time 88.8 seconds
Started Jul 17 05:40:39 PM PDT 24
Finished Jul 17 05:42:10 PM PDT 24
Peak memory 1007692 kb
Host smart-7e638469-272d-4ec9-af26-89fce7513bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399988367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2399988367
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2958264698
Short name T1548
Test name
Test status
Simulation time 336772185 ps
CPU time 5.8 seconds
Started Jul 17 05:46:09 PM PDT 24
Finished Jul 17 05:46:16 PM PDT 24
Peak memory 205328 kb
Host smart-ca7e97c0-6a9b-46b9-8beb-e55657fb749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958264698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2958264698
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3363208009
Short name T1670
Test name
Test status
Simulation time 128561458 ps
CPU time 1.68 seconds
Started Jul 17 05:41:07 PM PDT 24
Finished Jul 17 05:41:10 PM PDT 24
Peak memory 213700 kb
Host smart-bd84b8b3-557d-4b15-bfc0-762e35d74e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363208009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3363208009
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.4190311486
Short name T79
Test name
Test status
Simulation time 85109671 ps
CPU time 0.74 seconds
Started Jul 17 05:40:37 PM PDT 24
Finished Jul 17 05:40:40 PM PDT 24
Peak memory 205184 kb
Host smart-2957de04-91a9-49bf-b36e-1dc93844da0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190311486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.4190311486
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.251028685
Short name T706
Test name
Test status
Simulation time 12381608319 ps
CPU time 162.02 seconds
Started Jul 17 05:40:49 PM PDT 24
Finished Jul 17 05:43:32 PM PDT 24
Peak memory 221756 kb
Host smart-79563203-a07c-4a55-8d4a-a1032ab1edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251028685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.251028685
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.1138034091
Short name T304
Test name
Test status
Simulation time 107888742 ps
CPU time 1.94 seconds
Started Jul 17 05:46:05 PM PDT 24
Finished Jul 17 05:46:08 PM PDT 24
Peak memory 223616 kb
Host smart-ea414c33-6d3f-4292-8fe6-566aadba6dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138034091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1138034091
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.413633964
Short name T1422
Test name
Test status
Simulation time 6134429976 ps
CPU time 67.53 seconds
Started Jul 17 05:40:36 PM PDT 24
Finished Jul 17 05:41:45 PM PDT 24
Peak memory 313792 kb
Host smart-ec857c15-8494-4b88-b3ba-9b36e95373cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413633964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.413633964
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1152960741
Short name T300
Test name
Test status
Simulation time 1021028661 ps
CPU time 16.89 seconds
Started Jul 17 05:40:52 PM PDT 24
Finished Jul 17 05:41:10 PM PDT 24
Peak memory 230068 kb
Host smart-0c9e7458-5f74-4a09-8f22-8ed0a4f75993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152960741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1152960741
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.1557299309
Short name T1585
Test name
Test status
Simulation time 1517873859 ps
CPU time 4.06 seconds
Started Jul 17 05:41:01 PM PDT 24
Finished Jul 17 05:41:06 PM PDT 24
Peak memory 219120 kb
Host smart-f6585d9d-754f-49fc-bd40-061e97fdd114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557299309 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1557299309
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.1443023316
Short name T670
Test name
Test status
Simulation time 231748162 ps
CPU time 0.92 seconds
Started Jul 17 05:40:50 PM PDT 24
Finished Jul 17 05:40:52 PM PDT 24
Peak memory 205428 kb
Host smart-320ae3b9-9f24-4f5b-adc4-28cb0a8e6da8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443023316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.1443023316
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2816996382
Short name T698
Test name
Test status
Simulation time 389379946 ps
CPU time 1.54 seconds
Started Jul 17 05:40:50 PM PDT 24
Finished Jul 17 05:40:53 PM PDT 24
Peak memory 213848 kb
Host smart-a802f9c4-db06-43f5-bf33-82ec0d345760
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816996382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2816996382
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.201629587
Short name T445
Test name
Test status
Simulation time 3159861380 ps
CPU time 1.97 seconds
Started Jul 17 05:41:02 PM PDT 24
Finished Jul 17 05:41:05 PM PDT 24
Peak memory 205640 kb
Host smart-19e8fff1-7189-46eb-9be6-0923611d2d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201629587 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.201629587
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.2779345549
Short name T362
Test name
Test status
Simulation time 260034665 ps
CPU time 1.23 seconds
Started Jul 17 05:41:03 PM PDT 24
Finished Jul 17 05:41:05 PM PDT 24
Peak memory 205448 kb
Host smart-e38c8e7d-1371-4933-aa3c-a3e7bcd017d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779345549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.2779345549
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3788783850
Short name T409
Test name
Test status
Simulation time 2884265837 ps
CPU time 4.14 seconds
Started Jul 17 05:47:28 PM PDT 24
Finished Jul 17 05:47:34 PM PDT 24
Peak memory 213836 kb
Host smart-de9682da-ab47-40ee-96ea-bafd9a32b591
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788783850 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3788783850
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3755629387
Short name T386
Test name
Test status
Simulation time 8278874128 ps
CPU time 4.66 seconds
Started Jul 17 05:42:21 PM PDT 24
Finished Jul 17 05:42:26 PM PDT 24
Peak memory 205692 kb
Host smart-bb8b287d-eba6-46fe-a7c8-fe077607d741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755629387 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3755629387
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.1110786072
Short name T608
Test name
Test status
Simulation time 1139746649 ps
CPU time 3.01 seconds
Started Jul 17 05:41:03 PM PDT 24
Finished Jul 17 05:41:08 PM PDT 24
Peak memory 213896 kb
Host smart-521c38d6-a908-4d08-b614-186b4ec613fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110786072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_nack_acqfull.1110786072
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.837757634
Short name T1542
Test name
Test status
Simulation time 2056949854 ps
CPU time 2.4 seconds
Started Jul 17 05:41:08 PM PDT 24
Finished Jul 17 05:41:11 PM PDT 24
Peak memory 205624 kb
Host smart-4c65fd97-7a9a-4e92-aeda-5f11b4655ef9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837757634 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.837757634
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_txstretch.2349764746
Short name T1098
Test name
Test status
Simulation time 199923059 ps
CPU time 1.54 seconds
Started Jul 17 05:41:01 PM PDT 24
Finished Jul 17 05:41:04 PM PDT 24
Peak memory 222124 kb
Host smart-6c2dbf8f-0e74-46e5-afe3-5e610c4166b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349764746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_nack_txstretch.2349764746
Directory /workspace/6.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/6.i2c_target_perf.2019792282
Short name T1476
Test name
Test status
Simulation time 1359265607 ps
CPU time 5.24 seconds
Started Jul 17 05:45:48 PM PDT 24
Finished Jul 17 05:45:54 PM PDT 24
Peak memory 215128 kb
Host smart-fca855da-ff78-47e0-8cd8-88ce958ed86c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019792282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.2019792282
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.85131872
Short name T1551
Test name
Test status
Simulation time 1076548811 ps
CPU time 2.36 seconds
Started Jul 17 05:41:02 PM PDT 24
Finished Jul 17 05:41:06 PM PDT 24
Peak memory 205420 kb
Host smart-90d9cd28-0dfc-4e8a-bb0a-0f7b0f07852d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85131872 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_target_smbus_maxlen.85131872
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1724317243
Short name T1160
Test name
Test status
Simulation time 879297696 ps
CPU time 12.78 seconds
Started Jul 17 05:40:52 PM PDT 24
Finished Jul 17 05:41:06 PM PDT 24
Peak memory 208356 kb
Host smart-04bcb0c3-9881-41e4-9844-0abcadbffc28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724317243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1724317243
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.2387080273
Short name T1272
Test name
Test status
Simulation time 3921472495 ps
CPU time 21.42 seconds
Started Jul 17 05:40:51 PM PDT 24
Finished Jul 17 05:41:13 PM PDT 24
Peak memory 233872 kb
Host smart-7d6e796b-110f-40b3-a81b-4b15fe3bc17f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387080273 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.2387080273
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.374130295
Short name T516
Test name
Test status
Simulation time 3980229878 ps
CPU time 84.86 seconds
Started Jul 17 05:42:05 PM PDT 24
Finished Jul 17 05:43:31 PM PDT 24
Peak memory 218676 kb
Host smart-21bea09d-bac1-46c4-a0f9-a85f2f66c6cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374130295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_rd.374130295
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1846891545
Short name T817
Test name
Test status
Simulation time 9005358710 ps
CPU time 6.12 seconds
Started Jul 17 05:40:54 PM PDT 24
Finished Jul 17 05:41:01 PM PDT 24
Peak memory 205584 kb
Host smart-8972a351-7fb2-49d7-863e-d18383933ea8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846891545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1846891545
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2548419165
Short name T1385
Test name
Test status
Simulation time 1131224627 ps
CPU time 3.79 seconds
Started Jul 17 05:40:49 PM PDT 24
Finished Jul 17 05:40:53 PM PDT 24
Peak memory 247756 kb
Host smart-13b979ba-38c4-4f64-a2f5-aa1bd7e62a33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548419165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2548419165
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1050680722
Short name T1625
Test name
Test status
Simulation time 1422256778 ps
CPU time 7.18 seconds
Started Jul 17 05:40:52 PM PDT 24
Finished Jul 17 05:41:00 PM PDT 24
Peak memory 213948 kb
Host smart-a2e14117-74e8-4ae0-b22f-f9048afaa3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050680722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1050680722
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.3349272587
Short name T1647
Test name
Test status
Simulation time 22979796 ps
CPU time 0.63 seconds
Started Jul 17 05:41:20 PM PDT 24
Finished Jul 17 05:41:21 PM PDT 24
Peak memory 204832 kb
Host smart-3a399068-7d32-4a1d-be0d-55cb778fa51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349272587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3349272587
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1246437377
Short name T1637
Test name
Test status
Simulation time 1343833468 ps
CPU time 3.26 seconds
Started Jul 17 05:41:08 PM PDT 24
Finished Jul 17 05:41:12 PM PDT 24
Peak memory 231180 kb
Host smart-a2e56a50-a14c-4438-8b55-cf02b795363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246437377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1246437377
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.893447934
Short name T888
Test name
Test status
Simulation time 1599280164 ps
CPU time 17.03 seconds
Started Jul 17 05:41:02 PM PDT 24
Finished Jul 17 05:41:20 PM PDT 24
Peak memory 274928 kb
Host smart-dc79fe9d-181a-4e51-a491-29f16a03ea8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893447934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.893447934
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1640899453
Short name T1682
Test name
Test status
Simulation time 2888633855 ps
CPU time 115.6 seconds
Started Jul 17 05:41:02 PM PDT 24
Finished Jul 17 05:42:59 PM PDT 24
Peak memory 792564 kb
Host smart-209cf4c9-b049-436e-97ab-5ed4fe6a9790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640899453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1640899453
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3039106760
Short name T1201
Test name
Test status
Simulation time 2355681070 ps
CPU time 166.59 seconds
Started Jul 17 05:41:03 PM PDT 24
Finished Jul 17 05:43:51 PM PDT 24
Peak memory 702140 kb
Host smart-853c617d-babb-48d1-ba02-6947a4b91669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039106760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3039106760
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2935651686
Short name T1736
Test name
Test status
Simulation time 96903965 ps
CPU time 1.18 seconds
Started Jul 17 05:46:09 PM PDT 24
Finished Jul 17 05:46:11 PM PDT 24
Peak memory 205288 kb
Host smart-7fd189e7-5213-4cd7-99e7-51be98dd635e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935651686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2935651686
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2029694158
Short name T856
Test name
Test status
Simulation time 594771128 ps
CPU time 4.36 seconds
Started Jul 17 05:41:05 PM PDT 24
Finished Jul 17 05:41:10 PM PDT 24
Peak memory 230248 kb
Host smart-2fc8ac84-ee8f-4fd1-9dd5-22d5760dc2d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029694158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2029694158
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3934111524
Short name T664
Test name
Test status
Simulation time 3489376708 ps
CPU time 225.78 seconds
Started Jul 17 05:41:04 PM PDT 24
Finished Jul 17 05:44:52 PM PDT 24
Peak memory 1039248 kb
Host smart-57ccb33f-f6db-48c8-b7aa-0b79740356b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934111524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3934111524
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_override.2406504876
Short name T136
Test name
Test status
Simulation time 18426843 ps
CPU time 0.72 seconds
Started Jul 17 05:41:01 PM PDT 24
Finished Jul 17 05:41:03 PM PDT 24
Peak memory 205196 kb
Host smart-26d159c9-46ef-4edc-bc2a-9b2700b4ea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406504876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2406504876
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.831130422
Short name T37
Test name
Test status
Simulation time 12554146031 ps
CPU time 1317.98 seconds
Started Jul 17 05:46:17 PM PDT 24
Finished Jul 17 06:08:16 PM PDT 24
Peak memory 2172692 kb
Host smart-3d984738-3ab1-4d05-aa0b-66e24683f3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831130422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.831130422
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.4222245341
Short name T723
Test name
Test status
Simulation time 150238617 ps
CPU time 1.23 seconds
Started Jul 17 05:43:59 PM PDT 24
Finished Jul 17 05:44:01 PM PDT 24
Peak memory 213564 kb
Host smart-eb699435-c27b-4ca4-84dd-0060082ac841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222245341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.4222245341
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.461038580
Short name T764
Test name
Test status
Simulation time 2545968221 ps
CPU time 22.15 seconds
Started Jul 17 05:43:59 PM PDT 24
Finished Jul 17 05:44:22 PM PDT 24
Peak memory 280988 kb
Host smart-e8506f80-73a6-4439-8ddd-e1507fdb9aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461038580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.461038580
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.477989556
Short name T513
Test name
Test status
Simulation time 1149483968 ps
CPU time 13.31 seconds
Started Jul 17 05:46:18 PM PDT 24
Finished Jul 17 05:46:32 PM PDT 24
Peak memory 221132 kb
Host smart-1eb6a18e-8767-4e27-8341-667ceb94c623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477989556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.477989556
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1388096915
Short name T647
Test name
Test status
Simulation time 8804528789 ps
CPU time 6.6 seconds
Started Jul 17 05:41:18 PM PDT 24
Finished Jul 17 05:41:25 PM PDT 24
Peak memory 220068 kb
Host smart-080ec919-efa4-43fe-9e73-7323966a9f48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388096915 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1388096915
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1016262652
Short name T1429
Test name
Test status
Simulation time 672434797 ps
CPU time 1.1 seconds
Started Jul 17 05:41:01 PM PDT 24
Finished Jul 17 05:41:03 PM PDT 24
Peak memory 205668 kb
Host smart-7a4b3a34-f25a-400c-8cf9-634d97af46b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016262652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1016262652
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1265834310
Short name T1608
Test name
Test status
Simulation time 758993927 ps
CPU time 1.61 seconds
Started Jul 17 05:41:04 PM PDT 24
Finished Jul 17 05:41:06 PM PDT 24
Peak memory 205712 kb
Host smart-03ce7611-b286-40c7-a7bb-2bcd5b481462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265834310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1265834310
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.461292635
Short name T819
Test name
Test status
Simulation time 1542466952 ps
CPU time 2.2 seconds
Started Jul 17 05:41:16 PM PDT 24
Finished Jul 17 05:41:19 PM PDT 24
Peak memory 205608 kb
Host smart-b8df5b64-ed27-4fbb-ae1b-39574dc96d77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461292635 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.461292635
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.4125848700
Short name T1249
Test name
Test status
Simulation time 491874426 ps
CPU time 1.38 seconds
Started Jul 17 05:41:15 PM PDT 24
Finished Jul 17 05:41:17 PM PDT 24
Peak memory 205452 kb
Host smart-d1fdee07-6764-448d-9428-9fdaaa63c3ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125848700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.4125848700
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2345355365
Short name T546
Test name
Test status
Simulation time 17976880725 ps
CPU time 7.9 seconds
Started Jul 17 05:46:09 PM PDT 24
Finished Jul 17 05:46:18 PM PDT 24
Peak memory 230896 kb
Host smart-7fa725f2-9fcb-434a-a4a0-699edcc4cebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345355365 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2345355365
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1028493240
Short name T1260
Test name
Test status
Simulation time 17592635272 ps
CPU time 25.96 seconds
Started Jul 17 05:41:04 PM PDT 24
Finished Jul 17 05:41:31 PM PDT 24
Peak memory 766408 kb
Host smart-a43df2f8-9ef9-490f-a0bf-9b39e80043f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028493240 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1028493240
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.4151631419
Short name T648
Test name
Test status
Simulation time 2635336679 ps
CPU time 2.82 seconds
Started Jul 17 05:41:14 PM PDT 24
Finished Jul 17 05:41:17 PM PDT 24
Peak memory 213900 kb
Host smart-fb3d9207-b0f1-4521-95f1-0e8520b5474d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151631419 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_acqfull.4151631419
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.3223141139
Short name T1667
Test name
Test status
Simulation time 2427801223 ps
CPU time 2.68 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:46:27 PM PDT 24
Peak memory 205716 kb
Host smart-fadb7795-0d72-4a48-a104-a8c1cc3bd0fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223141139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.3223141139
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_txstretch.1801492385
Short name T1652
Test name
Test status
Simulation time 508801774 ps
CPU time 1.54 seconds
Started Jul 17 05:47:22 PM PDT 24
Finished Jul 17 05:47:25 PM PDT 24
Peak memory 222336 kb
Host smart-339103f3-b27d-4bb4-b6ee-f1f88d51bf16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801492385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_nack_txstretch.1801492385
Directory /workspace/7.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/7.i2c_target_perf.1736280699
Short name T296
Test name
Test status
Simulation time 606835394 ps
CPU time 4 seconds
Started Jul 17 05:41:03 PM PDT 24
Finished Jul 17 05:41:09 PM PDT 24
Peak memory 222076 kb
Host smart-40e0f4f1-2834-49a7-be52-aacf49517791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736280699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.1736280699
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.3787603152
Short name T782
Test name
Test status
Simulation time 1694575933 ps
CPU time 2.48 seconds
Started Jul 17 05:46:09 PM PDT 24
Finished Jul 17 05:46:12 PM PDT 24
Peak memory 205304 kb
Host smart-c25762cd-f4fb-4d9f-a868-71a86327dbbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787603152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_smbus_maxlen.3787603152
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3670252019
Short name T82
Test name
Test status
Simulation time 3494010228 ps
CPU time 25.99 seconds
Started Jul 17 05:45:50 PM PDT 24
Finished Jul 17 05:46:17 PM PDT 24
Peak memory 213896 kb
Host smart-750224db-80e9-4342-99c2-79089515fe63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670252019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3670252019
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.717057821
Short name T1207
Test name
Test status
Simulation time 69586142359 ps
CPU time 324.71 seconds
Started Jul 17 05:41:01 PM PDT 24
Finished Jul 17 05:46:27 PM PDT 24
Peak memory 2055036 kb
Host smart-14ac8fbc-9095-4411-aa8f-ae1ec84b4f02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717057821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_target_stress_all.717057821
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2951450099
Short name T1497
Test name
Test status
Simulation time 3876895439 ps
CPU time 14.39 seconds
Started Jul 17 05:41:08 PM PDT 24
Finished Jul 17 05:41:24 PM PDT 24
Peak memory 219840 kb
Host smart-260347d9-8012-452f-820d-2ebabcd6ea5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951450099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2951450099
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.166099133
Short name T1713
Test name
Test status
Simulation time 7061977852 ps
CPU time 7.95 seconds
Started Jul 17 05:41:02 PM PDT 24
Finished Jul 17 05:41:11 PM PDT 24
Peak memory 205516 kb
Host smart-e3eb83c0-5a5b-4de0-bb50-a3c3750e261f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166099133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.166099133
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3198753900
Short name T1240
Test name
Test status
Simulation time 3967047418 ps
CPU time 33.47 seconds
Started Jul 17 05:41:01 PM PDT 24
Finished Jul 17 05:41:36 PM PDT 24
Peak memory 655100 kb
Host smart-4da0e969-336f-439d-b192-eedfbc5b3536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198753900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3198753900
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.811416036
Short name T1635
Test name
Test status
Simulation time 9358688025 ps
CPU time 7.14 seconds
Started Jul 17 05:47:21 PM PDT 24
Finished Jul 17 05:47:30 PM PDT 24
Peak memory 222044 kb
Host smart-adadb8f7-5435-4d1d-8e52-25c10779b127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811416036 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.811416036
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.2124588756
Short name T1581
Test name
Test status
Simulation time 132988149 ps
CPU time 3.09 seconds
Started Jul 17 05:41:18 PM PDT 24
Finished Jul 17 05:41:21 PM PDT 24
Peak memory 205608 kb
Host smart-8ff23f25-b034-4968-8e6a-b527b4d4b201
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124588756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2124588756
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1015588155
Short name T449
Test name
Test status
Simulation time 40454322 ps
CPU time 0.6 seconds
Started Jul 17 05:41:38 PM PDT 24
Finished Jul 17 05:41:40 PM PDT 24
Peak memory 204776 kb
Host smart-a68a147c-0597-47d8-838a-14de43c76544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015588155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1015588155
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.911162083
Short name T962
Test name
Test status
Simulation time 1354325510 ps
CPU time 1.27 seconds
Started Jul 17 05:41:17 PM PDT 24
Finished Jul 17 05:41:19 PM PDT 24
Peak memory 213792 kb
Host smart-12ff1746-df98-42ab-a90b-d3943ce164f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911162083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.911162083
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1070466845
Short name T415
Test name
Test status
Simulation time 1441689583 ps
CPU time 19.85 seconds
Started Jul 17 05:41:18 PM PDT 24
Finished Jul 17 05:41:39 PM PDT 24
Peak memory 285012 kb
Host smart-b13ea0da-4cb2-4dc2-93e4-b6be34467f8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070466845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1070466845
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1626703853
Short name T481
Test name
Test status
Simulation time 3736854726 ps
CPU time 48.97 seconds
Started Jul 17 05:46:23 PM PDT 24
Finished Jul 17 05:47:13 PM PDT 24
Peak memory 361504 kb
Host smart-3a7604d4-9e84-4dd9-8aaa-768153400fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626703853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1626703853
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1378360252
Short name T101
Test name
Test status
Simulation time 5598564824 ps
CPU time 60.39 seconds
Started Jul 17 05:41:16 PM PDT 24
Finished Jul 17 05:42:17 PM PDT 24
Peak memory 693956 kb
Host smart-dc6d7e67-0601-4f6f-bdf6-4dea8bf02e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378360252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1378360252
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3843471040
Short name T491
Test name
Test status
Simulation time 164185245 ps
CPU time 1.25 seconds
Started Jul 17 05:41:13 PM PDT 24
Finished Jul 17 05:41:15 PM PDT 24
Peak memory 205244 kb
Host smart-6e1aab5a-7677-4810-9b2e-81732168d87b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843471040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3843471040
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1217515484
Short name T762
Test name
Test status
Simulation time 642040268 ps
CPU time 4.06 seconds
Started Jul 17 05:46:10 PM PDT 24
Finished Jul 17 05:46:15 PM PDT 24
Peak memory 234004 kb
Host smart-9abb5b5a-a789-4f6c-a5b0-6e8ec8c63b7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217515484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1217515484
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.789762147
Short name T29
Test name
Test status
Simulation time 14946211578 ps
CPU time 103.51 seconds
Started Jul 17 05:45:39 PM PDT 24
Finished Jul 17 05:47:24 PM PDT 24
Peak memory 1100164 kb
Host smart-b4732e0f-0fb9-4d64-aeb0-4d3b259e1c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789762147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.789762147
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1085393989
Short name T245
Test name
Test status
Simulation time 3266659018 ps
CPU time 9.5 seconds
Started Jul 17 05:46:22 PM PDT 24
Finished Jul 17 05:46:32 PM PDT 24
Peak memory 205628 kb
Host smart-4b3447a0-7a8b-4750-9270-2ef7735858e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085393989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1085393989
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_override.4033362608
Short name T744
Test name
Test status
Simulation time 100296000 ps
CPU time 0.65 seconds
Started Jul 17 05:41:14 PM PDT 24
Finished Jul 17 05:41:15 PM PDT 24
Peak memory 205192 kb
Host smart-a05c3722-dba1-4ca9-89a6-c8fbba3cac4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033362608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.4033362608
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.510795839
Short name T910
Test name
Test status
Simulation time 24836096748 ps
CPU time 172.61 seconds
Started Jul 17 05:47:19 PM PDT 24
Finished Jul 17 05:50:13 PM PDT 24
Peak memory 205560 kb
Host smart-d980cd18-0ca0-4f1d-af55-8b290b1b33c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510795839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.510795839
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.53017271
Short name T1073
Test name
Test status
Simulation time 181978767 ps
CPU time 1.39 seconds
Started Jul 17 05:41:14 PM PDT 24
Finished Jul 17 05:41:16 PM PDT 24
Peak memory 206028 kb
Host smart-e2541b85-1278-43aa-ba75-1bce64f9c47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53017271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.53017271
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.3924140165
Short name T1110
Test name
Test status
Simulation time 1988284584 ps
CPU time 29.71 seconds
Started Jul 17 05:46:04 PM PDT 24
Finished Jul 17 05:46:34 PM PDT 24
Peak memory 359772 kb
Host smart-0dddb9ee-2b73-4f0b-8fbc-90300051ba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924140165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3924140165
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1680191936
Short name T1446
Test name
Test status
Simulation time 925432743 ps
CPU time 35.85 seconds
Started Jul 17 05:41:12 PM PDT 24
Finished Jul 17 05:41:48 PM PDT 24
Peak memory 213700 kb
Host smart-de30a83c-3458-4f3c-98a9-7af0f0492b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680191936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1680191936
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2397204355
Short name T778
Test name
Test status
Simulation time 1511575837 ps
CPU time 4.58 seconds
Started Jul 17 05:41:25 PM PDT 24
Finished Jul 17 05:41:31 PM PDT 24
Peak memory 210724 kb
Host smart-d48fa3dc-9cb6-4bae-9e76-cc1ea6fec5e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397204355 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2397204355
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.422725608
Short name T1401
Test name
Test status
Simulation time 486820205 ps
CPU time 0.89 seconds
Started Jul 17 05:41:27 PM PDT 24
Finished Jul 17 05:41:29 PM PDT 24
Peak memory 205448 kb
Host smart-9ba14fd9-22c3-4163-afed-130438cf2881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422725608 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_acq.422725608
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3020282505
Short name T162
Test name
Test status
Simulation time 174273962 ps
CPU time 1.24 seconds
Started Jul 17 05:41:25 PM PDT 24
Finished Jul 17 05:41:27 PM PDT 24
Peak memory 205548 kb
Host smart-b6a6d802-e50d-45bc-b4ce-fddddf962374
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020282505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3020282505
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.259919639
Short name T854
Test name
Test status
Simulation time 435182910 ps
CPU time 2.48 seconds
Started Jul 17 05:41:24 PM PDT 24
Finished Jul 17 05:41:28 PM PDT 24
Peak memory 205648 kb
Host smart-50072a26-060a-4749-93f8-8eb92408c3a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259919639 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.259919639
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.2231153464
Short name T631
Test name
Test status
Simulation time 179667467 ps
CPU time 1.22 seconds
Started Jul 17 05:41:25 PM PDT 24
Finished Jul 17 05:41:27 PM PDT 24
Peak memory 205428 kb
Host smart-4f013faf-b534-4995-9113-f5d8a220faa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231153464 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.2231153464
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3836677655
Short name T1243
Test name
Test status
Simulation time 277955625 ps
CPU time 1.88 seconds
Started Jul 17 05:41:29 PM PDT 24
Finished Jul 17 05:41:31 PM PDT 24
Peak memory 213788 kb
Host smart-04210e19-826e-4353-9c35-875502b7dac4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836677655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3836677655
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.869444333
Short name T1024
Test name
Test status
Simulation time 4478171959 ps
CPU time 7.03 seconds
Started Jul 17 05:41:25 PM PDT 24
Finished Jul 17 05:41:34 PM PDT 24
Peak memory 222136 kb
Host smart-59b5db36-5d53-4387-a754-31ee8124683f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869444333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.869444333
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2835532191
Short name T1005
Test name
Test status
Simulation time 19325798106 ps
CPU time 148.6 seconds
Started Jul 17 05:41:26 PM PDT 24
Finished Jul 17 05:43:56 PM PDT 24
Peak memory 2163832 kb
Host smart-b6836187-f939-485e-85ed-a8e8e6e81516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835532191 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2835532191
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.2971611453
Short name T1743
Test name
Test status
Simulation time 669559534 ps
CPU time 3.27 seconds
Started Jul 17 05:41:27 PM PDT 24
Finished Jul 17 05:41:31 PM PDT 24
Peak memory 213848 kb
Host smart-c3161cd9-06e4-40e4-a0b6-85411cdc58c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971611453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.2971611453
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.2275228851
Short name T990
Test name
Test status
Simulation time 501933534 ps
CPU time 2.85 seconds
Started Jul 17 05:41:25 PM PDT 24
Finished Jul 17 05:41:29 PM PDT 24
Peak memory 205608 kb
Host smart-894d1401-f491-4d8f-8122-a53993a88f06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275228851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.2275228851
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.1328433338
Short name T853
Test name
Test status
Simulation time 2931522680 ps
CPU time 5.57 seconds
Started Jul 17 05:41:26 PM PDT 24
Finished Jul 17 05:41:32 PM PDT 24
Peak memory 213868 kb
Host smart-5a1ee964-daa0-4d6a-9394-6afb712cd495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328433338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.1328433338
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.3390595835
Short name T1619
Test name
Test status
Simulation time 1573849771 ps
CPU time 2.18 seconds
Started Jul 17 05:41:25 PM PDT 24
Finished Jul 17 05:41:28 PM PDT 24
Peak memory 205408 kb
Host smart-71d3dbcf-fc34-4fe6-8fec-24f0a9a6e1d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390595835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.3390595835
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2439280838
Short name T86
Test name
Test status
Simulation time 2538610723 ps
CPU time 9.11 seconds
Started Jul 17 05:41:26 PM PDT 24
Finished Jul 17 05:41:36 PM PDT 24
Peak memory 213848 kb
Host smart-5063eac5-7050-4641-b9a3-9bf43d1c6952
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439280838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2439280838
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.1641692931
Short name T1080
Test name
Test status
Simulation time 30210122996 ps
CPU time 847.98 seconds
Started Jul 17 05:47:21 PM PDT 24
Finished Jul 17 06:01:30 PM PDT 24
Peak memory 4514268 kb
Host smart-41215c13-4a36-4e53-a703-62d71ae20624
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641692931 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.1641692931
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.83764826
Short name T983
Test name
Test status
Simulation time 1087425039 ps
CPU time 45.96 seconds
Started Jul 17 05:46:12 PM PDT 24
Finished Jul 17 05:46:59 PM PDT 24
Peak memory 213800 kb
Host smart-83364d7e-5eaf-4494-9970-e6278ee77c51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83764826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stress_rd.83764826
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3432930303
Short name T211
Test name
Test status
Simulation time 54192433002 ps
CPU time 153.32 seconds
Started Jul 17 05:41:23 PM PDT 24
Finished Jul 17 05:43:57 PM PDT 24
Peak memory 1867452 kb
Host smart-8c1b5f6d-7021-4b46-a502-9ffa6a1e49b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432930303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3432930303
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3559260763
Short name T1014
Test name
Test status
Simulation time 5719550958 ps
CPU time 60.84 seconds
Started Jul 17 05:41:24 PM PDT 24
Finished Jul 17 05:42:26 PM PDT 24
Peak memory 507108 kb
Host smart-0ce75862-32a5-491d-ac59-8d5c9c4aa506
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559260763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3559260763
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2922170285
Short name T1179
Test name
Test status
Simulation time 3036862679 ps
CPU time 7.79 seconds
Started Jul 17 05:41:25 PM PDT 24
Finished Jul 17 05:41:34 PM PDT 24
Peak memory 218804 kb
Host smart-2159d1c7-471d-40a1-84ea-7dce97ee4804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922170285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2922170285
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.4167323014
Short name T916
Test name
Test status
Simulation time 392211710 ps
CPU time 5.54 seconds
Started Jul 17 05:41:24 PM PDT 24
Finished Jul 17 05:41:31 PM PDT 24
Peak memory 205636 kb
Host smart-c0146206-80b2-4836-a944-b8276733aa64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167323014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.4167323014
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2494989111
Short name T1487
Test name
Test status
Simulation time 30652202 ps
CPU time 0.7 seconds
Started Jul 17 05:41:52 PM PDT 24
Finished Jul 17 05:41:53 PM PDT 24
Peak memory 204788 kb
Host smart-7bbffd55-47fd-4240-a0c9-ff89fd6df722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494989111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2494989111
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1990294306
Short name T1478
Test name
Test status
Simulation time 144327108 ps
CPU time 1.86 seconds
Started Jul 17 05:41:36 PM PDT 24
Finished Jul 17 05:41:39 PM PDT 24
Peak memory 213768 kb
Host smart-94af88b1-8998-4a49-ac3c-19f572749abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990294306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1990294306
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2351460391
Short name T770
Test name
Test status
Simulation time 958939887 ps
CPU time 3.38 seconds
Started Jul 17 05:41:37 PM PDT 24
Finished Jul 17 05:41:41 PM PDT 24
Peak memory 216828 kb
Host smart-3b17cf38-388f-4b96-8ecb-3efed87ad3d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351460391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2351460391
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.634412510
Short name T1416
Test name
Test status
Simulation time 13887646857 ps
CPU time 62.87 seconds
Started Jul 17 05:43:59 PM PDT 24
Finished Jul 17 05:45:03 PM PDT 24
Peak memory 579748 kb
Host smart-d0d69549-c46d-476a-b0d1-25079816f2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634412510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.634412510
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2080511723
Short name T102
Test name
Test status
Simulation time 2321391369 ps
CPU time 168.41 seconds
Started Jul 17 05:46:42 PM PDT 24
Finished Jul 17 05:49:31 PM PDT 24
Peak memory 694520 kb
Host smart-4a4939b3-1815-41e8-b399-84aad70dd653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080511723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2080511723
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1304395435
Short name T1503
Test name
Test status
Simulation time 754954705 ps
CPU time 1.22 seconds
Started Jul 17 05:46:25 PM PDT 24
Finished Jul 17 05:46:27 PM PDT 24
Peak memory 205412 kb
Host smart-10b9646d-2f80-4400-8cf2-265060bfa621
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304395435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1304395435
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.24429147
Short name T423
Test name
Test status
Simulation time 1173335816 ps
CPU time 5.08 seconds
Started Jul 17 05:46:24 PM PDT 24
Finished Jul 17 05:46:30 PM PDT 24
Peak memory 243404 kb
Host smart-3fff9cf1-f30f-475c-8aa6-c8a3dcb1f441
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24429147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.24429147
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3118190078
Short name T114
Test name
Test status
Simulation time 29969134042 ps
CPU time 70.4 seconds
Started Jul 17 05:41:38 PM PDT 24
Finished Jul 17 05:42:49 PM PDT 24
Peak memory 952756 kb
Host smart-e9cece90-a320-4788-9b51-40afe37ddfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118190078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3118190078
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.3436857843
Short name T255
Test name
Test status
Simulation time 1213756837 ps
CPU time 3.93 seconds
Started Jul 17 05:41:51 PM PDT 24
Finished Jul 17 05:41:56 PM PDT 24
Peak memory 205524 kb
Host smart-d18dc0ec-cf08-4d30-9df3-01341e9ffee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436857843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3436857843
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.74054964
Short name T1274
Test name
Test status
Simulation time 94111150 ps
CPU time 0.66 seconds
Started Jul 17 05:41:36 PM PDT 24
Finished Jul 17 05:41:37 PM PDT 24
Peak memory 205176 kb
Host smart-5dcf6b22-17be-4cc3-aa00-d9ffb535b63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74054964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.74054964
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3260833889
Short name T8
Test name
Test status
Simulation time 7190649309 ps
CPU time 44.23 seconds
Started Jul 17 05:47:28 PM PDT 24
Finished Jul 17 05:48:14 PM PDT 24
Peak memory 606120 kb
Host smart-72808230-2be2-4745-9eb6-176fe93fc7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260833889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3260833889
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.767624362
Short name T605
Test name
Test status
Simulation time 349156649 ps
CPU time 1.76 seconds
Started Jul 17 05:41:39 PM PDT 24
Finished Jul 17 05:41:42 PM PDT 24
Peak memory 215704 kb
Host smart-1264143a-c320-4b6c-9457-a2bc77506044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767624362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.767624362
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2459114660
Short name T1168
Test name
Test status
Simulation time 4446636485 ps
CPU time 48.35 seconds
Started Jul 17 05:41:37 PM PDT 24
Finished Jul 17 05:42:26 PM PDT 24
Peak memory 299632 kb
Host smart-2ed9f9a4-c446-4b35-82c3-6f32377e0796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459114660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2459114660
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.210277089
Short name T686
Test name
Test status
Simulation time 4158760711 ps
CPU time 13.02 seconds
Started Jul 17 05:41:36 PM PDT 24
Finished Jul 17 05:41:50 PM PDT 24
Peak memory 221596 kb
Host smart-c2578d7b-30ac-460f-9344-38662f1e68d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210277089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.210277089
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.3393299885
Short name T976
Test name
Test status
Simulation time 5527723436 ps
CPU time 5 seconds
Started Jul 17 05:41:49 PM PDT 24
Finished Jul 17 05:41:55 PM PDT 24
Peak memory 218780 kb
Host smart-7d37ae0c-f462-43b6-85df-0b87aa2f8cde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393299885 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.3393299885
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2722456072
Short name T1623
Test name
Test status
Simulation time 271491348 ps
CPU time 0.82 seconds
Started Jul 17 05:41:39 PM PDT 24
Finished Jul 17 05:41:41 PM PDT 24
Peak memory 205448 kb
Host smart-96762086-f42e-43f2-9409-0b028d04cfcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722456072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2722456072
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.132849630
Short name T758
Test name
Test status
Simulation time 1831637136 ps
CPU time 1.18 seconds
Started Jul 17 05:41:51 PM PDT 24
Finished Jul 17 05:41:53 PM PDT 24
Peak memory 205456 kb
Host smart-0aff0a5a-cfad-42ed-9e9c-92ebfd52f2df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132849630 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.132849630
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.1076034796
Short name T311
Test name
Test status
Simulation time 754876781 ps
CPU time 1.72 seconds
Started Jul 17 05:41:51 PM PDT 24
Finished Jul 17 05:41:54 PM PDT 24
Peak memory 205448 kb
Host smart-5c615149-2518-44a0-b95d-32cfeff2b069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076034796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.1076034796
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.3951430101
Short name T1566
Test name
Test status
Simulation time 114402228 ps
CPU time 1.19 seconds
Started Jul 17 05:41:51 PM PDT 24
Finished Jul 17 05:41:53 PM PDT 24
Peak memory 205452 kb
Host smart-020dd1dd-6280-4b03-ae5d-7bddad9d97d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951430101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.3951430101
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1560051719
Short name T867
Test name
Test status
Simulation time 221588859 ps
CPU time 1.98 seconds
Started Jul 17 05:41:48 PM PDT 24
Finished Jul 17 05:41:51 PM PDT 24
Peak memory 213832 kb
Host smart-6a99e40e-27bd-44a6-b048-bcfb16a373a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560051719 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1560051719
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2699141482
Short name T1089
Test name
Test status
Simulation time 754892737 ps
CPU time 4.56 seconds
Started Jul 17 05:41:37 PM PDT 24
Finished Jul 17 05:41:42 PM PDT 24
Peak memory 213900 kb
Host smart-f96492a4-3daa-4f23-92b4-78a64caac8a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699141482 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2699141482
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2643783737
Short name T1519
Test name
Test status
Simulation time 22917806555 ps
CPU time 63.82 seconds
Started Jul 17 05:41:40 PM PDT 24
Finished Jul 17 05:42:44 PM PDT 24
Peak memory 1406340 kb
Host smart-1d275a0c-db79-4910-bb6a-f7b549c46d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643783737 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2643783737
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.420785619
Short name T1358
Test name
Test status
Simulation time 2455107471 ps
CPU time 3.1 seconds
Started Jul 17 05:46:52 PM PDT 24
Finished Jul 17 05:46:56 PM PDT 24
Peak memory 213848 kb
Host smart-3d9938f1-6ef9-4864-b110-f520eaf6fbb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420785619 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_nack_acqfull.420785619
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.985556599
Short name T1017
Test name
Test status
Simulation time 509912466 ps
CPU time 2.3 seconds
Started Jul 17 05:41:48 PM PDT 24
Finished Jul 17 05:41:51 PM PDT 24
Peak memory 205608 kb
Host smart-e5ac67ac-7625-4551-813e-629c16c23198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985556599 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.985556599
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.2956584702
Short name T1462
Test name
Test status
Simulation time 4310291750 ps
CPU time 7.45 seconds
Started Jul 17 05:41:50 PM PDT 24
Finished Jul 17 05:41:58 PM PDT 24
Peak memory 231508 kb
Host smart-6b26fb1b-d38f-4957-bc9e-77c8bca9b84f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956584702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.2956584702
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.637873484
Short name T468
Test name
Test status
Simulation time 2007171136 ps
CPU time 2.28 seconds
Started Jul 17 05:41:49 PM PDT 24
Finished Jul 17 05:41:52 PM PDT 24
Peak memory 205432 kb
Host smart-fbd6b069-b3c1-465e-9cf9-33e712fdee9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637873484 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_smbus_maxlen.637873484
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2010428342
Short name T834
Test name
Test status
Simulation time 2042681859 ps
CPU time 12.72 seconds
Started Jul 17 05:41:40 PM PDT 24
Finished Jul 17 05:41:53 PM PDT 24
Peak memory 217072 kb
Host smart-13c6f260-a731-4dc0-87b5-5e325001d42a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010428342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2010428342
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.3462127756
Short name T459
Test name
Test status
Simulation time 66136520149 ps
CPU time 224.06 seconds
Started Jul 17 05:46:24 PM PDT 24
Finished Jul 17 05:50:09 PM PDT 24
Peak memory 1296464 kb
Host smart-f0a9056e-91ef-47e8-83ae-1073fcac05ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462127756 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.3462127756
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.521877214
Short name T595
Test name
Test status
Simulation time 1603036046 ps
CPU time 31.03 seconds
Started Jul 17 05:47:43 PM PDT 24
Finished Jul 17 05:48:22 PM PDT 24
Peak memory 223712 kb
Host smart-34fe986b-6e4b-41f9-8ebe-dcf320b25462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521877214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.521877214
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.4264726327
Short name T973
Test name
Test status
Simulation time 6587739827 ps
CPU time 11.97 seconds
Started Jul 17 05:41:37 PM PDT 24
Finished Jul 17 05:41:50 PM PDT 24
Peak memory 205488 kb
Host smart-52cba658-46de-485a-b153-20aa07568108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264726327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.4264726327
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2203760313
Short name T798
Test name
Test status
Simulation time 3424875276 ps
CPU time 49.28 seconds
Started Jul 17 05:41:36 PM PDT 24
Finished Jul 17 05:42:26 PM PDT 24
Peak memory 754396 kb
Host smart-a7baeb7d-6f72-411a-8e5c-67f12c1716cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203760313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2203760313
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1900905161
Short name T1396
Test name
Test status
Simulation time 2137019220 ps
CPU time 6.27 seconds
Started Jul 17 05:41:38 PM PDT 24
Finished Jul 17 05:41:45 PM PDT 24
Peak memory 213852 kb
Host smart-14a9ea2d-9da6-400c-88da-2772b576829d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900905161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1900905161
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.3766707301
Short name T1431
Test name
Test status
Simulation time 159566154 ps
CPU time 3.25 seconds
Started Jul 17 05:41:50 PM PDT 24
Finished Jul 17 05:41:54 PM PDT 24
Peak memory 205648 kb
Host smart-4d6178f4-a555-40dd-8d67-57b9a8ed1224
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766707301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.3766707301
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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