Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	666645	1			T1	12		T2	57		T3	11
all_values[1]	666645	1			T1	12		T2	57		T3	11
all_values[2]	666645	1			T1	12		T2	57		T3	11
all_values[3]	666645	1			T1	12		T2	57		T3	11
all_values[4]	666645	1			T1	12		T2	57		T3	11
all_values[5]	666645	1			T1	12		T2	57		T3	11
all_values[6]	666645	1			T1	12		T2	57		T3	11
all_values[7]	666645	1			T1	12		T2	57		T3	11
all_values[8]	666645	1			T1	12		T2	57		T3	11
all_values[9]	666645	1			T1	12		T2	57		T3	11
all_values[10]	666645	1			T1	12		T2	57		T3	11
all_values[11]	666645	1			T1	12		T2	57		T3	11
all_values[12]	666645	1			T1	12		T2	57		T3	11
all_values[13]	666645	1			T1	12		T2	57		T3	11
all_values[14]	666645	1			T1	12		T2	57		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8210525

1

T1

162

T2

713

T3

165

auto[1]

1789150

1

T1

18

T2

142

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9187147

1

T1

180

T2

855

T3

165

auto[1]

812528

1

T27

61454

T18

10016

T14

140370

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	90917	1			T1	3		T2	2		T3	11
all_values[0]	auto[0]	auto[1]	5948	1			T27	667		T18	351		T14	468
all_values[0]	auto[1]	auto[0]	541151	1			T1	9		T2	55		T4	2
all_values[0]	auto[1]	auto[1]	28629	1			T27	3723		T18	318		T14	8891
all_values[1]	auto[0]	auto[0]	608806	1			T1	12		T2	57		T3	11
all_values[1]	auto[0]	auto[1]	57437	1			T27	4388		T18	663		T14	9352
all_values[1]	auto[1]	auto[0]	259	1			T27	1		T247	1		T248	7
all_values[1]	auto[1]	auto[1]	143	1			T27	2		T18	6		T14	5
all_values[2]	auto[0]	auto[0]	608881	1			T1	12		T2	57		T3	11
all_values[2]	auto[0]	auto[1]	57437	1			T27	4388		T18	665		T14	9350
all_values[2]	auto[1]	auto[0]	192	1			T107	1		T47	1		T48	1
all_values[2]	auto[1]	auto[1]	135	1			T27	2		T18	3		T14	9
all_values[3]	auto[0]	auto[0]	609904	1			T1	12		T2	57		T3	11
all_values[3]	auto[0]	auto[1]	56591	1			T27	4388		T18	660		T14	9352
all_values[3]	auto[1]	auto[1]	150	1			T27	1		T18	7		T14	4
all_values[4]	auto[0]	auto[0]	609023	1			T1	12		T2	56		T3	11
all_values[4]	auto[0]	auto[1]	57448	1			T27	4387		T18	663		T14	9353
all_values[4]	auto[1]	auto[0]	22	1			T2	1		T249	1		T243	1
all_values[4]	auto[1]	auto[1]	152	1			T27	1		T18	4		T14	6
all_values[5]	auto[0]	auto[0]	609060	1			T1	12		T2	57		T3	11
all_values[5]	auto[0]	auto[1]	57447	1			T27	4386		T18	666		T14	9353
all_values[5]	auto[1]	auto[1]	138	1			T27	2		T18	3		T14	6
all_values[6]	auto[0]	auto[0]	609054	1			T1	12		T2	57		T3	11
all_values[6]	auto[0]	auto[1]	57445	1			T27	4386		T18	664		T14	9355
all_values[6]	auto[1]	auto[1]	146	1			T27	4		T18	5		T14	1
all_values[7]	auto[0]	auto[0]	586502	1			T1	12		T2	29		T3	11
all_values[7]	auto[0]	auto[1]	56116	1			T27	4202		T18	507		T14	9275
all_values[7]	auto[1]	auto[0]	22534	1			T2	28		T27	243		T40	1
all_values[7]	auto[1]	auto[1]	1493	1			T27	187		T18	161		T14	84
all_values[8]	auto[0]	auto[0]	613447	1			T1	12		T2	57		T3	11
all_values[8]	auto[0]	auto[1]	53032	1			T18	661		T14	9350		T135	23002
all_values[8]	auto[1]	auto[1]	166	1			T18	8		T14	6		T135	3
all_values[9]	auto[0]	auto[0]	130172	1			T1	12		T2	54		T3	11
all_values[9]	auto[0]	auto[1]	7473	1			T27	441		T18	645		T14	505
all_values[9]	auto[1]	auto[0]	478880	1			T2	3		T6	4		T27	5498
all_values[9]	auto[1]	auto[1]	50120	1			T27	3949		T18	23		T14	8854
all_values[10]	auto[0]	auto[0]	609067	1			T1	12		T2	57		T3	11
all_values[10]	auto[0]	auto[1]	57418	1			T27	4388		T18	662		T14	9351
all_values[10]	auto[1]	auto[1]	160	1			T27	2		T18	5		T14	8
all_values[11]	auto[0]	auto[0]	2215	1			T1	3		T2	2		T3	11
all_values[11]	auto[0]	auto[1]	286	1			T27	12		T18	8		T14	18
all_values[11]	auto[1]	auto[0]	629868	1			T1	9		T2	55		T4	2
all_values[11]	auto[1]	auto[1]	34276	1			T27	4378		T18	653		T14	9339
all_values[12]	auto[0]	auto[0]	609014	1			T1	12		T2	57		T3	11
all_values[12]	auto[0]	auto[1]	57434	1			T27	4389		T18	662		T14	9354
all_values[12]	auto[1]	auto[0]	60	1			T47	1		T48	1		T49	1
all_values[12]	auto[1]	auto[1]	137	1			T27	1		T18	6		T14	4
all_values[13]	auto[0]	auto[0]	609061	1			T1	12		T2	57		T3	11
all_values[13]	auto[0]	auto[1]	57409	1			T27	4386		T18	666		T14	9352
all_values[13]	auto[1]	auto[1]	175	1			T27	4		T18	2		T14	6
all_values[14]	auto[0]	auto[0]	609058	1			T1	12		T2	57		T3	11
all_values[14]	auto[0]	auto[1]	57423	1			T27	4386		T18	665		T14	9355
all_values[14]	auto[1]	auto[1]	164	1			T27	4		T18	4		T14	4