Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	666645	1			T1	12		T2	57		T3	11
all_pins[1]	666645	1			T1	12		T2	57		T3	11
all_pins[2]	666645	1			T1	12		T2	57		T3	11
all_pins[3]	666645	1			T1	12		T2	57		T3	11
all_pins[4]	666645	1			T1	12		T2	57		T3	11
all_pins[5]	666645	1			T1	12		T2	57		T3	11
all_pins[6]	666645	1			T1	12		T2	57		T3	11
all_pins[7]	666645	1			T1	12		T2	57		T3	11
all_pins[8]	666645	1			T1	12		T2	57		T3	11
all_pins[9]	666645	1			T1	12		T2	57		T3	11
all_pins[10]	666645	1			T1	12		T2	57		T3	11
all_pins[11]	666645	1			T1	12		T2	57		T3	11
all_pins[12]	666645	1			T1	12		T2	57		T3	11
all_pins[13]	666645	1			T1	12		T2	57		T3	11
all_pins[14]	666645	1			T1	12		T2	57		T3	11

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8217191	1			T1	162		T2	851		T3	165
values[0x1]	1782484	1			T1	18		T2	4		T4	4
transitions[0x0=>0x1]	1781916	1			T1	18		T2	4		T4	4
transitions[0x1=>0x0]	1780597	1			T1	17		T2	4		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100463	1			T1	3		T2	57		T3	11
all_pins[0]	values[0x1]	566182	1			T1	9		T4	2		T5	2
all_pins[0]	transitions[0x0=>0x1]	565854	1			T1	9		T4	2		T5	2
all_pins[0]	transitions[0x1=>0x0]	44	1			T27	1		T18	1		T14	1
all_pins[1]	values[0x0]	666273	1			T1	12		T2	57		T3	11
all_pins[1]	values[0x1]	372	1			T27	2		T18	4		T14	2
all_pins[1]	transitions[0x0=>0x1]	363	1			T27	2		T18	4		T14	2
all_pins[1]	transitions[0x1=>0x0]	102	1			T27	1		T18	1		T107	1
all_pins[2]	values[0x0]	666534	1			T1	12		T2	57		T3	11
all_pins[2]	values[0x1]	111	1			T27	1		T18	1		T107	1
all_pins[2]	transitions[0x0=>0x1]	98	1			T27	1		T18	1		T107	1
all_pins[2]	transitions[0x1=>0x0]	52	1			T18	3		T14	1		T29	3
all_pins[3]	values[0x0]	666580	1			T1	12		T2	57		T3	11
all_pins[3]	values[0x1]	65	1			T18	3		T14	2		T29	4
all_pins[3]	transitions[0x0=>0x1]	56	1			T18	3		T14	1		T29	4
all_pins[3]	transitions[0x1=>0x0]	88	1			T2	1		T27	1		T18	4
all_pins[4]	values[0x0]	666548	1			T1	12		T2	56		T3	11
all_pins[4]	values[0x1]	97	1			T2	1		T27	1		T18	4
all_pins[4]	transitions[0x0=>0x1]	83	1			T2	1		T27	1		T18	3
all_pins[4]	transitions[0x1=>0x0]	52	1			T18	1		T14	2		T256	1
all_pins[5]	values[0x0]	666579	1			T1	12		T2	57		T3	11
all_pins[5]	values[0x1]	66	1			T18	2		T14	2		T256	1
all_pins[5]	transitions[0x0=>0x1]	57	1			T14	2		T256	1		T257	2
all_pins[5]	transitions[0x1=>0x0]	49	1			T27	1		T18	2		T14	1
all_pins[6]	values[0x0]	666587	1			T1	12		T2	57		T3	11
all_pins[6]	values[0x1]	58	1			T27	1		T18	4		T14	1
all_pins[6]	transitions[0x0=>0x1]	45	1			T27	1		T18	4		T29	1
all_pins[6]	transitions[0x1=>0x0]	26178	1			T27	523		T18	169		T40	1
all_pins[7]	values[0x0]	640454	1			T1	12		T2	57		T3	11
all_pins[7]	values[0x1]	26191	1			T27	523		T18	169		T40	1
all_pins[7]	transitions[0x0=>0x1]	26169	1			T27	523		T18	169		T40	1
all_pins[7]	transitions[0x1=>0x0]	60	1			T18	4		T135	2		T29	3
all_pins[8]	values[0x0]	666563	1			T1	12		T2	57		T3	11
all_pins[8]	values[0x1]	82	1			T18	4		T14	4		T135	3
all_pins[8]	transitions[0x0=>0x1]	66	1			T18	4		T14	3		T135	3
all_pins[8]	transitions[0x1=>0x0]	528918	1			T2	3		T6	4		T27	9444
all_pins[9]	values[0x0]	137711	1			T1	12		T2	54		T3	11
all_pins[9]	values[0x1]	528934	1			T2	3		T6	4		T27	9444
all_pins[9]	transitions[0x0=>0x1]	528915	1			T2	3		T6	4		T27	9444
all_pins[9]	transitions[0x1=>0x0]	65	1			T18	1		T14	3		T135	1
all_pins[10]	values[0x0]	666561	1			T1	12		T2	57		T3	11
all_pins[10]	values[0x1]	84	1			T18	1		T14	3		T135	1
all_pins[10]	transitions[0x0=>0x1]	63	1			T18	1		T14	3		T135	1
all_pins[10]	transitions[0x1=>0x0]	659919	1			T1	9		T4	2		T5	2
all_pins[11]	values[0x0]	6705	1			T1	3		T2	57		T3	11
all_pins[11]	values[0x1]	659940	1			T1	9		T4	2		T5	2
all_pins[11]	transitions[0x0=>0x1]	659911	1			T1	9		T4	2		T5	2
all_pins[11]	transitions[0x1=>0x0]	111	1			T27	1		T18	3		T47	1
all_pins[12]	values[0x0]	666505	1			T1	12		T2	57		T3	11
all_pins[12]	values[0x1]	140	1			T27	1		T18	5		T47	1
all_pins[12]	transitions[0x0=>0x1]	124	1			T27	1		T18	5		T47	1
all_pins[12]	transitions[0x1=>0x0]	65	1			T18	2		T14	2		T135	2
all_pins[13]	values[0x0]	666564	1			T1	12		T2	57		T3	11
all_pins[13]	values[0x1]	81	1			T18	2		T14	2		T135	2
all_pins[13]	transitions[0x0=>0x1]	57	1			T18	2		T14	2		T29	2
all_pins[13]	transitions[0x1=>0x0]	57	1			T27	1		T18	3		T14	3
all_pins[14]	values[0x0]	666564	1			T1	12		T2	57		T3	11
all_pins[14]	values[0x1]	81	1			T27	1		T18	3		T14	3
all_pins[14]	transitions[0x0=>0x1]	55	1			T27	1		T18	2		T14	2
all_pins[14]	transitions[0x1=>0x0]	564837	1			T1	8		T4	1		T5	1