Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	354	1			T27	4		T18	11		T14	14
all_values[1]	354	1			T27	4		T18	11		T14	14
all_values[2]	354	1			T27	4		T18	11		T14	14
all_values[3]	354	1			T27	4		T18	11		T14	14
all_values[4]	354	1			T27	4		T18	11		T14	14
all_values[5]	354	1			T27	4		T18	11		T14	14
all_values[6]	354	1			T27	4		T18	11		T14	14
all_values[7]	354	1			T27	4		T18	11		T14	14
all_values[8]	354	1			T27	4		T18	11		T14	14
all_values[9]	354	1			T27	4		T18	11		T14	14
all_values[10]	354	1			T27	4		T18	11		T14	14
all_values[11]	354	1			T27	4		T18	11		T14	14
all_values[12]	354	1			T27	4		T18	11		T14	14
all_values[13]	354	1			T27	4		T18	11		T14	14
all_values[14]	354	1			T27	4		T18	11		T14	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2939

1

T27

41

T18

87

T14

107

auto[1]

2371

1

T27

19

T18

78

T14

103

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

835

1

T27

10

T18

15

T14

15

auto[1]

4475

1

T27

50

T18

150

T14

195

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3113

1

T27

37

T18

100

T14

112

auto[1]

2197

1

T27

23

T18

65

T14

98

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	35	1			T135	3		T29	1		T258	1
all_values[0]	auto[0]	auto[0]	auto[1]	67	1			T27	2		T18	2		T14	3
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T135	1		T257	2		T259	3
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T27	1		T18	5		T14	3
all_values[0]	auto[1]	auto[0]	auto[1]	85	1			T27	1		T18	1		T14	5
all_values[0]	auto[1]	auto[1]	auto[1]	63	1			T18	3		T14	3		T29	2
all_values[1]	auto[0]	auto[0]	auto[0]	35	1			T20	1		T260	1		T261	3
all_values[1]	auto[0]	auto[0]	auto[1]	88	1			T18	5		T14	5		T29	5
all_values[1]	auto[0]	auto[1]	auto[0]	24	1			T14	2		T29	3		T257	2
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T27	2		T18	2		T14	2
all_values[1]	auto[1]	auto[0]	auto[1]	78	1			T27	1		T18	3		T14	3
all_values[1]	auto[1]	auto[1]	auto[1]	55	1			T27	1		T18	1		T14	2
all_values[2]	auto[0]	auto[0]	auto[0]	37	1			T258	1		T260	2		T261	2
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T27	1		T18	5		T14	3
all_values[2]	auto[0]	auto[1]	auto[0]	30	1			T18	1		T135	2		T29	2
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T27	1		T18	2		T14	2
all_values[2]	auto[1]	auto[0]	auto[1]	85	1			T27	2		T18	2		T14	4
all_values[2]	auto[1]	auto[1]	auto[1]	50	1			T18	1		T14	5		T135	1
all_values[3]	auto[0]	auto[0]	auto[0]	33	1			T27	1		T18	1		T14	1
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T18	2		T14	4		T135	1
all_values[3]	auto[0]	auto[1]	auto[0]	22	1			T18	1		T14	2		T20	3
all_values[3]	auto[0]	auto[1]	auto[1]	88	1			T27	2		T18	3		T14	2
all_values[3]	auto[1]	auto[0]	auto[1]	84	1			T27	1		T18	3		T14	3
all_values[3]	auto[1]	auto[1]	auto[1]	51	1			T18	1		T14	2		T135	2
all_values[4]	auto[0]	auto[0]	auto[0]	27	1			T27	1		T18	1		T256	1
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T18	4		T14	4		T135	1
all_values[4]	auto[0]	auto[1]	auto[0]	14	1			T27	1		T18	1		T259	1
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T27	1		T18	1		T14	4
all_values[4]	auto[1]	auto[0]	auto[1]	85	1			T18	2		T14	2		T29	3
all_values[4]	auto[1]	auto[1]	auto[1]	67	1			T27	1		T18	2		T14	4
all_values[5]	auto[0]	auto[0]	auto[0]	36	1			T27	1		T135	1		T29	2
all_values[5]	auto[0]	auto[0]	auto[1]	80	1			T27	1		T18	3		T14	2
all_values[5]	auto[0]	auto[1]	auto[0]	21	1			T27	1		T256	1		T259	1
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T18	1		T14	4		T257	2
all_values[5]	auto[1]	auto[0]	auto[1]	83	1			T27	1		T18	2		T14	5
all_values[5]	auto[1]	auto[1]	auto[1]	64	1			T18	5		T14	3		T29	2
all_values[6]	auto[0]	auto[0]	auto[0]	34	1			T259	1		T262	1		T260	1
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T27	3		T18	2		T14	4
all_values[6]	auto[0]	auto[1]	auto[0]	16	1			T14	3		T259	2		T263	1
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T18	4		T14	2		T29	2
all_values[6]	auto[1]	auto[0]	auto[1]	81	1			T27	1		T18	2		T14	2
all_values[6]	auto[1]	auto[1]	auto[1]	63	1			T18	3		T14	3		T135	1
all_values[7]	auto[0]	auto[0]	auto[0]	24	1			T27	1		T264	1		T262	2
all_values[7]	auto[0]	auto[0]	auto[1]	93	1			T27	2		T18	4		T14	2
all_values[7]	auto[0]	auto[1]	auto[0]	9	1			T18	1		T29	1		T20	1
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T18	2		T14	5		T135	1
all_values[7]	auto[1]	auto[0]	auto[1]	85	1			T27	1		T18	3		T14	3
all_values[7]	auto[1]	auto[1]	auto[1]	67	1			T18	1		T14	4		T135	2
all_values[8]	auto[0]	auto[0]	auto[0]	33	1			T27	2		T14	1		T256	1
all_values[8]	auto[0]	auto[0]	auto[1]	76	1			T18	4		T14	1		T29	4
all_values[8]	auto[0]	auto[1]	auto[0]	24	1			T27	2		T14	2		T259	1
all_values[8]	auto[0]	auto[1]	auto[1]	72	1			T18	1		T14	5		T135	1
all_values[8]	auto[1]	auto[0]	auto[1]	85	1			T18	3		T14	1		T135	2
all_values[8]	auto[1]	auto[1]	auto[1]	64	1			T18	3		T14	4		T135	1
all_values[9]	auto[0]	auto[0]	auto[0]	38	1			T256	1		T20	1		T258	1
all_values[9]	auto[0]	auto[0]	auto[1]	74	1			T27	2		T18	5		T14	4
all_values[9]	auto[0]	auto[1]	auto[0]	9	1			T18	1		T265	1		T266	1
all_values[9]	auto[0]	auto[1]	auto[1]	73	1			T18	2		T14	1		T29	4
all_values[9]	auto[1]	auto[0]	auto[1]	92	1			T27	2		T18	3		T14	5
all_values[9]	auto[1]	auto[1]	auto[1]	68	1			T14	4		T29	2		T257	3
all_values[10]	auto[0]	auto[0]	auto[0]	47	1			T18	1		T259	1		T264	1
all_values[10]	auto[0]	auto[0]	auto[1]	59	1			T27	2		T18	1		T14	3
all_values[10]	auto[0]	auto[1]	auto[0]	13	1			T18	1		T256	1		T259	1
all_values[10]	auto[0]	auto[1]	auto[1]	75	1			T18	3		T14	3		T135	1
all_values[10]	auto[1]	auto[0]	auto[1]	89	1			T27	2		T18	4		T14	4
all_values[10]	auto[1]	auto[1]	auto[1]	71	1			T18	1		T14	4		T135	1
all_values[11]	auto[0]	auto[0]	auto[0]	50	1			T18	3		T14	2		T135	3
all_values[11]	auto[0]	auto[0]	auto[1]	77	1			T27	1		T18	2		T14	4
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T18	1		T135	1		T256	4
all_values[11]	auto[0]	auto[1]	auto[1]	69	1			T27	1		T18	2		T14	2
all_values[11]	auto[1]	auto[0]	auto[1]	79	1			T27	1		T18	2		T14	6
all_values[11]	auto[1]	auto[1]	auto[1]	58	1			T27	1		T18	1		T29	3
all_values[12]	auto[0]	auto[0]	auto[0]	41	1			T14	1		T256	2		T264	1
all_values[12]	auto[0]	auto[0]	auto[1]	69	1			T18	3		T14	4		T135	1
all_values[12]	auto[0]	auto[1]	auto[0]	27	1			T18	1		T29	1		T257	1
all_values[12]	auto[0]	auto[1]	auto[1]	80	1			T27	3		T18	1		T14	5
all_values[12]	auto[1]	auto[0]	auto[1]	64	1			T27	1		T18	2		T14	3
all_values[12]	auto[1]	auto[1]	auto[1]	73	1			T18	4		T14	1		T29	3
all_values[13]	auto[0]	auto[0]	auto[0]	38	1			T29	4		T20	1		T264	1
all_values[13]	auto[0]	auto[0]	auto[1]	68	1			T27	1		T18	2		T14	4
all_values[13]	auto[0]	auto[1]	auto[0]	18	1			T18	1		T14	1		T135	1
all_values[13]	auto[0]	auto[1]	auto[1]	77	1			T18	5		T14	3		T135	1
all_values[13]	auto[1]	auto[0]	auto[1]	83	1			T27	3		T18	1		T14	2
all_values[13]	auto[1]	auto[1]	auto[1]	70	1			T18	2		T14	4		T135	2
all_values[14]	auto[0]	auto[0]	auto[0]	33	1			T29	1		T264	2		T258	1
all_values[14]	auto[0]	auto[0]	auto[1]	70	1			T27	1		T18	2		T14	3
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T264	1		T267	2		T268	1
all_values[14]	auto[0]	auto[1]	auto[1]	77	1			T18	5		T14	4		T135	2
all_values[14]	auto[1]	auto[0]	auto[1]	91	1			T27	2		T18	2		T14	4
all_values[14]	auto[1]	auto[1]	auto[1]	64	1			T27	1		T18	2		T14	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal