Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.27 97.21 89.76 97.22 72.02 94.26 98.44 90.00


Total test records in report: 1857
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T185 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4189982788 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:54 PM PDT 24 268361283 ps
T1774 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1871758502 Jul 18 05:12:23 PM PDT 24 Jul 18 05:12:26 PM PDT 24 34657898 ps
T1775 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2038581800 Jul 18 05:10:39 PM PDT 24 Jul 18 05:10:45 PM PDT 24 186529946 ps
T1776 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3970194859 Jul 18 05:11:19 PM PDT 24 Jul 18 05:11:22 PM PDT 24 155366640 ps
T1777 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.501188815 Jul 18 05:10:59 PM PDT 24 Jul 18 05:11:01 PM PDT 24 17202617 ps
T95 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1589909495 Jul 18 05:11:48 PM PDT 24 Jul 18 05:11:50 PM PDT 24 358237410 ps
T96 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1854304763 Jul 18 05:10:40 PM PDT 24 Jul 18 05:10:43 PM PDT 24 130969256 ps
T1778 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.148275109 Jul 18 05:10:38 PM PDT 24 Jul 18 05:10:42 PM PDT 24 84309660 ps
T1779 /workspace/coverage/cover_reg_top/1.i2c_intr_test.236202601 Jul 18 05:10:40 PM PDT 24 Jul 18 05:10:43 PM PDT 24 30634585 ps
T97 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3901163624 Jul 18 05:11:49 PM PDT 24 Jul 18 05:11:52 PM PDT 24 266351841 ps
T108 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2083958250 Jul 18 05:11:56 PM PDT 24 Jul 18 05:12:01 PM PDT 24 506625671 ps
T1780 /workspace/coverage/cover_reg_top/12.i2c_intr_test.408372096 Jul 18 05:11:51 PM PDT 24 Jul 18 05:11:55 PM PDT 24 19219877 ps
T266 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1870368662 Jul 18 05:12:24 PM PDT 24 Jul 18 05:12:27 PM PDT 24 18290415 ps
T187 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2219002919 Jul 18 05:11:01 PM PDT 24 Jul 18 05:11:04 PM PDT 24 485231561 ps
T1781 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3935819072 Jul 18 05:11:56 PM PDT 24 Jul 18 05:12:00 PM PDT 24 46213338 ps
T1782 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3421074200 Jul 18 05:11:53 PM PDT 24 Jul 18 05:11:58 PM PDT 24 18602193 ps
T1783 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2022398201 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:53 PM PDT 24 114158174 ps
T1784 /workspace/coverage/cover_reg_top/28.i2c_intr_test.416936008 Jul 18 05:12:26 PM PDT 24 Jul 18 05:12:28 PM PDT 24 15211591 ps
T1785 /workspace/coverage/cover_reg_top/9.i2c_intr_test.736679095 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:53 PM PDT 24 30265055 ps
T186 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3927590751 Jul 18 05:12:29 PM PDT 24 Jul 18 05:12:32 PM PDT 24 86520435 ps
T201 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2336201995 Jul 18 05:11:53 PM PDT 24 Jul 18 05:11:59 PM PDT 24 247539953 ps
T1786 /workspace/coverage/cover_reg_top/24.i2c_intr_test.721692085 Jul 18 05:12:24 PM PDT 24 Jul 18 05:12:27 PM PDT 24 26046785 ps
T188 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3937566083 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:54 PM PDT 24 175478674 ps
T1787 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2123774952 Jul 18 05:11:53 PM PDT 24 Jul 18 05:11:59 PM PDT 24 39325603 ps
T1788 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2955391483 Jul 18 05:11:51 PM PDT 24 Jul 18 05:11:54 PM PDT 24 67455354 ps
T1789 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3095712168 Jul 18 05:12:30 PM PDT 24 Jul 18 05:12:31 PM PDT 24 32230000 ps
T1790 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1817506046 Jul 18 05:12:28 PM PDT 24 Jul 18 05:12:29 PM PDT 24 46433705 ps
T1791 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.389786255 Jul 18 05:10:59 PM PDT 24 Jul 18 05:11:01 PM PDT 24 48586595 ps
T1792 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2447802883 Jul 18 05:11:20 PM PDT 24 Jul 18 05:11:22 PM PDT 24 55501803 ps
T1793 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2673427588 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:57 PM PDT 24 189963578 ps
T1794 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1395564046 Jul 18 05:10:59 PM PDT 24 Jul 18 05:11:02 PM PDT 24 293438805 ps
T1795 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3058115862 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:56 PM PDT 24 18156249 ps
T202 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3253833029 Jul 18 05:11:00 PM PDT 24 Jul 18 05:11:02 PM PDT 24 71906512 ps
T1796 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2216303413 Jul 18 05:12:36 PM PDT 24 Jul 18 05:12:38 PM PDT 24 29682534 ps
T1797 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3278994016 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:57 PM PDT 24 71195609 ps
T1798 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3734616861 Jul 18 05:12:22 PM PDT 24 Jul 18 05:12:25 PM PDT 24 33436231 ps
T1799 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2777779860 Jul 18 05:12:22 PM PDT 24 Jul 18 05:12:25 PM PDT 24 58803852 ps
T1800 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2966187605 Jul 18 05:11:16 PM PDT 24 Jul 18 05:11:20 PM PDT 24 216699749 ps
T1801 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3268767725 Jul 18 05:11:18 PM PDT 24 Jul 18 05:11:22 PM PDT 24 328315488 ps
T1802 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2184661409 Jul 18 05:10:58 PM PDT 24 Jul 18 05:11:00 PM PDT 24 74033071 ps
T1803 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3352518686 Jul 18 05:12:22 PM PDT 24 Jul 18 05:12:25 PM PDT 24 38035738 ps
T1804 /workspace/coverage/cover_reg_top/7.i2c_intr_test.3698529654 Jul 18 05:11:16 PM PDT 24 Jul 18 05:11:18 PM PDT 24 198389928 ps
T1805 /workspace/coverage/cover_reg_top/38.i2c_intr_test.4264060889 Jul 18 05:12:24 PM PDT 24 Jul 18 05:12:26 PM PDT 24 39592565 ps
T183 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.962281376 Jul 18 05:11:17 PM PDT 24 Jul 18 05:11:21 PM PDT 24 103632011 ps
T1806 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2193985448 Jul 18 05:11:54 PM PDT 24 Jul 18 05:11:59 PM PDT 24 55881862 ps
T1807 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2897116082 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:57 PM PDT 24 17755218 ps
T203 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2593525041 Jul 18 05:10:38 PM PDT 24 Jul 18 05:10:41 PM PDT 24 23227897 ps
T204 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2161522991 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:54 PM PDT 24 20786107 ps
T250 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1879797814 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:57 PM PDT 24 300725816 ps
T1808 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3499642907 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:57 PM PDT 24 183480797 ps
T184 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.644553836 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:54 PM PDT 24 81867166 ps
T205 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3640444094 Jul 18 05:10:39 PM PDT 24 Jul 18 05:10:43 PM PDT 24 27748005 ps
T1809 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.977708532 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:53 PM PDT 24 29583353 ps
T1810 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1168381803 Jul 18 05:12:44 PM PDT 24 Jul 18 05:12:46 PM PDT 24 15949785 ps
T1811 /workspace/coverage/cover_reg_top/19.i2c_intr_test.182517866 Jul 18 05:13:05 PM PDT 24 Jul 18 05:13:08 PM PDT 24 28033522 ps
T1812 /workspace/coverage/cover_reg_top/42.i2c_intr_test.232415809 Jul 18 05:12:47 PM PDT 24 Jul 18 05:12:51 PM PDT 24 49085454 ps
T206 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2264573688 Jul 18 05:11:02 PM PDT 24 Jul 18 05:11:04 PM PDT 24 73108069 ps
T1813 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1483426773 Jul 18 05:10:38 PM PDT 24 Jul 18 05:10:43 PM PDT 24 194294732 ps
T1814 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3166233523 Jul 18 05:12:24 PM PDT 24 Jul 18 05:12:28 PM PDT 24 331780568 ps
T1815 /workspace/coverage/cover_reg_top/43.i2c_intr_test.3819370468 Jul 18 05:12:46 PM PDT 24 Jul 18 05:12:50 PM PDT 24 14616284 ps
T1816 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.882302988 Jul 18 05:11:48 PM PDT 24 Jul 18 05:11:51 PM PDT 24 133064991 ps
T1817 /workspace/coverage/cover_reg_top/6.i2c_intr_test.3561158689 Jul 18 05:11:18 PM PDT 24 Jul 18 05:11:21 PM PDT 24 25872842 ps
T136 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3532505952 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:58 PM PDT 24 89229267 ps
T1818 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1557424738 Jul 18 05:11:51 PM PDT 24 Jul 18 05:11:57 PM PDT 24 659313212 ps
T1819 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2489236501 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:58 PM PDT 24 205994325 ps
T1820 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3884222740 Jul 18 05:12:29 PM PDT 24 Jul 18 05:12:30 PM PDT 24 56713762 ps
T1821 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.808233700 Jul 18 05:11:17 PM PDT 24 Jul 18 05:11:21 PM PDT 24 133562025 ps
T1822 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1376892867 Jul 18 05:11:49 PM PDT 24 Jul 18 05:11:50 PM PDT 24 102617824 ps
T1823 /workspace/coverage/cover_reg_top/21.i2c_intr_test.3025656261 Jul 18 05:12:23 PM PDT 24 Jul 18 05:12:25 PM PDT 24 121542411 ps
T1824 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3943983736 Jul 18 05:11:01 PM PDT 24 Jul 18 05:11:03 PM PDT 24 30988339 ps
T1825 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2748410200 Jul 18 05:12:22 PM PDT 24 Jul 18 05:12:25 PM PDT 24 42519260 ps
T1826 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1972106954 Jul 18 05:11:19 PM PDT 24 Jul 18 05:11:24 PM PDT 24 165480507 ps
T1827 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1875156995 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:54 PM PDT 24 34517022 ps
T1828 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2876273134 Jul 18 05:11:19 PM PDT 24 Jul 18 05:11:22 PM PDT 24 53413948 ps
T1829 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2091495144 Jul 18 05:11:56 PM PDT 24 Jul 18 05:12:00 PM PDT 24 103226228 ps
T137 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.689439326 Jul 18 05:11:53 PM PDT 24 Jul 18 05:11:59 PM PDT 24 184038368 ps
T1830 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2869103403 Jul 18 05:11:53 PM PDT 24 Jul 18 05:12:00 PM PDT 24 114389930 ps
T1831 /workspace/coverage/cover_reg_top/45.i2c_intr_test.1856250779 Jul 18 05:12:46 PM PDT 24 Jul 18 05:12:50 PM PDT 24 18286138 ps
T207 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1459707660 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:54 PM PDT 24 19493243 ps
T1832 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1495785507 Jul 18 05:10:39 PM PDT 24 Jul 18 05:10:43 PM PDT 24 24724826 ps
T1833 /workspace/coverage/cover_reg_top/0.i2c_intr_test.455160744 Jul 18 05:10:38 PM PDT 24 Jul 18 05:10:40 PM PDT 24 65398145 ps
T1834 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.55267732 Jul 18 05:11:50 PM PDT 24 Jul 18 05:11:54 PM PDT 24 25477007 ps
T1835 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3767667520 Jul 18 05:10:59 PM PDT 24 Jul 18 05:11:03 PM PDT 24 1052954105 ps
T1836 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2584844789 Jul 18 05:11:25 PM PDT 24 Jul 18 05:11:27 PM PDT 24 29260079 ps
T1837 /workspace/coverage/cover_reg_top/27.i2c_intr_test.702367246 Jul 18 05:12:28 PM PDT 24 Jul 18 05:12:30 PM PDT 24 15121625 ps
T189 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3795611315 Jul 18 05:11:17 PM PDT 24 Jul 18 05:11:22 PM PDT 24 90011597 ps
T1838 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2889916491 Jul 18 05:11:00 PM PDT 24 Jul 18 05:11:05 PM PDT 24 278622241 ps
T1839 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4085584350 Jul 18 05:11:51 PM PDT 24 Jul 18 05:11:56 PM PDT 24 68997709 ps
T1840 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1671991171 Jul 18 05:12:49 PM PDT 24 Jul 18 05:12:54 PM PDT 24 19521917 ps
T1841 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.240211537 Jul 18 05:11:52 PM PDT 24 Jul 18 05:11:58 PM PDT 24 82208479 ps
T1842 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.832518925 Jul 18 05:11:18 PM PDT 24 Jul 18 05:11:21 PM PDT 24 91605861 ps
T1843 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.284984175 Jul 18 05:11:19 PM PDT 24 Jul 18 05:11:22 PM PDT 24 43107115 ps
T1844 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.313778867 Jul 18 05:11:16 PM PDT 24 Jul 18 05:11:18 PM PDT 24 269878536 ps
T1845 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1969988651 Jul 18 05:10:58 PM PDT 24 Jul 18 05:11:00 PM PDT 24 20662123 ps
T1846 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2818294390 Jul 18 05:11:54 PM PDT 24 Jul 18 05:11:59 PM PDT 24 18074719 ps
T190 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.567528229 Jul 18 05:11:53 PM PDT 24 Jul 18 05:11:59 PM PDT 24 97415100 ps
T1847 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2202210770 Jul 18 05:10:39 PM PDT 24 Jul 18 05:10:43 PM PDT 24 58916502 ps
T1848 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2661557507 Jul 18 05:10:38 PM PDT 24 Jul 18 05:10:43 PM PDT 24 272562330 ps
T1849 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2010739989 Jul 18 05:11:17 PM PDT 24 Jul 18 05:11:19 PM PDT 24 439841939 ps
T1850 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2419628272 Jul 18 05:11:18 PM PDT 24 Jul 18 05:11:21 PM PDT 24 110874598 ps
T1851 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1355314108 Jul 18 05:11:51 PM PDT 24 Jul 18 05:11:56 PM PDT 24 246747163 ps
T1852 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1331281998 Jul 18 05:11:17 PM PDT 24 Jul 18 05:11:19 PM PDT 24 47724802 ps
T1853 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3585929510 Jul 18 05:12:46 PM PDT 24 Jul 18 05:12:50 PM PDT 24 17492730 ps
T1854 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1646567531 Jul 18 05:11:54 PM PDT 24 Jul 18 05:11:59 PM PDT 24 64334662 ps
T1855 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2945846588 Jul 18 05:11:17 PM PDT 24 Jul 18 05:11:20 PM PDT 24 32040534 ps
T1856 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1936670000 Jul 18 05:11:01 PM PDT 24 Jul 18 05:11:04 PM PDT 24 143014232 ps
T1857 /workspace/coverage/cover_reg_top/11.i2c_intr_test.208622468 Jul 18 05:11:48 PM PDT 24 Jul 18 05:11:50 PM PDT 24 18005482 ps

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2124886530
Short name T10
Test name
Test status
Simulation time 3767036294 ps
CPU time 4.53 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:29 PM PDT 24
Peak memory 213908 kb
Host smart-34441cdb-c926-4919-b8da-643103e04411
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124886530 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2124886530
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2333041979
Short name T18
Test name
Test status
Simulation time 11967447455 ps
CPU time 612.96 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:39:33 PM PDT 24
Peak memory 1958052 kb
Host smart-f4895ba3-ea81-48ac-9048-344fc4d53986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333041979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2333041979
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1735700670
Short name T44
Test name
Test status
Simulation time 12354110081 ps
CPU time 9.83 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:19 PM PDT 24
Peak memory 214256 kb
Host smart-d6dbf396-34d3-4be2-9af6-4345c9e27d2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735700670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1735700670
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1468696748
Short name T88
Test name
Test status
Simulation time 507507035 ps
CPU time 2.31 seconds
Started Jul 18 05:10:59 PM PDT 24
Finished Jul 18 05:11:03 PM PDT 24
Peak memory 204564 kb
Host smart-8baa4a50-a872-4c2e-b5cf-041f1dc55d33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468696748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1468696748
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.146777164
Short name T47
Test name
Test status
Simulation time 1428293154 ps
CPU time 2.52 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:28:05 PM PDT 24
Peak memory 205660 kb
Host smart-a657a313-f272-4b4d-90bd-088c9e7e34b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146777164 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.146777164
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3562185298
Short name T3
Test name
Test status
Simulation time 921457946 ps
CPU time 3.8 seconds
Started Jul 18 05:30:54 PM PDT 24
Finished Jul 18 05:31:01 PM PDT 24
Peak memory 223732 kb
Host smart-7979f9cb-7dac-46d7-8c7a-4bef987004d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562185298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3562185298
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_override.4232341933
Short name T386
Test name
Test status
Simulation time 15665251 ps
CPU time 0.71 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 205200 kb
Host smart-1c9e7448-94b0-4446-aaee-176f1ffadcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232341933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.4232341933
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.134756078
Short name T52
Test name
Test status
Simulation time 51143059605 ps
CPU time 101.75 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:32:29 PM PDT 24
Peak memory 459116 kb
Host smart-6a760b8d-1d79-4d17-910a-7311c9e9badd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134756078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.i2c_target_stress_all.134756078
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.1309327480
Short name T234
Test name
Test status
Simulation time 300504141 ps
CPU time 12.72 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:28:41 PM PDT 24
Peak memory 205432 kb
Host smart-4855ae8d-3551-422a-9e94-fb6285b563cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309327480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1309327480
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_target_nack_txstretch.2430617819
Short name T43
Test name
Test status
Simulation time 183431992 ps
CPU time 1.41 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:29:16 PM PDT 24
Peak memory 222580 kb
Host smart-58505380-cd09-4126-baae-86dbec3afcd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430617819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_nack_txstretch.2430617819
Directory /workspace/25.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.3878787850
Short name T170
Test name
Test status
Simulation time 83356225 ps
CPU time 1.04 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 224044 kb
Host smart-70a1f804-717e-4c94-b549-97c1f2cfba97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878787850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3878787850
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.4224096001
Short name T27
Test name
Test status
Simulation time 53176431747 ps
CPU time 370.41 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:38:05 PM PDT 24
Peak memory 1345196 kb
Host smart-94b52740-e99b-447e-9237-2bd5f8a11751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224096001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.4224096001
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3906119265
Short name T177
Test name
Test status
Simulation time 419985982 ps
CPU time 2.46 seconds
Started Jul 18 05:11:21 PM PDT 24
Finished Jul 18 05:11:25 PM PDT 24
Peak memory 204668 kb
Host smart-6aa26aab-7ba5-4e63-9a24-4bbf0915829d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906119265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3906119265
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.360273749
Short name T34
Test name
Test status
Simulation time 297602171 ps
CPU time 1.19 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 205396 kb
Host smart-6f47b0a8-d6b1-4236-ac4b-07b04d7999ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360273749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.360273749
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1423889394
Short name T197
Test name
Test status
Simulation time 32571033 ps
CPU time 0.76 seconds
Started Jul 18 05:12:32 PM PDT 24
Finished Jul 18 05:12:34 PM PDT 24
Peak memory 204412 kb
Host smart-49ed940d-fcc6-48f6-a6d7-5647963d1324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423889394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1423889394
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3048254174
Short name T30
Test name
Test status
Simulation time 428136617 ps
CPU time 2.64 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:28:01 PM PDT 24
Peak memory 216948 kb
Host smart-aed9904a-2f99-4435-8060-623b4ea14010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048254174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3048254174
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.4181760747
Short name T390
Test name
Test status
Simulation time 517254856 ps
CPU time 2.96 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:30 PM PDT 24
Peak memory 213784 kb
Host smart-f28c91c7-5c22-4239-a853-21360834f8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181760747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.4181760747
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.3213358841
Short name T60
Test name
Test status
Simulation time 1334433387 ps
CPU time 2.52 seconds
Started Jul 18 05:28:21 PM PDT 24
Finished Jul 18 05:28:25 PM PDT 24
Peak memory 213768 kb
Host smart-6d05106e-6b5a-4c49-a26a-7a79960bdfe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213358841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.3213358841
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.4127565620
Short name T258
Test name
Test status
Simulation time 15898892 ps
CPU time 0.72 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204352 kb
Host smart-73c549d9-0f20-440b-90a3-733579f1bd72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127565620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.4127565620
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.55829273
Short name T217
Test name
Test status
Simulation time 555289245 ps
CPU time 7.02 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 205524 kb
Host smart-e3d61e97-da53-4174-901c-21472e316e91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55829273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.55829273
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_alert_test.4203226492
Short name T334
Test name
Test status
Simulation time 33399166 ps
CPU time 0.62 seconds
Started Jul 18 05:26:19 PM PDT 24
Finished Jul 18 05:26:21 PM PDT 24
Peak memory 204784 kb
Host smart-7cc3739c-d33a-4b14-8330-893e59f2e5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203226492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.4203226492
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_override.103892201
Short name T114
Test name
Test status
Simulation time 47437770 ps
CPU time 0.69 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:29:15 PM PDT 24
Peak memory 205256 kb
Host smart-0de182fe-a1e0-49cc-8f0d-b647203908f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103892201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.103892201
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.829561733
Short name T261
Test name
Test status
Simulation time 32911208 ps
CPU time 0.69 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:12:53 PM PDT 24
Peak memory 204404 kb
Host smart-7853b3d0-8df5-42d3-8f75-ac4a263f4f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829561733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.829561733
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2295134972
Short name T237
Test name
Test status
Simulation time 1430171059 ps
CPU time 8.9 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:28 PM PDT 24
Peak memory 205536 kb
Host smart-2393d754-47a5-4d2d-b1d3-1a1da489e0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295134972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2295134972
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1660768569
Short name T227
Test name
Test status
Simulation time 163348069 ps
CPU time 1.2 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:26:44 PM PDT 24
Peak memory 205272 kb
Host smart-f6b06a67-90b2-4dd0-9179-2b2eb89322b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660768569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1660768569
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2915062753
Short name T72
Test name
Test status
Simulation time 3528602110 ps
CPU time 20.79 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:28:12 PM PDT 24
Peak memory 213860 kb
Host smart-ff204042-b4d8-4c98-a2ea-55312e1787a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915062753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2915062753
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2131248570
Short name T634
Test name
Test status
Simulation time 1148421669 ps
CPU time 4.18 seconds
Started Jul 18 05:30:26 PM PDT 24
Finished Jul 18 05:30:34 PM PDT 24
Peak memory 213744 kb
Host smart-c07de877-513c-457b-9d1d-98d01f2fa2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131248570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2131248570
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3927590751
Short name T186
Test name
Test status
Simulation time 86520435 ps
CPU time 2.16 seconds
Started Jul 18 05:12:29 PM PDT 24
Finished Jul 18 05:12:32 PM PDT 24
Peak memory 204552 kb
Host smart-3c13af76-78d8-493b-9ed9-d98a14aceb36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927590751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3927590751
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.440379065
Short name T242
Test name
Test status
Simulation time 46551424 ps
CPU time 1.48 seconds
Started Jul 18 05:30:47 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 213664 kb
Host smart-4c08bee5-fca1-46de-be75-f26feae7bf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440379065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.440379065
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.3480059194
Short name T802
Test name
Test status
Simulation time 39452256209 ps
CPU time 191.63 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:29:50 PM PDT 24
Peak memory 1247020 kb
Host smart-1891fd4e-ede0-47a5-9f07-55d3a30cfc33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480059194 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.3480059194
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.63410868
Short name T135
Test name
Test status
Simulation time 57027063284 ps
CPU time 1449.15 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:56:28 PM PDT 24
Peak memory 1751336 kb
Host smart-bfdef9b1-29bd-4b3c-8deb-cb3bf9651748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63410868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.63410868
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2795261406
Short name T71
Test name
Test status
Simulation time 282136614 ps
CPU time 1.93 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:29:55 PM PDT 24
Peak memory 208532 kb
Host smart-61244f8a-0537-4533-90ad-2422ccaf9382
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795261406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2795261406
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.3229227440
Short name T1386
Test name
Test status
Simulation time 32622785625 ps
CPU time 1066.7 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 5691080 kb
Host smart-a8b7af53-f289-4c17-9fd9-b5389e4fc602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229227440 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.3229227440
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3788119656
Short name T1669
Test name
Test status
Simulation time 562883043 ps
CPU time 8.72 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:51 PM PDT 24
Peak memory 205532 kb
Host smart-5d6bf87c-5de4-4b08-89c1-90373c5ce298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788119656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3788119656
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.3234870019
Short name T216
Test name
Test status
Simulation time 113672297 ps
CPU time 0.87 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:11 PM PDT 24
Peak memory 205448 kb
Host smart-a84b7d69-8da5-4d7c-9c19-0207af8c9b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234870019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.3234870019
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3532505952
Short name T136
Test name
Test status
Simulation time 89229267 ps
CPU time 2.17 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:58 PM PDT 24
Peak memory 204580 kb
Host smart-5a854994-b1db-498a-a422-58be9efb0c45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532505952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3532505952
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.343314971
Short name T46
Test name
Test status
Simulation time 2100192893 ps
CPU time 11.3 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:16 PM PDT 24
Peak memory 214140 kb
Host smart-98001f73-b402-45a7-967e-46020071391d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343314971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.343314971
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1246217090
Short name T37
Test name
Test status
Simulation time 11865875829 ps
CPU time 461.01 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:38:07 PM PDT 24
Peak memory 205532 kb
Host smart-bdd6d279-b082-401a-8a00-47afcaff35e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246217090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1246217090
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1646567531
Short name T1854
Test name
Test status
Simulation time 64334662 ps
CPU time 0.66 seconds
Started Jul 18 05:11:54 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204400 kb
Host smart-4d5e7255-7a88-4e9c-9227-b93e24fb3b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646567531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1646567531
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.512073319
Short name T274
Test name
Test status
Simulation time 234183121 ps
CPU time 3.25 seconds
Started Jul 18 05:26:15 PM PDT 24
Finished Jul 18 05:26:20 PM PDT 24
Peak memory 205596 kb
Host smart-18d2baf2-4aee-4bac-9725-e811250de92e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512073319 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.512073319
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3798223647
Short name T244
Test name
Test status
Simulation time 4158670735 ps
CPU time 43.18 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:29:09 PM PDT 24
Peak memory 213884 kb
Host smart-433810e3-d07e-4303-90a4-c59f835ad694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798223647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3798223647
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2719072352
Short name T750
Test name
Test status
Simulation time 1103210701 ps
CPU time 5.94 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 213628 kb
Host smart-cf889746-e3a6-4870-b3b9-6e5f8ea03487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719072352 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2719072352
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.567528229
Short name T190
Test name
Test status
Simulation time 97415100 ps
CPU time 2.13 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204480 kb
Host smart-afe4fcb5-bc2d-4c5f-921d-ef68a3085448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567528229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.567528229
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.618422928
Short name T641
Test name
Test status
Simulation time 12840129976 ps
CPU time 82.49 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:27:31 PM PDT 24
Peak memory 438052 kb
Host smart-bdd2ef9f-dc95-4e36-9ed3-f8d1b7f1b231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618422928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.618422928
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.295494768
Short name T180
Test name
Test status
Simulation time 200663153 ps
CPU time 2.36 seconds
Started Jul 18 05:10:37 PM PDT 24
Finished Jul 18 05:10:40 PM PDT 24
Peak memory 204652 kb
Host smart-fda4d6e3-3c1f-4d66-8f68-5321d0387c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295494768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.295494768
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.781151607
Short name T590
Test name
Test status
Simulation time 292197164 ps
CPU time 2.24 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:27:35 PM PDT 24
Peak memory 213848 kb
Host smart-f62cd7f2-2e44-4aec-9c2c-2ee140201ccf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781151607 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.781151607
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2909921011
Short name T12
Test name
Test status
Simulation time 113336497 ps
CPU time 3.82 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:27:49 PM PDT 24
Peak memory 213740 kb
Host smart-f9bc206c-b4f2-48af-847a-238d774b7eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909921011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2909921011
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.2886524045
Short name T1
Test name
Test status
Simulation time 551559771 ps
CPU time 1.62 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:26 PM PDT 24
Peak memory 205456 kb
Host smart-187f986a-62b1-4cb3-947c-a3d5b1686fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886524045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2886524045
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.4036325164
Short name T20
Test name
Test status
Simulation time 56819681458 ps
CPU time 584.93 seconds
Started Jul 18 05:28:45 PM PDT 24
Finished Jul 18 05:38:32 PM PDT 24
Peak memory 1372544 kb
Host smart-c649cf2e-e535-4fcb-af03-12b90e00db2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036325164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.4036325164
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.148275109
Short name T1778
Test name
Test status
Simulation time 84309660 ps
CPU time 1.22 seconds
Started Jul 18 05:10:38 PM PDT 24
Finished Jul 18 05:10:42 PM PDT 24
Peak memory 204748 kb
Host smart-ddfb3bd9-73ff-4cc3-95cb-abe4dab38df1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148275109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.148275109
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2038581800
Short name T1775
Test name
Test status
Simulation time 186529946 ps
CPU time 2.8 seconds
Started Jul 18 05:10:39 PM PDT 24
Finished Jul 18 05:10:45 PM PDT 24
Peak memory 204552 kb
Host smart-61b8e30d-f748-4b63-b24a-8f4abfce587f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038581800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2038581800
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2593525041
Short name T203
Test name
Test status
Simulation time 23227897 ps
CPU time 0.71 seconds
Started Jul 18 05:10:38 PM PDT 24
Finished Jul 18 05:10:41 PM PDT 24
Peak memory 204440 kb
Host smart-06a0cff3-2bcd-42a8-903b-16fb37a81c21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593525041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2593525041
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1495785507
Short name T1832
Test name
Test status
Simulation time 24724826 ps
CPU time 0.95 seconds
Started Jul 18 05:10:39 PM PDT 24
Finished Jul 18 05:10:43 PM PDT 24
Peak memory 204456 kb
Host smart-a2d92ca4-a355-4379-a93a-e4e8badd809b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495785507 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1495785507
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2202210770
Short name T1847
Test name
Test status
Simulation time 58916502 ps
CPU time 0.76 seconds
Started Jul 18 05:10:39 PM PDT 24
Finished Jul 18 05:10:43 PM PDT 24
Peak memory 204464 kb
Host smart-5c87c3de-1be3-42d4-8e6d-15c48d85d70d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202210770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2202210770
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.455160744
Short name T1833
Test name
Test status
Simulation time 65398145 ps
CPU time 0.71 seconds
Started Jul 18 05:10:38 PM PDT 24
Finished Jul 18 05:10:40 PM PDT 24
Peak memory 204408 kb
Host smart-d6999a8a-286d-476c-a511-477feb9be929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455160744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.455160744
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1854304763
Short name T96
Test name
Test status
Simulation time 130969256 ps
CPU time 0.89 seconds
Started Jul 18 05:10:40 PM PDT 24
Finished Jul 18 05:10:43 PM PDT 24
Peak memory 204416 kb
Host smart-6664cdf1-cec3-4a7b-8d46-2ccc0724b97a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854304763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1854304763
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1483426773
Short name T1813
Test name
Test status
Simulation time 194294732 ps
CPU time 2.27 seconds
Started Jul 18 05:10:38 PM PDT 24
Finished Jul 18 05:10:43 PM PDT 24
Peak memory 204660 kb
Host smart-1b98c99d-0bf5-4f13-8fda-f77cc61a80fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483426773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1483426773
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3934163266
Short name T175
Test name
Test status
Simulation time 588171976 ps
CPU time 1.33 seconds
Started Jul 18 05:10:36 PM PDT 24
Finished Jul 18 05:10:39 PM PDT 24
Peak memory 204600 kb
Host smart-ad6dec6e-4fa4-442b-b515-c8a8f4badda2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934163266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3934163266
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4151864207
Short name T195
Test name
Test status
Simulation time 531016271 ps
CPU time 1.79 seconds
Started Jul 18 05:10:58 PM PDT 24
Finished Jul 18 05:11:01 PM PDT 24
Peak memory 204532 kb
Host smart-cb47c8ac-0c55-4990-b83d-55a352f8d4a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151864207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.4151864207
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3767667520
Short name T1835
Test name
Test status
Simulation time 1052954105 ps
CPU time 2.98 seconds
Started Jul 18 05:10:59 PM PDT 24
Finished Jul 18 05:11:03 PM PDT 24
Peak memory 204464 kb
Host smart-1448d170-2a21-45ed-b1e3-27a796f66fc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767667520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3767667520
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3640444094
Short name T205
Test name
Test status
Simulation time 27748005 ps
CPU time 0.79 seconds
Started Jul 18 05:10:39 PM PDT 24
Finished Jul 18 05:10:43 PM PDT 24
Peak memory 204388 kb
Host smart-f1fb9e26-1743-4c75-94ae-3b67da955425
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640444094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3640444094
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2606834674
Short name T169
Test name
Test status
Simulation time 104923076 ps
CPU time 1.05 seconds
Started Jul 18 05:11:01 PM PDT 24
Finished Jul 18 05:11:03 PM PDT 24
Peak memory 204520 kb
Host smart-48bd9cc5-711b-4ab5-b789-ac8ad7d26718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606834674 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2606834674
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.351761595
Short name T211
Test name
Test status
Simulation time 36969370 ps
CPU time 0.68 seconds
Started Jul 18 05:10:59 PM PDT 24
Finished Jul 18 05:11:02 PM PDT 24
Peak memory 204404 kb
Host smart-253bb5e4-7018-429b-8d25-cc07512c3839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351761595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.351761595
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.236202601
Short name T1779
Test name
Test status
Simulation time 30634585 ps
CPU time 0.65 seconds
Started Jul 18 05:10:40 PM PDT 24
Finished Jul 18 05:10:43 PM PDT 24
Peak memory 204392 kb
Host smart-6f23e6af-2947-4d21-b041-023267726571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236202601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.236202601
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.389786255
Short name T1791
Test name
Test status
Simulation time 48586595 ps
CPU time 0.94 seconds
Started Jul 18 05:10:59 PM PDT 24
Finished Jul 18 05:11:01 PM PDT 24
Peak memory 204396 kb
Host smart-6bc4936d-d203-4ad3-a9c3-f5d5c6c0df9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389786255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.389786255
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2661557507
Short name T1848
Test name
Test status
Simulation time 272562330 ps
CPU time 2.19 seconds
Started Jul 18 05:10:38 PM PDT 24
Finished Jul 18 05:10:43 PM PDT 24
Peak memory 204760 kb
Host smart-4c89c12d-5a13-4fd2-8f0c-166898754734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661557507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2661557507
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.55267732
Short name T1834
Test name
Test status
Simulation time 25477007 ps
CPU time 0.95 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204508 kb
Host smart-f666dabb-8e50-41a4-ae07-5bbbacf3c9e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55267732 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.55267732
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1459707660
Short name T207
Test name
Test status
Simulation time 19493243 ps
CPU time 0.76 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204440 kb
Host smart-1aebecd8-7859-4021-ba31-6ac5f5f14b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459707660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1459707660
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3058115862
Short name T1795
Test name
Test status
Simulation time 18156249 ps
CPU time 0.64 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:56 PM PDT 24
Peak memory 204368 kb
Host smart-8bfc0661-e3a3-47cc-ac85-e2cabb6744fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058115862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3058115862
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1376892867
Short name T1822
Test name
Test status
Simulation time 102617824 ps
CPU time 1.12 seconds
Started Jul 18 05:11:49 PM PDT 24
Finished Jul 18 05:11:50 PM PDT 24
Peak memory 204528 kb
Host smart-7b0adeab-3744-4d2f-9ee7-972e7ece6d5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376892867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1376892867
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3139325219
Short name T181
Test name
Test status
Simulation time 143227796 ps
CPU time 1.14 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:53 PM PDT 24
Peak memory 204640 kb
Host smart-47152ee0-28a0-43d8-96cc-5aac4834b401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139325219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3139325219
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.279046678
Short name T94
Test name
Test status
Simulation time 56896201 ps
CPU time 1.02 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204504 kb
Host smart-ba7c29b3-504f-4097-b80c-343c5219b6b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279046678 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.279046678
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2955391483
Short name T1788
Test name
Test status
Simulation time 67455354 ps
CPU time 0.72 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204440 kb
Host smart-6d1c8edc-0e9c-4bfc-9923-fb1f12bb0511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955391483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2955391483
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.208622468
Short name T1857
Test name
Test status
Simulation time 18005482 ps
CPU time 0.68 seconds
Started Jul 18 05:11:48 PM PDT 24
Finished Jul 18 05:11:50 PM PDT 24
Peak memory 204408 kb
Host smart-6b491151-d3bf-44c2-b83b-13acda5ede88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208622468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.208622468
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.689439326
Short name T137
Test name
Test status
Simulation time 184038368 ps
CPU time 1.23 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204632 kb
Host smart-b72d8ec8-aa5f-4443-860e-1025bc24b99b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689439326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.689439326
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3901163624
Short name T97
Test name
Test status
Simulation time 266351841 ps
CPU time 1.48 seconds
Started Jul 18 05:11:49 PM PDT 24
Finished Jul 18 05:11:52 PM PDT 24
Peak memory 204652 kb
Host smart-d896cf33-294d-4674-bc3f-066ed49c481b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901163624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3901163624
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3278994016
Short name T1797
Test name
Test status
Simulation time 71195609 ps
CPU time 1.45 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204572 kb
Host smart-17f7a931-ae84-4f6e-845d-d7baeca37fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278994016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3278994016
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2673427588
Short name T1793
Test name
Test status
Simulation time 189963578 ps
CPU time 0.91 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204460 kb
Host smart-502716c2-fab0-43eb-99d0-a2d33fa449fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673427588 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2673427588
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.279736026
Short name T198
Test name
Test status
Simulation time 69253240 ps
CPU time 0.75 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204332 kb
Host smart-abdf7a17-3f0c-453b-bb18-4441f7209c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279736026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.279736026
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.408372096
Short name T1780
Test name
Test status
Simulation time 19219877 ps
CPU time 0.69 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:55 PM PDT 24
Peak memory 204440 kb
Host smart-bd02792a-9eb2-40d7-a215-4e412154f79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408372096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.408372096
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.813268458
Short name T213
Test name
Test status
Simulation time 27732235 ps
CPU time 1.11 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204484 kb
Host smart-1a819fa8-6362-42bd-9e06-1a54ae048e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813268458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.813268458
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2489236501
Short name T1819
Test name
Test status
Simulation time 205994325 ps
CPU time 2.4 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:58 PM PDT 24
Peak memory 204688 kb
Host smart-13d0fee0-18a1-401b-a9c9-bab4a2500ae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489236501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2489236501
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4189982788
Short name T185
Test name
Test status
Simulation time 268361283 ps
CPU time 2.08 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204608 kb
Host smart-537965a5-c63a-453f-b5a1-027bedd32b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189982788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4189982788
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.709046732
Short name T1766
Test name
Test status
Simulation time 30657797 ps
CPU time 1.39 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 212748 kb
Host smart-99336729-4699-44cb-91eb-a256a55538a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709046732 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.709046732
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3556900379
Short name T200
Test name
Test status
Simulation time 118072817 ps
CPU time 0.73 seconds
Started Jul 18 05:11:49 PM PDT 24
Finished Jul 18 05:11:51 PM PDT 24
Peak memory 204436 kb
Host smart-802f8780-8fa4-4178-98dd-ad554e4c4ee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556900379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3556900379
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2123774952
Short name T1787
Test name
Test status
Simulation time 39325603 ps
CPU time 0.89 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204440 kb
Host smart-e04264fc-0123-4186-9b48-09ea4de07a27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123774952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.2123774952
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1557424738
Short name T1818
Test name
Test status
Simulation time 659313212 ps
CPU time 2.97 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 212748 kb
Host smart-7e7ac868-afa1-4c67-b61c-a53f55f7872f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557424738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1557424738
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.882302988
Short name T1816
Test name
Test status
Simulation time 133064991 ps
CPU time 1.45 seconds
Started Jul 18 05:11:48 PM PDT 24
Finished Jul 18 05:11:51 PM PDT 24
Peak memory 204512 kb
Host smart-fcbc91fa-52ef-40c1-b3ff-33a2195ec906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882302988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.882302988
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2453668260
Short name T178
Test name
Test status
Simulation time 29094338 ps
CPU time 1.29 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:56 PM PDT 24
Peak memory 204680 kb
Host smart-0e6cda26-e684-4779-a6dd-b03d93757fb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453668260 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2453668260
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2022398201
Short name T1783
Test name
Test status
Simulation time 114158174 ps
CPU time 0.7 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:53 PM PDT 24
Peak memory 204440 kb
Host smart-f40fba17-a571-47f2-9adf-3c7dec88e3a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022398201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2022398201
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3521839912
Short name T1773
Test name
Test status
Simulation time 18963480 ps
CPU time 0.71 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:56 PM PDT 24
Peak memory 204404 kb
Host smart-3b5437b8-655c-4a40-9313-bbb9d4831104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521839912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3521839912
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1414387679
Short name T208
Test name
Test status
Simulation time 294295710 ps
CPU time 1.18 seconds
Started Jul 18 05:11:54 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204524 kb
Host smart-80cd6a75-d2e6-40a3-aedf-879e60397baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414387679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1414387679
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.654006828
Short name T1765
Test name
Test status
Simulation time 94737464 ps
CPU time 2.01 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:55 PM PDT 24
Peak memory 204600 kb
Host smart-32b62e14-83a5-460f-8ab6-f37b4ceb6e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654006828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.654006828
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.644553836
Short name T184
Test name
Test status
Simulation time 81867166 ps
CPU time 1.5 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204592 kb
Host smart-681ac9e8-97ea-490a-b9b3-878b53e73518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644553836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.644553836
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3499642907
Short name T1808
Test name
Test status
Simulation time 183480797 ps
CPU time 1.14 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204668 kb
Host smart-64445f50-8900-43eb-b840-3d9ec930bf77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499642907 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3499642907
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2336201995
Short name T201
Test name
Test status
Simulation time 247539953 ps
CPU time 0.86 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204416 kb
Host smart-1173ff97-b4c7-4b73-8744-3fdfe2342297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336201995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2336201995
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3421074200
Short name T1782
Test name
Test status
Simulation time 18602193 ps
CPU time 0.7 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:11:58 PM PDT 24
Peak memory 204380 kb
Host smart-a0411b02-5123-46e3-995b-1ae2bd7c2a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421074200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3421074200
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1355314108
Short name T1851
Test name
Test status
Simulation time 246747163 ps
CPU time 1.2 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:56 PM PDT 24
Peak memory 204572 kb
Host smart-86d4a905-ee4f-42c8-b83b-3145bae51167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355314108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1355314108
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2869103403
Short name T1830
Test name
Test status
Simulation time 114389930 ps
CPU time 2.67 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:12:00 PM PDT 24
Peak memory 204644 kb
Host smart-1fca2f27-84e6-4209-8992-20a75b2e257c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869103403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2869103403
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.240211537
Short name T1841
Test name
Test status
Simulation time 82208479 ps
CPU time 1.55 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:58 PM PDT 24
Peak memory 204548 kb
Host smart-fa7121d7-4bfe-47be-94ec-c82a110a8819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240211537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.240211537
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2944587560
Short name T89
Test name
Test status
Simulation time 77236145 ps
CPU time 0.77 seconds
Started Jul 18 05:12:05 PM PDT 24
Finished Jul 18 05:12:07 PM PDT 24
Peak memory 204512 kb
Host smart-f9f25c9d-c510-4de9-8d4e-4b36bb4fece7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944587560 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2944587560
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2161522991
Short name T204
Test name
Test status
Simulation time 20786107 ps
CPU time 0.73 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204456 kb
Host smart-837a8b06-530e-4300-a31d-c01ab762a3fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161522991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2161522991
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1757238337
Short name T1762
Test name
Test status
Simulation time 30820930 ps
CPU time 0.83 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204424 kb
Host smart-c4d29c33-86cb-43b7-b5c3-a4c6b71f0dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757238337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1757238337
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.896078554
Short name T167
Test name
Test status
Simulation time 151278377 ps
CPU time 2.09 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:56 PM PDT 24
Peak memory 212736 kb
Host smart-fa71f7b9-fc3e-4d5b-9dd7-5f025fb87b56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896078554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.896078554
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2853019726
Short name T193
Test name
Test status
Simulation time 23663772 ps
CPU time 0.82 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204468 kb
Host smart-0b4d0dab-537b-4906-82a1-b5bec19a659d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853019726 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2853019726
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3838518195
Short name T196
Test name
Test status
Simulation time 42074508 ps
CPU time 0.7 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:55 PM PDT 24
Peak memory 204392 kb
Host smart-fb13ea43-355e-4dbb-b123-c08ed1082b15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838518195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3838518195
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2897116082
Short name T1807
Test name
Test status
Simulation time 17755218 ps
CPU time 0.69 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204432 kb
Host smart-b5927efb-3370-4ad4-a261-405148c4c6f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897116082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2897116082
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1279020966
Short name T209
Test name
Test status
Simulation time 96243175 ps
CPU time 1.25 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:55 PM PDT 24
Peak memory 204544 kb
Host smart-4e998fcf-d6d8-4aa9-846e-2c6a43e55675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279020966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1279020966
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3393339920
Short name T182
Test name
Test status
Simulation time 89499768 ps
CPU time 1.53 seconds
Started Jul 18 05:11:54 PM PDT 24
Finished Jul 18 05:12:00 PM PDT 24
Peak memory 204640 kb
Host smart-404424ec-2921-490f-b795-cad0cb9c346a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393339920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3393339920
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2438138431
Short name T93
Test name
Test status
Simulation time 256349086 ps
CPU time 2.35 seconds
Started Jul 18 05:11:53 PM PDT 24
Finished Jul 18 05:12:00 PM PDT 24
Peak memory 204504 kb
Host smart-f1116c80-d3eb-4858-8c99-4faaf3082bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438138431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2438138431
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3734616861
Short name T1798
Test name
Test status
Simulation time 33436231 ps
CPU time 1.04 seconds
Started Jul 18 05:12:22 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 204528 kb
Host smart-ce554ab9-8918-406d-bd44-19a956b5b3ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734616861 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3734616861
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3935819072
Short name T1781
Test name
Test status
Simulation time 46213338 ps
CPU time 0.82 seconds
Started Jul 18 05:11:56 PM PDT 24
Finished Jul 18 05:12:00 PM PDT 24
Peak memory 204408 kb
Host smart-16255b72-5ff3-4922-88e3-aad26e65071d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935819072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3935819072
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2818294390
Short name T1846
Test name
Test status
Simulation time 18074719 ps
CPU time 0.67 seconds
Started Jul 18 05:11:54 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204412 kb
Host smart-b3c3ff67-a7c0-4e24-8b43-567fe1813599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818294390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2818294390
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2083958250
Short name T108
Test name
Test status
Simulation time 506625671 ps
CPU time 1.19 seconds
Started Jul 18 05:11:56 PM PDT 24
Finished Jul 18 05:12:01 PM PDT 24
Peak memory 204624 kb
Host smart-b948e36f-e344-4063-bcca-c1ee92307574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083958250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2083958250
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2091495144
Short name T1829
Test name
Test status
Simulation time 103226228 ps
CPU time 1.15 seconds
Started Jul 18 05:11:56 PM PDT 24
Finished Jul 18 05:12:00 PM PDT 24
Peak memory 204592 kb
Host smart-3de7b93e-2037-46b9-a447-1f89b6e14a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091495144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2091495144
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3096243134
Short name T176
Test name
Test status
Simulation time 348303456 ps
CPU time 2.13 seconds
Started Jul 18 05:11:56 PM PDT 24
Finished Jul 18 05:12:02 PM PDT 24
Peak memory 204468 kb
Host smart-48c3b09f-8c0d-4a86-a57a-a0df72d463ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096243134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3096243134
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1147445520
Short name T168
Test name
Test status
Simulation time 81752235 ps
CPU time 1.03 seconds
Started Jul 18 05:12:36 PM PDT 24
Finished Jul 18 05:12:38 PM PDT 24
Peak memory 204568 kb
Host smart-38d9b5c5-44db-434e-a383-d6921af88f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147445520 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1147445520
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.182517866
Short name T1811
Test name
Test status
Simulation time 28033522 ps
CPU time 0.66 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:08 PM PDT 24
Peak memory 204412 kb
Host smart-d8288576-ea50-4bf2-a5db-527fa74f6aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182517866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.182517866
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3352518686
Short name T1803
Test name
Test status
Simulation time 38035738 ps
CPU time 0.88 seconds
Started Jul 18 05:12:22 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 204432 kb
Host smart-fb26dfdd-ee07-4afd-9c20-78e4dbfe222c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352518686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3352518686
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3166233523
Short name T1814
Test name
Test status
Simulation time 331780568 ps
CPU time 1.32 seconds
Started Jul 18 05:12:24 PM PDT 24
Finished Jul 18 05:12:28 PM PDT 24
Peak memory 204628 kb
Host smart-f70bf9ff-b7f0-4323-a49b-c02faf86c39e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166233523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3166233523
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2264573688
Short name T206
Test name
Test status
Simulation time 73108069 ps
CPU time 1.77 seconds
Started Jul 18 05:11:02 PM PDT 24
Finished Jul 18 05:11:04 PM PDT 24
Peak memory 204588 kb
Host smart-a284ce9d-d14c-4650-8309-d88a8c434fa2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264573688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2264573688
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1805893923
Short name T1772
Test name
Test status
Simulation time 232928599 ps
CPU time 2.58 seconds
Started Jul 18 05:10:56 PM PDT 24
Finished Jul 18 05:10:59 PM PDT 24
Peak memory 204500 kb
Host smart-78b5c6d7-0257-40b3-82b6-c0bfe6172cd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805893923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1805893923
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3253833029
Short name T202
Test name
Test status
Simulation time 71906512 ps
CPU time 0.86 seconds
Started Jul 18 05:11:00 PM PDT 24
Finished Jul 18 05:11:02 PM PDT 24
Peak memory 204352 kb
Host smart-7de99943-8c39-468d-8631-3888567bf2a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253833029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3253833029
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.501188815
Short name T1777
Test name
Test status
Simulation time 17202617 ps
CPU time 0.82 seconds
Started Jul 18 05:10:59 PM PDT 24
Finished Jul 18 05:11:01 PM PDT 24
Peak memory 204448 kb
Host smart-1261dc25-8f90-430c-b7ce-fb16526f40b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501188815 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.501188815
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.148981408
Short name T191
Test name
Test status
Simulation time 87061363 ps
CPU time 0.78 seconds
Started Jul 18 05:10:58 PM PDT 24
Finished Jul 18 05:10:59 PM PDT 24
Peak memory 204484 kb
Host smart-b46e9ee3-8d2c-4a30-92fc-266df7b389d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148981408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.148981408
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1969988651
Short name T1845
Test name
Test status
Simulation time 20662123 ps
CPU time 0.71 seconds
Started Jul 18 05:10:58 PM PDT 24
Finished Jul 18 05:11:00 PM PDT 24
Peak memory 204416 kb
Host smart-79c2d3ea-3943-4692-8cb1-b78c0b14ea93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969988651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1969988651
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3943983736
Short name T1824
Test name
Test status
Simulation time 30988339 ps
CPU time 0.89 seconds
Started Jul 18 05:11:01 PM PDT 24
Finished Jul 18 05:11:03 PM PDT 24
Peak memory 204468 kb
Host smart-2e62385a-346f-4c76-83ba-0993f0e011f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943983736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3943983736
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1936670000
Short name T1856
Test name
Test status
Simulation time 143014232 ps
CPU time 2 seconds
Started Jul 18 05:11:01 PM PDT 24
Finished Jul 18 05:11:04 PM PDT 24
Peak memory 212868 kb
Host smart-3dffce3d-bc15-41b2-a808-318514de4e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936670000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1936670000
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2219002919
Short name T187
Test name
Test status
Simulation time 485231561 ps
CPU time 1.5 seconds
Started Jul 18 05:11:01 PM PDT 24
Finished Jul 18 05:11:04 PM PDT 24
Peak memory 204564 kb
Host smart-569ae6fb-35c7-43d5-8175-235ecffec095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219002919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2219002919
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3884222740
Short name T1820
Test name
Test status
Simulation time 56713762 ps
CPU time 0.66 seconds
Started Jul 18 05:12:29 PM PDT 24
Finished Jul 18 05:12:30 PM PDT 24
Peak memory 204416 kb
Host smart-daba208f-f937-4816-9c7a-84928a1ae365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884222740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3884222740
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3025656261
Short name T1823
Test name
Test status
Simulation time 121542411 ps
CPU time 0.67 seconds
Started Jul 18 05:12:23 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 204432 kb
Host smart-13d9a4f7-8072-4768-97b8-cb8ada0bd9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025656261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3025656261
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1908701536
Short name T1764
Test name
Test status
Simulation time 16970067 ps
CPU time 0.68 seconds
Started Jul 18 05:12:22 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 204388 kb
Host smart-8e2bb638-b4fe-4761-a959-0d58c0740740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908701536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1908701536
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2748410200
Short name T1825
Test name
Test status
Simulation time 42519260 ps
CPU time 0.7 seconds
Started Jul 18 05:12:22 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 204376 kb
Host smart-3c9b741e-894f-4fc8-91b4-5c4a69be9d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748410200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2748410200
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.721692085
Short name T1786
Test name
Test status
Simulation time 26046785 ps
CPU time 0.71 seconds
Started Jul 18 05:12:24 PM PDT 24
Finished Jul 18 05:12:27 PM PDT 24
Peak memory 204456 kb
Host smart-b5312d4c-a08b-460e-abd3-7183e6c5a495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721692085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.721692085
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3186477470
Short name T1763
Test name
Test status
Simulation time 34039365 ps
CPU time 0.7 seconds
Started Jul 18 05:12:22 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 204400 kb
Host smart-ba99d6de-0931-4e29-96d6-8e68d23ff338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186477470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3186477470
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2777779860
Short name T1799
Test name
Test status
Simulation time 58803852 ps
CPU time 0.72 seconds
Started Jul 18 05:12:22 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 204416 kb
Host smart-d1b6514b-e498-41c7-868b-d620d0e5c6da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777779860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2777779860
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.702367246
Short name T1837
Test name
Test status
Simulation time 15121625 ps
CPU time 0.68 seconds
Started Jul 18 05:12:28 PM PDT 24
Finished Jul 18 05:12:30 PM PDT 24
Peak memory 204356 kb
Host smart-2ebe235d-3cca-4e52-adae-45f32e15f6c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702367246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.702367246
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.416936008
Short name T1784
Test name
Test status
Simulation time 15211591 ps
CPU time 0.71 seconds
Started Jul 18 05:12:26 PM PDT 24
Finished Jul 18 05:12:28 PM PDT 24
Peak memory 204404 kb
Host smart-559a9a54-dfa3-4f2f-a5c9-f1fde7b37007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416936008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.416936008
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1133627976
Short name T263
Test name
Test status
Simulation time 28598844 ps
CPU time 0.69 seconds
Started Jul 18 05:12:23 PM PDT 24
Finished Jul 18 05:12:26 PM PDT 24
Peak memory 204388 kb
Host smart-fb376853-eacb-468b-9cda-d873530d8a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133627976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1133627976
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2969912510
Short name T1767
Test name
Test status
Simulation time 85972392 ps
CPU time 1.3 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:20 PM PDT 24
Peak memory 204516 kb
Host smart-6acdef9d-3101-4ba4-bff0-80c2ab9e73f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969912510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2969912510
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2889916491
Short name T1838
Test name
Test status
Simulation time 278622241 ps
CPU time 3.14 seconds
Started Jul 18 05:11:00 PM PDT 24
Finished Jul 18 05:11:05 PM PDT 24
Peak memory 204468 kb
Host smart-e40e9cbe-86b9-463e-a67f-675360614ece
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889916491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2889916491
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.116335412
Short name T91
Test name
Test status
Simulation time 28393141 ps
CPU time 0.8 seconds
Started Jul 18 05:10:59 PM PDT 24
Finished Jul 18 05:11:01 PM PDT 24
Peak memory 204392 kb
Host smart-e951e1a2-a46d-4ca3-9b5b-3cc6653b374d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116335412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.116335412
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2876273134
Short name T1828
Test name
Test status
Simulation time 53413948 ps
CPU time 1.03 seconds
Started Jul 18 05:11:19 PM PDT 24
Finished Jul 18 05:11:22 PM PDT 24
Peak memory 204492 kb
Host smart-a5fc6c3e-a4ac-4486-b2fa-27ad26203fe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876273134 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2876273134
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2184661409
Short name T1802
Test name
Test status
Simulation time 74033071 ps
CPU time 0.74 seconds
Started Jul 18 05:10:58 PM PDT 24
Finished Jul 18 05:11:00 PM PDT 24
Peak memory 204464 kb
Host smart-a05d5555-00f1-46df-a3e5-b7d7f931caac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184661409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2184661409
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.749239236
Short name T1760
Test name
Test status
Simulation time 20214045 ps
CPU time 0.73 seconds
Started Jul 18 05:11:00 PM PDT 24
Finished Jul 18 05:11:02 PM PDT 24
Peak memory 204396 kb
Host smart-95b2a41e-1ebe-4d01-8ee6-cbc82c0e994a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749239236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.749239236
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2945846588
Short name T1855
Test name
Test status
Simulation time 32040534 ps
CPU time 0.83 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:20 PM PDT 24
Peak memory 204384 kb
Host smart-5c62ddb5-cb94-4a5f-88ce-d320ed8af5c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945846588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.2945846588
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1395564046
Short name T1794
Test name
Test status
Simulation time 293438805 ps
CPU time 1.66 seconds
Started Jul 18 05:10:59 PM PDT 24
Finished Jul 18 05:11:02 PM PDT 24
Peak memory 204580 kb
Host smart-e4d5f436-93a4-4838-a0a3-d5f8e51c7354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395564046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1395564046
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1871758502
Short name T1774
Test name
Test status
Simulation time 34657898 ps
CPU time 0.71 seconds
Started Jul 18 05:12:23 PM PDT 24
Finished Jul 18 05:12:26 PM PDT 24
Peak memory 204412 kb
Host smart-d8a87111-48dc-4ba3-bf25-75a3b912dfa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871758502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1871758502
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3095712168
Short name T1789
Test name
Test status
Simulation time 32230000 ps
CPU time 0.69 seconds
Started Jul 18 05:12:30 PM PDT 24
Finished Jul 18 05:12:31 PM PDT 24
Peak memory 204404 kb
Host smart-314def23-d0b6-4ba0-9050-024fc89f3b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095712168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3095712168
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2216303413
Short name T1796
Test name
Test status
Simulation time 29682534 ps
CPU time 0.64 seconds
Started Jul 18 05:12:36 PM PDT 24
Finished Jul 18 05:12:38 PM PDT 24
Peak memory 204416 kb
Host smart-fdb00ae9-9bf3-45cd-8058-ca7516744ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216303413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2216303413
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2733487590
Short name T264
Test name
Test status
Simulation time 26632227 ps
CPU time 0.79 seconds
Started Jul 18 05:12:27 PM PDT 24
Finished Jul 18 05:12:29 PM PDT 24
Peak memory 204404 kb
Host smart-7ca99c6a-b3f7-4bec-862a-6c4e337333e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733487590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2733487590
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1165446466
Short name T109
Test name
Test status
Simulation time 18667758 ps
CPU time 0.71 seconds
Started Jul 18 05:12:23 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 204360 kb
Host smart-aedd0270-6da9-4702-9636-2235e3ed72a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165446466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1165446466
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1870368662
Short name T266
Test name
Test status
Simulation time 18290415 ps
CPU time 0.67 seconds
Started Jul 18 05:12:24 PM PDT 24
Finished Jul 18 05:12:27 PM PDT 24
Peak memory 204440 kb
Host smart-c5f38c62-a749-4d82-bb67-e094b56891b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870368662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1870368662
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1881442542
Short name T1771
Test name
Test status
Simulation time 16115710 ps
CPU time 0.65 seconds
Started Jul 18 05:12:25 PM PDT 24
Finished Jul 18 05:12:27 PM PDT 24
Peak memory 204444 kb
Host smart-84ec81ac-03f3-422d-a808-8e8d765e1657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881442542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1881442542
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3729939919
Short name T260
Test name
Test status
Simulation time 17825016 ps
CPU time 0.68 seconds
Started Jul 18 05:12:26 PM PDT 24
Finished Jul 18 05:12:27 PM PDT 24
Peak memory 204376 kb
Host smart-3a728aec-02b3-4d66-81dc-5ac9de03429c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729939919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3729939919
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.4264060889
Short name T1805
Test name
Test status
Simulation time 39592565 ps
CPU time 0.68 seconds
Started Jul 18 05:12:24 PM PDT 24
Finished Jul 18 05:12:26 PM PDT 24
Peak memory 204456 kb
Host smart-8641b72a-0a27-4e42-8f30-30f2c6b12db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264060889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.4264060889
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1817506046
Short name T1790
Test name
Test status
Simulation time 46433705 ps
CPU time 0.7 seconds
Started Jul 18 05:12:28 PM PDT 24
Finished Jul 18 05:12:29 PM PDT 24
Peak memory 204464 kb
Host smart-8980bdd2-bd6e-43b9-8521-f1f7da47e951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817506046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1817506046
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2584844789
Short name T1836
Test name
Test status
Simulation time 29260079 ps
CPU time 1.28 seconds
Started Jul 18 05:11:25 PM PDT 24
Finished Jul 18 05:11:27 PM PDT 24
Peak memory 204556 kb
Host smart-178db9a9-0329-48b4-8b56-2aa094a189bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584844789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2584844789
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.65178481
Short name T92
Test name
Test status
Simulation time 284701665 ps
CPU time 2.85 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:22 PM PDT 24
Peak memory 204516 kb
Host smart-2bac5434-bf7a-4855-ab24-40866252fd76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65178481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.65178481
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2419628272
Short name T1850
Test name
Test status
Simulation time 110874598 ps
CPU time 0.76 seconds
Started Jul 18 05:11:18 PM PDT 24
Finished Jul 18 05:11:21 PM PDT 24
Peak memory 204436 kb
Host smart-c22ae227-4fa2-4bea-b32c-7d2dc4d64a27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419628272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2419628272
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3970194859
Short name T1776
Test name
Test status
Simulation time 155366640 ps
CPU time 1.01 seconds
Started Jul 18 05:11:19 PM PDT 24
Finished Jul 18 05:11:22 PM PDT 24
Peak memory 204496 kb
Host smart-9909c74a-e4f3-4c4d-946f-66ce700505bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970194859 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3970194859
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.4022591291
Short name T212
Test name
Test status
Simulation time 53127501 ps
CPU time 0.75 seconds
Started Jul 18 05:11:16 PM PDT 24
Finished Jul 18 05:11:18 PM PDT 24
Peak memory 204580 kb
Host smart-4dd6064a-aac4-4697-bc66-ba0faa2ec174
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022591291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.4022591291
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.2881210676
Short name T1768
Test name
Test status
Simulation time 17764403 ps
CPU time 0.7 seconds
Started Jul 18 05:11:16 PM PDT 24
Finished Jul 18 05:11:18 PM PDT 24
Peak memory 204412 kb
Host smart-1674efbd-cda1-4442-bf40-86c83291e45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881210676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2881210676
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.313778867
Short name T1844
Test name
Test status
Simulation time 269878536 ps
CPU time 1.06 seconds
Started Jul 18 05:11:16 PM PDT 24
Finished Jul 18 05:11:18 PM PDT 24
Peak memory 204512 kb
Host smart-9b65c606-9d2d-4d70-8491-a536880be6b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313778867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.313778867
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2966187605
Short name T1800
Test name
Test status
Simulation time 216699749 ps
CPU time 2.23 seconds
Started Jul 18 05:11:16 PM PDT 24
Finished Jul 18 05:11:20 PM PDT 24
Peak memory 204552 kb
Host smart-a62174f9-af53-4c13-8a77-441acb6a0c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966187605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2966187605
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3795611315
Short name T189
Test name
Test status
Simulation time 90011597 ps
CPU time 2.19 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:22 PM PDT 24
Peak memory 204444 kb
Host smart-c6b71a57-56b2-422e-ae89-31c058d26e19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795611315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3795611315
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.1161334844
Short name T265
Test name
Test status
Simulation time 68069956 ps
CPU time 0.69 seconds
Started Jul 18 05:12:23 PM PDT 24
Finished Jul 18 05:12:26 PM PDT 24
Peak memory 204460 kb
Host smart-2572621c-e68e-429f-959b-d4675b8423d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161334844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1161334844
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.925262049
Short name T267
Test name
Test status
Simulation time 31376055 ps
CPU time 0.7 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:12:51 PM PDT 24
Peak memory 204412 kb
Host smart-962636c8-296e-47bc-a497-8be229ab43a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925262049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.925262049
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.232415809
Short name T1812
Test name
Test status
Simulation time 49085454 ps
CPU time 0.69 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:12:51 PM PDT 24
Peak memory 204412 kb
Host smart-63caff22-a4ed-44b6-a505-8be0445814a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232415809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.232415809
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3819370468
Short name T1815
Test name
Test status
Simulation time 14616284 ps
CPU time 0.63 seconds
Started Jul 18 05:12:46 PM PDT 24
Finished Jul 18 05:12:50 PM PDT 24
Peak memory 204456 kb
Host smart-aa31d66b-262a-4beb-bf9b-41df5ea096a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819370468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3819370468
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1671991171
Short name T1840
Test name
Test status
Simulation time 19521917 ps
CPU time 0.69 seconds
Started Jul 18 05:12:49 PM PDT 24
Finished Jul 18 05:12:54 PM PDT 24
Peak memory 204404 kb
Host smart-90208936-8372-4c69-8b0f-45e95adb800c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671991171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1671991171
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.1856250779
Short name T1831
Test name
Test status
Simulation time 18286138 ps
CPU time 0.69 seconds
Started Jul 18 05:12:46 PM PDT 24
Finished Jul 18 05:12:50 PM PDT 24
Peak memory 204456 kb
Host smart-5afbea02-26f3-4fc5-9aec-35f2d5f900c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856250779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1856250779
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1168381803
Short name T1810
Test name
Test status
Simulation time 15949785 ps
CPU time 0.67 seconds
Started Jul 18 05:12:44 PM PDT 24
Finished Jul 18 05:12:46 PM PDT 24
Peak memory 204456 kb
Host smart-a66c506b-7a4e-492c-9b26-e250f34eb67f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168381803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1168381803
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.388243308
Short name T1761
Test name
Test status
Simulation time 57366476 ps
CPU time 0.72 seconds
Started Jul 18 05:12:45 PM PDT 24
Finished Jul 18 05:12:48 PM PDT 24
Peak memory 204412 kb
Host smart-8a9498dc-aa77-4d15-8f51-1f6d5326b10a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388243308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.388243308
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3585929510
Short name T1853
Test name
Test status
Simulation time 17492730 ps
CPU time 0.7 seconds
Started Jul 18 05:12:46 PM PDT 24
Finished Jul 18 05:12:50 PM PDT 24
Peak memory 204376 kb
Host smart-94f06c09-dd38-456b-a12c-158bdc099bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585929510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3585929510
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.832518925
Short name T1842
Test name
Test status
Simulation time 91605861 ps
CPU time 0.77 seconds
Started Jul 18 05:11:18 PM PDT 24
Finished Jul 18 05:11:21 PM PDT 24
Peak memory 204440 kb
Host smart-cca7cce6-4dfa-41c6-a566-fa403c1a29c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832518925 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.832518925
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3108408087
Short name T1759
Test name
Test status
Simulation time 115307830 ps
CPU time 0.73 seconds
Started Jul 18 05:11:19 PM PDT 24
Finished Jul 18 05:11:22 PM PDT 24
Peak memory 204672 kb
Host smart-27ae5543-cbba-43bb-a410-5cb6f7abc02f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108408087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3108408087
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.307065332
Short name T268
Test name
Test status
Simulation time 60172826 ps
CPU time 0.65 seconds
Started Jul 18 05:11:18 PM PDT 24
Finished Jul 18 05:11:21 PM PDT 24
Peak memory 204396 kb
Host smart-2c3d3960-cc07-40ba-b721-2baee562ae85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307065332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.307065332
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2010739989
Short name T1849
Test name
Test status
Simulation time 439841939 ps
CPU time 1.14 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:19 PM PDT 24
Peak memory 204504 kb
Host smart-a3b9ea53-2938-430b-a589-15f339241288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010739989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2010739989
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.4259966244
Short name T1770
Test name
Test status
Simulation time 89520893 ps
CPU time 2.43 seconds
Started Jul 18 05:11:18 PM PDT 24
Finished Jul 18 05:11:23 PM PDT 24
Peak memory 204628 kb
Host smart-26f6a040-60dc-4c14-8500-f358cc31f469
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259966244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.4259966244
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.962281376
Short name T183
Test name
Test status
Simulation time 103632011 ps
CPU time 1.5 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:21 PM PDT 24
Peak memory 204596 kb
Host smart-2f35a71f-4669-43fe-9681-438d026c5dec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962281376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.962281376
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.808233700
Short name T1821
Test name
Test status
Simulation time 133562025 ps
CPU time 1 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:21 PM PDT 24
Peak memory 204492 kb
Host smart-ffbb9544-00d4-48bf-abca-5410bcbf8f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808233700 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.808233700
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3828424366
Short name T199
Test name
Test status
Simulation time 55579065 ps
CPU time 0.77 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:20 PM PDT 24
Peak memory 204556 kb
Host smart-10393c31-c840-4c8b-b80e-60413ff2de22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828424366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3828424366
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3561158689
Short name T1817
Test name
Test status
Simulation time 25872842 ps
CPU time 0.68 seconds
Started Jul 18 05:11:18 PM PDT 24
Finished Jul 18 05:11:21 PM PDT 24
Peak memory 204372 kb
Host smart-6b0355d2-1d24-4986-ad07-1b565cce1ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561158689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3561158689
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2447802883
Short name T1792
Test name
Test status
Simulation time 55501803 ps
CPU time 0.88 seconds
Started Jul 18 05:11:20 PM PDT 24
Finished Jul 18 05:11:22 PM PDT 24
Peak memory 204432 kb
Host smart-2b1e4e85-cae3-47b9-9ffd-9cd757531a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447802883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2447802883
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3268767725
Short name T1801
Test name
Test status
Simulation time 328315488 ps
CPU time 2.36 seconds
Started Jul 18 05:11:18 PM PDT 24
Finished Jul 18 05:11:22 PM PDT 24
Peak memory 204568 kb
Host smart-f234d528-7599-4d3e-a0bd-ea6c9605415b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268767725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3268767725
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1972106954
Short name T1826
Test name
Test status
Simulation time 165480507 ps
CPU time 2.23 seconds
Started Jul 18 05:11:19 PM PDT 24
Finished Jul 18 05:11:24 PM PDT 24
Peak memory 204556 kb
Host smart-27bf2223-d223-4707-954a-93c1f27f465c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972106954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1972106954
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1470842587
Short name T194
Test name
Test status
Simulation time 116806524 ps
CPU time 1.03 seconds
Started Jul 18 05:11:20 PM PDT 24
Finished Jul 18 05:11:23 PM PDT 24
Peak memory 204504 kb
Host smart-55e7dd48-906d-4ae6-a669-20a88934c62c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470842587 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1470842587
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.284984175
Short name T1843
Test name
Test status
Simulation time 43107115 ps
CPU time 0.8 seconds
Started Jul 18 05:11:19 PM PDT 24
Finished Jul 18 05:11:22 PM PDT 24
Peak memory 204480 kb
Host smart-d19baf5d-1aa4-4993-816f-ce82e9336dc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284984175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.284984175
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3698529654
Short name T1804
Test name
Test status
Simulation time 198389928 ps
CPU time 0.7 seconds
Started Jul 18 05:11:16 PM PDT 24
Finished Jul 18 05:11:18 PM PDT 24
Peak memory 204444 kb
Host smart-2ff626ab-4041-444f-b738-6e364a074932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698529654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3698529654
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1331281998
Short name T1852
Test name
Test status
Simulation time 47724802 ps
CPU time 0.89 seconds
Started Jul 18 05:11:17 PM PDT 24
Finished Jul 18 05:11:19 PM PDT 24
Peak memory 204476 kb
Host smart-be37ec87-434a-42a5-bde5-aae1048af4b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331281998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1331281998
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3527284269
Short name T90
Test name
Test status
Simulation time 162395680 ps
CPU time 1.59 seconds
Started Jul 18 05:11:24 PM PDT 24
Finished Jul 18 05:11:26 PM PDT 24
Peak memory 204568 kb
Host smart-ef2a9f49-66dc-41bb-9057-fc1f32843adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527284269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3527284269
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1589909495
Short name T95
Test name
Test status
Simulation time 358237410 ps
CPU time 0.98 seconds
Started Jul 18 05:11:48 PM PDT 24
Finished Jul 18 05:11:50 PM PDT 24
Peak memory 204540 kb
Host smart-3d846386-750a-4f1c-9166-671da9b6ff9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589909495 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1589909495
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1639147255
Short name T210
Test name
Test status
Simulation time 38025963 ps
CPU time 0.72 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204436 kb
Host smart-63c2ffa2-3632-4f8b-a742-5fdd2e72c84e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639147255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1639147255
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1324599195
Short name T262
Test name
Test status
Simulation time 36036913 ps
CPU time 0.63 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204380 kb
Host smart-ef09d243-e01d-4410-9743-d67158d670be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324599195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1324599195
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.977708532
Short name T1809
Test name
Test status
Simulation time 29583353 ps
CPU time 1.13 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:53 PM PDT 24
Peak memory 204544 kb
Host smart-7a49100a-5365-4f39-b2ad-4a3bfd097d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977708532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out
standing.977708532
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2451207558
Short name T179
Test name
Test status
Simulation time 36880095 ps
CPU time 1.69 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:55 PM PDT 24
Peak memory 204852 kb
Host smart-e2f713a7-fe9e-456b-8175-50e3226cc2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451207558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2451207558
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1879797814
Short name T250
Test name
Test status
Simulation time 300725816 ps
CPU time 1.48 seconds
Started Jul 18 05:11:52 PM PDT 24
Finished Jul 18 05:11:57 PM PDT 24
Peak memory 204548 kb
Host smart-5c067a71-380b-4df9-8b6c-510de8d7d948
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879797814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1879797814
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4085584350
Short name T1839
Test name
Test status
Simulation time 68997709 ps
CPU time 1.02 seconds
Started Jul 18 05:11:51 PM PDT 24
Finished Jul 18 05:11:56 PM PDT 24
Peak memory 204736 kb
Host smart-088f59e4-677c-4fd0-aa31-19069227ac78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085584350 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.4085584350
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4196435944
Short name T1769
Test name
Test status
Simulation time 56706368 ps
CPU time 0.75 seconds
Started Jul 18 05:11:54 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204468 kb
Host smart-76ef209e-981d-4eed-83db-0fb8680936f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196435944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4196435944
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.736679095
Short name T1785
Test name
Test status
Simulation time 30265055 ps
CPU time 0.69 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:53 PM PDT 24
Peak memory 204416 kb
Host smart-0cb540cd-155e-4f35-8fa4-d79368893137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736679095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.736679095
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2193985448
Short name T1806
Test name
Test status
Simulation time 55881862 ps
CPU time 0.86 seconds
Started Jul 18 05:11:54 PM PDT 24
Finished Jul 18 05:11:59 PM PDT 24
Peak memory 204400 kb
Host smart-8bec64db-010f-4c5c-81e1-baddddf79dd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193985448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2193985448
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1875156995
Short name T1827
Test name
Test status
Simulation time 34517022 ps
CPU time 1.25 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204620 kb
Host smart-78d48fc7-263a-423b-bf3f-3625b2b40e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875156995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1875156995
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3937566083
Short name T188
Test name
Test status
Simulation time 175478674 ps
CPU time 1.38 seconds
Started Jul 18 05:11:50 PM PDT 24
Finished Jul 18 05:11:54 PM PDT 24
Peak memory 204576 kb
Host smart-7853ac85-8f70-4237-8fad-998d90c32d83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937566083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3937566083
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.663912682
Short name T1475
Test name
Test status
Simulation time 49284947 ps
CPU time 0.66 seconds
Started Jul 18 05:26:09 PM PDT 24
Finished Jul 18 05:26:12 PM PDT 24
Peak memory 204844 kb
Host smart-8723d38e-a8c5-48cb-84e6-b30f0921a60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663912682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.663912682
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3276829788
Short name T960
Test name
Test status
Simulation time 1473919788 ps
CPU time 10.66 seconds
Started Jul 18 05:25:59 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 311804 kb
Host smart-b0a21d2f-a9b2-46b7-bb06-7fcc40afdfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276829788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3276829788
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.952297543
Short name T606
Test name
Test status
Simulation time 1221828724 ps
CPU time 30.72 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:35 PM PDT 24
Peak memory 340732 kb
Host smart-92625ea8-8926-4bab-96e7-f1f5aeaf0d3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952297543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.952297543
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.483153746
Short name T601
Test name
Test status
Simulation time 2189916037 ps
CPU time 65.76 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:27:11 PM PDT 24
Peak memory 416412 kb
Host smart-455e03a3-0786-4c8d-86b4-a30bb4e71f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483153746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.483153746
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.161260662
Short name T464
Test name
Test status
Simulation time 1620327245 ps
CPU time 114.69 seconds
Started Jul 18 05:26:04 PM PDT 24
Finished Jul 18 05:28:02 PM PDT 24
Peak memory 592424 kb
Host smart-a8dc5e3f-7c8a-4f6f-9343-90083fb1a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161260662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.161260662
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2936727009
Short name T1077
Test name
Test status
Simulation time 405098900 ps
CPU time 0.99 seconds
Started Jul 18 05:26:05 PM PDT 24
Finished Jul 18 05:26:09 PM PDT 24
Peak memory 205240 kb
Host smart-c87e98e2-20e2-4f24-bfa2-23cc4cb8bc1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936727009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2936727009
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.4282757570
Short name T1003
Test name
Test status
Simulation time 843049595 ps
CPU time 5.57 seconds
Started Jul 18 05:26:01 PM PDT 24
Finished Jul 18 05:26:09 PM PDT 24
Peak memory 247136 kb
Host smart-a205a96e-ef62-4de0-b7c6-2e61924394b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282757570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
4282757570
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1013919706
Short name T103
Test name
Test status
Simulation time 14433193260 ps
CPU time 76.64 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:27:22 PM PDT 24
Peak memory 1035664 kb
Host smart-1bc16866-af13-4bc3-a302-88a8309ea172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013919706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1013919706
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.2926130583
Short name T1437
Test name
Test status
Simulation time 354065985 ps
CPU time 6.06 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:12 PM PDT 24
Peak memory 205484 kb
Host smart-1dc7e8d9-ec89-478c-8162-5c7de7b336b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926130583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.2926130583
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3753870725
Short name T1315
Test name
Test status
Simulation time 561099337 ps
CPU time 9.01 seconds
Started Jul 18 05:26:01 PM PDT 24
Finished Jul 18 05:26:12 PM PDT 24
Peak memory 235392 kb
Host smart-a4cc3ad6-049e-4567-b344-6714c6eb42c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753870725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3753870725
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.1985052171
Short name T39
Test name
Test status
Simulation time 107420366 ps
CPU time 1.47 seconds
Started Jul 18 05:26:01 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 205400 kb
Host smart-920efce0-1f8b-4cf0-a7be-4922b24f1aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985052171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.1985052171
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.732831648
Short name T1071
Test name
Test status
Simulation time 1739833502 ps
CPU time 30.96 seconds
Started Jul 18 05:26:01 PM PDT 24
Finished Jul 18 05:26:34 PM PDT 24
Peak memory 423556 kb
Host smart-fda8e649-dab2-420e-a30e-33d031d2e6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732831648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.732831648
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1073016612
Short name T447
Test name
Test status
Simulation time 453266361 ps
CPU time 8.34 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:17 PM PDT 24
Peak memory 213736 kb
Host smart-39930e6f-5880-4d37-a584-51aca969b0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073016612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1073016612
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.2431691190
Short name T1010
Test name
Test status
Simulation time 1111843347 ps
CPU time 6.08 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:15 PM PDT 24
Peak memory 213832 kb
Host smart-43b5dccb-b2ad-4020-bb2e-79ee8098b736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431691190 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2431691190
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1165652856
Short name T220
Test name
Test status
Simulation time 180771838 ps
CPU time 1.25 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:06 PM PDT 24
Peak memory 205640 kb
Host smart-f6227e61-d232-40ee-8767-3add484f0fcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165652856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1165652856
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1535210353
Short name T325
Test name
Test status
Simulation time 408112670 ps
CPU time 1 seconds
Started Jul 18 05:26:05 PM PDT 24
Finished Jul 18 05:26:09 PM PDT 24
Peak memory 205412 kb
Host smart-8a1ad303-15f5-4570-a861-fcfa79760b1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535210353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1535210353
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.234165588
Short name T1040
Test name
Test status
Simulation time 160643392 ps
CPU time 1.27 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:07 PM PDT 24
Peak memory 205452 kb
Host smart-61e26605-bc17-452a-b893-cfc74faa7507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234165588 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.234165588
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.2213293785
Short name T471
Test name
Test status
Simulation time 905741479 ps
CPU time 1.4 seconds
Started Jul 18 05:26:05 PM PDT 24
Finished Jul 18 05:26:10 PM PDT 24
Peak memory 205440 kb
Host smart-e6770174-f98f-4ddd-93a6-c7daadb10bf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213293785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.2213293785
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1397046820
Short name T1691
Test name
Test status
Simulation time 629190494 ps
CPU time 2.57 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:06 PM PDT 24
Peak memory 213884 kb
Host smart-8f90abf5-94dd-4c68-ac2a-dbad34369789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397046820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1397046820
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.2259805945
Short name T1365
Test name
Test status
Simulation time 4220811983 ps
CPU time 5.8 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 222040 kb
Host smart-02418037-0726-47cb-a158-856939a4923d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259805945 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.2259805945
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.975604278
Short name T1158
Test name
Test status
Simulation time 5159661103 ps
CPU time 48.72 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:55 PM PDT 24
Peak memory 1227884 kb
Host smart-59388030-5617-43d3-9093-4e29a698059e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975604278 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.975604278
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.576589947
Short name T1721
Test name
Test status
Simulation time 2288299242 ps
CPU time 3.01 seconds
Started Jul 18 05:26:00 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 213828 kb
Host smart-b81cb836-26da-4635-aecb-484b2abe8588
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576589947 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_nack_acqfull.576589947
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.567680363
Short name T882
Test name
Test status
Simulation time 2340179679 ps
CPU time 2.79 seconds
Started Jul 18 05:26:09 PM PDT 24
Finished Jul 18 05:26:14 PM PDT 24
Peak memory 205664 kb
Host smart-7d14db5a-f526-4761-87da-e45b8660a62b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567680363 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.567680363
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_txstretch.3608972434
Short name T1197
Test name
Test status
Simulation time 540224996 ps
CPU time 1.58 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:06 PM PDT 24
Peak memory 222580 kb
Host smart-005056d9-e7ab-4883-b7d7-62f73acd1655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608972434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_nack_txstretch.3608972434
Directory /workspace/0.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/0.i2c_target_perf.1481043082
Short name T584
Test name
Test status
Simulation time 468459796 ps
CPU time 4.14 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:09 PM PDT 24
Peak memory 213776 kb
Host smart-a13a1610-bd73-4d05-bdc8-3f74ad13f621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481043082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.1481043082
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.3663131925
Short name T1363
Test name
Test status
Simulation time 2223976283 ps
CPU time 2.5 seconds
Started Jul 18 05:26:07 PM PDT 24
Finished Jul 18 05:26:12 PM PDT 24
Peak memory 205404 kb
Host smart-b4fe59ea-64ce-4f18-9ea3-d8c7bea5c8e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663131925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_smbus_maxlen.3663131925
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2854287099
Short name T522
Test name
Test status
Simulation time 4589707861 ps
CPU time 17.33 seconds
Started Jul 18 05:26:01 PM PDT 24
Finished Jul 18 05:26:20 PM PDT 24
Peak memory 213896 kb
Host smart-c5ad1ae7-5be9-4680-a57d-0e83332b604c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854287099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2854287099
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.2610254040
Short name T251
Test name
Test status
Simulation time 10423888252 ps
CPU time 45.7 seconds
Started Jul 18 05:26:00 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 228988 kb
Host smart-e15a0cd2-0014-4500-b24a-e5fb4010e7c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610254040 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_stress_all.2610254040
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.2319034983
Short name T944
Test name
Test status
Simulation time 7176871739 ps
CPU time 26.22 seconds
Started Jul 18 05:26:04 PM PDT 24
Finished Jul 18 05:26:33 PM PDT 24
Peak memory 249720 kb
Host smart-92f02e73-25ed-486a-8863-738428a30741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319034983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.2319034983
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3444184161
Short name T692
Test name
Test status
Simulation time 69666790506 ps
CPU time 2712.67 seconds
Started Jul 18 05:26:01 PM PDT 24
Finished Jul 18 06:11:16 PM PDT 24
Peak memory 11007584 kb
Host smart-dfecc022-286b-458c-9a22-cb7b3a55170c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444184161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3444184161
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3310419631
Short name T436
Test name
Test status
Simulation time 4084992154 ps
CPU time 3.31 seconds
Started Jul 18 05:26:00 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 237816 kb
Host smart-5a1ca591-b58b-439f-a36f-12ff26083173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310419631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3310419631
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.243095548
Short name T519
Test name
Test status
Simulation time 5184904965 ps
CPU time 7.63 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:14 PM PDT 24
Peak memory 218424 kb
Host smart-13dc59bf-d16d-4fc1-9de1-e21d7ab0d8a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243095548 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.243095548
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.2064638289
Short name T1598
Test name
Test status
Simulation time 427334820 ps
CPU time 5.75 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 213808 kb
Host smart-a3018bea-2953-4c2d-83dd-6be8220fa71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064638289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.2064638289
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1530302345
Short name T1096
Test name
Test status
Simulation time 487903279 ps
CPU time 3.39 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:09 PM PDT 24
Peak memory 205592 kb
Host smart-9983c208-54fe-43e8-93b4-a66764254768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530302345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1530302345
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3806761400
Short name T707
Test name
Test status
Simulation time 934980246 ps
CPU time 9.32 seconds
Started Jul 18 05:26:07 PM PDT 24
Finished Jul 18 05:26:20 PM PDT 24
Peak memory 308368 kb
Host smart-0d48a3e6-7e2f-41f9-9bb7-133b0648c0b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806761400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3806761400
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.576398035
Short name T506
Test name
Test status
Simulation time 4672602386 ps
CPU time 181.32 seconds
Started Jul 18 05:26:07 PM PDT 24
Finished Jul 18 05:29:12 PM PDT 24
Peak memory 765572 kb
Host smart-5c42c889-6209-4687-914b-188507e974a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576398035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.576398035
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.943524751
Short name T1338
Test name
Test status
Simulation time 176867327 ps
CPU time 1.26 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 205252 kb
Host smart-92986527-f6c3-4394-a1ee-2c1887479d4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943524751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt
.943524751
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.667087266
Short name T494
Test name
Test status
Simulation time 169484669 ps
CPU time 3.65 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:12 PM PDT 24
Peak memory 205496 kb
Host smart-08696daa-d076-4b39-b905-de0691c29ca8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667087266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.667087266
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.545857958
Short name T1605
Test name
Test status
Simulation time 20534751555 ps
CPU time 376.45 seconds
Started Jul 18 05:26:07 PM PDT 24
Finished Jul 18 05:32:27 PM PDT 24
Peak memory 1463184 kb
Host smart-ae8b756a-c621-4b43-b521-881300fc0edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545857958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.545857958
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.2058992285
Short name T230
Test name
Test status
Simulation time 553009697 ps
CPU time 8.6 seconds
Started Jul 18 05:26:15 PM PDT 24
Finished Jul 18 05:26:24 PM PDT 24
Peak memory 205568 kb
Host smart-2b7e2d87-16e0-4ad1-b8aa-accd52de442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058992285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2058992285
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.2541568364
Short name T117
Test name
Test status
Simulation time 58467787 ps
CPU time 0.75 seconds
Started Jul 18 05:26:09 PM PDT 24
Finished Jul 18 05:26:12 PM PDT 24
Peak memory 205200 kb
Host smart-a8bebc34-18f5-4258-8227-a74f147d9151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541568364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2541568364
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3383937800
Short name T495
Test name
Test status
Simulation time 989292968 ps
CPU time 17.08 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:27 PM PDT 24
Peak memory 363884 kb
Host smart-302c47ac-4fb1-4cd3-8669-3ace0a8c6bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383937800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3383937800
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.332331374
Short name T901
Test name
Test status
Simulation time 2559903105 ps
CPU time 26.67 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:36 PM PDT 24
Peak memory 501984 kb
Host smart-11899f46-06d7-4688-8982-8dbcb63683f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332331374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.332331374
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.1132822518
Short name T1030
Test name
Test status
Simulation time 1355387107 ps
CPU time 62.35 seconds
Started Jul 18 05:26:09 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 301404 kb
Host smart-3fab4d7f-05bc-46ef-85f5-c9e90fede0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132822518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1132822518
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2818263579
Short name T1751
Test name
Test status
Simulation time 3627125965 ps
CPU time 12.56 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:22 PM PDT 24
Peak memory 231792 kb
Host smart-b2cc0c75-ef94-4c14-a3d8-7b9962abe50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818263579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2818263579
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2268895817
Short name T171
Test name
Test status
Simulation time 128796907 ps
CPU time 0.98 seconds
Started Jul 18 05:26:20 PM PDT 24
Finished Jul 18 05:26:24 PM PDT 24
Peak memory 224152 kb
Host smart-5551d783-28d3-48d0-970e-4cc766b7ed8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268895817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2268895817
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3108115715
Short name T1532
Test name
Test status
Simulation time 2156324364 ps
CPU time 5 seconds
Started Jul 18 05:26:15 PM PDT 24
Finished Jul 18 05:26:21 PM PDT 24
Peak memory 213964 kb
Host smart-7bed8546-5e08-413c-b455-66042197a24e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108115715 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3108115715
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1028708775
Short name T1549
Test name
Test status
Simulation time 252800536 ps
CPU time 1.59 seconds
Started Jul 18 05:26:07 PM PDT 24
Finished Jul 18 05:26:12 PM PDT 24
Peak memory 207368 kb
Host smart-edace287-a2e5-4c73-b5b4-3e1fa232bda3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028708775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1028708775
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2081135453
Short name T1033
Test name
Test status
Simulation time 787252869 ps
CPU time 1.8 seconds
Started Jul 18 05:26:20 PM PDT 24
Finished Jul 18 05:26:25 PM PDT 24
Peak memory 205696 kb
Host smart-bdfa4d92-1722-42ca-ac97-9559a7697c41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081135453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2081135453
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.682548582
Short name T319
Test name
Test status
Simulation time 748812125 ps
CPU time 3.53 seconds
Started Jul 18 05:26:15 PM PDT 24
Finished Jul 18 05:26:20 PM PDT 24
Peak memory 213808 kb
Host smart-eec7f72d-b90b-4fde-b144-0f54555d47d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682548582 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.682548582
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.1574016646
Short name T332
Test name
Test status
Simulation time 113452191 ps
CPU time 1.48 seconds
Started Jul 18 05:26:19 PM PDT 24
Finished Jul 18 05:26:22 PM PDT 24
Peak memory 205468 kb
Host smart-7f377060-99f9-4704-8e9e-d05b4edae9dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574016646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.1574016646
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2664257785
Short name T943
Test name
Test status
Simulation time 2249649937 ps
CPU time 6.54 seconds
Started Jul 18 05:26:07 PM PDT 24
Finished Jul 18 05:26:16 PM PDT 24
Peak memory 222060 kb
Host smart-9193e416-19d9-42dc-b98f-7e193a9e20ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664257785 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2664257785
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.834279107
Short name T1438
Test name
Test status
Simulation time 31771959649 ps
CPU time 20.17 seconds
Started Jul 18 05:26:04 PM PDT 24
Finished Jul 18 05:26:27 PM PDT 24
Peak memory 538952 kb
Host smart-6e2c703e-bfea-46bf-9621-54eca5dacbb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834279107 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.834279107
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.1161992762
Short name T981
Test name
Test status
Simulation time 1450297729 ps
CPU time 2.54 seconds
Started Jul 18 05:26:19 PM PDT 24
Finished Jul 18 05:26:23 PM PDT 24
Peak memory 213928 kb
Host smart-596d4e0f-242c-4bd8-bf54-35dd650aeb04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161992762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_nack_acqfull.1161992762
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.181001935
Short name T1136
Test name
Test status
Simulation time 1742701654 ps
CPU time 2.32 seconds
Started Jul 18 05:26:24 PM PDT 24
Finished Jul 18 05:26:31 PM PDT 24
Peak memory 205604 kb
Host smart-96546e7e-f9ee-4a4b-b4d9-c39cd85af2cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181001935 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.181001935
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.1013755726
Short name T693
Test name
Test status
Simulation time 1440283615 ps
CPU time 5.33 seconds
Started Jul 18 05:26:17 PM PDT 24
Finished Jul 18 05:26:23 PM PDT 24
Peak memory 213868 kb
Host smart-71df290d-8bc3-4d88-9e55-d414e5d81b3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013755726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.1013755726
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.666947094
Short name T1329
Test name
Test status
Simulation time 2475088577 ps
CPU time 2.32 seconds
Started Jul 18 05:26:17 PM PDT 24
Finished Jul 18 05:26:20 PM PDT 24
Peak memory 205440 kb
Host smart-5f67777c-604c-4bea-ae59-2866deaad1ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666947094 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_smbus_maxlen.666947094
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3163714270
Short name T302
Test name
Test status
Simulation time 1673504175 ps
CPU time 21.1 seconds
Started Jul 18 05:26:09 PM PDT 24
Finished Jul 18 05:26:32 PM PDT 24
Peak memory 213856 kb
Host smart-cf449aa1-1032-4253-bb6b-7317ac2f3a62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163714270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3163714270
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.2377703154
Short name T1125
Test name
Test status
Simulation time 31177596973 ps
CPU time 26.76 seconds
Started Jul 18 05:26:15 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 246836 kb
Host smart-c8dd285f-d26a-4162-bab4-0ba288971c88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377703154 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.2377703154
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1034584982
Short name T313
Test name
Test status
Simulation time 2438900992 ps
CPU time 5.16 seconds
Started Jul 18 05:26:09 PM PDT 24
Finished Jul 18 05:26:16 PM PDT 24
Peak memory 205656 kb
Host smart-659bae5e-42f1-4f15-8d71-f3a7b5fb2f93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034584982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1034584982
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3293430170
Short name T147
Test name
Test status
Simulation time 22221379111 ps
CPU time 13.23 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:22 PM PDT 24
Peak memory 205708 kb
Host smart-b97d6100-7483-4b19-8652-32d862a5d761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293430170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3293430170
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1891866362
Short name T1076
Test name
Test status
Simulation time 339764265 ps
CPU time 1.23 seconds
Started Jul 18 05:26:05 PM PDT 24
Finished Jul 18 05:26:09 PM PDT 24
Peak memory 205528 kb
Host smart-86d8f6f0-7c2b-4436-9181-ec9166a1d4ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891866362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1891866362
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.3970970965
Short name T1607
Test name
Test status
Simulation time 1345887607 ps
CPU time 7.06 seconds
Started Jul 18 05:26:07 PM PDT 24
Finished Jul 18 05:26:17 PM PDT 24
Peak memory 222040 kb
Host smart-1a394dc3-8b4b-4694-9651-d7314f9bdc01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970970965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.3970970965
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.618129258
Short name T450
Test name
Test status
Simulation time 16816624 ps
CPU time 0.64 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:38 PM PDT 24
Peak memory 204844 kb
Host smart-20e1718a-b401-4ca9-b812-d9c5b6fa52e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618129258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.618129258
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.840443611
Short name T827
Test name
Test status
Simulation time 239732000 ps
CPU time 1.68 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:27:31 PM PDT 24
Peak memory 213788 kb
Host smart-451302c6-e4ff-469f-acda-eded07540099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840443611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.840443611
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1615912371
Short name T284
Test name
Test status
Simulation time 652511335 ps
CPU time 6.86 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:27:40 PM PDT 24
Peak memory 229852 kb
Host smart-77deb4a3-afcb-4e9c-8801-8bd06fb8702b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615912371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1615912371
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2748653050
Short name T484
Test name
Test status
Simulation time 2733012520 ps
CPU time 184.86 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:30:33 PM PDT 24
Peak memory 586468 kb
Host smart-83e16e5d-1fb8-4a1e-ad5d-d13d9d18c335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748653050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2748653050
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.817273757
Short name T907
Test name
Test status
Simulation time 1260977133 ps
CPU time 77.54 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:28:53 PM PDT 24
Peak memory 474768 kb
Host smart-70f3e270-33ae-45bb-9216-45aee3bbc425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817273757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.817273757
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3943285748
Short name T1587
Test name
Test status
Simulation time 141679662 ps
CPU time 1.21 seconds
Started Jul 18 05:27:36 PM PDT 24
Finished Jul 18 05:27:41 PM PDT 24
Peak memory 205224 kb
Host smart-7c1fbf81-2d3b-48cf-a921-306764d8f475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943285748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3943285748
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3575679217
Short name T1670
Test name
Test status
Simulation time 655254937 ps
CPU time 5.23 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:41 PM PDT 24
Peak memory 238480 kb
Host smart-79cfff01-40f0-47dd-aa45-3f62594789ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575679217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3575679217
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3109161621
Short name T1515
Test name
Test status
Simulation time 5193569097 ps
CPU time 396.48 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:34:11 PM PDT 24
Peak memory 1528600 kb
Host smart-51aade0d-fbc1-48fe-8d88-504d3b328524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109161621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3109161621
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.3218531359
Short name T1559
Test name
Test status
Simulation time 564539692 ps
CPU time 22.15 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 205512 kb
Host smart-73478050-986b-4b49-bf51-5476e3c7f95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218531359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.3218531359
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_override.4239832080
Short name T849
Test name
Test status
Simulation time 24449008 ps
CPU time 0.7 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:27:29 PM PDT 24
Peak memory 205444 kb
Host smart-cee01b3b-dfe2-4c0b-9398-b1e98013ff91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239832080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.4239832080
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.2164302808
Short name T1542
Test name
Test status
Simulation time 4598840404 ps
CPU time 130.59 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:29:46 PM PDT 24
Peak memory 619816 kb
Host smart-a86884c1-ec20-4b9e-8bfe-3e0cb21eac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164302808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2164302808
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.1730107575
Short name T1432
Test name
Test status
Simulation time 98993097 ps
CPU time 1.06 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:35 PM PDT 24
Peak memory 222952 kb
Host smart-8887c8c6-5f4b-4143-b479-113ca2852336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730107575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1730107575
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.64149399
Short name T300
Test name
Test status
Simulation time 2379262311 ps
CPU time 24.86 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:27:58 PM PDT 24
Peak memory 348636 kb
Host smart-545a6bbd-a7d0-40ce-afd2-19803d2593fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64149399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.64149399
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1916523746
Short name T257
Test name
Test status
Simulation time 10377236229 ps
CPU time 493.07 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:35:50 PM PDT 24
Peak memory 1929532 kb
Host smart-13d6982b-40a8-43a2-9fa8-59cb04ee4edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916523746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1916523746
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.957355712
Short name T1019
Test name
Test status
Simulation time 899576458 ps
CPU time 18.92 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:53 PM PDT 24
Peak memory 213744 kb
Host smart-14dc005d-4830-427f-bf0c-26a57ae610b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957355712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.957355712
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.4140697555
Short name T489
Test name
Test status
Simulation time 658566146 ps
CPU time 4.05 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:38 PM PDT 24
Peak memory 216508 kb
Host smart-2eec9465-9aaf-4bac-9602-0d2fc9fa1f3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140697555 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.4140697555
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3987931584
Short name T1253
Test name
Test status
Simulation time 492318842 ps
CPU time 1.1 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:37 PM PDT 24
Peak memory 205428 kb
Host smart-8d79309d-c1c3-42f5-9a44-ddea1d1660bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987931584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3987931584
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.583463575
Short name T1160
Test name
Test status
Simulation time 302745178 ps
CPU time 0.86 seconds
Started Jul 18 05:27:29 PM PDT 24
Finished Jul 18 05:27:32 PM PDT 24
Peak memory 205356 kb
Host smart-585623cc-074a-44a6-9318-1d5f8b1a3e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583463575 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.583463575
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.2652355496
Short name T850
Test name
Test status
Simulation time 890100610 ps
CPU time 2.62 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:40 PM PDT 24
Peak memory 205592 kb
Host smart-18752f2f-09d4-4784-bb54-66c32b66b497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652355496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.2652355496
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2487301196
Short name T158
Test name
Test status
Simulation time 169651659 ps
CPU time 1.34 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:39 PM PDT 24
Peak memory 205428 kb
Host smart-b31fe26a-d337-4305-ac88-00e9b99a892c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487301196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2487301196
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1257364797
Short name T880
Test name
Test status
Simulation time 5323301217 ps
CPU time 8.04 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:27:36 PM PDT 24
Peak memory 222072 kb
Host smart-878459c9-bb72-4a55-84d1-c2b50ed01792
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257364797 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1257364797
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1844259837
Short name T852
Test name
Test status
Simulation time 15717717756 ps
CPU time 99.82 seconds
Started Jul 18 05:27:29 PM PDT 24
Finished Jul 18 05:29:11 PM PDT 24
Peak memory 1941972 kb
Host smart-99431d62-d28f-4a50-8547-422ed2aa90c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844259837 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1844259837
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.967474033
Short name T1141
Test name
Test status
Simulation time 2000492805 ps
CPU time 2.78 seconds
Started Jul 18 05:27:37 PM PDT 24
Finished Jul 18 05:27:43 PM PDT 24
Peak memory 213888 kb
Host smart-fc589713-b401-4683-a75e-4499ad11ef91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967474033 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_nack_acqfull.967474033
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.4255179596
Short name T863
Test name
Test status
Simulation time 1247000490 ps
CPU time 3.02 seconds
Started Jul 18 05:27:37 PM PDT 24
Finished Jul 18 05:27:43 PM PDT 24
Peak memory 205784 kb
Host smart-43ee6854-ee7b-4c94-90d8-404b343553aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255179596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.4255179596
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_txstretch.3014872304
Short name T611
Test name
Test status
Simulation time 922015831 ps
CPU time 1.33 seconds
Started Jul 18 05:27:37 PM PDT 24
Finished Jul 18 05:27:42 PM PDT 24
Peak memory 222420 kb
Host smart-18847d27-b140-4644-bb0c-a9783e9015bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014872304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_nack_txstretch.3014872304
Directory /workspace/10.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/10.i2c_target_perf.1320864431
Short name T1540
Test name
Test status
Simulation time 1109834085 ps
CPU time 5.8 seconds
Started Jul 18 05:27:25 PM PDT 24
Finished Jul 18 05:27:31 PM PDT 24
Peak memory 220668 kb
Host smart-228211a4-f793-43e3-813f-1e059c3b454f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320864431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.1320864431
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.496833149
Short name T1231
Test name
Test status
Simulation time 2789672366 ps
CPU time 2.03 seconds
Started Jul 18 05:27:36 PM PDT 24
Finished Jul 18 05:27:42 PM PDT 24
Peak memory 205508 kb
Host smart-1898ccfb-355c-467f-9c3b-c808f7e7e149
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496833149 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_smbus_maxlen.496833149
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2775698189
Short name T75
Test name
Test status
Simulation time 2788665388 ps
CPU time 22.64 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 222104 kb
Host smart-a789bf1f-7172-4259-9f7f-a417d014cf0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775698189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2775698189
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2306767563
Short name T842
Test name
Test status
Simulation time 3002763312 ps
CPU time 65.35 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:28:38 PM PDT 24
Peak memory 218048 kb
Host smart-1e784fa2-c2f7-48de-8402-6d8b97065d06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306767563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2306767563
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.4003371181
Short name T428
Test name
Test status
Simulation time 46115687110 ps
CPU time 325.13 seconds
Started Jul 18 05:27:28 PM PDT 24
Finished Jul 18 05:32:55 PM PDT 24
Peak memory 3166856 kb
Host smart-5c451c04-a0f7-4937-936c-5e82762b0e3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003371181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.4003371181
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.265439945
Short name T1296
Test name
Test status
Simulation time 454420144 ps
CPU time 1.61 seconds
Started Jul 18 05:27:26 PM PDT 24
Finished Jul 18 05:27:29 PM PDT 24
Peak memory 205456 kb
Host smart-89a1ba1d-2248-46f7-8d61-d21ea1c9652f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265439945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.265439945
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2508195160
Short name T324
Test name
Test status
Simulation time 2249729403 ps
CPU time 6.35 seconds
Started Jul 18 05:27:25 PM PDT 24
Finished Jul 18 05:27:32 PM PDT 24
Peak memory 214032 kb
Host smart-360b5473-0204-42d9-b4f8-5347019401fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508195160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2508195160
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.3854125181
Short name T743
Test name
Test status
Simulation time 65868119 ps
CPU time 1.63 seconds
Started Jul 18 05:27:35 PM PDT 24
Finished Jul 18 05:27:40 PM PDT 24
Peak memory 205656 kb
Host smart-62e41254-0a17-48d0-b37e-efde3a3c939a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854125181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.3854125181
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.239303389
Short name T314
Test name
Test status
Simulation time 37816815 ps
CPU time 0.62 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:39 PM PDT 24
Peak memory 204760 kb
Host smart-75344cba-914c-498e-b6fc-a200b542d146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239303389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.239303389
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.3113956050
Short name T804
Test name
Test status
Simulation time 313881605 ps
CPU time 5.98 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:27:51 PM PDT 24
Peak memory 229648 kb
Host smart-d669ffb2-335a-4f68-a681-a934de124c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113956050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.3113956050
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.149932237
Short name T535
Test name
Test status
Simulation time 1122064761 ps
CPU time 17.75 seconds
Started Jul 18 05:27:38 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 278924 kb
Host smart-c6265fbc-d885-48fc-bc18-4d1bca210491
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149932237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.149932237
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.850185121
Short name T792
Test name
Test status
Simulation time 31647910338 ps
CPU time 168.24 seconds
Started Jul 18 05:27:37 PM PDT 24
Finished Jul 18 05:30:29 PM PDT 24
Peak memory 464732 kb
Host smart-5b3a7f39-6590-43d1-9ec1-cde25f73976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850185121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.850185121
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.5095051
Short name T691
Test name
Test status
Simulation time 5771665489 ps
CPU time 106.76 seconds
Started Jul 18 05:27:38 PM PDT 24
Finished Jul 18 05:29:29 PM PDT 24
Peak memory 541004 kb
Host smart-eef28b15-f6cc-4937-ad79-20891f112ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5095051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.5095051
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.834779392
Short name T1708
Test name
Test status
Simulation time 54241131 ps
CPU time 0.84 seconds
Started Jul 18 05:27:38 PM PDT 24
Finished Jul 18 05:27:42 PM PDT 24
Peak memory 204840 kb
Host smart-1c43ecbe-4d1a-4587-8a85-8c657cf20d60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834779392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.834779392
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3618295944
Short name T479
Test name
Test status
Simulation time 728604754 ps
CPU time 3.14 seconds
Started Jul 18 05:27:38 PM PDT 24
Finished Jul 18 05:27:45 PM PDT 24
Peak memory 222136 kb
Host smart-a2fce8b9-d6c5-46b2-baf7-05d9cf11cc9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618295944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3618295944
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3772818881
Short name T1087
Test name
Test status
Simulation time 4790280905 ps
CPU time 357.84 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:33:36 PM PDT 24
Peak memory 1367216 kb
Host smart-b51800e1-f44a-4412-bead-035aee6c0105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772818881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3772818881
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2667254322
Short name T1732
Test name
Test status
Simulation time 325517212 ps
CPU time 13.09 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:27:42 PM PDT 24
Peak memory 205464 kb
Host smart-49e41948-a910-4a82-bbee-60a9e3b97761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667254322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2667254322
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.1130371154
Short name T1654
Test name
Test status
Simulation time 125628212 ps
CPU time 4.56 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:39 PM PDT 24
Peak memory 213724 kb
Host smart-877a5093-9f76-440f-a3a3-9f38a24a4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130371154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.1130371154
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.1896510380
Short name T656
Test name
Test status
Simulation time 17324128 ps
CPU time 0.67 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:39 PM PDT 24
Peak memory 205204 kb
Host smart-cd0ad929-afdc-489b-a59b-db1df9d38a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896510380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1896510380
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2367171728
Short name T1214
Test name
Test status
Simulation time 12800138001 ps
CPU time 216.07 seconds
Started Jul 18 05:27:39 PM PDT 24
Finished Jul 18 05:31:19 PM PDT 24
Peak memory 1666916 kb
Host smart-4283e2bc-b0c8-4f2c-9e32-c0325bc9783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367171728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2367171728
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.4147545073
Short name T1451
Test name
Test status
Simulation time 272722192 ps
CPU time 2.13 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:38 PM PDT 24
Peak memory 223328 kb
Host smart-d4a64f6a-d64c-4670-9743-28b3f5792dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147545073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.4147545073
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.171743227
Short name T121
Test name
Test status
Simulation time 1095018720 ps
CPU time 20.73 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 324176 kb
Host smart-a56e0f87-e8da-4e10-ae9d-4b4086d21694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171743227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.171743227
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3787124587
Short name T485
Test name
Test status
Simulation time 1261496784 ps
CPU time 28.92 seconds
Started Jul 18 05:27:39 PM PDT 24
Finished Jul 18 05:28:12 PM PDT 24
Peak memory 213720 kb
Host smart-a2e93634-3b8a-4a8b-9ee1-83b9d84bf7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787124587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3787124587
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.589802464
Short name T860
Test name
Test status
Simulation time 773103100 ps
CPU time 4.14 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:39 PM PDT 24
Peak memory 217220 kb
Host smart-e62a78c1-c86d-4f60-b88e-0acb986bb1a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589802464 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.589802464
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2241888783
Short name T1066
Test name
Test status
Simulation time 594680928 ps
CPU time 1.34 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:27:30 PM PDT 24
Peak memory 205684 kb
Host smart-a942c166-98cc-461d-b99a-a5232910d2b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241888783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2241888783
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.71560369
Short name T735
Test name
Test status
Simulation time 298325180 ps
CPU time 0.89 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:36 PM PDT 24
Peak memory 205440 kb
Host smart-3d9e2a49-bf95-4065-b451-09be51d9e0de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71560369 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_fifo_reset_tx.71560369
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.3134288349
Short name T323
Test name
Test status
Simulation time 1131688921 ps
CPU time 3.24 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:39 PM PDT 24
Peak memory 205576 kb
Host smart-3ec80550-efbc-4777-bed4-5df2ccd8ebaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134288349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.3134288349
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.1652668345
Short name T873
Test name
Test status
Simulation time 469373932 ps
CPU time 1.04 seconds
Started Jul 18 05:27:28 PM PDT 24
Finished Jul 18 05:27:31 PM PDT 24
Peak memory 205396 kb
Host smart-328b96e5-3609-4baf-8b53-84fbb2fd4eee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652668345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.1652668345
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3386622231
Short name T1369
Test name
Test status
Simulation time 1013801603 ps
CPU time 6.87 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:27:53 PM PDT 24
Peak memory 222012 kb
Host smart-049f84f7-734d-4e54-a75f-aa3f5afc5d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386622231 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3386622231
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1511842923
Short name T1359
Test name
Test status
Simulation time 16011473554 ps
CPU time 359.75 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:33:45 PM PDT 24
Peak memory 3977680 kb
Host smart-aec0c803-a8b8-4110-b095-3a05a3b7f52a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511842923 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1511842923
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.4190808621
Short name T469
Test name
Test status
Simulation time 2714478130 ps
CPU time 3.02 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:39 PM PDT 24
Peak memory 213908 kb
Host smart-62ec6dd5-f47b-4d40-93df-855a78c00d72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190808621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_nack_acqfull.4190808621
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.3984220746
Short name T1027
Test name
Test status
Simulation time 2215119365 ps
CPU time 2.89 seconds
Started Jul 18 05:27:29 PM PDT 24
Finished Jul 18 05:27:34 PM PDT 24
Peak memory 205620 kb
Host smart-8b93d214-ac48-4998-910b-6c748c36a89e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984220746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.3984220746
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_txstretch.2029969516
Short name T835
Test name
Test status
Simulation time 548487394 ps
CPU time 1.42 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:27:33 PM PDT 24
Peak memory 222212 kb
Host smart-1895a6c7-f966-4ba8-a555-f40ccc9356b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029969516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_nack_txstretch.2029969516
Directory /workspace/11.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/11.i2c_target_perf.948242208
Short name T1384
Test name
Test status
Simulation time 669354456 ps
CPU time 4.99 seconds
Started Jul 18 05:27:28 PM PDT 24
Finished Jul 18 05:27:35 PM PDT 24
Peak memory 221992 kb
Host smart-6ceea88e-59d3-466a-8649-1c95d15f31cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948242208 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_perf.948242208
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.1108972862
Short name T1207
Test name
Test status
Simulation time 9546649660 ps
CPU time 2.39 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:37 PM PDT 24
Peak memory 205468 kb
Host smart-79f6b147-4f7e-4503-a63f-385f56fb40af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108972862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_smbus_maxlen.1108972862
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.4108573147
Short name T1036
Test name
Test status
Simulation time 5189770935 ps
CPU time 15.1 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 213916 kb
Host smart-94407414-1217-44f7-93a5-368eb0ee20ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108573147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.4108573147
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.4160130936
Short name T1350
Test name
Test status
Simulation time 14934669401 ps
CPU time 34.7 seconds
Started Jul 18 05:27:28 PM PDT 24
Finished Jul 18 05:28:05 PM PDT 24
Peak memory 270948 kb
Host smart-aa0b8531-3e77-48fc-8853-2b31f505d680
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160130936 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_stress_all.4160130936
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.609816001
Short name T854
Test name
Test status
Simulation time 771070453 ps
CPU time 14.37 seconds
Started Jul 18 05:27:40 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 215804 kb
Host smart-2bdce882-56d9-4bd5-810e-f08cb3513f64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609816001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.609816001
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1897922202
Short name T1446
Test name
Test status
Simulation time 14810082570 ps
CPU time 30.82 seconds
Started Jul 18 05:27:40 PM PDT 24
Finished Jul 18 05:28:15 PM PDT 24
Peak memory 205700 kb
Host smart-c1f58293-6613-488f-afc8-729468b7c3a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897922202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1897922202
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3423900142
Short name T66
Test name
Test status
Simulation time 215290258 ps
CPU time 1.4 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:27:47 PM PDT 24
Peak memory 205556 kb
Host smart-d6deb8b6-3636-49a8-8046-d1c85bfbb2d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423900142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3423900142
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.376964374
Short name T556
Test name
Test status
Simulation time 4636624488 ps
CPU time 6.78 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:27:52 PM PDT 24
Peak memory 222060 kb
Host smart-b75a80d6-fe2e-4963-a5d2-30fa5c829a51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376964374 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.376964374
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.492953645
Short name T1715
Test name
Test status
Simulation time 186800385 ps
CPU time 3.12 seconds
Started Jul 18 05:27:29 PM PDT 24
Finished Jul 18 05:27:34 PM PDT 24
Peak memory 205508 kb
Host smart-7ae424d1-08e1-46ef-9112-fe46b544ac83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492953645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.492953645
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.705345545
Short name T8
Test name
Test status
Simulation time 16232832 ps
CPU time 0.62 seconds
Started Jul 18 05:27:28 PM PDT 24
Finished Jul 18 05:27:31 PM PDT 24
Peak memory 205184 kb
Host smart-d06a5daa-8627-47d9-9395-18e6b71a6e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705345545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.705345545
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.167946862
Short name T1007
Test name
Test status
Simulation time 295081139 ps
CPU time 2.57 seconds
Started Jul 18 05:27:35 PM PDT 24
Finished Jul 18 05:27:42 PM PDT 24
Peak memory 222576 kb
Host smart-13a6baeb-55da-4552-882c-411833a0faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167946862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.167946862
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2430936190
Short name T1005
Test name
Test status
Simulation time 492364923 ps
CPU time 8.81 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:27:41 PM PDT 24
Peak memory 298460 kb
Host smart-1d612543-f96d-4524-bc4a-0e7c19bef909
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430936190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2430936190
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.6264403
Short name T22
Test name
Test status
Simulation time 2824439085 ps
CPU time 103.62 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:29:30 PM PDT 24
Peak memory 734460 kb
Host smart-e38333b5-7d63-4878-8e26-48d66e81f293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6264403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.6264403
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2810855159
Short name T683
Test name
Test status
Simulation time 2163786403 ps
CPU time 60.38 seconds
Started Jul 18 05:27:35 PM PDT 24
Finished Jul 18 05:28:40 PM PDT 24
Peak memory 650092 kb
Host smart-fe7d5b35-56f8-4999-a77d-760fceef84da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810855159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2810855159
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3747381201
Short name T512
Test name
Test status
Simulation time 365951552 ps
CPU time 1.06 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:37 PM PDT 24
Peak memory 205204 kb
Host smart-b1a80b5e-df98-466d-a50d-08a008964836
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747381201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3747381201
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2115659687
Short name T968
Test name
Test status
Simulation time 773717095 ps
CPU time 5.08 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:40 PM PDT 24
Peak memory 205448 kb
Host smart-cccc8c7a-3aaa-4635-8467-2a9959857934
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115659687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2115659687
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.3714654241
Short name T1097
Test name
Test status
Simulation time 4468164022 ps
CPU time 124.71 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:29:42 PM PDT 24
Peak memory 1212696 kb
Host smart-420f5587-1146-4953-8b50-4147aa2957a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714654241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3714654241
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.226621143
Short name T1539
Test name
Test status
Simulation time 138862588 ps
CPU time 1.99 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 205500 kb
Host smart-18412708-2507-45e5-a3a9-941ad1702988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226621143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.226621143
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.2294563103
Short name T1034
Test name
Test status
Simulation time 41843539 ps
CPU time 0.65 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:37 PM PDT 24
Peak memory 205200 kb
Host smart-ceea0f95-46c5-4378-b09d-4bc343c685f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294563103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2294563103
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3037467673
Short name T687
Test name
Test status
Simulation time 8149516308 ps
CPU time 83.13 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:29:08 PM PDT 24
Peak memory 205948 kb
Host smart-006abcea-1e66-4c5b-8d8c-619b38a2ba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037467673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3037467673
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.2941323854
Short name T543
Test name
Test status
Simulation time 585186252 ps
CPU time 4.61 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:27:51 PM PDT 24
Peak memory 205400 kb
Host smart-c339c049-c19c-4895-be0d-d35d18c8e157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941323854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.2941323854
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3472235164
Short name T1469
Test name
Test status
Simulation time 20983960969 ps
CPU time 73.21 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:28:50 PM PDT 24
Peak memory 342648 kb
Host smart-1400c926-ddad-401e-ac96-bce130c55106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472235164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3472235164
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1793703450
Short name T1375
Test name
Test status
Simulation time 2287497140 ps
CPU time 9.62 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 221980 kb
Host smart-2ea35f0f-99a3-40fb-897a-15099e872ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793703450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1793703450
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3187457274
Short name T1240
Test name
Test status
Simulation time 552782790 ps
CPU time 3.39 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:40 PM PDT 24
Peak memory 216616 kb
Host smart-57647976-e2c2-43ba-bcda-f1ef13905196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187457274 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3187457274
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1541113420
Short name T511
Test name
Test status
Simulation time 158606639 ps
CPU time 1.08 seconds
Started Jul 18 05:27:37 PM PDT 24
Finished Jul 18 05:27:42 PM PDT 24
Peak memory 205324 kb
Host smart-0cc60b6c-ce76-4f81-8eed-c4b74fa0fa58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541113420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1541113420
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.1622247845
Short name T1651
Test name
Test status
Simulation time 174557397 ps
CPU time 0.89 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:38 PM PDT 24
Peak memory 213572 kb
Host smart-809e2b61-49d1-46dd-bfe8-190a9c544a8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622247845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.1622247845
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.2563517248
Short name T307
Test name
Test status
Simulation time 899191618 ps
CPU time 1.79 seconds
Started Jul 18 05:27:39 PM PDT 24
Finished Jul 18 05:27:45 PM PDT 24
Peak memory 205388 kb
Host smart-db8eaad1-74de-4e8a-a206-33a0a4c858cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563517248 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.2563517248
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.2865054405
Short name T920
Test name
Test status
Simulation time 188717103 ps
CPU time 1.35 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:36 PM PDT 24
Peak memory 205476 kb
Host smart-c3c5b088-b68b-4e02-9448-99c18aa2b01e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865054405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.2865054405
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3597764783
Short name T1191
Test name
Test status
Simulation time 1331193566 ps
CPU time 2.92 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 213832 kb
Host smart-a6c1d8ec-ea59-46cf-8294-c814019cac44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597764783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3597764783
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.2703973431
Short name T431
Test name
Test status
Simulation time 1028817395 ps
CPU time 5.07 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:43 PM PDT 24
Peak memory 215756 kb
Host smart-ac7f07ee-6b18-4ac4-b16c-8aa5b0e19f77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703973431 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.2703973431
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3919082636
Short name T729
Test name
Test status
Simulation time 16026667541 ps
CPU time 382.97 seconds
Started Jul 18 05:27:37 PM PDT 24
Finished Jul 18 05:34:04 PM PDT 24
Peak memory 3941776 kb
Host smart-5534cdd3-f606-43b5-b431-d8eb068aaef7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919082636 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3919082636
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.2848041556
Short name T1364
Test name
Test status
Simulation time 3865048344 ps
CPU time 2.61 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 213912 kb
Host smart-c55bbbaa-b603-4a5d-aae4-98b3e201b56d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848041556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_acqfull.2848041556
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.3007449899
Short name T1753
Test name
Test status
Simulation time 2249290396 ps
CPU time 2.91 seconds
Started Jul 18 05:27:40 PM PDT 24
Finished Jul 18 05:27:47 PM PDT 24
Peak memory 205716 kb
Host smart-96cff532-f482-4320-8721-325420972f30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007449899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.3007449899
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_txstretch.3000527604
Short name T1163
Test name
Test status
Simulation time 139444039 ps
CPU time 1.38 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 221020 kb
Host smart-29fb2830-0d75-4b63-803f-98e42af7d354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000527604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_nack_txstretch.3000527604
Directory /workspace/12.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/12.i2c_target_perf.947354741
Short name T1594
Test name
Test status
Simulation time 3521390016 ps
CPU time 4.5 seconds
Started Jul 18 05:27:38 PM PDT 24
Finished Jul 18 05:27:46 PM PDT 24
Peak memory 219428 kb
Host smart-68b26a57-39ae-40bb-956e-0d4eec4e1540
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947354741 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_perf.947354741
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.1329187243
Short name T776
Test name
Test status
Simulation time 2195746989 ps
CPU time 2.44 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 205508 kb
Host smart-1ec4b909-4795-42f7-a277-df695950920d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329187243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.1329187243
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3479672592
Short name T909
Test name
Test status
Simulation time 1981817684 ps
CPU time 26.27 seconds
Started Jul 18 05:27:37 PM PDT 24
Finished Jul 18 05:28:07 PM PDT 24
Peak memory 213812 kb
Host smart-70ca1169-b074-4257-8a41-3f9d8e6d5fe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479672592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3479672592
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.1981589180
Short name T526
Test name
Test status
Simulation time 36346578651 ps
CPU time 517.66 seconds
Started Jul 18 05:27:39 PM PDT 24
Finished Jul 18 05:36:21 PM PDT 24
Peak memory 3332416 kb
Host smart-54045269-00a5-4801-92de-abfaa525000f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981589180 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.1981589180
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.864037766
Short name T305
Test name
Test status
Simulation time 3202454608 ps
CPU time 16.56 seconds
Started Jul 18 05:27:37 PM PDT 24
Finished Jul 18 05:27:57 PM PDT 24
Peak memory 222100 kb
Host smart-3e0ca00f-e0f4-4bf4-936e-997d09f79dca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864037766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_rd.864037766
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2528185686
Short name T433
Test name
Test status
Simulation time 46656932847 ps
CPU time 359.54 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:33:34 PM PDT 24
Peak memory 3395356 kb
Host smart-725c438d-5098-4adc-b0c8-6f2684738901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528185686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2528185686
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.266636968
Short name T1132
Test name
Test status
Simulation time 4173102950 ps
CPU time 39.74 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:28:17 PM PDT 24
Peak memory 389584 kb
Host smart-16bccecd-0c1d-4b0a-aa8c-ef37c87df864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266636968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.266636968
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2469223277
Short name T830
Test name
Test status
Simulation time 1532898295 ps
CPU time 8.04 seconds
Started Jul 18 05:27:28 PM PDT 24
Finished Jul 18 05:27:38 PM PDT 24
Peak memory 215664 kb
Host smart-abc40778-257a-4a36-afdc-4f6d79f30a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469223277 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2469223277
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.1877935493
Short name T1724
Test name
Test status
Simulation time 677948120 ps
CPU time 8.75 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 206100 kb
Host smart-bb78665c-b33b-46a0-a0ca-f35247dc1bb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877935493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.1877935493
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.4187924259
Short name T1663
Test name
Test status
Simulation time 23208608 ps
CPU time 0.61 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 204716 kb
Host smart-014edb55-38d3-41a8-b84d-f079b9a2b050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187924259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.4187924259
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1022968142
Short name T1109
Test name
Test status
Simulation time 400534969 ps
CPU time 1.17 seconds
Started Jul 18 05:27:44 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 213284 kb
Host smart-127eaad1-2c45-4970-8224-a7407988a443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022968142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1022968142
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2190161109
Short name T649
Test name
Test status
Simulation time 301284708 ps
CPU time 6.15 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:27:52 PM PDT 24
Peak memory 251796 kb
Host smart-be0cc19e-ff4a-44a5-9856-d43bd6aa16a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190161109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2190161109
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.935133511
Short name T1747
Test name
Test status
Simulation time 2384438601 ps
CPU time 82.95 seconds
Started Jul 18 05:27:44 PM PDT 24
Finished Jul 18 05:29:10 PM PDT 24
Peak memory 638480 kb
Host smart-7bafa11b-0204-42ec-b2f9-8a201fb772f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935133511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.935133511
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3505058375
Short name T1709
Test name
Test status
Simulation time 8729223020 ps
CPU time 79.37 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:28:56 PM PDT 24
Peak memory 711268 kb
Host smart-ae3b84c1-5b80-4322-9d1a-9f2e784a05bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505058375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3505058375
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2312256229
Short name T483
Test name
Test status
Simulation time 148664257 ps
CPU time 1.02 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:27:47 PM PDT 24
Peak memory 205244 kb
Host smart-e37b6b93-ccad-45bd-aa64-463c7e5c39e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312256229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2312256229
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1849667621
Short name T839
Test name
Test status
Simulation time 924069504 ps
CPU time 5.31 seconds
Started Jul 18 05:27:40 PM PDT 24
Finished Jul 18 05:27:49 PM PDT 24
Peak memory 247388 kb
Host smart-a5260147-65da-469e-8a18-4ff069a315ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849667621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1849667621
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.119929448
Short name T430
Test name
Test status
Simulation time 4289949881 ps
CPU time 315.04 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:32:48 PM PDT 24
Peak memory 1216468 kb
Host smart-d6fcf665-ae68-42f3-9ee3-a0760109d739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119929448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.119929448
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1770379846
Short name T1564
Test name
Test status
Simulation time 1899806059 ps
CPU time 16.38 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:28:09 PM PDT 24
Peak memory 205460 kb
Host smart-b8e9a0ed-1f53-4e2c-a2c2-d62e7654257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770379846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1770379846
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.1187366974
Short name T116
Test name
Test status
Simulation time 19253507 ps
CPU time 0.67 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:36 PM PDT 24
Peak memory 205252 kb
Host smart-6d804caf-edf6-4f18-9b61-164b418e92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187366974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1187366974
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3681099
Short name T887
Test name
Test status
Simulation time 3031363714 ps
CPU time 128.44 seconds
Started Jul 18 05:27:47 PM PDT 24
Finished Jul 18 05:29:59 PM PDT 24
Peak memory 717336 kb
Host smart-1d9e5fe9-01b8-445c-b012-81f4e4ad7635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3681099
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1123548295
Short name T1621
Test name
Test status
Simulation time 6921187737 ps
CPU time 35.6 seconds
Started Jul 18 05:27:29 PM PDT 24
Finished Jul 18 05:28:07 PM PDT 24
Peak memory 359172 kb
Host smart-f699a172-aa1a-4228-b0dc-410e1a9286b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123548295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1123548295
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.925604424
Short name T1137
Test name
Test status
Simulation time 3291943540 ps
CPU time 38.11 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:28:31 PM PDT 24
Peak memory 213828 kb
Host smart-458cb63a-b195-4d35-81ac-c717014586ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925604424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.925604424
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3800190321
Short name T1742
Test name
Test status
Simulation time 1046560711 ps
CPU time 5.5 seconds
Started Jul 18 05:27:47 PM PDT 24
Finished Jul 18 05:27:56 PM PDT 24
Peak memory 217896 kb
Host smart-29a023cb-d589-40af-be73-f4ce8d18c394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800190321 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3800190321
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2618294499
Short name T1385
Test name
Test status
Simulation time 262595276 ps
CPU time 0.79 seconds
Started Jul 18 05:27:47 PM PDT 24
Finished Jul 18 05:27:51 PM PDT 24
Peak memory 205468 kb
Host smart-5630ed24-24e3-4cb1-a0d8-1fe37770fd9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618294499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.2618294499
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.329528435
Short name T597
Test name
Test status
Simulation time 407729585 ps
CPU time 1.62 seconds
Started Jul 18 05:27:40 PM PDT 24
Finished Jul 18 05:27:45 PM PDT 24
Peak memory 205772 kb
Host smart-027feec3-e34a-4db9-abb8-4eaac51aded7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329528435 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.329528435
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.1042868382
Short name T1146
Test name
Test status
Simulation time 801213266 ps
CPU time 1.62 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:27:53 PM PDT 24
Peak memory 205448 kb
Host smart-a26e0b2b-8626-46a0-b511-7797ba2432d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042868382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.1042868382
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.1667366933
Short name T898
Test name
Test status
Simulation time 140741554 ps
CPU time 1.28 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 205416 kb
Host smart-8ebb4b0c-99fd-4c3d-a06a-f05d9e5421ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667366933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.1667366933
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2433458314
Short name T508
Test name
Test status
Simulation time 414570825 ps
CPU time 2.74 seconds
Started Jul 18 05:27:44 PM PDT 24
Finished Jul 18 05:27:50 PM PDT 24
Peak memory 213868 kb
Host smart-d16ab3ce-aa1c-4ed4-8e07-0e4be215f61e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433458314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2433458314
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1289440582
Short name T1321
Test name
Test status
Simulation time 4984444923 ps
CPU time 5.24 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:27:50 PM PDT 24
Peak memory 222188 kb
Host smart-1315c034-ddad-4d72-9ce8-46c244988ed9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289440582 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1289440582
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.404184693
Short name T859
Test name
Test status
Simulation time 8263924328 ps
CPU time 5.49 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:27:52 PM PDT 24
Peak memory 205676 kb
Host smart-dd4810a9-2bc9-437b-ab5b-c86d238ed0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404184693 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.404184693
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.2237420934
Short name T768
Test name
Test status
Simulation time 535958428 ps
CPU time 2.91 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:27:55 PM PDT 24
Peak memory 213852 kb
Host smart-81fd35a5-e116-4888-9051-839a85cc93ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237420934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.2237420934
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.1768615339
Short name T497
Test name
Test status
Simulation time 947178390 ps
CPU time 2.29 seconds
Started Jul 18 05:27:42 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 205576 kb
Host smart-8988f157-2fb6-4588-ac3b-fc707c060955
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768615339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.1768615339
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_txstretch.3359915486
Short name T1117
Test name
Test status
Simulation time 1709852127 ps
CPU time 1.24 seconds
Started Jul 18 05:27:47 PM PDT 24
Finished Jul 18 05:27:52 PM PDT 24
Peak memory 222344 kb
Host smart-d88dc24e-3c80-49a1-86c9-a5e21970c1e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359915486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_nack_txstretch.3359915486
Directory /workspace/13.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/13.i2c_target_perf.3147597914
Short name T1055
Test name
Test status
Simulation time 2166063429 ps
CPU time 7.59 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 230252 kb
Host smart-69cbcf0d-99e7-4373-af66-8d253c0bf4ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147597914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.3147597914
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.2580032790
Short name T577
Test name
Test status
Simulation time 2694195534 ps
CPU time 2.15 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 204220 kb
Host smart-6b3c8166-e6a0-44fc-ac2a-75459c416ecb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580032790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_smbus_maxlen.2580032790
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3110973548
Short name T164
Test name
Test status
Simulation time 3404332022 ps
CPU time 27.6 seconds
Started Jul 18 05:27:44 PM PDT 24
Finished Jul 18 05:28:14 PM PDT 24
Peak memory 213828 kb
Host smart-ab791bd1-a287-455b-b831-be21fc217a50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110973548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3110973548
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.4293482522
Short name T1341
Test name
Test status
Simulation time 23925760129 ps
CPU time 82.22 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:29:15 PM PDT 24
Peak memory 717940 kb
Host smart-57891fae-adae-4946-8d70-547bab0b5b0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293482522 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.4293482522
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1974140383
Short name T551
Test name
Test status
Simulation time 1699643307 ps
CPU time 16.01 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:28:01 PM PDT 24
Peak memory 225220 kb
Host smart-e3832835-088b-46cb-b47b-1d81d0db585c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974140383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1974140383
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.456824978
Short name T996
Test name
Test status
Simulation time 40080573306 ps
CPU time 85.33 seconds
Started Jul 18 05:27:39 PM PDT 24
Finished Jul 18 05:29:08 PM PDT 24
Peak memory 1273000 kb
Host smart-aa3804a6-4677-4520-9944-de7beb7c4988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456824978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.456824978
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.630555504
Short name T782
Test name
Test status
Simulation time 3809766687 ps
CPU time 36.17 seconds
Started Jul 18 05:27:38 PM PDT 24
Finished Jul 18 05:28:18 PM PDT 24
Peak memory 386956 kb
Host smart-313710b3-7222-45d0-8799-1e017627765a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630555504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.630555504
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2475145060
Short name T1080
Test name
Test status
Simulation time 11314387438 ps
CPU time 8.08 seconds
Started Jul 18 05:27:40 PM PDT 24
Finished Jul 18 05:27:52 PM PDT 24
Peak memory 230472 kb
Host smart-b4a9ae23-4738-4ad7-8c96-ab0747a7ba71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475145060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2475145060
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.665720973
Short name T1091
Test name
Test status
Simulation time 818934684 ps
CPU time 11.02 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:28:03 PM PDT 24
Peak memory 206560 kb
Host smart-ecf8a945-1160-41c9-89c9-8a32546e0028
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665720973 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.665720973
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.959436144
Short name T1213
Test name
Test status
Simulation time 34066909 ps
CPU time 0.61 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:28:03 PM PDT 24
Peak memory 204712 kb
Host smart-bca169ef-6a08-4475-a45a-420126eaa578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959436144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.959436144
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1643820101
Short name T1302
Test name
Test status
Simulation time 531260606 ps
CPU time 1.72 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 213772 kb
Host smart-82b272a3-714d-456d-b360-c2dfb0bae712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643820101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1643820101
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1326782442
Short name T1088
Test name
Test status
Simulation time 1542598599 ps
CPU time 18.77 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:28:11 PM PDT 24
Peak memory 275740 kb
Host smart-e6cff41d-62e4-44a2-85f2-8803c71d582b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326782442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1326782442
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1286486
Short name T359
Test name
Test status
Simulation time 4911880914 ps
CPU time 190.35 seconds
Started Jul 18 05:28:09 PM PDT 24
Finished Jul 18 05:31:19 PM PDT 24
Peak memory 716720 kb
Host smart-3148ba3d-ac97-4ed6-83d1-4c0abe6ec7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1286486
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.968036419
Short name T152
Test name
Test status
Simulation time 1537767312 ps
CPU time 41.69 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:28:33 PM PDT 24
Peak memory 574360 kb
Host smart-f981ccef-e2c4-4944-a5d0-fc34a02195e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968036419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.968036419
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2971547930
Short name T598
Test name
Test status
Simulation time 598684571 ps
CPU time 1.22 seconds
Started Jul 18 05:27:47 PM PDT 24
Finished Jul 18 05:27:52 PM PDT 24
Peak memory 205388 kb
Host smart-fd2b3147-5d35-4a57-8c43-e453b5bf68ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971547930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2971547930
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1728380545
Short name T1450
Test name
Test status
Simulation time 161039666 ps
CPU time 3.25 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:27:56 PM PDT 24
Peak memory 205512 kb
Host smart-b5bb4ee8-ec07-4fa9-a2b9-c386e2b4e3c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728380545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1728380545
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2246529495
Short name T1309
Test name
Test status
Simulation time 8275858684 ps
CPU time 222.37 seconds
Started Jul 18 05:27:50 PM PDT 24
Finished Jul 18 05:31:36 PM PDT 24
Peak memory 1033008 kb
Host smart-4c8ab65d-df23-42c6-b779-dcfa28635ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246529495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2246529495
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.1880927610
Short name T1424
Test name
Test status
Simulation time 709378584 ps
CPU time 9.78 seconds
Started Jul 18 05:27:52 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 205520 kb
Host smart-1e314e51-0e77-4fca-bc5c-ba58f088dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880927610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.1880927610
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_override.1168728585
Short name T1547
Test name
Test status
Simulation time 27989917 ps
CPU time 0.75 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:27:47 PM PDT 24
Peak memory 205232 kb
Host smart-2417b871-8f67-4789-8c53-27cf6064629c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168728585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1168728585
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.4279012712
Short name T139
Test name
Test status
Simulation time 2676497784 ps
CPU time 75.93 seconds
Started Jul 18 05:27:55 PM PDT 24
Finished Jul 18 05:29:13 PM PDT 24
Peak memory 830760 kb
Host smart-e4d30db9-1ed0-4d88-a44b-3e6996fd130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279012712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.4279012712
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.2244993049
Short name T1182
Test name
Test status
Simulation time 234463859 ps
CPU time 5.57 seconds
Started Jul 18 05:28:00 PM PDT 24
Finished Jul 18 05:28:10 PM PDT 24
Peak memory 217448 kb
Host smart-4017388b-c740-4d10-bdf5-f15a21edc42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244993049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.2244993049
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2638091607
Short name T570
Test name
Test status
Simulation time 2192884333 ps
CPU time 29.16 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:28:21 PM PDT 24
Peak memory 314800 kb
Host smart-bb3dd349-c91a-4591-bb07-6c5e2e6c0cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638091607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2638091607
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2015523833
Short name T539
Test name
Test status
Simulation time 830657010 ps
CPU time 36.36 seconds
Started Jul 18 05:27:55 PM PDT 24
Finished Jul 18 05:28:32 PM PDT 24
Peak memory 213932 kb
Host smart-95440ad5-bd4b-481b-8b31-e156e8c800f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015523833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2015523833
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1564506687
Short name T1749
Test name
Test status
Simulation time 3161022238 ps
CPU time 4.66 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:28:03 PM PDT 24
Peak memory 211492 kb
Host smart-03b5c4ff-b8d0-42b9-9fd1-9048479c818c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564506687 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1564506687
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.3737764675
Short name T906
Test name
Test status
Simulation time 132534418 ps
CPU time 0.9 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 205364 kb
Host smart-06411ff6-90e9-4a69-8bf9-891dbe0bd376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737764675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.3737764675
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2343992433
Short name T1441
Test name
Test status
Simulation time 131017091 ps
CPU time 0.97 seconds
Started Jul 18 05:27:53 PM PDT 24
Finished Jul 18 05:27:56 PM PDT 24
Peak memory 205484 kb
Host smart-11c5b907-ec5f-4633-be26-990817752b0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343992433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2343992433
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.1588412575
Short name T507
Test name
Test status
Simulation time 7665059047 ps
CPU time 3.19 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 205696 kb
Host smart-412b4aab-0cfe-46ac-a60f-6ce80e04c394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588412575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.1588412575
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.3299500748
Short name T321
Test name
Test status
Simulation time 562657606 ps
CPU time 1.23 seconds
Started Jul 18 05:27:53 PM PDT 24
Finished Jul 18 05:27:56 PM PDT 24
Peak memory 205480 kb
Host smart-3249bd83-a693-49c6-8d12-036578a32191
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299500748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.3299500748
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.3972297267
Short name T132
Test name
Test status
Simulation time 303370668 ps
CPU time 2.12 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 213092 kb
Host smart-bb84a855-02ab-42b9-a212-ca749baeb683
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972297267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.3972297267
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2934321764
Short name T1650
Test name
Test status
Simulation time 1300078285 ps
CPU time 8.08 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 213180 kb
Host smart-494753d6-80bf-4e95-b2f3-383320889b97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934321764 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2934321764
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.621045679
Short name T1143
Test name
Test status
Simulation time 2960572342 ps
CPU time 2.97 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 205756 kb
Host smart-7f0fcffc-0f1b-421b-932f-7f29cb2506b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621045679 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.621045679
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.2459658779
Short name T754
Test name
Test status
Simulation time 2118734292 ps
CPU time 2.86 seconds
Started Jul 18 05:27:50 PM PDT 24
Finished Jul 18 05:27:57 PM PDT 24
Peak memory 213852 kb
Host smart-b4514d8f-9e09-4224-82c4-decb2eb96d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459658779 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_nack_acqfull.2459658779
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.3101723761
Short name T1194
Test name
Test status
Simulation time 2825146043 ps
CPU time 2.23 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 205524 kb
Host smart-be7ae349-41b2-41b9-be0b-f1f14ad373c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101723761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.3101723761
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.2564551966
Short name T536
Test name
Test status
Simulation time 865094810 ps
CPU time 5.43 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 221964 kb
Host smart-25f6b213-501f-4212-b142-637c628a2b1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564551966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.2564551966
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.1351999841
Short name T888
Test name
Test status
Simulation time 2264420296 ps
CPU time 2.2 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:27:49 PM PDT 24
Peak memory 205460 kb
Host smart-aea3573a-ec0f-42fe-b6ef-4383d46ff559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351999841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.1351999841
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.3399563944
Short name T1531
Test name
Test status
Simulation time 60774742998 ps
CPU time 260 seconds
Started Jul 18 05:27:44 PM PDT 24
Finished Jul 18 05:32:07 PM PDT 24
Peak memory 1540872 kb
Host smart-4c49b721-b954-4bcb-80b2-c68e2ce2f39a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399563944 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.3399563944
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3196960290
Short name T769
Test name
Test status
Simulation time 2403909699 ps
CPU time 20.4 seconds
Started Jul 18 05:27:52 PM PDT 24
Finished Jul 18 05:28:15 PM PDT 24
Peak memory 230064 kb
Host smart-54f9f690-e909-4f87-87a3-98e02ccea28b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196960290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3196960290
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.247985976
Short name T1698
Test name
Test status
Simulation time 10435119312 ps
CPU time 16.59 seconds
Started Jul 18 05:27:52 PM PDT 24
Finished Jul 18 05:28:11 PM PDT 24
Peak memory 205672 kb
Host smart-092d1efc-1c56-4397-b05c-28405c8958da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247985976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.247985976
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2385155330
Short name T780
Test name
Test status
Simulation time 2080548190 ps
CPU time 39.44 seconds
Started Jul 18 05:27:52 PM PDT 24
Finished Jul 18 05:28:34 PM PDT 24
Peak memory 667556 kb
Host smart-7c7afbad-b936-4117-a1c3-8ac8f94f8d81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385155330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2385155330
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.4081089528
Short name T1086
Test name
Test status
Simulation time 1253458210 ps
CPU time 6.26 seconds
Started Jul 18 05:27:53 PM PDT 24
Finished Jul 18 05:28:01 PM PDT 24
Peak memory 222012 kb
Host smart-8e8a6077-5c5b-4601-9abc-0cfbcec9b811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081089528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.4081089528
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.1083830153
Short name T548
Test name
Test status
Simulation time 50741609 ps
CPU time 1.28 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 205584 kb
Host smart-31105da4-9147-418e-8500-59c36a6cc4f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083830153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.1083830153
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.3888005052
Short name T664
Test name
Test status
Simulation time 16670307 ps
CPU time 0.68 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 204804 kb
Host smart-2ac2e409-98b9-4cc8-962a-1eb92a59267d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888005052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3888005052
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.805160833
Short name T803
Test name
Test status
Simulation time 633006895 ps
CPU time 4.67 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:08 PM PDT 24
Peak memory 229924 kb
Host smart-751d6d22-1f8f-4d9f-9c9c-bacffc21d3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805160833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.805160833
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2771427020
Short name T637
Test name
Test status
Simulation time 557789911 ps
CPU time 7.12 seconds
Started Jul 18 05:27:44 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 228996 kb
Host smart-1b2795f8-f0c1-4c62-bce2-897fe766b00f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771427020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2771427020
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1832115655
Short name T1328
Test name
Test status
Simulation time 4640572471 ps
CPU time 245.79 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:32:08 PM PDT 24
Peak memory 585524 kb
Host smart-48f3af15-dcfc-4c54-b647-74a98844e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832115655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1832115655
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.164126819
Short name T1744
Test name
Test status
Simulation time 1656598315 ps
CPU time 51.68 seconds
Started Jul 18 05:27:45 PM PDT 24
Finished Jul 18 05:28:40 PM PDT 24
Peak memory 585236 kb
Host smart-20fe3689-7944-4d20-83f8-593ea11e546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164126819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.164126819
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.3930331139
Short name T1111
Test name
Test status
Simulation time 440553829 ps
CPU time 1.27 seconds
Started Jul 18 05:27:41 PM PDT 24
Finished Jul 18 05:27:46 PM PDT 24
Peak memory 205416 kb
Host smart-f37d07e9-9c10-4fbf-831b-749184f858b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930331139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.3930331139
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3122416273
Short name T1307
Test name
Test status
Simulation time 189537022 ps
CPU time 4.48 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:27:57 PM PDT 24
Peak memory 205492 kb
Host smart-844e04d2-a170-4e4a-b8b4-78f3b656a66c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122416273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3122416273
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.240772120
Short name T104
Test name
Test status
Simulation time 5207822035 ps
CPU time 140.12 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:30:22 PM PDT 24
Peak memory 1482752 kb
Host smart-9c859b1b-4299-475a-ab83-619027e19b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240772120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.240772120
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2091941074
Short name T6
Test name
Test status
Simulation time 321770115 ps
CPU time 5.43 seconds
Started Jul 18 05:27:52 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 205424 kb
Host smart-267931e3-145b-42d9-9aee-5a9869daf3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091941074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2091941074
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.1190505286
Short name T1360
Test name
Test status
Simulation time 81747425 ps
CPU time 0.68 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:02 PM PDT 24
Peak memory 205188 kb
Host smart-de71d1c8-f26c-4621-b728-5b16caadfbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190505286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1190505286
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2255515851
Short name T1714
Test name
Test status
Simulation time 49163008327 ps
CPU time 2895.72 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 06:16:19 PM PDT 24
Peak memory 4607368 kb
Host smart-53048bba-8e77-4a3d-bb5b-f8d880c71411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255515851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2255515851
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.2161727685
Short name T836
Test name
Test status
Simulation time 2425708352 ps
CPU time 35.15 seconds
Started Jul 18 05:27:43 PM PDT 24
Finished Jul 18 05:28:22 PM PDT 24
Peak memory 223608 kb
Host smart-9409c2d5-4c21-428b-8fe9-cab96c033163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161727685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.2161727685
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.4147771796
Short name T1425
Test name
Test status
Simulation time 3976449827 ps
CPU time 91.01 seconds
Started Jul 18 05:27:51 PM PDT 24
Finished Jul 18 05:29:25 PM PDT 24
Peak memory 338648 kb
Host smart-f77478bc-1195-4154-bb81-bbaf7b44ae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147771796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.4147771796
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3236708297
Short name T1032
Test name
Test status
Simulation time 3520383928 ps
CPU time 38.07 seconds
Started Jul 18 05:27:45 PM PDT 24
Finished Jul 18 05:28:26 PM PDT 24
Peak memory 213724 kb
Host smart-d4f9c54c-2d84-40ec-b001-dd710a01747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236708297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3236708297
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.281396583
Short name T1520
Test name
Test status
Simulation time 683668551 ps
CPU time 3.33 seconds
Started Jul 18 05:27:54 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 216728 kb
Host smart-7684438c-dc09-4a28-887c-2330f9344758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281396583 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.281396583
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.928006179
Short name T1480
Test name
Test status
Simulation time 867000370 ps
CPU time 1.25 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 213812 kb
Host smart-9604b4fd-c4ed-4861-81c2-8add9c2caecd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928006179 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.928006179
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.4274195810
Short name T273
Test name
Test status
Simulation time 371418564 ps
CPU time 1.29 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:27:53 PM PDT 24
Peak memory 205628 kb
Host smart-dc0d2720-58df-4bed-88dd-97489bca7043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274195810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.4274195810
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.3542521431
Short name T702
Test name
Test status
Simulation time 843088961 ps
CPU time 2.51 seconds
Started Jul 18 05:27:55 PM PDT 24
Finished Jul 18 05:27:58 PM PDT 24
Peak memory 205612 kb
Host smart-796cd953-1b79-4608-b822-b4e17dd9c86e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542521431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.3542521431
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.3225984533
Short name T922
Test name
Test status
Simulation time 91588807 ps
CPU time 1.04 seconds
Started Jul 18 05:27:55 PM PDT 24
Finished Jul 18 05:27:58 PM PDT 24
Peak memory 205372 kb
Host smart-84f97ea6-af74-4500-b910-bc8912a889c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225984533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.3225984533
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1462358073
Short name T369
Test name
Test status
Simulation time 4862947959 ps
CPU time 4.82 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:27:57 PM PDT 24
Peak memory 220472 kb
Host smart-2662e8af-6cf3-4693-ac6c-cc635d5a50c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462358073 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1462358073
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.2253639058
Short name T1333
Test name
Test status
Simulation time 28835594878 ps
CPU time 59.25 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:28:51 PM PDT 24
Peak memory 1127292 kb
Host smart-a9473e54-cea4-43bf-82ff-b793617dcc9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253639058 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2253639058
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.340672669
Short name T510
Test name
Test status
Simulation time 523263873 ps
CPU time 2.72 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 213808 kb
Host smart-5b14f649-24d0-45d5-b253-70aee282f9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340672669 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_nack_acqfull.340672669
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.1602072988
Short name T1712
Test name
Test status
Simulation time 930183151 ps
CPU time 2.36 seconds
Started Jul 18 05:28:03 PM PDT 24
Finished Jul 18 05:28:07 PM PDT 24
Peak memory 205568 kb
Host smart-210c1e8e-7fbe-4145-84f6-67944d5d4677
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602072988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.1602072988
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.3945934281
Short name T360
Test name
Test status
Simulation time 560439735 ps
CPU time 4.33 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:27:57 PM PDT 24
Peak memory 219768 kb
Host smart-c2bb7f95-ce16-4748-823d-593fb097095d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945934281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.3945934281
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.760417701
Short name T616
Test name
Test status
Simulation time 2637146580 ps
CPU time 2.44 seconds
Started Jul 18 05:28:00 PM PDT 24
Finished Jul 18 05:28:07 PM PDT 24
Peak memory 205472 kb
Host smart-e6c0af86-9b60-4cfb-9f7e-f63986574674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760417701 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_smbus_maxlen.760417701
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.727075193
Short name T74
Test name
Test status
Simulation time 3152986543 ps
CPU time 12.77 seconds
Started Jul 18 05:27:50 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 213868 kb
Host smart-f7928ed0-299a-4aa5-81f1-13f8d60bc52e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727075193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.727075193
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.21859523
Short name T1016
Test name
Test status
Simulation time 8832520407 ps
CPU time 30.83 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:28:23 PM PDT 24
Peak memory 250796 kb
Host smart-9027f54b-6691-4867-a514-41399fe2ff84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21859523 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.i2c_target_stress_all.21859523
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.830031529
Short name T800
Test name
Test status
Simulation time 293970800 ps
CPU time 12.24 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 205620 kb
Host smart-cb045a5b-d597-4878-b206-75e604628b63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830031529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.830031529
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1734245153
Short name T383
Test name
Test status
Simulation time 65194067390 ps
CPU time 136.72 seconds
Started Jul 18 05:27:45 PM PDT 24
Finished Jul 18 05:30:04 PM PDT 24
Peak memory 1543596 kb
Host smart-87757214-8ca6-41cc-b1c5-b35bb058d014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734245153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1734245153
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3169822522
Short name T777
Test name
Test status
Simulation time 1663979299 ps
CPU time 6 seconds
Started Jul 18 05:27:48 PM PDT 24
Finished Jul 18 05:27:58 PM PDT 24
Peak memory 278760 kb
Host smart-8fab8073-981c-4205-bcb9-412d56250aeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169822522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3169822522
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3571608631
Short name T67
Test name
Test status
Simulation time 1446494707 ps
CPU time 7.64 seconds
Started Jul 18 05:27:49 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 220580 kb
Host smart-770f7a7e-fc8a-42d5-8fc0-e15c7ac4e4d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571608631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3571608631
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.1404200566
Short name T963
Test name
Test status
Simulation time 138210784 ps
CPU time 3.27 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 205900 kb
Host smart-2a377fe0-a60e-4bf2-bf8d-bb03f164abea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404200566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.1404200566
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.766171420
Short name T1595
Test name
Test status
Simulation time 26407622 ps
CPU time 0.64 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 204796 kb
Host smart-067aa09c-7a84-487b-a9c1-b2c5a7e5969b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766171420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.766171420
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.718469890
Short name T1456
Test name
Test status
Simulation time 813916785 ps
CPU time 9.23 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:13 PM PDT 24
Peak memory 295888 kb
Host smart-ba6880a6-9337-4d59-a20f-9bae82ece68c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718469890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.718469890
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2220419607
Short name T655
Test name
Test status
Simulation time 7917208925 ps
CPU time 167.75 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:30:50 PM PDT 24
Peak memory 668148 kb
Host smart-0843ae42-3ac9-4243-8982-d61b49e55328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220419607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2220419607
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.734948646
Short name T684
Test name
Test status
Simulation time 5346821338 ps
CPU time 92.94 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:29:33 PM PDT 24
Peak memory 806032 kb
Host smart-50de61ef-2a57-4d2a-af47-969bcfa99f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734948646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.734948646
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3045775995
Short name T1589
Test name
Test status
Simulation time 411577995 ps
CPU time 0.87 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 205188 kb
Host smart-ea0a3aa8-d7f8-49c2-95fa-fb8063f0cbe6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045775995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3045775995
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.256505255
Short name T1290
Test name
Test status
Simulation time 346354970 ps
CPU time 3.83 seconds
Started Jul 18 05:27:55 PM PDT 24
Finished Jul 18 05:28:01 PM PDT 24
Peak memory 205564 kb
Host smart-485d4c9c-bdfe-4a87-b464-d0451b0d35ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256505255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
256505255
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1526941294
Short name T150
Test name
Test status
Simulation time 17086638973 ps
CPU time 124.47 seconds
Started Jul 18 05:28:02 PM PDT 24
Finished Jul 18 05:30:09 PM PDT 24
Peak memory 1228496 kb
Host smart-f35ce492-0614-4682-b5fb-a895ca750adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526941294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1526941294
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3594877946
Short name T249
Test name
Test status
Simulation time 966275083 ps
CPU time 2.81 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 205508 kb
Host smart-95342e69-39cc-4d26-8a94-7588c2e828db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594877946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3594877946
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.104405258
Short name T111
Test name
Test status
Simulation time 28711856 ps
CPU time 0.74 seconds
Started Jul 18 05:28:04 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 205200 kb
Host smart-cb40634c-6337-4faa-9cf7-89b29fb9a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104405258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.104405258
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.284454616
Short name T1264
Test name
Test status
Simulation time 7062552033 ps
CPU time 13.18 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:28:11 PM PDT 24
Peak memory 205584 kb
Host smart-a0f01482-760e-48ab-b18a-ec9235053616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284454616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.284454616
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.3859675422
Short name T1128
Test name
Test status
Simulation time 151692354 ps
CPU time 1.4 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:05 PM PDT 24
Peak memory 228484 kb
Host smart-652c42c0-ffd0-439b-93cb-76dc96bd638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859675422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3859675422
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1391041265
Short name T1427
Test name
Test status
Simulation time 1754493307 ps
CPU time 85.92 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:29:28 PM PDT 24
Peak memory 366256 kb
Host smart-9f0fe17e-774d-4903-a099-540ce7a5d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391041265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1391041265
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1001491965
Short name T760
Test name
Test status
Simulation time 3061512194 ps
CPU time 22.75 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:26 PM PDT 24
Peak memory 213732 kb
Host smart-d5eb0cb6-5126-4525-be03-69f622ff8f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001491965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1001491965
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3054790486
Short name T602
Test name
Test status
Simulation time 745432265 ps
CPU time 4.2 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 208900 kb
Host smart-0d332e59-34b8-4a52-9f56-043f7e850fe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054790486 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3054790486
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2485606120
Short name T1294
Test name
Test status
Simulation time 283264978 ps
CPU time 1.8 seconds
Started Jul 18 05:28:01 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 205596 kb
Host smart-1d080d59-fcdd-43fd-88f9-592a28038d15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485606120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2485606120
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3536492140
Short name T1048
Test name
Test status
Simulation time 278701434 ps
CPU time 0.87 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 205440 kb
Host smart-f30d1992-7877-4b51-8d30-70e5ce273c1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536492140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3536492140
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.644481798
Short name T1050
Test name
Test status
Simulation time 616224802 ps
CPU time 2 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 205628 kb
Host smart-d1394a8b-4d51-4dcb-beb7-6d821f8d93dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644481798 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.644481798
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.49801088
Short name T1104
Test name
Test status
Simulation time 390548042 ps
CPU time 1.61 seconds
Started Jul 18 05:28:01 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 205420 kb
Host smart-cbf2d376-9965-41a4-91da-66ecfeda7f0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49801088 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.49801088
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2075631906
Short name T1145
Test name
Test status
Simulation time 685660214 ps
CPU time 1.62 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:03 PM PDT 24
Peak memory 213888 kb
Host smart-28ba3105-1081-4436-b484-2292bd419688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075631906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2075631906
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2882879558
Short name T876
Test name
Test status
Simulation time 10306221107 ps
CPU time 4.39 seconds
Started Jul 18 05:27:55 PM PDT 24
Finished Jul 18 05:28:01 PM PDT 24
Peak memory 217724 kb
Host smart-5736a791-9e69-4355-af9a-ada63db6e7af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882879558 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2882879558
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3453230233
Short name T129
Test name
Test status
Simulation time 17104235268 ps
CPU time 38.39 seconds
Started Jul 18 05:27:55 PM PDT 24
Finished Jul 18 05:28:35 PM PDT 24
Peak memory 650880 kb
Host smart-e0dd6ac7-b85c-4523-8409-254b9f9cb97e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453230233 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3453230233
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.2364837374
Short name T1161
Test name
Test status
Simulation time 1136003252 ps
CPU time 2.87 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 213888 kb
Host smart-ad1f5110-32e7-4fba-8838-e43fd8082089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364837374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_nack_acqfull.2364837374
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_txstretch.843041307
Short name T1159
Test name
Test status
Simulation time 701363320 ps
CPU time 1.57 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 222388 kb
Host smart-2fbdb786-070f-4818-8e4d-219b66b503c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843041307 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_nack_txstretch.843041307
Directory /workspace/16.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/16.i2c_target_perf.835685944
Short name T843
Test name
Test status
Simulation time 1416340691 ps
CPU time 7.31 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:08 PM PDT 24
Peak memory 221756 kb
Host smart-d33d1418-ba26-4952-be5f-350ac965ad43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835685944 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_perf.835685944
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.3660800808
Short name T1149
Test name
Test status
Simulation time 2240247927 ps
CPU time 2.52 seconds
Started Jul 18 05:28:01 PM PDT 24
Finished Jul 18 05:28:07 PM PDT 24
Peak memory 205512 kb
Host smart-e5a0fff0-1ecd-4ad8-9e29-80649d00e1e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660800808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.3660800808
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.1766599520
Short name T125
Test name
Test status
Simulation time 1964242786 ps
CPU time 19.75 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:21 PM PDT 24
Peak memory 213764 kb
Host smart-705948e7-2d31-4598-ad2f-842ff289ad98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766599520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.1766599520
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.3764416561
Short name T549
Test name
Test status
Simulation time 85319124429 ps
CPU time 347.91 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:33:51 PM PDT 24
Peak memory 2084016 kb
Host smart-a32a4fba-b36b-4484-a582-c7997e0a58ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764416561 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.3764416561
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3616919780
Short name T940
Test name
Test status
Simulation time 709633321 ps
CPU time 12.96 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:16 PM PDT 24
Peak memory 217980 kb
Host smart-d5526951-4245-4c0c-8db0-a5d2d47dfa1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616919780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3616919780
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.4077260581
Short name T985
Test name
Test status
Simulation time 30976918501 ps
CPU time 76.69 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:29:18 PM PDT 24
Peak memory 1287524 kb
Host smart-29ee8116-13c2-4081-8776-22de7de6cbcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077260581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.4077260581
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1586935157
Short name T1601
Test name
Test status
Simulation time 5068364970 ps
CPU time 7.18 seconds
Started Jul 18 05:28:02 PM PDT 24
Finished Jul 18 05:28:12 PM PDT 24
Peak memory 218816 kb
Host smart-717db3a3-fd1e-4c2f-8c1e-ca2f71bc48e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586935157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1586935157
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.3602942250
Short name T991
Test name
Test status
Simulation time 731729004 ps
CPU time 9.71 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:28:11 PM PDT 24
Peak memory 205496 kb
Host smart-919fd1e8-9440-4a85-9f30-d1fa6a72c868
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602942250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.3602942250
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.879177878
Short name T748
Test name
Test status
Simulation time 46155472 ps
CPU time 0.63 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:28 PM PDT 24
Peak memory 204712 kb
Host smart-267503fc-ba30-4688-9033-8fe25da42299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879177878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.879177878
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.4267148175
Short name T16
Test name
Test status
Simulation time 532133064 ps
CPU time 1.97 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 217300 kb
Host smart-6de96faf-e54e-466f-a18d-b16139dde407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267148175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.4267148175
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2319677397
Short name T1107
Test name
Test status
Simulation time 1737023364 ps
CPU time 7.72 seconds
Started Jul 18 05:28:01 PM PDT 24
Finished Jul 18 05:28:12 PM PDT 24
Peak memory 287740 kb
Host smart-d3998ed7-99b3-49a8-ad6e-9b737125b95a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319677397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2319677397
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1987340394
Short name T1464
Test name
Test status
Simulation time 16055927088 ps
CPU time 176.58 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:31:00 PM PDT 24
Peak memory 632512 kb
Host smart-a9889d23-c46d-42ba-a699-48bd6943f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987340394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1987340394
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.72054045
Short name T461
Test name
Test status
Simulation time 3657110744 ps
CPU time 124.02 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:30:08 PM PDT 24
Peak memory 643808 kb
Host smart-362ff676-f861-4ca9-b785-381451858553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72054045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.72054045
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3527245683
Short name T1353
Test name
Test status
Simulation time 1373962132 ps
CPU time 0.94 seconds
Started Jul 18 05:27:56 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 205264 kb
Host smart-a2133393-d332-4388-a737-d2a5949f1551
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527245683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3527245683
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1753754043
Short name T143
Test name
Test status
Simulation time 341231421 ps
CPU time 3.82 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:07 PM PDT 24
Peak memory 205480 kb
Host smart-c12207c6-5af6-454a-a501-0b58f73a7616
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753754043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1753754043
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2626288559
Short name T740
Test name
Test status
Simulation time 6413773440 ps
CPU time 169.92 seconds
Started Jul 18 05:27:57 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 1499944 kb
Host smart-f410cfdd-0c46-4dbf-b4b1-eb5d33f1c50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626288559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2626288559
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1217414599
Short name T232
Test name
Test status
Simulation time 1436374191 ps
CPU time 7.3 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:32 PM PDT 24
Peak memory 205480 kb
Host smart-c037cfd2-2c0c-4293-9769-67101a20ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217414599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1217414599
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.536608881
Short name T1453
Test name
Test status
Simulation time 72769345 ps
CPU time 1.55 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:27 PM PDT 24
Peak memory 217804 kb
Host smart-a62086a4-661d-4e12-9e6c-45f73927b7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536608881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.536608881
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.3129038050
Short name T123
Test name
Test status
Simulation time 379068949 ps
CPU time 0.7 seconds
Started Jul 18 05:28:00 PM PDT 24
Finished Jul 18 05:28:05 PM PDT 24
Peak memory 205224 kb
Host smart-506eef81-0d15-4fec-adb6-251d933ee36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129038050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3129038050
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3512484823
Short name T15
Test name
Test status
Simulation time 5441517731 ps
CPU time 20.71 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:28:23 PM PDT 24
Peak memory 214016 kb
Host smart-2345919f-3a91-456a-bb09-689ab1fc9b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512484823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3512484823
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.1198249422
Short name T1017
Test name
Test status
Simulation time 2035592487 ps
CPU time 42.73 seconds
Started Jul 18 05:27:55 PM PDT 24
Finished Jul 18 05:28:40 PM PDT 24
Peak memory 502480 kb
Host smart-1badad38-0c8a-4487-975c-5d141894a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198249422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.1198249422
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.435569812
Short name T1144
Test name
Test status
Simulation time 20212849189 ps
CPU time 30.71 seconds
Started Jul 18 05:27:58 PM PDT 24
Finished Jul 18 05:28:33 PM PDT 24
Peak memory 324012 kb
Host smart-09dcf716-f2ac-4cbd-9929-c0f80e84364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435569812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.435569812
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1829051046
Short name T435
Test name
Test status
Simulation time 613509378 ps
CPU time 10.54 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:14 PM PDT 24
Peak memory 215304 kb
Host smart-6532ab45-acf1-4dd2-a14d-42a93b7e2289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829051046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1829051046
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2088888528
Short name T311
Test name
Test status
Simulation time 5016016773 ps
CPU time 6.39 seconds
Started Jul 18 05:28:21 PM PDT 24
Finished Jul 18 05:28:29 PM PDT 24
Peak memory 213844 kb
Host smart-aff46198-ff63-4213-a520-85ceef7e8771
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088888528 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2088888528
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3858331531
Short name T350
Test name
Test status
Simulation time 246277709 ps
CPU time 1.8 seconds
Started Jul 18 05:28:20 PM PDT 24
Finished Jul 18 05:28:23 PM PDT 24
Peak memory 205816 kb
Host smart-a372e93e-ca25-4b3a-82df-9dc82a56faa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858331531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3858331531
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.1580883249
Short name T1687
Test name
Test status
Simulation time 232238417 ps
CPU time 1.12 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:28:30 PM PDT 24
Peak memory 205568 kb
Host smart-68b93bee-c8c1-46dc-bd33-ebab96ca9f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580883249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.1580883249
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.966416395
Short name T711
Test name
Test status
Simulation time 454082398 ps
CPU time 2.41 seconds
Started Jul 18 05:28:21 PM PDT 24
Finished Jul 18 05:28:26 PM PDT 24
Peak memory 205668 kb
Host smart-6827d84d-10dd-46df-bebb-bf65fa40a173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966416395 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.966416395
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.3075268953
Short name T537
Test name
Test status
Simulation time 1305994279 ps
CPU time 1.45 seconds
Started Jul 18 05:28:21 PM PDT 24
Finished Jul 18 05:28:24 PM PDT 24
Peak memory 205472 kb
Host smart-473cd740-7870-40e8-bb75-aa799a5052e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075268953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.3075268953
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1825843775
Short name T320
Test name
Test status
Simulation time 5006974810 ps
CPU time 5.82 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:32 PM PDT 24
Peak memory 221532 kb
Host smart-18617a21-8843-47fb-b744-3141c3a46315
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825843775 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1825843775
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.4086982316
Short name T131
Test name
Test status
Simulation time 5801514883 ps
CPU time 13.22 seconds
Started Jul 18 05:28:25 PM PDT 24
Finished Jul 18 05:28:43 PM PDT 24
Peak memory 205680 kb
Host smart-e25d7952-9034-4b7f-ae51-fc26ca31762e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086982316 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4086982316
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.2532408652
Short name T817
Test name
Test status
Simulation time 1028144226 ps
CPU time 2.74 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:28:31 PM PDT 24
Peak memory 205628 kb
Host smart-dcc22d32-6673-4602-8bf5-791759dd1042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532408652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.2532408652
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_txstretch.3527153919
Short name T1465
Test name
Test status
Simulation time 244712139 ps
CPU time 1.35 seconds
Started Jul 18 05:28:21 PM PDT 24
Finished Jul 18 05:28:24 PM PDT 24
Peak memory 222344 kb
Host smart-ee958754-266a-4ead-9a56-dd4cd27c51fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527153919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_nack_txstretch.3527153919
Directory /workspace/17.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/17.i2c_target_perf.1726460200
Short name T1455
Test name
Test status
Simulation time 720903504 ps
CPU time 5.2 seconds
Started Jul 18 05:28:20 PM PDT 24
Finished Jul 18 05:28:27 PM PDT 24
Peak memory 213800 kb
Host smart-cc7d2d08-eb8d-4b3c-b24c-ab8327585a71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726460200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.1726460200
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.89933147
Short name T1250
Test name
Test status
Simulation time 429203113 ps
CPU time 2.21 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:27 PM PDT 24
Peak memory 205464 kb
Host smart-c3661dcf-0f6e-443d-8c3e-6c9c2dc14276
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89933147 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.i2c_target_smbus_maxlen.89933147
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3249683209
Short name T1620
Test name
Test status
Simulation time 3391737876 ps
CPU time 22.63 seconds
Started Jul 18 05:27:59 PM PDT 24
Finished Jul 18 05:28:26 PM PDT 24
Peak memory 213852 kb
Host smart-815ceeab-b996-4c0b-b0a3-dc9bbdda3b9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249683209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3249683209
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.45833195
Short name T1195
Test name
Test status
Simulation time 20300002031 ps
CPU time 72.9 seconds
Started Jul 18 05:28:20 PM PDT 24
Finished Jul 18 05:29:34 PM PDT 24
Peak memory 594600 kb
Host smart-6f2bc1ca-4087-42ae-818f-889efb512f05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45833195 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.i2c_target_stress_all.45833195
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.974641453
Short name T1271
Test name
Test status
Simulation time 982497419 ps
CPU time 8.97 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 219416 kb
Host smart-6e874edf-1b9a-4aef-a987-15da99759f25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974641453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.974641453
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2293435254
Short name T1310
Test name
Test status
Simulation time 7275332483 ps
CPU time 15.4 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:28:44 PM PDT 24
Peak memory 205512 kb
Host smart-11fb7f24-014a-43f1-b7e5-2d0e390daa01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293435254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2293435254
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1190234521
Short name T1489
Test name
Test status
Simulation time 1324041927 ps
CPU time 7.29 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:35 PM PDT 24
Peak memory 221976 kb
Host smart-ddf458dc-74d5-4ef6-acee-738863443019
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190234521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1190234521
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.2597844847
Short name T1262
Test name
Test status
Simulation time 579248822 ps
CPU time 7.99 seconds
Started Jul 18 05:28:20 PM PDT 24
Finished Jul 18 05:28:29 PM PDT 24
Peak memory 213748 kb
Host smart-2c0c2985-3257-4c57-a1b2-8b4258ec3f60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597844847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2597844847
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3446722155
Short name T813
Test name
Test status
Simulation time 164160980 ps
CPU time 0.65 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:28:29 PM PDT 24
Peak memory 204764 kb
Host smart-c7c08191-6a38-4da3-97eb-f5c4502e83ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446722155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3446722155
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1893116106
Short name T1228
Test name
Test status
Simulation time 281486849 ps
CPU time 4.08 seconds
Started Jul 18 05:28:25 PM PDT 24
Finished Jul 18 05:28:33 PM PDT 24
Peak memory 219732 kb
Host smart-f6ac80bf-c579-40e2-bbe0-749610cb94a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893116106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1893116106
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3752094932
Short name T1572
Test name
Test status
Simulation time 261484792 ps
CPU time 13.38 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:41 PM PDT 24
Peak memory 245208 kb
Host smart-52a5a077-5dcb-4746-aed1-d437c0b8d443
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752094932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3752094932
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2775680723
Short name T1509
Test name
Test status
Simulation time 11465803379 ps
CPU time 66.21 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:29:34 PM PDT 24
Peak memory 447472 kb
Host smart-62c92199-c10d-4403-9934-44cef58d54e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775680723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2775680723
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1254671160
Short name T690
Test name
Test status
Simulation time 2680104374 ps
CPU time 88 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:29:55 PM PDT 24
Peak memory 480128 kb
Host smart-edf6f7ff-b34e-4721-824d-2946fda2eb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254671160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1254671160
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2993131333
Short name T1449
Test name
Test status
Simulation time 113268328 ps
CPU time 1.13 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:28 PM PDT 24
Peak memory 205392 kb
Host smart-efedc88d-3d03-4515-b48d-77fb689d219f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993131333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2993131333
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2894192347
Short name T1232
Test name
Test status
Simulation time 1396499943 ps
CPU time 3.41 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:30 PM PDT 24
Peak memory 205520 kb
Host smart-dce9c35a-c49f-42be-96a5-13b0c5cf213f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894192347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2894192347
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.4172377984
Short name T1664
Test name
Test status
Simulation time 3274905054 ps
CPU time 76.12 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:29:43 PM PDT 24
Peak memory 942976 kb
Host smart-9698fb9d-5f22-434e-bd04-e329db2c3f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172377984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.4172377984
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_override.3639245269
Short name T119
Test name
Test status
Simulation time 32006531 ps
CPU time 0.71 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:28:29 PM PDT 24
Peak memory 205184 kb
Host smart-67e7e2ca-5c57-478f-a7ae-b5ade4a58397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639245269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3639245269
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1965182868
Short name T946
Test name
Test status
Simulation time 12992241502 ps
CPU time 47.52 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:29:16 PM PDT 24
Peak memory 452956 kb
Host smart-203c0883-cdda-4ce0-a970-1a9489c02ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965182868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1965182868
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.3846747992
Short name T1168
Test name
Test status
Simulation time 1921821863 ps
CPU time 97.67 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:30:02 PM PDT 24
Peak memory 495932 kb
Host smart-c53f3ea9-d4fa-4d6f-9f80-f56bad4437f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846747992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.3846747992
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1753549444
Short name T1703
Test name
Test status
Simulation time 28169764657 ps
CPU time 100.16 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:30:08 PM PDT 24
Peak memory 416612 kb
Host smart-5b8b18c6-7912-4f12-ab24-98b67ccd9856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753549444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1753549444
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3504090953
Short name T644
Test name
Test status
Simulation time 802055474 ps
CPU time 33.52 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 213664 kb
Host smart-dc4dba85-969f-429a-b912-7548b0d8dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504090953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3504090953
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.1163957729
Short name T1009
Test name
Test status
Simulation time 14847674714 ps
CPU time 6.38 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:33 PM PDT 24
Peak memory 219316 kb
Host smart-69ca2bca-62f3-439c-9cea-9ee3e74ba700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163957729 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1163957729
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3742086417
Short name T1612
Test name
Test status
Simulation time 305714969 ps
CPU time 1.12 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:27 PM PDT 24
Peak memory 213668 kb
Host smart-d9bc6077-5d6a-49e8-a31a-fb83abd10cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742086417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3742086417
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.1893435782
Short name T87
Test name
Test status
Simulation time 1421378166 ps
CPU time 1.93 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:28:30 PM PDT 24
Peak memory 221756 kb
Host smart-c12fddf0-7c9a-4815-90e3-47fc64956b02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893435782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.1893435782
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.3864113501
Short name T591
Test name
Test status
Simulation time 967868709 ps
CPU time 2.7 seconds
Started Jul 18 05:28:25 PM PDT 24
Finished Jul 18 05:28:32 PM PDT 24
Peak memory 205600 kb
Host smart-c2c1fd78-dbb0-4257-96a1-25777966d968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864113501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.3864113501
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.1854286168
Short name T874
Test name
Test status
Simulation time 571250056 ps
CPU time 1.34 seconds
Started Jul 18 05:28:26 PM PDT 24
Finished Jul 18 05:28:31 PM PDT 24
Peak memory 205404 kb
Host smart-ae0c7d69-2c80-4c76-85c7-e7b4cc217d3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854286168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.1854286168
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1374369793
Short name T330
Test name
Test status
Simulation time 6652074269 ps
CPU time 6.76 seconds
Started Jul 18 05:28:21 PM PDT 24
Finished Jul 18 05:28:30 PM PDT 24
Peak memory 222076 kb
Host smart-3fc4d11b-b592-494e-8f98-576a1a32d986
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374369793 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1374369793
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.4023759125
Short name T460
Test name
Test status
Simulation time 11940364983 ps
CPU time 23.03 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:28:51 PM PDT 24
Peak memory 767664 kb
Host smart-b6a6cf2f-c76e-4620-b107-431f3194a4c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023759125 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.4023759125
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.2450306805
Short name T373
Test name
Test status
Simulation time 545477686 ps
CPU time 2.73 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:29 PM PDT 24
Peak memory 206328 kb
Host smart-488667f1-f851-470e-a22e-9d6f7e0f2dd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450306805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.2450306805
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_txstretch.2549655317
Short name T900
Test name
Test status
Simulation time 661385920 ps
CPU time 1.54 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:29 PM PDT 24
Peak memory 222384 kb
Host smart-9d2f7965-6915-4c93-9756-29d4f25bf3f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549655317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_nack_txstretch.2549655317
Directory /workspace/18.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/18.i2c_target_perf.4230697769
Short name T1176
Test name
Test status
Simulation time 1647548045 ps
CPU time 3.34 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:27 PM PDT 24
Peak memory 213800 kb
Host smart-98bba0e3-5165-462c-bd6c-9e73799d55db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230697769 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.4230697769
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.2428104555
Short name T1406
Test name
Test status
Simulation time 2694410382 ps
CPU time 2.21 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:29 PM PDT 24
Peak memory 205460 kb
Host smart-6cc419e9-c9e9-4221-8146-8db159332fdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428104555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_smbus_maxlen.2428104555
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1241014227
Short name T76
Test name
Test status
Simulation time 2937830471 ps
CPU time 20.86 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:46 PM PDT 24
Peak memory 214048 kb
Host smart-34739794-ec91-44e6-b412-42803c04aed3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241014227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1241014227
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.3990498654
Short name T749
Test name
Test status
Simulation time 68588538511 ps
CPU time 218.03 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 1716916 kb
Host smart-2afe7c7d-b6b3-451e-9f77-555246468abc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990498654 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.3990498654
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.3440311689
Short name T1004
Test name
Test status
Simulation time 49334329707 ps
CPU time 1402.12 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:51:47 PM PDT 24
Peak memory 7660648 kb
Host smart-183defc1-2bf9-4dbb-b21a-27039012c01f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440311689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.3440311689
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1766929820
Short name T1001
Test name
Test status
Simulation time 4522862283 ps
CPU time 6.15 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:33 PM PDT 24
Peak memory 230032 kb
Host smart-7bd3c34d-db70-4815-ab15-81139d938d1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766929820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1766929820
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.894598555
Short name T365
Test name
Test status
Simulation time 1276156335 ps
CPU time 6.71 seconds
Started Jul 18 05:28:22 PM PDT 24
Finished Jul 18 05:28:32 PM PDT 24
Peak memory 213780 kb
Host smart-ebd56312-c616-4e9e-995f-c52ac18ab88a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894598555 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.894598555
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.1299335391
Short name T917
Test name
Test status
Simulation time 103989996 ps
CPU time 2.19 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:28 PM PDT 24
Peak memory 205596 kb
Host smart-d0f46b89-4243-418f-addf-bf416f11e2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299335391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.1299335391
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2015443414
Short name T1056
Test name
Test status
Simulation time 15589973 ps
CPU time 0.66 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 204072 kb
Host smart-dbc028c4-5068-4363-937d-89f9eb5ad8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015443414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2015443414
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1209102744
Short name T706
Test name
Test status
Simulation time 77100290 ps
CPU time 1.66 seconds
Started Jul 18 05:28:45 PM PDT 24
Finished Jul 18 05:28:50 PM PDT 24
Peak memory 213740 kb
Host smart-bff2474e-45c2-40dd-8a4f-c287417fb5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209102744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1209102744
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1261679671
Short name T1522
Test name
Test status
Simulation time 1430737015 ps
CPU time 8.35 seconds
Started Jul 18 05:28:27 PM PDT 24
Finished Jul 18 05:28:38 PM PDT 24
Peak memory 282664 kb
Host smart-4a5cc1cb-85d3-48a7-9acd-96e6f0af3dab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261679671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1261679671
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.952815943
Short name T1704
Test name
Test status
Simulation time 13389089404 ps
CPU time 72.83 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:29:39 PM PDT 24
Peak memory 378012 kb
Host smart-b86107cd-d42d-4657-aad4-8192f8690b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952815943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.952815943
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1306058757
Short name T694
Test name
Test status
Simulation time 37244116681 ps
CPU time 75.53 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:29:44 PM PDT 24
Peak memory 706096 kb
Host smart-8bd1de9e-4090-440e-8abe-73cd82e77e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306058757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1306058757
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3294904633
Short name T1428
Test name
Test status
Simulation time 413375061 ps
CPU time 1.1 seconds
Started Jul 18 05:28:28 PM PDT 24
Finished Jul 18 05:28:31 PM PDT 24
Peak memory 205204 kb
Host smart-0a0d7636-c3f3-4d39-a513-5cc4c72e7bdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294904633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3294904633
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4061202987
Short name T745
Test name
Test status
Simulation time 137591171 ps
CPU time 3.34 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:30 PM PDT 24
Peak memory 226032 kb
Host smart-8395d206-e9a5-40f3-bf14-b2b64fbe52e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061202987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.4061202987
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.560187782
Short name T269
Test name
Test status
Simulation time 28972279538 ps
CPU time 298.92 seconds
Started Jul 18 05:28:24 PM PDT 24
Finished Jul 18 05:33:27 PM PDT 24
Peak memory 1217368 kb
Host smart-e6ac10df-d2ea-48fe-a98a-53b7f928d5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560187782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.560187782
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.235452676
Short name T235
Test name
Test status
Simulation time 1544843268 ps
CPU time 5.28 seconds
Started Jul 18 05:28:46 PM PDT 24
Finished Jul 18 05:28:55 PM PDT 24
Peak memory 205512 kb
Host smart-de0634b4-5e62-40e9-9993-a4498c662a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235452676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.235452676
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_override.291873058
Short name T527
Test name
Test status
Simulation time 28874760 ps
CPU time 0.69 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:28 PM PDT 24
Peak memory 205216 kb
Host smart-76d6826a-330d-4f6c-83af-2668995ea6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291873058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.291873058
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.3919781596
Short name T1150
Test name
Test status
Simulation time 6213387866 ps
CPU time 208.7 seconds
Started Jul 18 05:28:25 PM PDT 24
Finished Jul 18 05:31:58 PM PDT 24
Peak memory 898024 kb
Host smart-d9e1d726-c168-425e-8770-0f49dd2e84ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919781596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3919781596
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.2463493334
Short name T1014
Test name
Test status
Simulation time 314127086 ps
CPU time 2.58 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:30 PM PDT 24
Peak memory 220844 kb
Host smart-41762ba1-e905-4d43-b6f4-7bb3118f3b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463493334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2463493334
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1752256264
Short name T1334
Test name
Test status
Simulation time 13152640283 ps
CPU time 29.84 seconds
Started Jul 18 05:28:23 PM PDT 24
Finished Jul 18 05:28:57 PM PDT 24
Peak memory 364908 kb
Host smart-7dcbed55-14a3-4031-9600-08dc03f325d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752256264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1752256264
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2312486655
Short name T388
Test name
Test status
Simulation time 3232770641 ps
CPU time 13.07 seconds
Started Jul 18 05:28:27 PM PDT 24
Finished Jul 18 05:28:43 PM PDT 24
Peak memory 217912 kb
Host smart-2b37fb77-8f24-4b66-b36c-30c025859f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312486655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2312486655
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1684414992
Short name T275
Test name
Test status
Simulation time 299739035 ps
CPU time 1.24 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:53 PM PDT 24
Peak memory 205620 kb
Host smart-48affa67-de01-4513-ad27-b22033d17f1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684414992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1684414992
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2052658629
Short name T915
Test name
Test status
Simulation time 250857537 ps
CPU time 1.63 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:28:56 PM PDT 24
Peak memory 205644 kb
Host smart-f6d564b0-27fd-468b-94f4-9eea8b8c1c93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052658629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2052658629
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.3175086660
Short name T107
Test name
Test status
Simulation time 1517858113 ps
CPU time 2.17 seconds
Started Jul 18 05:28:46 PM PDT 24
Finished Jul 18 05:28:53 PM PDT 24
Peak memory 205588 kb
Host smart-28d07b28-6fbd-4405-8aea-082ffa71a187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175086660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.3175086660
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.1204964217
Short name T758
Test name
Test status
Simulation time 492851948 ps
CPU time 1.53 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:54 PM PDT 24
Peak memory 205404 kb
Host smart-4436f9b6-6039-4671-920d-24e54bd6e109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204964217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.1204964217
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2070851029
Short name T725
Test name
Test status
Simulation time 4351537728 ps
CPU time 2.6 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 213932 kb
Host smart-f9b67a41-d7b5-49d7-8b2c-2210d51d5445
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070851029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2070851029
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.819065920
Short name T296
Test name
Test status
Simulation time 784250343 ps
CPU time 4.23 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 217376 kb
Host smart-d5916ce6-cf10-43a1-a9c7-879285675fab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819065920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.819065920
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2883858733
Short name T993
Test name
Test status
Simulation time 8904327643 ps
CPU time 12.76 seconds
Started Jul 18 05:28:45 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 284440 kb
Host smart-c334b9d5-0171-4be3-8b12-61e26a45b62e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883858733 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2883858733
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.516106639
Short name T786
Test name
Test status
Simulation time 2012498683 ps
CPU time 2.73 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:29:00 PM PDT 24
Peak memory 213900 kb
Host smart-7850307d-2471-4d22-b015-5b2da0c3e29b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516106639 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_nack_acqfull.516106639
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.2868204972
Short name T1482
Test name
Test status
Simulation time 1013801779 ps
CPU time 2.56 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 205872 kb
Host smart-7674fe96-7b72-4453-ad0a-1cf7b1dd6ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868204972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.2868204972
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_txstretch.3565086142
Short name T1711
Test name
Test status
Simulation time 472616337 ps
CPU time 1.34 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:28:56 PM PDT 24
Peak memory 222360 kb
Host smart-c9e72d19-6a25-441d-aca6-980d1d400cc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565086142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_nack_txstretch.3565086142
Directory /workspace/19.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/19.i2c_target_perf.4057412061
Short name T336
Test name
Test status
Simulation time 2546633108 ps
CPU time 6.86 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:29:03 PM PDT 24
Peak memory 222028 kb
Host smart-b544703e-d359-4f62-9134-20c1687785d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057412061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.4057412061
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.1481443602
Short name T977
Test name
Test status
Simulation time 494746451 ps
CPU time 2.44 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:29:00 PM PDT 24
Peak memory 205380 kb
Host smart-22d57f99-c60f-48ee-a52e-e342bea26078
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481443602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_smbus_maxlen.1481443602
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3102562141
Short name T410
Test name
Test status
Simulation time 2306915673 ps
CPU time 34.85 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:29:33 PM PDT 24
Peak memory 221216 kb
Host smart-03540dc7-cd80-4af0-8942-a4d4bd908dba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102562141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3102562141
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.2198088375
Short name T1521
Test name
Test status
Simulation time 17813346287 ps
CPU time 51.91 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:29:44 PM PDT 24
Peak memory 247824 kb
Host smart-455ff3a3-89ef-419c-bdde-4696478ee30c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198088375 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.2198088375
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3232107288
Short name T1053
Test name
Test status
Simulation time 2769280408 ps
CPU time 31.81 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:29:29 PM PDT 24
Peak memory 213852 kb
Host smart-77556d3b-7a5d-40a4-ac8e-4c153745f0dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232107288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3232107288
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3012692136
Short name T700
Test name
Test status
Simulation time 31769394967 ps
CPU time 38.05 seconds
Started Jul 18 05:28:46 PM PDT 24
Finished Jul 18 05:29:28 PM PDT 24
Peak memory 769516 kb
Host smart-ee5d63bf-831f-4719-ab93-506c78aab021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012692136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3012692136
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.222689167
Short name T1311
Test name
Test status
Simulation time 383346863 ps
CPU time 11.21 seconds
Started Jul 18 05:28:46 PM PDT 24
Finished Jul 18 05:29:02 PM PDT 24
Peak memory 244012 kb
Host smart-23b63a3b-2e1b-42b7-b0f9-a0874d5b4ed5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222689167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_t
arget_stretch.222689167
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.962164851
Short name T329
Test name
Test status
Simulation time 1420281443 ps
CPU time 6.93 seconds
Started Jul 18 05:28:46 PM PDT 24
Finished Jul 18 05:28:57 PM PDT 24
Peak memory 234708 kb
Host smart-cb4618d0-527e-489a-b5e4-2aaab854e8db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962164851 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.962164851
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.1836351261
Short name T1374
Test name
Test status
Simulation time 60070617 ps
CPU time 1.43 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 205604 kb
Host smart-43a5220a-29df-447a-bf02-01545789b173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836351261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.1836351261
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3639774732
Short name T1057
Test name
Test status
Simulation time 19146498 ps
CPU time 0.67 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 204848 kb
Host smart-d04b43e8-209d-4ac4-b503-bd716b61e36b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639774732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3639774732
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.597527897
Short name T1497
Test name
Test status
Simulation time 106795441 ps
CPU time 1.71 seconds
Started Jul 18 05:26:17 PM PDT 24
Finished Jul 18 05:26:19 PM PDT 24
Peak memory 213728 kb
Host smart-dcf74a89-b052-4d71-8491-da835965e3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597527897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.597527897
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.3190841112
Short name T986
Test name
Test status
Simulation time 394731458 ps
CPU time 20.29 seconds
Started Jul 18 05:26:19 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 288148 kb
Host smart-d7e21dfe-b2dd-42ba-ab08-785f1f856fdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190841112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.3190841112
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3181272248
Short name T679
Test name
Test status
Simulation time 15258574260 ps
CPU time 112.41 seconds
Started Jul 18 05:26:25 PM PDT 24
Finished Jul 18 05:28:21 PM PDT 24
Peak memory 634036 kb
Host smart-16a72516-08a3-4b3d-b84c-9670e2bd69bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181272248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3181272248
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3357035429
Short name T525
Test name
Test status
Simulation time 6431283795 ps
CPU time 43.53 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:27:10 PM PDT 24
Peak memory 606248 kb
Host smart-bdc62f05-6718-424b-a11c-d86276102efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357035429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3357035429
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2051904960
Short name T975
Test name
Test status
Simulation time 358396736 ps
CPU time 1.2 seconds
Started Jul 18 05:26:15 PM PDT 24
Finished Jul 18 05:26:18 PM PDT 24
Peak memory 205236 kb
Host smart-2592721c-54f6-40db-8e4b-404c58022ae8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051904960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2051904960
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3083645691
Short name T219
Test name
Test status
Simulation time 767380848 ps
CPU time 9.26 seconds
Started Jul 18 05:26:15 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 234172 kb
Host smart-6a091c00-aa8e-4f58-a070-a93da26d3bc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083645691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3083645691
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.688402700
Short name T1548
Test name
Test status
Simulation time 4827690236 ps
CPU time 361.78 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:32:26 PM PDT 24
Peak memory 1387016 kb
Host smart-34351d1a-9030-431c-a3d6-3ba58686a24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688402700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.688402700
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3185173284
Short name T19
Test name
Test status
Simulation time 548978548 ps
CPU time 6.48 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:26:34 PM PDT 24
Peak memory 205528 kb
Host smart-4b1e374b-7b4d-4d92-a8fa-2b4e4177ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185173284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3185173284
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.2617460925
Short name T1377
Test name
Test status
Simulation time 54142163 ps
CPU time 0.67 seconds
Started Jul 18 05:26:18 PM PDT 24
Finished Jul 18 05:26:20 PM PDT 24
Peak memory 205236 kb
Host smart-007fd876-d32f-4bf4-8ca7-86099731b353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617460925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2617460925
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.4106418265
Short name T1443
Test name
Test status
Simulation time 1224947138 ps
CPU time 11.94 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:39 PM PDT 24
Peak memory 232612 kb
Host smart-c02d8342-2280-4365-95ec-900a70add1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106418265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.4106418265
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.2866088123
Short name T1174
Test name
Test status
Simulation time 6104327047 ps
CPU time 138.81 seconds
Started Jul 18 05:26:16 PM PDT 24
Finished Jul 18 05:28:36 PM PDT 24
Peak memory 205668 kb
Host smart-dfc8d9ea-3729-4868-99e6-06c5b32c99bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866088123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2866088123
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3309726394
Short name T1336
Test name
Test status
Simulation time 2014127880 ps
CPU time 34.59 seconds
Started Jul 18 05:26:19 PM PDT 24
Finished Jul 18 05:26:55 PM PDT 24
Peak memory 388904 kb
Host smart-281371df-a1a0-4404-bdef-61bd06e5ba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309726394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3309726394
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.270889329
Short name T734
Test name
Test status
Simulation time 1392983867 ps
CPU time 15.95 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:40 PM PDT 24
Peak memory 213692 kb
Host smart-2f9b0b30-3137-4ef0-b6bc-a240e8a78433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270889329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.270889329
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.4103700514
Short name T172
Test name
Test status
Simulation time 400554480 ps
CPU time 0.91 seconds
Started Jul 18 05:26:18 PM PDT 24
Finished Jul 18 05:26:20 PM PDT 24
Peak memory 223904 kb
Host smart-24bbdaf7-0228-406a-a740-89655a6361a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103700514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.4103700514
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1333189897
Short name T1733
Test name
Test status
Simulation time 228221114 ps
CPU time 1.36 seconds
Started Jul 18 05:26:18 PM PDT 24
Finished Jul 18 05:26:21 PM PDT 24
Peak memory 205440 kb
Host smart-9bfc1f0d-7c5b-41f3-977b-ac76454edde6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333189897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1333189897
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3493853264
Short name T1395
Test name
Test status
Simulation time 277062106 ps
CPU time 1.03 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:25 PM PDT 24
Peak memory 205420 kb
Host smart-ddadcedd-1ae9-46b5-92e1-ce0ad72fe79b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493853264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3493853264
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.4269685574
Short name T820
Test name
Test status
Simulation time 2722712793 ps
CPU time 2.84 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:30 PM PDT 24
Peak memory 205680 kb
Host smart-6fc77c61-6854-4bd9-930d-2bccb1ec1881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269685574 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.4269685574
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.1457773583
Short name T281
Test name
Test status
Simulation time 666084757 ps
CPU time 1.56 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:29 PM PDT 24
Peak memory 205380 kb
Host smart-6fdba479-dd88-4b2c-97d7-f649206b3816
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457773583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.1457773583
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.606806238
Short name T864
Test name
Test status
Simulation time 790806152 ps
CPU time 1.79 seconds
Started Jul 18 05:26:20 PM PDT 24
Finished Jul 18 05:26:24 PM PDT 24
Peak memory 205596 kb
Host smart-4ba418d8-d959-4c3a-ac1a-4cdccea5f0be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606806238 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.606806238
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2241755678
Short name T778
Test name
Test status
Simulation time 2536566469 ps
CPU time 4.38 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:31 PM PDT 24
Peak memory 214128 kb
Host smart-b5bf8879-4dd2-4b73-8e23-2cddaa77a035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241755678 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2241755678
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3642846800
Short name T1707
Test name
Test status
Simulation time 15493521906 ps
CPU time 31.8 seconds
Started Jul 18 05:26:18 PM PDT 24
Finished Jul 18 05:26:52 PM PDT 24
Peak memory 787764 kb
Host smart-0dee6e39-cc8e-49e1-9dc1-e835300f87a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642846800 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3642846800
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.3078935287
Short name T61
Test name
Test status
Simulation time 472160944 ps
CPU time 2.54 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 213812 kb
Host smart-dfd7571f-2d3a-40b7-9576-071f5068d585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078935287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.3078935287
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.3449368632
Short name T789
Test name
Test status
Simulation time 414302050 ps
CPU time 2.39 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:29 PM PDT 24
Peak memory 205628 kb
Host smart-7c06b80f-ab77-4940-b071-78ee270bc925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449368632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.3449368632
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_txstretch.1996302629
Short name T1361
Test name
Test status
Simulation time 130028292 ps
CPU time 1.5 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:27 PM PDT 24
Peak memory 222232 kb
Host smart-8d10852c-db51-4ded-b58f-80839253bc62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996302629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_nack_txstretch.1996302629
Directory /workspace/2.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/2.i2c_target_perf.1186841110
Short name T502
Test name
Test status
Simulation time 3718476523 ps
CPU time 5.78 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:31 PM PDT 24
Peak memory 222012 kb
Host smart-75b04e26-d237-4090-816b-903e7ee04090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186841110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.1186841110
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.634468925
Short name T163
Test name
Test status
Simulation time 447934803 ps
CPU time 2.08 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:26:30 PM PDT 24
Peak memory 205476 kb
Host smart-dab5f0e8-9e81-4240-8d76-727f2bee803c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634468925 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_smbus_maxlen.634468925
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1676999200
Short name T1403
Test name
Test status
Simulation time 588999408 ps
CPU time 15.33 seconds
Started Jul 18 05:26:20 PM PDT 24
Finished Jul 18 05:26:37 PM PDT 24
Peak memory 213984 kb
Host smart-8c4ada9a-9a91-4155-9b24-79d455467fb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676999200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1676999200
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.1635211512
Short name T1276
Test name
Test status
Simulation time 34461033557 ps
CPU time 751.76 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:38:56 PM PDT 24
Peak memory 4094308 kb
Host smart-84ec8e34-9fd9-47eb-b639-018d61c7e326
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635211512 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.1635211512
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3478366322
Short name T352
Test name
Test status
Simulation time 3305847806 ps
CPU time 38.73 seconds
Started Jul 18 05:26:17 PM PDT 24
Finished Jul 18 05:26:57 PM PDT 24
Peak memory 213888 kb
Host smart-eb790513-c8b2-4d92-bdef-83001c74f277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478366322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3478366322
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.3434854693
Short name T1011
Test name
Test status
Simulation time 55306604852 ps
CPU time 1731.13 seconds
Started Jul 18 05:26:20 PM PDT 24
Finished Jul 18 05:55:14 PM PDT 24
Peak memory 8718128 kb
Host smart-abcc6c4b-c708-4bc7-a547-ad85e8af2d81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434854693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.3434854693
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.368395845
Short name T481
Test name
Test status
Simulation time 2095789639 ps
CPU time 15.53 seconds
Started Jul 18 05:26:18 PM PDT 24
Finished Jul 18 05:26:35 PM PDT 24
Peak memory 624540 kb
Host smart-80fb8f87-a332-4161-b18e-23acda042734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368395845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.368395845
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1228292731
Short name T1400
Test name
Test status
Simulation time 2701785279 ps
CPU time 7.66 seconds
Started Jul 18 05:26:15 PM PDT 24
Finished Jul 18 05:26:24 PM PDT 24
Peak memory 231020 kb
Host smart-9cbe4de4-3906-4717-a5eb-bf8a93940c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228292731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1228292731
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.1655823216
Short name T1389
Test name
Test status
Simulation time 560168267 ps
CPU time 6.21 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:31 PM PDT 24
Peak memory 221824 kb
Host smart-3eba7532-37b5-468a-aef0-f69fece2d5df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655823216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.1655823216
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2794443030
Short name T1442
Test name
Test status
Simulation time 21802545 ps
CPU time 0.61 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 204748 kb
Host smart-641bc115-7ab4-42ee-a9a0-2c629209e612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794443030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2794443030
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.4265579972
Short name T638
Test name
Test status
Simulation time 226179733 ps
CPU time 2.96 seconds
Started Jul 18 05:28:45 PM PDT 24
Finished Jul 18 05:28:48 PM PDT 24
Peak memory 213800 kb
Host smart-b125cf2e-c1ff-49b4-be72-94abc16f9a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265579972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.4265579972
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1558798760
Short name T1026
Test name
Test status
Simulation time 497460740 ps
CPU time 3.34 seconds
Started Jul 18 05:28:49 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 229268 kb
Host smart-4dc159d6-6bbe-4de3-a6bf-2089dd614e88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558798760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1558798760
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2046078948
Short name T1278
Test name
Test status
Simulation time 2744951182 ps
CPU time 71.65 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:30:05 PM PDT 24
Peak memory 331204 kb
Host smart-2a15fae0-c632-496a-8121-43822ad5a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046078948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2046078948
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.4251105726
Short name T939
Test name
Test status
Simulation time 7951057294 ps
CPU time 136.03 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:31:09 PM PDT 24
Peak memory 655772 kb
Host smart-1b83bed5-8614-450c-be80-b22402cd58e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251105726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.4251105726
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3828993557
Short name T518
Test name
Test status
Simulation time 110165566 ps
CPU time 0.96 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 205188 kb
Host smart-0b0d6a73-7d66-444a-b2f3-f6d472a863ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828993557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3828993557
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2929688797
Short name T517
Test name
Test status
Simulation time 284742232 ps
CPU time 4.22 seconds
Started Jul 18 05:28:45 PM PDT 24
Finished Jul 18 05:28:52 PM PDT 24
Peak memory 205676 kb
Host smart-92e1015f-bb24-4df2-bcdf-ba434faef6d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929688797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2929688797
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3939877972
Short name T102
Test name
Test status
Simulation time 4163724946 ps
CPU time 96.32 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:30:37 PM PDT 24
Peak memory 1192876 kb
Host smart-6db84fd2-985f-411a-b8a1-fa5e767f9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939877972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3939877972
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3929698451
Short name T1586
Test name
Test status
Simulation time 294835852 ps
CPU time 4.67 seconds
Started Jul 18 05:28:45 PM PDT 24
Finished Jul 18 05:28:54 PM PDT 24
Peak memory 205516 kb
Host smart-5bfc5c9f-90b7-4cf0-9401-c65e5506b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929698451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3929698451
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_override.1838139916
Short name T415
Test name
Test status
Simulation time 66820104 ps
CPU time 0.65 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:52 PM PDT 24
Peak memory 205208 kb
Host smart-685e17bc-fb00-4196-abda-7dad0777fc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838139916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1838139916
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2208252278
Short name T367
Test name
Test status
Simulation time 28508831914 ps
CPU time 519.92 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:37:37 PM PDT 24
Peak memory 213976 kb
Host smart-cd9ee340-5e9c-4470-b987-2d8a64fe5dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208252278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2208252278
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.3725795563
Short name T1266
Test name
Test status
Simulation time 147545270 ps
CPU time 6.4 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:29:04 PM PDT 24
Peak memory 230012 kb
Host smart-ac9dad01-a058-4e6e-80ac-d80e04af5759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725795563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.3725795563
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2259589858
Short name T1613
Test name
Test status
Simulation time 1843837677 ps
CPU time 86.87 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:30:24 PM PDT 24
Peak memory 383736 kb
Host smart-4e68957f-e37f-4018-8d58-4c4440627fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259589858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2259589858
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2611818628
Short name T1485
Test name
Test status
Simulation time 877261714 ps
CPU time 13.35 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 219948 kb
Host smart-f577b97a-b0dd-48ca-ab98-084d9230fef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611818628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2611818628
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1775135078
Short name T310
Test name
Test status
Simulation time 1872680223 ps
CPU time 4.88 seconds
Started Jul 18 05:28:46 PM PDT 24
Finished Jul 18 05:28:55 PM PDT 24
Peak memory 214112 kb
Host smart-e2c4e87a-d1cb-43d7-91b0-bee613b8576a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775135078 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1775135078
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3260043890
Short name T654
Test name
Test status
Simulation time 160911888 ps
CPU time 1.12 seconds
Started Jul 18 05:28:49 PM PDT 24
Finished Jul 18 05:28:56 PM PDT 24
Peak memory 205424 kb
Host smart-9d462d8b-6867-4780-8644-ac1ba2c9d964
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260043890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.3260043890
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.504247799
Short name T731
Test name
Test status
Simulation time 307756712 ps
CPU time 1.21 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:54 PM PDT 24
Peak memory 205564 kb
Host smart-7e6e142c-a008-46ca-b824-93786d517837
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504247799 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.504247799
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.3739651765
Short name T1645
Test name
Test status
Simulation time 1731265988 ps
CPU time 2.65 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:29:00 PM PDT 24
Peak memory 205588 kb
Host smart-344a39df-9112-478d-a3e2-5851c0065b01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739651765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.3739651765
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.715761216
Short name T552
Test name
Test status
Simulation time 306901630 ps
CPU time 0.98 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:28:57 PM PDT 24
Peak memory 205364 kb
Host smart-cdb650ce-9727-4f81-9b40-4cfb0f23a485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715761216 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.715761216
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2671155619
Short name T1410
Test name
Test status
Simulation time 279935209 ps
CPU time 1.8 seconds
Started Jul 18 05:29:06 PM PDT 24
Finished Jul 18 05:29:09 PM PDT 24
Peak memory 216152 kb
Host smart-8932aa21-a633-469c-9106-5f593feeaa7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671155619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2671155619
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.559259609
Short name T1134
Test name
Test status
Simulation time 1197426390 ps
CPU time 8.41 seconds
Started Jul 18 05:28:49 PM PDT 24
Finished Jul 18 05:29:04 PM PDT 24
Peak memory 222604 kb
Host smart-5e8c6731-5ec5-4ad3-ad31-3c45bb179ef8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559259609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.559259609
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2927905317
Short name T955
Test name
Test status
Simulation time 17216688292 ps
CPU time 438.53 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:36:10 PM PDT 24
Peak memory 4221752 kb
Host smart-7739017e-999a-4f90-a3a8-b843ca533769
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927905317 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2927905317
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.497303620
Short name T1022
Test name
Test status
Simulation time 1552701098 ps
CPU time 2.87 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:29:00 PM PDT 24
Peak memory 213852 kb
Host smart-6f11fb03-b8b7-4e05-8430-f2bb72b54878
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497303620 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_nack_acqfull.497303620
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.1394744332
Short name T1175
Test name
Test status
Simulation time 2253514329 ps
CPU time 2.66 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 205680 kb
Host smart-4ef6c05d-63f7-49a7-94ae-e4c2f8ba97f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394744332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.1394744332
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_txstretch.1004086008
Short name T1694
Test name
Test status
Simulation time 134542377 ps
CPU time 1.58 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 222244 kb
Host smart-7da205d8-b64b-4da9-9f4d-d936d85af30f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004086008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_nack_txstretch.1004086008
Directory /workspace/20.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/20.i2c_target_perf.1198811839
Short name T1578
Test name
Test status
Simulation time 1793026280 ps
CPU time 3.46 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 213836 kb
Host smart-9fbdf942-10d6-4635-852f-2b2130da8028
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198811839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.1198811839
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.2039542473
Short name T1718
Test name
Test status
Simulation time 1372551842 ps
CPU time 1.97 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:29:02 PM PDT 24
Peak memory 205388 kb
Host smart-17117930-6fd5-4198-a810-58adfcb0414c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039542473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_smbus_maxlen.2039542473
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2586283371
Short name T1591
Test name
Test status
Simulation time 2941205951 ps
CPU time 11.82 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:10 PM PDT 24
Peak memory 213840 kb
Host smart-ff569f01-7c3c-419a-ac8f-929ab4a3e137
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586283371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2586283371
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.731093791
Short name T1632
Test name
Test status
Simulation time 16140627707 ps
CPU time 336.7 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:34:37 PM PDT 24
Peak memory 2466892 kb
Host smart-351025fe-7d91-4a4d-82e6-c4e5b81f4c7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731093791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_target_stress_all.731093791
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2208117354
Short name T1407
Test name
Test status
Simulation time 866933926 ps
CPU time 38.89 seconds
Started Jul 18 05:28:45 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 213788 kb
Host smart-f694a9c7-4e55-4b26-8bdc-797f5cd6b5e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208117354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2208117354
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2535709980
Short name T1249
Test name
Test status
Simulation time 46899708688 ps
CPU time 21.95 seconds
Started Jul 18 05:28:45 PM PDT 24
Finished Jul 18 05:29:11 PM PDT 24
Peak memory 502628 kb
Host smart-9c204057-cdf8-430e-8173-c1cabe273d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535709980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2535709980
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.265620224
Short name T1624
Test name
Test status
Simulation time 4968441547 ps
CPU time 18.17 seconds
Started Jul 18 05:28:46 PM PDT 24
Finished Jul 18 05:29:09 PM PDT 24
Peak memory 407784 kb
Host smart-502d6a8a-e947-40fe-b3bf-48d435e04af0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265620224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.265620224
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1761804935
Short name T503
Test name
Test status
Simulation time 4790795114 ps
CPU time 6.73 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 214000 kb
Host smart-9b301c0c-7320-4381-a9ef-5be53c0e0042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761804935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1761804935
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.1701400676
Short name T349
Test name
Test status
Simulation time 157188706 ps
CPU time 3.33 seconds
Started Jul 18 05:28:49 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 206280 kb
Host smart-7c449fe8-6c2c-4606-ae11-7be34b1b44b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701400676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1701400676
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1026031106
Short name T688
Test name
Test status
Simulation time 16126585 ps
CPU time 0.64 seconds
Started Jul 18 05:28:55 PM PDT 24
Finished Jul 18 05:29:02 PM PDT 24
Peak memory 204780 kb
Host smart-a62010bf-c5c9-42b2-b171-341ffc231791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026031106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1026031106
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2199007613
Short name T891
Test name
Test status
Simulation time 191511412 ps
CPU time 2.55 seconds
Started Jul 18 05:28:49 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 213740 kb
Host smart-3c40ece2-6f28-48c9-97fd-22f73d096b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199007613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2199007613
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2893854041
Short name T441
Test name
Test status
Simulation time 270313942 ps
CPU time 13.33 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:29:06 PM PDT 24
Peak memory 257216 kb
Host smart-178379fb-7be4-45cc-ba5b-d7c2212765f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893854041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2893854041
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.843383304
Short name T587
Test name
Test status
Simulation time 10133677899 ps
CPU time 64.62 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:30:00 PM PDT 24
Peak memory 534212 kb
Host smart-095195c7-ecfc-46c6-9c40-b01b11fcf2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843383304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.843383304
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3093917645
Short name T467
Test name
Test status
Simulation time 7586689049 ps
CPU time 126.89 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 623192 kb
Host smart-fe99707c-8781-46cf-aef4-605ef491cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093917645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3093917645
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1095969146
Short name T1569
Test name
Test status
Simulation time 576301599 ps
CPU time 1.19 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 205220 kb
Host smart-cb635989-e373-4e08-99eb-1d4695548f2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095969146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1095969146
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2561961398
Short name T1081
Test name
Test status
Simulation time 140174755 ps
CPU time 6.62 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:29:02 PM PDT 24
Peak memory 205508 kb
Host smart-41eb5079-220d-4ca5-bae0-e779610d806f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561961398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2561961398
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2065187618
Short name T1037
Test name
Test status
Simulation time 17565940180 ps
CPU time 209.3 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:32:24 PM PDT 24
Peak memory 993784 kb
Host smart-36e50bc5-cdf9-4960-a152-e28ecc3f33d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065187618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2065187618
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.844301205
Short name T861
Test name
Test status
Simulation time 507724903 ps
CPU time 20.11 seconds
Started Jul 18 05:28:57 PM PDT 24
Finished Jul 18 05:29:23 PM PDT 24
Peak memory 205488 kb
Host smart-9753ee0b-e80d-4da5-93e0-1b46cf0c4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844301205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.844301205
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.403627999
Short name T599
Test name
Test status
Simulation time 17788207 ps
CPU time 0.68 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 205188 kb
Host smart-6a37a6d5-5f86-4092-8ae5-87761d755c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403627999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.403627999
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.844886739
Short name T801
Test name
Test status
Simulation time 539473684 ps
CPU time 9.37 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:29:06 PM PDT 24
Peak memory 261124 kb
Host smart-65ba659f-5c82-405c-adc8-29b907594785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844886739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.844886739
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.3330754001
Short name T613
Test name
Test status
Simulation time 1197596994 ps
CPU time 12.83 seconds
Started Jul 18 05:28:56 PM PDT 24
Finished Jul 18 05:29:15 PM PDT 24
Peak memory 221684 kb
Host smart-6bcb9e1e-2df0-49e7-aef1-dcb6e7d9ac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330754001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3330754001
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2546505533
Short name T1699
Test name
Test status
Simulation time 1046855788 ps
CPU time 53.59 seconds
Started Jul 18 05:28:46 PM PDT 24
Finished Jul 18 05:29:43 PM PDT 24
Peak memory 332904 kb
Host smart-ca1bd7d9-19e0-428c-847e-cd4a7d3cf0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546505533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2546505533
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2635049627
Short name T247
Test name
Test status
Simulation time 2768382306 ps
CPU time 27.73 seconds
Started Jul 18 05:28:54 PM PDT 24
Finished Jul 18 05:29:29 PM PDT 24
Peak memory 213772 kb
Host smart-8b8ac3a4-b76a-4b82-9cd5-1cfebfb07441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635049627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2635049627
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.374460399
Short name T759
Test name
Test status
Simulation time 4026221920 ps
CPU time 5.77 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:29:06 PM PDT 24
Peak memory 221960 kb
Host smart-f29ffc28-347f-4aaa-b644-18fb2cd8f030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374460399 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.374460399
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1028970270
Short name T375
Test name
Test status
Simulation time 328190041 ps
CPU time 1.19 seconds
Started Jul 18 05:28:58 PM PDT 24
Finished Jul 18 05:29:04 PM PDT 24
Peak memory 205460 kb
Host smart-2938b510-deb4-4323-89f8-83660eb1b366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028970270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1028970270
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3152416046
Short name T83
Test name
Test status
Simulation time 769697239 ps
CPU time 1.66 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:01 PM PDT 24
Peak memory 210064 kb
Host smart-6739720e-23b7-4eea-b58d-60a76f71c960
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152416046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3152416046
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.1370548776
Short name T1562
Test name
Test status
Simulation time 451791949 ps
CPU time 2.55 seconds
Started Jul 18 05:28:57 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 205564 kb
Host smart-60060838-05d4-4b2f-9c57-08cc72ecfa2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370548776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.1370548776
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.3290911825
Short name T1552
Test name
Test status
Simulation time 106538179 ps
CPU time 1.42 seconds
Started Jul 18 05:28:57 PM PDT 24
Finished Jul 18 05:29:04 PM PDT 24
Peak memory 205444 kb
Host smart-f3798e63-b0d2-400e-9163-2952b7330dd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290911825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.3290911825
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2349443367
Short name T1541
Test name
Test status
Simulation time 2341542988 ps
CPU time 1.71 seconds
Started Jul 18 05:28:59 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 205696 kb
Host smart-3d185fc0-45ac-44ba-bf1f-2e7ccc7f4c75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349443367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2349443367
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1268095611
Short name T480
Test name
Test status
Simulation time 988752446 ps
CPU time 4.92 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:57 PM PDT 24
Peak memory 214164 kb
Host smart-12a6d647-49fa-4be4-8fda-a883424f1111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268095611 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1268095611
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.407428860
Short name T496
Test name
Test status
Simulation time 7611121378 ps
CPU time 8.34 seconds
Started Jul 18 05:28:54 PM PDT 24
Finished Jul 18 05:29:09 PM PDT 24
Peak memory 205656 kb
Host smart-e04c7887-dd65-40cc-bd41-75e3eb2b84bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407428860 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.407428860
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.2961047235
Short name T1462
Test name
Test status
Simulation time 2028864525 ps
CPU time 2.72 seconds
Started Jul 18 05:28:57 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 213824 kb
Host smart-dd28b2ba-4b68-449f-849a-babad25ff957
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961047235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_acqfull.2961047235
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.1529921005
Short name T1236
Test name
Test status
Simulation time 1900192268 ps
CPU time 2.62 seconds
Started Jul 18 05:28:57 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 205612 kb
Host smart-2e73cdd1-dd6b-4985-974c-57c9c2389bc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529921005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.1529921005
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_txstretch.2093678628
Short name T1656
Test name
Test status
Simulation time 149207904 ps
CPU time 1.45 seconds
Started Jul 18 05:28:55 PM PDT 24
Finished Jul 18 05:29:03 PM PDT 24
Peak memory 222440 kb
Host smart-03e59d76-803c-43ec-ae1a-23fc2034fec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093678628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_nack_txstretch.2093678628
Directory /workspace/21.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/21.i2c_target_perf.2645722260
Short name T439
Test name
Test status
Simulation time 754450602 ps
CPU time 3.36 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:03 PM PDT 24
Peak memory 217840 kb
Host smart-a8b01dca-b4d1-46a1-be82-5b55c5c5dfbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645722260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.2645722260
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.3344994892
Short name T1652
Test name
Test status
Simulation time 480469218 ps
CPU time 2.13 seconds
Started Jul 18 05:28:58 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 205440 kb
Host smart-d51de3f0-7561-41f3-89b4-268cd83b31fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344994892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_smbus_maxlen.3344994892
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.2782587185
Short name T427
Test name
Test status
Simulation time 1549510096 ps
CPU time 29.37 seconds
Started Jul 18 05:28:56 PM PDT 24
Finished Jul 18 05:29:31 PM PDT 24
Peak memory 213808 kb
Host smart-d34d563d-7cb4-48fb-965d-6d5df57fcf15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782587185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.2782587185
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.952442809
Short name T42
Test name
Test status
Simulation time 22494879435 ps
CPU time 154.09 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:31:35 PM PDT 24
Peak memory 1500240 kb
Host smart-230ab764-2307-401d-96b2-c6d2add79e30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952442809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_stress_all.952442809
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.967523317
Short name T1756
Test name
Test status
Simulation time 268957886 ps
CPU time 9.5 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:29:10 PM PDT 24
Peak memory 205600 kb
Host smart-cce65013-78ac-4797-a42f-e96f97c829ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967523317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.967523317
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.2874794666
Short name T287
Test name
Test status
Simulation time 58703368827 ps
CPU time 406.36 seconds
Started Jul 18 05:28:54 PM PDT 24
Finished Jul 18 05:35:48 PM PDT 24
Peak memory 3393116 kb
Host smart-0e453f01-ce8b-4d7e-9aa2-9f104653103d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874794666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.2874794666
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.2222807081
Short name T533
Test name
Test status
Simulation time 161014682 ps
CPU time 1.85 seconds
Started Jul 18 05:28:54 PM PDT 24
Finished Jul 18 05:29:03 PM PDT 24
Peak memory 205568 kb
Host smart-0c095038-2865-4e52-add3-637f486d16b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222807081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.2222807081
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.4109217252
Short name T1682
Test name
Test status
Simulation time 4967537646 ps
CPU time 7.05 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:06 PM PDT 24
Peak memory 213904 kb
Host smart-526b18a7-3bd1-422b-8f93-760824f71a29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109217252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.4109217252
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.550123487
Short name T9
Test name
Test status
Simulation time 674625081 ps
CPU time 9.39 seconds
Started Jul 18 05:28:57 PM PDT 24
Finished Jul 18 05:29:12 PM PDT 24
Peak memory 221068 kb
Host smart-b716a62a-9818-4aad-abb7-4ee3f7364fcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550123487 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.550123487
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.738746803
Short name T1042
Test name
Test status
Simulation time 40668789 ps
CPU time 0.61 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:00 PM PDT 24
Peak memory 204760 kb
Host smart-a06b098f-32af-481f-85a0-8cae90fe82b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738746803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.738746803
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.407687053
Short name T17
Test name
Test status
Simulation time 106105344 ps
CPU time 1.61 seconds
Started Jul 18 05:28:48 PM PDT 24
Finished Jul 18 05:28:55 PM PDT 24
Peak memory 213852 kb
Host smart-24c76230-692d-414d-a9bf-60e2568a0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407687053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.407687053
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1779665034
Short name T1551
Test name
Test status
Simulation time 215217488 ps
CPU time 10.84 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:29:07 PM PDT 24
Peak memory 246888 kb
Host smart-7f70f93d-2db1-47a5-b91d-7a8abd420f43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779665034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1779665034
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2681191226
Short name T1603
Test name
Test status
Simulation time 3036922441 ps
CPU time 176.64 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:31:55 PM PDT 24
Peak memory 453888 kb
Host smart-d59e4398-c1cc-43b7-b7aa-ef34e4d3d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681191226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2681191226
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1140095106
Short name T448
Test name
Test status
Simulation time 3163375077 ps
CPU time 107.65 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:30:44 PM PDT 24
Peak memory 600424 kb
Host smart-e4462972-c246-40cc-89e8-e72771878487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140095106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1140095106
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.1848132553
Short name T1429
Test name
Test status
Simulation time 116722104 ps
CPU time 1.13 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:00 PM PDT 24
Peak memory 205216 kb
Host smart-ab69b33c-e069-4b32-9437-7ff039b39f70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848132553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.1848132553
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3876322491
Short name T1130
Test name
Test status
Simulation time 118497625 ps
CPU time 2.54 seconds
Started Jul 18 05:28:49 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 205500 kb
Host smart-93a05c53-acd5-4046-b650-4f7150d274ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876322491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3876322491
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.479682283
Short name T1729
Test name
Test status
Simulation time 17186869356 ps
CPU time 70.88 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:30:03 PM PDT 24
Peak memory 821340 kb
Host smart-707c7533-4bbe-4510-8892-f8515d77c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479682283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.479682283
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.726156134
Short name T1210
Test name
Test status
Simulation time 1480752220 ps
CPU time 16.81 seconds
Started Jul 18 05:28:57 PM PDT 24
Finished Jul 18 05:29:19 PM PDT 24
Peak memory 205500 kb
Host smart-7f10f590-24d0-45d7-b45c-2feb02061209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726156134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.726156134
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.1185755476
Short name T1000
Test name
Test status
Simulation time 61017890 ps
CPU time 0.66 seconds
Started Jul 18 05:28:55 PM PDT 24
Finished Jul 18 05:29:02 PM PDT 24
Peak memory 205236 kb
Host smart-d9e0c260-5db0-4051-a0c7-14c462ef3821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185755476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1185755476
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1423536022
Short name T1478
Test name
Test status
Simulation time 8869424695 ps
CPU time 92.61 seconds
Started Jul 18 05:28:49 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 213780 kb
Host smart-97d64112-15c6-40f3-a6e4-0922d0032318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423536022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1423536022
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.396565208
Short name T1390
Test name
Test status
Simulation time 273771287 ps
CPU time 1.53 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:29:00 PM PDT 24
Peak memory 205496 kb
Host smart-13453566-4572-4647-9186-9ea044418735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396565208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.396565208
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1293466811
Short name T248
Test name
Test status
Simulation time 9390639515 ps
CPU time 32.6 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 412260 kb
Host smart-cb069f41-c314-4699-9079-74c77ce2ae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293466811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1293466811
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.1129008778
Short name T931
Test name
Test status
Simulation time 14116652815 ps
CPU time 38.37 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:39 PM PDT 24
Peak memory 213780 kb
Host smart-a4cf4ee3-d705-4ebd-8255-9fbc48ef3c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129008778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1129008778
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3442370556
Short name T808
Test name
Test status
Simulation time 3192611497 ps
CPU time 5.01 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 218168 kb
Host smart-3b695a83-eb32-4619-88d1-bb2d8a7b4aca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442370556 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3442370556
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2541696275
Short name T542
Test name
Test status
Simulation time 175755603 ps
CPU time 1.07 seconds
Started Jul 18 05:28:55 PM PDT 24
Finished Jul 18 05:29:02 PM PDT 24
Peak memory 205380 kb
Host smart-2b845bba-d348-4d6d-b343-4764aa329372
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541696275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2541696275
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2539702930
Short name T501
Test name
Test status
Simulation time 436627447 ps
CPU time 1.09 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:01 PM PDT 24
Peak memory 213824 kb
Host smart-7a7e2b37-4fe1-4a82-8560-1fae7f0c456a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539702930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2539702930
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.2441530984
Short name T790
Test name
Test status
Simulation time 1363089845 ps
CPU time 2.02 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:01 PM PDT 24
Peak memory 205464 kb
Host smart-886bdbe6-e9fd-4f7e-acea-fe9441788eb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441530984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.2441530984
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.304868970
Short name T1596
Test name
Test status
Simulation time 482456128 ps
CPU time 1.15 seconds
Started Jul 18 05:28:50 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 205376 kb
Host smart-aec0f3db-975f-42cd-895c-e74acc592135
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304868970 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.304868970
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2705494398
Short name T1693
Test name
Test status
Simulation time 240741798 ps
CPU time 1.97 seconds
Started Jul 18 05:28:55 PM PDT 24
Finished Jul 18 05:29:03 PM PDT 24
Peak memory 213800 kb
Host smart-9d2b5ba0-7b09-454f-890e-544f6d110639
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705494398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2705494398
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3942797505
Short name T930
Test name
Test status
Simulation time 1200711379 ps
CPU time 4.99 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:57 PM PDT 24
Peak memory 213948 kb
Host smart-85d9cd8f-f314-423a-96f4-2bef9c195f1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942797505 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3942797505
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.4030998284
Short name T927
Test name
Test status
Simulation time 7365513329 ps
CPU time 14.91 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:14 PM PDT 24
Peak memory 501748 kb
Host smart-07b419da-d760-40e0-b077-7172fc102d37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030998284 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.4030998284
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.2088590396
Short name T1371
Test name
Test status
Simulation time 3409706591 ps
CPU time 3.17 seconds
Started Jul 18 05:28:58 PM PDT 24
Finished Jul 18 05:29:06 PM PDT 24
Peak memory 213896 kb
Host smart-1b5c577b-77b3-4318-bcf3-0dc425feefc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088590396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.2088590396
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.1062508168
Short name T56
Test name
Test status
Simulation time 1030340287 ps
CPU time 2.7 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:29:03 PM PDT 24
Peak memory 205628 kb
Host smart-b71dd4ed-64f6-4aaf-873a-1db8cdb08fdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062508168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.1062508168
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_txstretch.2443515648
Short name T1352
Test name
Test status
Simulation time 144518047 ps
CPU time 1.56 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:01 PM PDT 24
Peak memory 222584 kb
Host smart-2e6fc532-0c53-43ba-b3ae-9835d02399d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443515648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_nack_txstretch.2443515648
Directory /workspace/22.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/22.i2c_target_perf.2188505773
Short name T1561
Test name
Test status
Simulation time 1223873050 ps
CPU time 5.06 seconds
Started Jul 18 05:28:54 PM PDT 24
Finished Jul 18 05:29:06 PM PDT 24
Peak memory 214528 kb
Host smart-e09513da-a2fd-4d27-9b7e-a64ddbd540fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188505773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.2188505773
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.2016547092
Short name T1737
Test name
Test status
Simulation time 461706600 ps
CPU time 2.21 seconds
Started Jul 18 05:28:56 PM PDT 24
Finished Jul 18 05:29:04 PM PDT 24
Peak memory 205396 kb
Host smart-543cd03b-a9fa-45ed-8dbd-90ba91d3008c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016547092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_smbus_maxlen.2016547092
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.2179849426
Short name T253
Test name
Test status
Simulation time 1071339144 ps
CPU time 34.38 seconds
Started Jul 18 05:28:53 PM PDT 24
Finished Jul 18 05:29:35 PM PDT 24
Peak memory 213816 kb
Host smart-a372ba43-b981-4d6b-9ff2-9508229040ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179849426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.2179849426
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.247149234
Short name T1171
Test name
Test status
Simulation time 62845433064 ps
CPU time 29.37 seconds
Started Jul 18 05:28:54 PM PDT 24
Finished Jul 18 05:29:30 PM PDT 24
Peak memory 238556 kb
Host smart-33856a65-6901-412e-81e6-8c6618403fa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247149234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.i2c_target_stress_all.247149234
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.669377053
Short name T297
Test name
Test status
Simulation time 1472019615 ps
CPU time 64 seconds
Started Jul 18 05:28:54 PM PDT 24
Finished Jul 18 05:30:05 PM PDT 24
Peak memory 217328 kb
Host smart-69cc5efa-8a2f-4be1-9390-02f17529abee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669377053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.669377053
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.112003388
Short name T1411
Test name
Test status
Simulation time 53130898398 ps
CPU time 166.77 seconds
Started Jul 18 05:28:51 PM PDT 24
Finished Jul 18 05:31:44 PM PDT 24
Peak memory 1751376 kb
Host smart-c2891b6d-c2a7-40b7-b25b-7c77c75b968d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112003388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.112003388
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.822363021
Short name T677
Test name
Test status
Simulation time 3111591389 ps
CPU time 20.22 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:19 PM PDT 24
Peak memory 449192 kb
Host smart-91951474-abdb-472c-8fea-f85697ce49fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822363021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stretch.822363021
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.770460790
Short name T393
Test name
Test status
Simulation time 1461256744 ps
CPU time 7.36 seconds
Started Jul 18 05:28:47 PM PDT 24
Finished Jul 18 05:28:59 PM PDT 24
Peak memory 221900 kb
Host smart-a883bb25-7012-4699-b179-1476de94c2bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770460790 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.770460790
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.2248152284
Short name T546
Test name
Test status
Simulation time 380875960 ps
CPU time 5.66 seconds
Started Jul 18 05:28:56 PM PDT 24
Finished Jul 18 05:29:08 PM PDT 24
Peak memory 205620 kb
Host smart-f00fe605-93cd-4e48-9c84-2364a286595f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248152284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.2248152284
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2280491527
Short name T338
Test name
Test status
Simulation time 47668636 ps
CPU time 0.63 seconds
Started Jul 18 05:29:22 PM PDT 24
Finished Jul 18 05:29:26 PM PDT 24
Peak memory 204728 kb
Host smart-6edf7f11-b2e8-4712-bd47-6bb4e4a38f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280491527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2280491527
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.3408722228
Short name T1397
Test name
Test status
Simulation time 535393946 ps
CPU time 2.34 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:29:17 PM PDT 24
Peak memory 213784 kb
Host smart-8463f82e-8efd-45e3-8719-7ee0e4ea583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408722228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3408722228
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3346197922
Short name T953
Test name
Test status
Simulation time 2278425208 ps
CPU time 10.09 seconds
Started Jul 18 05:29:10 PM PDT 24
Finished Jul 18 05:29:23 PM PDT 24
Peak memory 330528 kb
Host smart-07f7797f-3366-4661-bff2-0c9ba62d8e3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346197922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3346197922
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3423706203
Short name T1184
Test name
Test status
Simulation time 18126197237 ps
CPU time 135.93 seconds
Started Jul 18 05:29:09 PM PDT 24
Finished Jul 18 05:31:26 PM PDT 24
Peak memory 636132 kb
Host smart-2b0645e3-b17c-4c7f-966f-bb81be52e60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423706203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3423706203
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1244220978
Short name T668
Test name
Test status
Simulation time 8949974839 ps
CPU time 69.13 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:30:23 PM PDT 24
Peak memory 741760 kb
Host smart-4510f45d-e247-437d-8f1f-8eed74df12fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244220978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1244220978
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2734284727
Short name T798
Test name
Test status
Simulation time 1255215977 ps
CPU time 1.03 seconds
Started Jul 18 05:29:10 PM PDT 24
Finished Jul 18 05:29:13 PM PDT 24
Peak memory 205432 kb
Host smart-53860317-75f3-4678-84e4-a4de89861251
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734284727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2734284727
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.4082723793
Short name T924
Test name
Test status
Simulation time 237625097 ps
CPU time 3.58 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:29:22 PM PDT 24
Peak memory 224084 kb
Host smart-e6f8780f-2007-408b-927f-4047de7e8199
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082723793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.4082723793
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3633743537
Short name T151
Test name
Test status
Simulation time 2758309843 ps
CPU time 56.93 seconds
Started Jul 18 05:29:17 PM PDT 24
Finished Jul 18 05:30:18 PM PDT 24
Peak memory 650212 kb
Host smart-03c20203-813e-4b0e-a4d3-5c60baaecdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633743537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3633743537
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1392553924
Short name T233
Test name
Test status
Simulation time 1043956009 ps
CPU time 22.01 seconds
Started Jul 18 05:29:17 PM PDT 24
Finished Jul 18 05:29:44 PM PDT 24
Peak memory 205624 kb
Host smart-0710976f-1339-4cfb-99d5-a92203a7ddbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392553924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1392553924
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.532834097
Short name T1748
Test name
Test status
Simulation time 80116174 ps
CPU time 0.68 seconds
Started Jul 18 05:29:09 PM PDT 24
Finished Jul 18 05:29:11 PM PDT 24
Peak memory 205256 kb
Host smart-5cebbe88-7c88-4249-9cf6-e98d9cc4258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532834097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.532834097
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3241300892
Short name T1351
Test name
Test status
Simulation time 2094656398 ps
CPU time 89.64 seconds
Started Jul 18 05:40:56 PM PDT 24
Finished Jul 18 05:42:31 PM PDT 24
Peak memory 219696 kb
Host smart-1706c28a-2489-44ec-80d2-325f657d0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241300892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3241300892
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.1002733464
Short name T983
Test name
Test status
Simulation time 2830494079 ps
CPU time 66.99 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:30:20 PM PDT 24
Peak memory 635120 kb
Host smart-e19ba04d-e7b2-46e0-ba0d-7e69c71e7d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002733464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1002733464
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.828239162
Short name T1444
Test name
Test status
Simulation time 4438025811 ps
CPU time 38.89 seconds
Started Jul 18 05:28:52 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 321764 kb
Host smart-63bc2018-b5cd-495e-aa61-7dd52ea141d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828239162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.828239162
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2573368427
Short name T775
Test name
Test status
Simulation time 2578025079 ps
CPU time 12.42 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:28 PM PDT 24
Peak memory 221320 kb
Host smart-76c66477-7e2a-46ba-a0dd-37877c0f9638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573368427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2573368427
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1928062861
Short name T371
Test name
Test status
Simulation time 2760603394 ps
CPU time 3.87 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 216084 kb
Host smart-28dc28d7-a5bf-4a45-8fb3-4d8b9eade2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928062861 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1928062861
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3751725571
Short name T1524
Test name
Test status
Simulation time 180542177 ps
CPU time 1.16 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:18 PM PDT 24
Peak memory 205424 kb
Host smart-433493c1-2c98-45b1-86c8-441ddb3dd176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751725571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3751725571
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3884759642
Short name T1090
Test name
Test status
Simulation time 172837053 ps
CPU time 1.1 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:29:16 PM PDT 24
Peak memory 205400 kb
Host smart-f38f95f2-0786-417d-98ab-6f729fa87d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884759642 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3884759642
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.4279884151
Short name T1685
Test name
Test status
Simulation time 2105487253 ps
CPU time 2.76 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:29:23 PM PDT 24
Peak memory 205360 kb
Host smart-78ebf4cd-d83f-49d5-a92d-9016bf73a5f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279884151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.4279884151
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.538564077
Short name T1028
Test name
Test status
Simulation time 2370244409 ps
CPU time 3.51 seconds
Started Jul 18 05:29:23 PM PDT 24
Finished Jul 18 05:29:30 PM PDT 24
Peak memory 214100 kb
Host smart-9f31a4bf-c38e-44f4-a7eb-02802245a832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538564077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.538564077
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2052823684
Short name T500
Test name
Test status
Simulation time 12130809145 ps
CPU time 85.87 seconds
Started Jul 18 05:29:16 PM PDT 24
Finished Jul 18 05:30:47 PM PDT 24
Peak memory 1380960 kb
Host smart-328f2359-17a0-4b9c-adc0-fb1e33e5598d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052823684 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2052823684
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.1102752148
Short name T1058
Test name
Test status
Simulation time 1230738749 ps
CPU time 2.72 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:29:22 PM PDT 24
Peak memory 213848 kb
Host smart-b72b803c-2462-47a1-98be-80511ec15b4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102752148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_nack_acqfull.1102752148
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.2015894700
Short name T465
Test name
Test status
Simulation time 465826541 ps
CPU time 2.45 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:18 PM PDT 24
Peak memory 205872 kb
Host smart-e0748366-1c6d-4cc7-b847-fbf7a0c05196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015894700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.2015894700
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.2922695107
Short name T669
Test name
Test status
Simulation time 1045392653 ps
CPU time 7.46 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:22 PM PDT 24
Peak memory 230360 kb
Host smart-7b2751ea-0f23-40e4-8863-4ac58debeabb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922695107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.2922695107
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.1096388283
Short name T1286
Test name
Test status
Simulation time 2235949645 ps
CPU time 2.35 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:29:25 PM PDT 24
Peak memory 205452 kb
Host smart-fcc8ed22-dbda-4f75-a2f9-cb88a5421e6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096388283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_smbus_maxlen.1096388283
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.3418302145
Short name T337
Test name
Test status
Simulation time 1961770663 ps
CPU time 12.4 seconds
Started Jul 18 05:29:13 PM PDT 24
Finished Jul 18 05:29:30 PM PDT 24
Peak memory 217244 kb
Host smart-571974ee-d8b6-4523-b127-dffe037a7cc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418302145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.3418302145
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.216089830
Short name T1558
Test name
Test status
Simulation time 29476067434 ps
CPU time 643.97 seconds
Started Jul 18 05:29:13 PM PDT 24
Finished Jul 18 05:40:02 PM PDT 24
Peak memory 5954892 kb
Host smart-855b11bf-74c4-4d8e-8edc-acdd4418d0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216089830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_target_stress_all.216089830
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2317296425
Short name T1293
Test name
Test status
Simulation time 756856393 ps
CPU time 12.77 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:28 PM PDT 24
Peak memory 221728 kb
Host smart-07196496-c3d5-4e03-b7d0-03ff301369a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317296425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2317296425
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.4016304332
Short name T1499
Test name
Test status
Simulation time 26011416656 ps
CPU time 18.03 seconds
Started Jul 18 05:29:13 PM PDT 24
Finished Jul 18 05:29:36 PM PDT 24
Peak memory 430828 kb
Host smart-9f63eea6-fe16-4a46-ba6e-39c1bdedf57f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016304332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.4016304332
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2262879587
Short name T714
Test name
Test status
Simulation time 1362992724 ps
CPU time 3.3 seconds
Started Jul 18 05:29:10 PM PDT 24
Finished Jul 18 05:29:15 PM PDT 24
Peak memory 229584 kb
Host smart-6053d2ab-b4ba-48c6-bd67-1122f9516152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262879587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2262879587
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2851943931
Short name T1178
Test name
Test status
Simulation time 1522514585 ps
CPU time 7.63 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:24 PM PDT 24
Peak memory 222028 kb
Host smart-79d6bc8b-bfb7-49c4-b8c3-8558fd9926ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851943931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2851943931
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.4034373470
Short name T1047
Test name
Test status
Simulation time 50183022 ps
CPU time 1.25 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:29:25 PM PDT 24
Peak memory 205652 kb
Host smart-363f0fb6-ffa8-4793-bbd3-27fbf7ec4bd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034373470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.4034373470
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2930061971
Short name T1083
Test name
Test status
Simulation time 30634074 ps
CPU time 0.63 seconds
Started Jul 18 05:29:16 PM PDT 24
Finished Jul 18 05:29:22 PM PDT 24
Peak memory 204856 kb
Host smart-557375e4-014b-48bf-bd80-57cc3d4b63f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930061971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2930061971
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3780023466
Short name T824
Test name
Test status
Simulation time 304973793 ps
CPU time 10.35 seconds
Started Jul 18 05:29:25 PM PDT 24
Finished Jul 18 05:29:37 PM PDT 24
Peak memory 213624 kb
Host smart-7077aad1-4455-4002-a228-9acbd45866ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780023466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3780023466
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3788417089
Short name T972
Test name
Test status
Simulation time 1506454677 ps
CPU time 6.97 seconds
Started Jul 18 05:29:22 PM PDT 24
Finished Jul 18 05:29:33 PM PDT 24
Peak memory 267068 kb
Host smart-94faa506-7331-44e5-981c-4c2ecc843667
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788417089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3788417089
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.3686947309
Short name T141
Test name
Test status
Simulation time 11981158924 ps
CPU time 81.52 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:30:45 PM PDT 24
Peak memory 423764 kb
Host smart-1395fc01-8c91-49e4-8974-062e29a4de34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686947309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.3686947309
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3261863857
Short name T1488
Test name
Test status
Simulation time 3822126475 ps
CPU time 52.44 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:30:17 PM PDT 24
Peak memory 642844 kb
Host smart-7889321c-3eba-4b6e-9908-6d506b568266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261863857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3261863857
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1873061076
Short name T1611
Test name
Test status
Simulation time 215322892 ps
CPU time 1.08 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:29:26 PM PDT 24
Peak memory 205264 kb
Host smart-accf074c-63c4-4a76-8912-705a0b37e0c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873061076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1873061076
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.512156229
Short name T1235
Test name
Test status
Simulation time 250852641 ps
CPU time 7.68 seconds
Started Jul 18 05:29:21 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 229392 kb
Host smart-78ff8b24-a480-4024-9659-42a67e21a248
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512156229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
512156229
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.175929168
Short name T98
Test name
Test status
Simulation time 19313720671 ps
CPU time 98.97 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:30:58 PM PDT 24
Peak memory 1195188 kb
Host smart-3dc9188b-7201-4940-9de2-f16ef7af6e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175929168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.175929168
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1492149313
Short name T1582
Test name
Test status
Simulation time 346668375 ps
CPU time 4.36 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:20 PM PDT 24
Peak memory 205552 kb
Host smart-a1342e95-08b7-425a-ab81-572132573e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492149313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1492149313
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.3680811759
Short name T1072
Test name
Test status
Simulation time 62880868 ps
CPU time 0.65 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:29:24 PM PDT 24
Peak memory 205252 kb
Host smart-b9f4457d-d230-4fdf-8ad4-9d281bdc5bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680811759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3680811759
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.485719549
Short name T327
Test name
Test status
Simulation time 962705114 ps
CPU time 10.76 seconds
Started Jul 18 05:29:21 PM PDT 24
Finished Jul 18 05:29:36 PM PDT 24
Peak memory 230036 kb
Host smart-ba13d8bd-c29b-41f1-a281-28a9a7c9643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485719549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.485719549
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.2228296005
Short name T932
Test name
Test status
Simulation time 117613463 ps
CPU time 1.06 seconds
Started Jul 18 05:29:25 PM PDT 24
Finished Jul 18 05:29:28 PM PDT 24
Peak memory 204812 kb
Host smart-cd446286-1807-4283-b4fa-03c61b78a6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228296005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.2228296005
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.106328381
Short name T457
Test name
Test status
Simulation time 1099412475 ps
CPU time 15.15 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 270432 kb
Host smart-20736014-fe2a-4141-a717-8734463c2f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106328381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.106328381
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.4103186345
Short name T1560
Test name
Test status
Simulation time 5422520968 ps
CPU time 10.26 seconds
Started Jul 18 05:29:24 PM PDT 24
Finished Jul 18 05:29:37 PM PDT 24
Peak memory 221900 kb
Host smart-835990c9-9c6c-4364-ab5b-5e2bb3c4dd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103186345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.4103186345
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3827105183
Short name T1170
Test name
Test status
Simulation time 11027017897 ps
CPU time 4.67 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:21 PM PDT 24
Peak memory 213916 kb
Host smart-9c722dda-148a-4eb7-84f9-925731f7d883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827105183 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3827105183
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.373867232
Short name T223
Test name
Test status
Simulation time 809382745 ps
CPU time 1.44 seconds
Started Jul 18 05:29:10 PM PDT 24
Finished Jul 18 05:29:14 PM PDT 24
Peak memory 212920 kb
Host smart-7f586a64-90de-42ab-be0f-1139348f63c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373867232 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.373867232
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3238076569
Short name T877
Test name
Test status
Simulation time 149130723 ps
CPU time 1.13 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:29:20 PM PDT 24
Peak memory 205424 kb
Host smart-84f51002-9732-450d-ab6a-8110ca42ada6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238076569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3238076569
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.1864248723
Short name T893
Test name
Test status
Simulation time 1359250135 ps
CPU time 2.24 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:29:21 PM PDT 24
Peak memory 205600 kb
Host smart-eba2b5fb-5cb5-4a37-b081-90f63f233b4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864248723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.1864248723
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.189642466
Short name T315
Test name
Test status
Simulation time 1669817270 ps
CPU time 1.12 seconds
Started Jul 18 05:29:13 PM PDT 24
Finished Jul 18 05:29:18 PM PDT 24
Peak memory 205400 kb
Host smart-27a217aa-1ca2-4b8e-a0ab-3cbfeb130cb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189642466 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.189642466
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1300342082
Short name T1041
Test name
Test status
Simulation time 3030770825 ps
CPU time 3.65 seconds
Started Jul 18 05:29:16 PM PDT 24
Finished Jul 18 05:29:24 PM PDT 24
Peak memory 216732 kb
Host smart-8fcd80a9-d4ef-4e22-bb46-1fc07834a739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300342082 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1300342082
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2427874966
Short name T1743
Test name
Test status
Simulation time 9982030284 ps
CPU time 18.97 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:29:39 PM PDT 24
Peak memory 452676 kb
Host smart-79132897-6b27-4a57-89d5-cffdfe063524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427874966 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2427874966
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.3546723027
Short name T704
Test name
Test status
Simulation time 449050772 ps
CPU time 2.8 seconds
Started Jul 18 05:29:17 PM PDT 24
Finished Jul 18 05:29:24 PM PDT 24
Peak memory 213800 kb
Host smart-0961dd6c-2dbd-4678-8e18-2bc1293897d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546723027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_nack_acqfull.3546723027
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.2234010452
Short name T936
Test name
Test status
Simulation time 431211875 ps
CPU time 2.6 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:29:22 PM PDT 24
Peak memory 205628 kb
Host smart-18e2ac1b-75d8-477b-8fa3-b5c597d47298
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234010452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.2234010452
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.1481789330
Short name T1556
Test name
Test status
Simulation time 3272972374 ps
CPU time 4.58 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:29:18 PM PDT 24
Peak memory 221348 kb
Host smart-92ba911d-c2fe-475f-8e30-47236856e31f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481789330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.1481789330
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.502103515
Short name T841
Test name
Test status
Simulation time 473769914 ps
CPU time 2.28 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:29:21 PM PDT 24
Peak memory 205400 kb
Host smart-eede2205-e91f-408e-abfb-6eceec468b62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502103515 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_smbus_maxlen.502103515
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2894442689
Short name T1616
Test name
Test status
Simulation time 1131026470 ps
CPU time 36.12 seconds
Started Jul 18 05:29:25 PM PDT 24
Finished Jul 18 05:30:03 PM PDT 24
Peak memory 213656 kb
Host smart-5b611ab8-e4ae-4847-95e2-0ebe8f4b4890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894442689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2894442689
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.1224622342
Short name T1326
Test name
Test status
Simulation time 17553452445 ps
CPU time 32.03 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:29:51 PM PDT 24
Peak memory 283380 kb
Host smart-922290a4-f8b0-41f4-b55f-8b8bb78bacc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224622342 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.1224622342
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2415399561
Short name T245
Test name
Test status
Simulation time 4441450991 ps
CPU time 5.07 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:29:25 PM PDT 24
Peak memory 205716 kb
Host smart-f2f742e5-2bc5-4b10-acee-a2da3dc31dd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415399561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2415399561
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.473640795
Short name T582
Test name
Test status
Simulation time 22034103535 ps
CPU time 49.4 seconds
Started Jul 18 05:29:10 PM PDT 24
Finished Jul 18 05:30:01 PM PDT 24
Peak memory 586120 kb
Host smart-87a4327a-478b-49a6-8e3b-feb13ef83a52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473640795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.473640795
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.4178322299
Short name T402
Test name
Test status
Simulation time 4760808826 ps
CPU time 6.43 seconds
Started Jul 18 05:29:13 PM PDT 24
Finished Jul 18 05:29:24 PM PDT 24
Peak memory 230308 kb
Host smart-132bbee8-f01e-480e-bdbb-cde28413ea13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178322299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.4178322299
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.3042792238
Short name T1067
Test name
Test status
Simulation time 188202917 ps
CPU time 2.7 seconds
Started Jul 18 05:29:13 PM PDT 24
Finished Jul 18 05:29:20 PM PDT 24
Peak memory 205600 kb
Host smart-5d60d37c-fa66-4151-9aa6-1cf15538e930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042792238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.3042792238
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.601309993
Short name T1069
Test name
Test status
Simulation time 28594008 ps
CPU time 0.62 seconds
Started Jul 18 05:29:22 PM PDT 24
Finished Jul 18 05:29:26 PM PDT 24
Peak memory 204712 kb
Host smart-3d2047b0-e7d2-483e-aa87-d7bd5beb183c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601309993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.601309993
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3761059451
Short name T1457
Test name
Test status
Simulation time 178709740 ps
CPU time 1.71 seconds
Started Jul 18 05:29:25 PM PDT 24
Finished Jul 18 05:29:29 PM PDT 24
Peak memory 213652 kb
Host smart-538fcdd4-e0ea-4f27-b4e1-29455b68d9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761059451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3761059451
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2105537557
Short name T1331
Test name
Test status
Simulation time 382484839 ps
CPU time 3.57 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 240612 kb
Host smart-e0759f4a-7030-4956-b35d-9628e4eb18bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105537557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2105537557
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1854868209
Short name T772
Test name
Test status
Simulation time 16672010433 ps
CPU time 144.14 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:31:48 PM PDT 24
Peak memory 323800 kb
Host smart-1e4d7638-841b-48cb-b22a-7b5a3c2d3ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854868209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1854868209
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.4082084771
Short name T1148
Test name
Test status
Simulation time 4615135648 ps
CPU time 72.77 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 652556 kb
Host smart-a8552a93-332b-44c7-ae1b-a47e75f3c027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082084771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.4082084771
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.4241958707
Short name T228
Test name
Test status
Simulation time 454145900 ps
CPU time 1.16 seconds
Started Jul 18 05:29:18 PM PDT 24
Finished Jul 18 05:29:24 PM PDT 24
Peak memory 205352 kb
Host smart-1757bc0c-466b-4304-aa6f-f1978d4a9c24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241958707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.4241958707
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.108268730
Short name T1472
Test name
Test status
Simulation time 1001525241 ps
CPU time 5.99 seconds
Started Jul 18 05:29:18 PM PDT 24
Finished Jul 18 05:29:29 PM PDT 24
Peak memory 205500 kb
Host smart-31e184fc-8889-4de3-8953-8774c5c4c1f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108268730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
108268730
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3538098443
Short name T105
Test name
Test status
Simulation time 13610385008 ps
CPU time 140.13 seconds
Started Jul 18 05:29:17 PM PDT 24
Finished Jul 18 05:31:42 PM PDT 24
Peak memory 1558620 kb
Host smart-b0ddd836-b152-449d-a415-a408fc153422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538098443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3538098443
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.616838134
Short name T974
Test name
Test status
Simulation time 205115761 ps
CPU time 3.57 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:29:17 PM PDT 24
Peak memory 205520 kb
Host smart-c29eff0d-7858-4426-a0a7-aa0c7b2a95bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616838134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.616838134
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2539033244
Short name T1051
Test name
Test status
Simulation time 117796057 ps
CPU time 3.54 seconds
Started Jul 18 05:29:10 PM PDT 24
Finished Jul 18 05:29:16 PM PDT 24
Peak memory 215688 kb
Host smart-b2c513c5-99bd-4bb1-a48b-73b342194b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539033244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2539033244
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1293492797
Short name T1376
Test name
Test status
Simulation time 2788033098 ps
CPU time 3.82 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:29:22 PM PDT 24
Peak memory 205560 kb
Host smart-d64ddb64-8375-421b-b72b-0fb68c0be428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293492797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1293492797
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.4124784358
Short name T1525
Test name
Test status
Simulation time 232455008 ps
CPU time 8.43 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 205444 kb
Host smart-c9870f4a-aa51-4e3a-a689-69a4d8ffa652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124784358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.4124784358
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3100596293
Short name T278
Test name
Test status
Simulation time 1290476319 ps
CPU time 21.63 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:29:42 PM PDT 24
Peak memory 354712 kb
Host smart-208e1363-f3a2-4f14-89eb-4bfacbb1c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100596293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3100596293
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.908139098
Short name T1261
Test name
Test status
Simulation time 1462675285 ps
CPU time 17.13 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:29:41 PM PDT 24
Peak memory 213612 kb
Host smart-fa8b521c-57bb-4752-ae30-604c69f3d677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908139098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.908139098
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2798091820
Short name T793
Test name
Test status
Simulation time 865130382 ps
CPU time 4.54 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:21 PM PDT 24
Peak memory 213820 kb
Host smart-1bc972e3-ffeb-4814-b50e-79f05c9f997f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798091820 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2798091820
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3205544987
Short name T1247
Test name
Test status
Simulation time 695630640 ps
CPU time 1.13 seconds
Started Jul 18 05:29:22 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 205584 kb
Host smart-91040f68-1f8e-408a-86e6-f5f9b680f781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205544987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3205544987
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3631690761
Short name T82
Test name
Test status
Simulation time 187330856 ps
CPU time 1.12 seconds
Started Jul 18 05:29:23 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 205408 kb
Host smart-d747620f-84cb-4f7c-9ff6-60745d40938f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631690761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3631690761
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.4202930790
Short name T1600
Test name
Test status
Simulation time 515905072 ps
CPU time 2.61 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:19 PM PDT 24
Peak memory 205556 kb
Host smart-ed2fefcf-1fbe-41c5-b3e6-e2516c148324
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202930790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.4202930790
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.3880680340
Short name T727
Test name
Test status
Simulation time 482599004 ps
CPU time 1.16 seconds
Started Jul 18 05:29:10 PM PDT 24
Finished Jul 18 05:29:14 PM PDT 24
Peak memory 205424 kb
Host smart-d4d5848e-0a15-4146-b0cd-d96305d66e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880680340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.3880680340
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.500674963
Short name T308
Test name
Test status
Simulation time 2177441635 ps
CPU time 6.62 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:29:31 PM PDT 24
Peak memory 222104 kb
Host smart-5fe12f7e-5342-4d3b-a70c-b8c7669f9305
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500674963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.500674963
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1806758263
Short name T368
Test name
Test status
Simulation time 22852856753 ps
CPU time 596.03 seconds
Started Jul 18 05:29:21 PM PDT 24
Finished Jul 18 05:39:21 PM PDT 24
Peak memory 5384904 kb
Host smart-24095c89-a728-42e5-8e3e-d88ec07e2f60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806758263 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1806758263
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.3339139561
Short name T728
Test name
Test status
Simulation time 2117901672 ps
CPU time 2.54 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:29:16 PM PDT 24
Peak memory 213892 kb
Host smart-61986243-2f8b-43d4-a4ac-82bf16932ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339139561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.3339139561
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.1299480207
Short name T621
Test name
Test status
Simulation time 484834949 ps
CPU time 2.29 seconds
Started Jul 18 05:29:13 PM PDT 24
Finished Jul 18 05:29:21 PM PDT 24
Peak memory 205660 kb
Host smart-3ed8f774-99eb-4f73-b52b-608a0f43517c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299480207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.1299480207
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.790643980
Short name T405
Test name
Test status
Simulation time 556556418 ps
CPU time 4.51 seconds
Started Jul 18 05:29:18 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 218336 kb
Host smart-5b951d98-e726-4aa2-bed5-5eed09b7e45e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790643980 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_perf.790643980
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.3943232777
Short name T276
Test name
Test status
Simulation time 519336182 ps
CPU time 2.47 seconds
Started Jul 18 05:29:11 PM PDT 24
Finished Jul 18 05:29:17 PM PDT 24
Peak memory 205400 kb
Host smart-a3986ea3-0565-4f7b-840a-eae6b57dd3f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943232777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_smbus_maxlen.3943232777
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1414318997
Short name T561
Test name
Test status
Simulation time 5468689968 ps
CPU time 8.3 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:29:33 PM PDT 24
Peak memory 213936 kb
Host smart-bbbc31a0-2ecb-47af-b54c-bd69da467ee6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414318997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1414318997
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.3789924085
Short name T788
Test name
Test status
Simulation time 10955701674 ps
CPU time 153.4 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 2021288 kb
Host smart-7b1694b9-0f23-434f-b50c-d55511163995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789924085 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.3789924085
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1872143499
Short name T1512
Test name
Test status
Simulation time 3337999933 ps
CPU time 15.3 seconds
Started Jul 18 05:29:22 PM PDT 24
Finished Jul 18 05:29:41 PM PDT 24
Peak memory 219868 kb
Host smart-c7a72f7c-f26f-4c37-9d13-78aadba07a5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872143499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1872143499
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3248146590
Short name T451
Test name
Test status
Simulation time 33176812283 ps
CPU time 13.3 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 339048 kb
Host smart-6505f3e5-f41a-40ba-984b-261848b18e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248146590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3248146590
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2958569644
Short name T947
Test name
Test status
Simulation time 6877855003 ps
CPU time 42.97 seconds
Started Jul 18 05:29:21 PM PDT 24
Finished Jul 18 05:30:08 PM PDT 24
Peak memory 463488 kb
Host smart-da7365a7-b543-4db7-b6c3-437167d585fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958569644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2958569644
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2546799481
Short name T1198
Test name
Test status
Simulation time 2581879365 ps
CPU time 7.04 seconds
Started Jul 18 05:29:21 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 220304 kb
Host smart-c65108e1-e32a-49a8-8f3f-50dd1f732ddb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546799481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2546799481
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.3708936770
Short name T1078
Test name
Test status
Simulation time 188758648 ps
CPU time 2.78 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:29:22 PM PDT 24
Peak memory 205556 kb
Host smart-9e72b866-4ee1-4bb9-93d0-198685f567ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708936770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.3708936770
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.287902221
Short name T456
Test name
Test status
Simulation time 57350867 ps
CPU time 0.72 seconds
Started Jul 18 05:29:27 PM PDT 24
Finished Jul 18 05:29:30 PM PDT 24
Peak memory 204780 kb
Host smart-1500e14f-914d-408b-9da0-3025092a01ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287902221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.287902221
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.3481104046
Short name T1679
Test name
Test status
Simulation time 88921744 ps
CPU time 1.4 seconds
Started Jul 18 05:29:18 PM PDT 24
Finished Jul 18 05:29:24 PM PDT 24
Peak memory 213780 kb
Host smart-300762e4-bd07-4e73-b0a0-efa5f524e8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481104046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3481104046
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.3513275455
Short name T1396
Test name
Test status
Simulation time 1483854338 ps
CPU time 8.39 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 287336 kb
Host smart-a65b3138-59bd-4138-843f-6d5202d2623b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513275455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.3513275455
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3734955830
Short name T819
Test name
Test status
Simulation time 6046850592 ps
CPU time 76.01 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:30:36 PM PDT 24
Peak memory 246780 kb
Host smart-d9cb0e51-8b75-431c-978f-dd2b91623704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734955830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3734955830
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3467018444
Short name T470
Test name
Test status
Simulation time 25530379013 ps
CPU time 148.99 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:31:44 PM PDT 24
Peak memory 687940 kb
Host smart-8016a772-19cd-486e-8431-cb12919303ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467018444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3467018444
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1711760932
Short name T875
Test name
Test status
Simulation time 319535233 ps
CPU time 1.15 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:18 PM PDT 24
Peak memory 205200 kb
Host smart-f05f4f5e-9550-4597-bd4b-d8109a0e9ec1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711760932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1711760932
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2351258245
Short name T1494
Test name
Test status
Simulation time 155768985 ps
CPU time 8.42 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:24 PM PDT 24
Peak memory 233088 kb
Host smart-8422882b-3c8f-4151-a732-30cf7573d158
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351258245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2351258245
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3196770034
Short name T444
Test name
Test status
Simulation time 26634984025 ps
CPU time 302.27 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:34:21 PM PDT 24
Peak memory 1268940 kb
Host smart-e515b44d-2ce0-4c70-97b9-f8e285b56a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196770034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3196770034
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3749168693
Short name T236
Test name
Test status
Simulation time 1631766835 ps
CPU time 9.59 seconds
Started Jul 18 05:29:27 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 205476 kb
Host smart-9dc73417-fb0b-4bcd-98d3-990c0543b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749168693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3749168693
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_override.2899726056
Short name T1657
Test name
Test status
Simulation time 145575051 ps
CPU time 0.68 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:17 PM PDT 24
Peak memory 205244 kb
Host smart-383bd9b6-c350-4bce-8941-cb1d8fa26493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899726056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2899726056
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3354580725
Short name T1347
Test name
Test status
Simulation time 27998283407 ps
CPU time 1328.96 seconds
Started Jul 18 05:29:18 PM PDT 24
Finished Jul 18 05:51:32 PM PDT 24
Peak memory 1315156 kb
Host smart-37a324ba-22c3-498d-81eb-04f7383209fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354580725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3354580725
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.4272423132
Short name T1024
Test name
Test status
Simulation time 5947250489 ps
CPU time 189.97 seconds
Started Jul 18 05:29:19 PM PDT 24
Finished Jul 18 05:32:33 PM PDT 24
Peak memory 205524 kb
Host smart-99dcc894-8b97-47cf-9897-1b95c2eff8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272423132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.4272423132
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.628006699
Short name T1399
Test name
Test status
Simulation time 3771015501 ps
CPU time 29.59 seconds
Started Jul 18 05:29:12 PM PDT 24
Finished Jul 18 05:29:46 PM PDT 24
Peak memory 382192 kb
Host smart-98a27b8a-799b-42eb-a969-ef7d1e5c8099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628006699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.628006699
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3040471593
Short name T878
Test name
Test status
Simulation time 2197724922 ps
CPU time 8.02 seconds
Started Jul 18 05:29:18 PM PDT 24
Finished Jul 18 05:29:30 PM PDT 24
Peak memory 213732 kb
Host smart-16ddbb66-d62f-4616-a0ce-877280bd5ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040471593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3040471593
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.1374011285
Short name T301
Test name
Test status
Simulation time 4159879130 ps
CPU time 5.78 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:51 PM PDT 24
Peak memory 222016 kb
Host smart-0e93de70-e2d4-4ef7-ade0-37c3e7af40ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374011285 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.1374011285
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.278370538
Short name T581
Test name
Test status
Simulation time 226636637 ps
CPU time 1.18 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:29:34 PM PDT 24
Peak memory 205496 kb
Host smart-f00555cc-0786-48ac-a69d-90a213be8355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278370538 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.278370538
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.1950166749
Short name T1187
Test name
Test status
Simulation time 1274307142 ps
CPU time 1.07 seconds
Started Jul 18 05:29:35 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 205448 kb
Host smart-5f73b0e6-d893-41d2-9337-88ea1b059cd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950166749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.1950166749
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.3131970024
Short name T1342
Test name
Test status
Simulation time 1018541792 ps
CPU time 2.7 seconds
Started Jul 18 05:29:27 PM PDT 24
Finished Jul 18 05:29:31 PM PDT 24
Peak memory 205544 kb
Host smart-90d560c4-00c3-4687-9aaa-edfdecdaf45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131970024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.3131970024
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.2861854249
Short name T146
Test name
Test status
Simulation time 108119172 ps
CPU time 1.32 seconds
Started Jul 18 05:29:27 PM PDT 24
Finished Jul 18 05:29:30 PM PDT 24
Peak memory 205404 kb
Host smart-b09004bd-ba7a-44d2-a677-7a8315ed8612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861854249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.2861854249
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1043754554
Short name T950
Test name
Test status
Simulation time 268696227 ps
CPU time 1.97 seconds
Started Jul 18 05:29:26 PM PDT 24
Finished Jul 18 05:29:29 PM PDT 24
Peak memory 221876 kb
Host smart-ee60b086-53fe-4578-91d9-0041120f142b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043754554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1043754554
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2297440898
Short name T1713
Test name
Test status
Simulation time 3610886885 ps
CPU time 5.36 seconds
Started Jul 18 05:29:25 PM PDT 24
Finished Jul 18 05:29:33 PM PDT 24
Peak memory 219500 kb
Host smart-dc0b0583-78a7-4489-a6b5-a5f4b78e7f80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297440898 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2297440898
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.4253477149
Short name T130
Test name
Test status
Simulation time 9386543233 ps
CPU time 4.52 seconds
Started Jul 18 05:29:26 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 205652 kb
Host smart-d9a7ee79-edc6-4a75-bff6-0fddbf0460ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253477149 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.4253477149
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.3239171837
Short name T142
Test name
Test status
Simulation time 985494230 ps
CPU time 3.01 seconds
Started Jul 18 05:29:28 PM PDT 24
Finished Jul 18 05:29:34 PM PDT 24
Peak memory 213888 kb
Host smart-8b58a98c-ee75-4ae3-8547-fd89c7fcf580
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239171837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_nack_acqfull.3239171837
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.694983359
Short name T628
Test name
Test status
Simulation time 433137669 ps
CPU time 2.57 seconds
Started Jul 18 05:29:27 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 205608 kb
Host smart-2b2a6e7a-8c81-4f64-9bf0-ee406d03a40a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694983359 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.694983359
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.3044768379
Short name T1573
Test name
Test status
Simulation time 525612914 ps
CPU time 4.31 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:29:37 PM PDT 24
Peak memory 214012 kb
Host smart-1b5fa8e6-46c3-4e87-b5ed-4eed6a260149
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044768379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.3044768379
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.3692857406
Short name T478
Test name
Test status
Simulation time 2533813733 ps
CPU time 2.34 seconds
Started Jul 18 05:29:34 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 205452 kb
Host smart-b4660b7b-79d9-4269-98f6-75a210b68fbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692857406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.3692857406
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1925167719
Short name T647
Test name
Test status
Simulation time 1872340218 ps
CPU time 10.68 seconds
Started Jul 18 05:29:14 PM PDT 24
Finished Jul 18 05:29:30 PM PDT 24
Peak memory 213828 kb
Host smart-ba190f7c-fa12-4923-abe3-03b89aca6204
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925167719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1925167719
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.752617366
Short name T1519
Test name
Test status
Simulation time 33907218518 ps
CPU time 26.24 seconds
Started Jul 18 05:29:32 PM PDT 24
Finished Jul 18 05:30:00 PM PDT 24
Peak memory 262688 kb
Host smart-89ab64e5-09f1-4e03-99b3-03ffb6725625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752617366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.i2c_target_stress_all.752617366
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2798620615
Short name T1323
Test name
Test status
Simulation time 337330820 ps
CPU time 14.49 seconds
Started Jul 18 05:29:20 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 205664 kb
Host smart-b9491335-2fb6-4050-987a-4af93b98a669
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798620615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2798620615
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.4098188081
Short name T1292
Test name
Test status
Simulation time 16155724950 ps
CPU time 6.48 seconds
Started Jul 18 05:29:15 PM PDT 24
Finished Jul 18 05:29:26 PM PDT 24
Peak memory 205708 kb
Host smart-369193df-d8cc-460d-8c6f-e71930943bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098188081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.4098188081
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1309598031
Short name T420
Test name
Test status
Simulation time 3498595272 ps
CPU time 31.45 seconds
Started Jul 18 05:29:29 PM PDT 24
Finished Jul 18 05:30:02 PM PDT 24
Peak memory 611860 kb
Host smart-6885bf6a-a95e-4ffb-a73c-5da8e3e23e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309598031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1309598031
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1933389335
Short name T751
Test name
Test status
Simulation time 2057890562 ps
CPU time 5.85 seconds
Started Jul 18 05:29:37 PM PDT 24
Finished Jul 18 05:29:44 PM PDT 24
Peak memory 218132 kb
Host smart-8b2f34ab-23b6-443a-91fa-24981f80c5eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933389335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1933389335
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.1274509810
Short name T1052
Test name
Test status
Simulation time 1116894143 ps
CPU time 12.35 seconds
Started Jul 18 05:29:25 PM PDT 24
Finished Jul 18 05:29:40 PM PDT 24
Peak memory 205596 kb
Host smart-5731f9bf-e573-48f3-882d-a1a28f044be7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274509810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.1274509810
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3899848590
Short name T934
Test name
Test status
Simulation time 16197658 ps
CPU time 0.65 seconds
Started Jul 18 05:29:40 PM PDT 24
Finished Jul 18 05:29:42 PM PDT 24
Peak memory 204784 kb
Host smart-f62caed6-82e2-439f-a8c1-9bdbfb1da5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899848590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3899848590
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1883824179
Short name T1492
Test name
Test status
Simulation time 423340520 ps
CPU time 1.77 seconds
Started Jul 18 05:29:28 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 213832 kb
Host smart-0ddca8f6-ed69-4352-8777-8d6fa87182c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883824179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1883824179
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.4133154518
Short name T916
Test name
Test status
Simulation time 488922473 ps
CPU time 10.65 seconds
Started Jul 18 05:29:35 PM PDT 24
Finished Jul 18 05:29:48 PM PDT 24
Peak memory 312832 kb
Host smart-fba8b43c-8117-4986-99bc-fe33bd9b6eac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133154518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.4133154518
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1294909891
Short name T344
Test name
Test status
Simulation time 4002485549 ps
CPU time 40.99 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:30:14 PM PDT 24
Peak memory 213780 kb
Host smart-d7802b22-06b3-4025-a8c9-413d9b4cbaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294909891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1294909891
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3886839283
Short name T1256
Test name
Test status
Simulation time 2671984951 ps
CPU time 78.64 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:31:03 PM PDT 24
Peak memory 723200 kb
Host smart-8e6db698-a548-411d-ac65-e279c26ea900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886839283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3886839283
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.906008972
Short name T419
Test name
Test status
Simulation time 129638193 ps
CPU time 1.21 seconds
Started Jul 18 05:29:29 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 205200 kb
Host smart-e4146b7e-069a-485e-a22f-93c102f72cbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906008972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.906008972
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2815546213
Short name T1357
Test name
Test status
Simulation time 577156966 ps
CPU time 3.39 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:48 PM PDT 24
Peak memory 205488 kb
Host smart-bed96e9f-68e5-4905-9041-18c9e5cff546
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815546213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2815546213
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3635218215
Short name T894
Test name
Test status
Simulation time 3369324613 ps
CPU time 92.41 seconds
Started Jul 18 05:29:26 PM PDT 24
Finished Jul 18 05:31:00 PM PDT 24
Peak memory 976936 kb
Host smart-5d5e9caa-bbc6-4ffa-ba5f-b3d9f70be474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635218215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3635218215
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3539667607
Short name T1023
Test name
Test status
Simulation time 201398902 ps
CPU time 3.08 seconds
Started Jul 18 05:29:34 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 205492 kb
Host smart-ee158d62-d40d-46df-b40d-da82b9164d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539667607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3539667607
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1211639565
Short name T1674
Test name
Test status
Simulation time 87373662 ps
CPU time 2.73 seconds
Started Jul 18 05:29:29 PM PDT 24
Finished Jul 18 05:29:34 PM PDT 24
Peak memory 221452 kb
Host smart-b0e790ee-d02b-4719-91ad-6a41e0ce205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211639565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1211639565
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3069690266
Short name T70
Test name
Test status
Simulation time 16606563 ps
CPU time 0.65 seconds
Started Jul 18 05:29:35 PM PDT 24
Finished Jul 18 05:29:37 PM PDT 24
Peak memory 205208 kb
Host smart-0472d93c-3193-44d0-9c1e-505a353d27b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069690266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3069690266
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.4227556567
Short name T1402
Test name
Test status
Simulation time 14423347365 ps
CPU time 13.98 seconds
Started Jul 18 05:29:26 PM PDT 24
Finished Jul 18 05:29:42 PM PDT 24
Peak memory 213824 kb
Host smart-902e0f67-7c8b-49a8-9578-5197b6e81c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227556567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.4227556567
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.1271493131
Short name T579
Test name
Test status
Simulation time 497020759 ps
CPU time 4.64 seconds
Started Jul 18 05:30:05 PM PDT 24
Finished Jul 18 05:30:14 PM PDT 24
Peak memory 246968 kb
Host smart-f751cc4b-e140-4428-8ebb-00175ffdf6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271493131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.1271493131
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.181991030
Short name T571
Test name
Test status
Simulation time 2110207491 ps
CPU time 114.57 seconds
Started Jul 18 05:29:28 PM PDT 24
Finished Jul 18 05:31:25 PM PDT 24
Peak memory 443872 kb
Host smart-30d460cd-c948-4a90-91c5-3e851c4d75ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181991030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.181991030
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1955871187
Short name T459
Test name
Test status
Simulation time 3956917962 ps
CPU time 16.68 seconds
Started Jul 18 05:29:44 PM PDT 24
Finished Jul 18 05:30:02 PM PDT 24
Peak memory 229992 kb
Host smart-dc5e6e6e-3bec-4230-8d3a-b5da895b4c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955871187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1955871187
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1275488823
Short name T1681
Test name
Test status
Simulation time 848243674 ps
CPU time 4.72 seconds
Started Jul 18 05:29:29 PM PDT 24
Finished Jul 18 05:29:36 PM PDT 24
Peak memory 217160 kb
Host smart-a54eb499-9627-4f4e-b1ff-7d412a82c5e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275488823 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1275488823
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3938049477
Short name T1635
Test name
Test status
Simulation time 383274147 ps
CPU time 1.34 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:45 PM PDT 24
Peak memory 205592 kb
Host smart-cf23306e-2f9a-4ea2-9966-2c3d123ca17a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938049477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3938049477
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2602512581
Short name T399
Test name
Test status
Simulation time 710031073 ps
CPU time 1.19 seconds
Started Jul 18 05:29:28 PM PDT 24
Finished Jul 18 05:29:32 PM PDT 24
Peak memory 205596 kb
Host smart-63395f71-51e8-4521-93f9-ae1771b062a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602512581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2602512581
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.4125970943
Short name T1115
Test name
Test status
Simulation time 388114479 ps
CPU time 2.23 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:47 PM PDT 24
Peak memory 205620 kb
Host smart-6e2eb970-1bed-490e-b308-85081cae1036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125970943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.4125970943
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.925047731
Short name T493
Test name
Test status
Simulation time 578347552 ps
CPU time 1.25 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:46 PM PDT 24
Peak memory 205408 kb
Host smart-fc783d0e-5d27-487d-b240-57f6a8611926
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925047731 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.925047731
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3531048041
Short name T1151
Test name
Test status
Simulation time 706758318 ps
CPU time 2.62 seconds
Started Jul 18 05:29:34 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 217896 kb
Host smart-e8203957-b579-4c82-b821-fc908685458c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531048041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3531048041
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2010759393
Short name T298
Test name
Test status
Simulation time 1838777870 ps
CPU time 7.43 seconds
Started Jul 18 05:29:27 PM PDT 24
Finished Jul 18 05:29:37 PM PDT 24
Peak memory 218816 kb
Host smart-4d03bd55-cfd9-4cae-98e3-67a8fea495a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010759393 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2010759393
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1689607099
Short name T1346
Test name
Test status
Simulation time 17339203231 ps
CPU time 15.86 seconds
Started Jul 18 05:29:35 PM PDT 24
Finished Jul 18 05:29:53 PM PDT 24
Peak memory 398072 kb
Host smart-7c10da95-ae3c-4ad0-b740-174456fcbe6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689607099 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1689607099
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.229826332
Short name T1126
Test name
Test status
Simulation time 1096918928 ps
CPU time 2.95 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:47 PM PDT 24
Peak memory 213796 kb
Host smart-bd4fcac7-0a74-4978-8465-6994e5c7e7f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229826332 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_nack_acqfull.229826332
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.1142572515
Short name T1340
Test name
Test status
Simulation time 1808648262 ps
CPU time 2.56 seconds
Started Jul 18 05:29:34 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 205616 kb
Host smart-5f33564e-9439-4382-891f-bddc46c1ea56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142572515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.1142572515
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_txstretch.491213624
Short name T815
Test name
Test status
Simulation time 1683939170 ps
CPU time 1.33 seconds
Started Jul 18 05:29:44 PM PDT 24
Finished Jul 18 05:29:47 PM PDT 24
Peak memory 222444 kb
Host smart-5d9686ba-ef86-42bf-8ab4-81c40419d4c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491213624 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_nack_txstretch.491213624
Directory /workspace/27.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/27.i2c_target_perf.3817726066
Short name T1212
Test name
Test status
Simulation time 770640463 ps
CPU time 5.43 seconds
Started Jul 18 05:29:34 PM PDT 24
Finished Jul 18 05:29:41 PM PDT 24
Peak memory 221968 kb
Host smart-c24f151d-1b85-49e3-a5e2-beab59685dfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817726066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.3817726066
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.2026186272
Short name T400
Test name
Test status
Simulation time 486320572 ps
CPU time 2.3 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:29:36 PM PDT 24
Peak memory 205440 kb
Host smart-26ebf827-8b11-4181-becb-b1f2129ab777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026186272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_smbus_maxlen.2026186272
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1711870435
Short name T1447
Test name
Test status
Simulation time 1358515013 ps
CPU time 24.15 seconds
Started Jul 18 05:29:28 PM PDT 24
Finished Jul 18 05:29:54 PM PDT 24
Peak memory 214036 kb
Host smart-7a3a54a6-35fd-40ee-bbac-776e846f2ebb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711870435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1711870435
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.3843524411
Short name T254
Test name
Test status
Simulation time 32924678938 ps
CPU time 36.86 seconds
Started Jul 18 05:29:26 PM PDT 24
Finished Jul 18 05:30:05 PM PDT 24
Peak memory 264448 kb
Host smart-e44c9e17-4607-49af-b2ab-25bfbaf295f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843524411 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.3843524411
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.4010859316
Short name T1615
Test name
Test status
Simulation time 490973098 ps
CPU time 8.22 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:53 PM PDT 24
Peak memory 217304 kb
Host smart-e8b46337-949d-4f6a-a4cf-82dbb0b6e0d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010859316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.4010859316
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.660307148
Short name T1073
Test name
Test status
Simulation time 53757931517 ps
CPU time 196.79 seconds
Started Jul 18 05:29:32 PM PDT 24
Finished Jul 18 05:32:50 PM PDT 24
Peak memory 2114820 kb
Host smart-df6ef7c0-a6e1-40c6-b6aa-f964624dc84c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660307148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_wr.660307148
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2272467035
Short name T366
Test name
Test status
Simulation time 4457422263 ps
CPU time 36.7 seconds
Started Jul 18 05:29:32 PM PDT 24
Finished Jul 18 05:30:10 PM PDT 24
Peak memory 383800 kb
Host smart-da7c3048-e4ba-4e0d-916e-be37e6b98bc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272467035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2272467035
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.201124476
Short name T303
Test name
Test status
Simulation time 1386102064 ps
CPU time 6.14 seconds
Started Jul 18 05:29:54 PM PDT 24
Finished Jul 18 05:30:02 PM PDT 24
Peak memory 219756 kb
Host smart-d7cd841d-3fa5-4394-93f4-3c761c1694be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201124476 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.201124476
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.1093478784
Short name T879
Test name
Test status
Simulation time 108626963 ps
CPU time 2.35 seconds
Started Jul 18 05:29:34 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 205604 kb
Host smart-4baf650f-4906-43f4-b71b-77dae115d8ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093478784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.1093478784
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.866824478
Short name T1227
Test name
Test status
Simulation time 53626989 ps
CPU time 0.66 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:29:53 PM PDT 24
Peak memory 204980 kb
Host smart-471d9200-c5f5-4b4a-b70f-34a9dbe9d599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866824478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.866824478
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3688189153
Short name T1345
Test name
Test status
Simulation time 377889504 ps
CPU time 1.51 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:46 PM PDT 24
Peak memory 213700 kb
Host smart-a4fc3ed6-14a6-449d-816d-a2950a8e2d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688189153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3688189153
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.310226056
Short name T575
Test name
Test status
Simulation time 5281870247 ps
CPU time 6.01 seconds
Started Jul 18 05:29:44 PM PDT 24
Finished Jul 18 05:29:51 PM PDT 24
Peak memory 274616 kb
Host smart-40b6671c-b141-4db0-ad0f-ba366079502d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310226056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.310226056
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.4056149672
Short name T703
Test name
Test status
Simulation time 9639317618 ps
CPU time 135.35 seconds
Started Jul 18 05:29:26 PM PDT 24
Finished Jul 18 05:31:44 PM PDT 24
Peak memory 326484 kb
Host smart-fd9b8ca5-4e3d-4ea8-be40-e4c3b5fdaf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056149672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.4056149672
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3317523959
Short name T421
Test name
Test status
Simulation time 9237252177 ps
CPU time 128.71 seconds
Started Jul 18 05:29:44 PM PDT 24
Finished Jul 18 05:31:54 PM PDT 24
Peak memory 495220 kb
Host smart-f92fbab0-083e-4c7a-a6de-20e7f1ef3d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317523959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3317523959
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2486352306
Short name T226
Test name
Test status
Simulation time 538938032 ps
CPU time 1.18 seconds
Started Jul 18 05:29:42 PM PDT 24
Finished Jul 18 05:29:44 PM PDT 24
Peak memory 205396 kb
Host smart-864fe2ca-16d6-4d7d-a09d-ec4ef391cc37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486352306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2486352306
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1348765887
Short name T1677
Test name
Test status
Simulation time 342490931 ps
CPU time 5.25 seconds
Started Jul 18 05:29:40 PM PDT 24
Finished Jul 18 05:29:47 PM PDT 24
Peak memory 205512 kb
Host smart-3afd6696-cf38-4a5b-a921-8b18ec120e52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348765887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1348765887
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3049309678
Short name T515
Test name
Test status
Simulation time 3125437640 ps
CPU time 207.67 seconds
Started Jul 18 05:29:35 PM PDT 24
Finished Jul 18 05:33:04 PM PDT 24
Peak memory 957032 kb
Host smart-7fbc3786-d1f9-4a8b-b825-24b6bc97253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049309678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3049309678
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.127384413
Short name T239
Test name
Test status
Simulation time 804338185 ps
CPU time 4.71 seconds
Started Jul 18 05:30:38 PM PDT 24
Finished Jul 18 05:30:45 PM PDT 24
Peak memory 204024 kb
Host smart-d89191c5-dc06-4fcb-a952-115e55ead208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127384413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.127384413
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_override.2274349697
Short name T1313
Test name
Test status
Simulation time 79766111 ps
CPU time 0.66 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:45 PM PDT 24
Peak memory 205148 kb
Host smart-bdc8b1f7-670d-428e-a010-ed5e69c46b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274349697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2274349697
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1348964225
Short name T1580
Test name
Test status
Simulation time 679708854 ps
CPU time 3.98 seconds
Started Jul 18 05:29:40 PM PDT 24
Finished Jul 18 05:29:45 PM PDT 24
Peak memory 233600 kb
Host smart-0f643a22-b985-4f4e-a41b-3a6e7c02fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348964225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1348964225
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.3153724665
Short name T1643
Test name
Test status
Simulation time 6007904242 ps
CPU time 167.84 seconds
Started Jul 18 05:29:40 PM PDT 24
Finished Jul 18 05:32:29 PM PDT 24
Peak memory 819100 kb
Host smart-5d84de31-e0ad-457b-a303-d559dae7aeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153724665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3153724665
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2427519600
Short name T128
Test name
Test status
Simulation time 1400106731 ps
CPU time 57.68 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:30:43 PM PDT 24
Peak memory 294596 kb
Host smart-0b1a3f9e-b9bf-4ad8-8924-8ee37e2a1072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427519600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2427519600
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3887093571
Short name T1226
Test name
Test status
Simulation time 1121263797 ps
CPU time 8.9 seconds
Started Jul 18 05:29:25 PM PDT 24
Finished Jul 18 05:29:36 PM PDT 24
Peak memory 213676 kb
Host smart-ee0cfa4c-e9bd-4b72-b05b-5a254b6069d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887093571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3887093571
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.4004514909
Short name T1314
Test name
Test status
Simulation time 3791398346 ps
CPU time 5.11 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:31:02 PM PDT 24
Peak memory 213840 kb
Host smart-90d0e187-54cc-4f64-8c57-3c30af20020e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004514909 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.4004514909
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.4050775873
Short name T482
Test name
Test status
Simulation time 637729037 ps
CPU time 1.15 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:29:34 PM PDT 24
Peak memory 205600 kb
Host smart-5df6557e-9a5e-4ed1-b4d5-bcfd124e20a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050775873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.4050775873
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1245049516
Short name T899
Test name
Test status
Simulation time 425384125 ps
CPU time 0.98 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:58 PM PDT 24
Peak memory 205244 kb
Host smart-6669bc95-4e9a-4273-877b-d98dc231575c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245049516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1245049516
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.908824878
Short name T965
Test name
Test status
Simulation time 2246916154 ps
CPU time 2.39 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 205468 kb
Host smart-c7a62cf6-a246-4e02-a220-7669308f99af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908824878 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.908824878
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.3102670349
Short name T1463
Test name
Test status
Simulation time 537012653 ps
CPU time 1.19 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:58 PM PDT 24
Peak memory 205220 kb
Host smart-f3bf198a-6c86-420d-b6cd-d0d872855752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102670349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.3102670349
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3794515881
Short name T342
Test name
Test status
Simulation time 1148074537 ps
CPU time 1.93 seconds
Started Jul 18 05:30:51 PM PDT 24
Finished Jul 18 05:30:55 PM PDT 24
Peak memory 213620 kb
Host smart-d9dbc0e4-d9f8-4f4f-b014-293571659904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794515881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3794515881
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1349517339
Short name T293
Test name
Test status
Simulation time 3651654073 ps
CPU time 6.03 seconds
Started Jul 18 05:29:42 PM PDT 24
Finished Jul 18 05:29:49 PM PDT 24
Peak memory 222040 kb
Host smart-e62844e5-2785-4df8-8501-a91ba207999e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349517339 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1349517339
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2153581024
Short name T1383
Test name
Test status
Simulation time 9955983029 ps
CPU time 8.06 seconds
Started Jul 18 05:29:43 PM PDT 24
Finished Jul 18 05:29:53 PM PDT 24
Peak memory 246516 kb
Host smart-e59f857f-7ee4-4624-95fc-4895cb3d3e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153581024 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2153581024
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.456617902
Short name T1506
Test name
Test status
Simulation time 2255808924 ps
CPU time 2.89 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:29:35 PM PDT 24
Peak memory 213848 kb
Host smart-7ec4ebae-2ef6-4abf-8adc-1292a3c073bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456617902 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_nack_acqfull.456617902
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.3658656482
Short name T1633
Test name
Test status
Simulation time 3822472249 ps
CPU time 2.71 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:29:54 PM PDT 24
Peak memory 205692 kb
Host smart-0d0156fc-8800-4ddd-92d1-38ce6f5661a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658656482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.3658656482
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_txstretch.566710400
Short name T871
Test name
Test status
Simulation time 466269804 ps
CPU time 1.55 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:29:53 PM PDT 24
Peak memory 222256 kb
Host smart-722a44b8-90a8-47fc-b639-fbcbf6601def
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566710400 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_nack_txstretch.566710400
Directory /workspace/28.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/28.i2c_target_perf.2682554469
Short name T398
Test name
Test status
Simulation time 4281803030 ps
CPU time 3.45 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 217696 kb
Host smart-d78ee711-5496-414f-8f20-d42801cd59fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682554469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.2682554469
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.779518838
Short name T468
Test name
Test status
Simulation time 2014911957 ps
CPU time 2.48 seconds
Started Jul 18 05:30:38 PM PDT 24
Finished Jul 18 05:30:43 PM PDT 24
Peak memory 203884 kb
Host smart-3862e427-209b-4359-8e1d-93b2b96966a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779518838 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_smbus_maxlen.779518838
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1116488155
Short name T1274
Test name
Test status
Simulation time 13293697005 ps
CPU time 8.81 seconds
Started Jul 18 05:29:40 PM PDT 24
Finished Jul 18 05:29:50 PM PDT 24
Peak memory 213824 kb
Host smart-c094cd8b-ad87-4b16-bec3-21f479d2d161
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116488155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1116488155
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.3650086276
Short name T554
Test name
Test status
Simulation time 25624500601 ps
CPU time 113.46 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:31:26 PM PDT 24
Peak memory 1085276 kb
Host smart-fa21f4cc-03e0-42f8-bb94-30e28d58f795
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650086276 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_stress_all.3650086276
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.114640362
Short name T1392
Test name
Test status
Simulation time 361051963 ps
CPU time 5.67 seconds
Started Jul 18 05:29:42 PM PDT 24
Finished Jul 18 05:29:49 PM PDT 24
Peak memory 204672 kb
Host smart-67e8f684-07b2-4cc4-9256-ad15c485cf15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114640362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.114640362
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1155710196
Short name T1074
Test name
Test status
Simulation time 36877088354 ps
CPU time 482.75 seconds
Started Jul 18 05:29:40 PM PDT 24
Finished Jul 18 05:37:44 PM PDT 24
Peak memory 4301360 kb
Host smart-1b6b8876-0184-4ef5-b8bd-15506ebb02a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155710196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1155710196
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1900049587
Short name T1662
Test name
Test status
Simulation time 4716911051 ps
CPU time 169.4 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 917184 kb
Host smart-d0f15bc7-2083-4385-a3f4-e9a18c902d96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900049587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1900049587
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2571805344
Short name T781
Test name
Test status
Simulation time 2595087226 ps
CPU time 6.67 seconds
Started Jul 18 05:29:31 PM PDT 24
Finished Jul 18 05:29:39 PM PDT 24
Peak memory 222200 kb
Host smart-e867ae80-c8e7-405e-9f09-36fdbf264f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571805344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2571805344
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.3001676167
Short name T1254
Test name
Test status
Simulation time 665588852 ps
CPU time 9.49 seconds
Started Jul 18 05:29:28 PM PDT 24
Finished Jul 18 05:29:39 PM PDT 24
Peak memory 205600 kb
Host smart-23113770-0c9b-4268-980b-de13a561e7ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001676167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.3001676167
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.721214048
Short name T746
Test name
Test status
Simulation time 17254140 ps
CPU time 0.65 seconds
Started Jul 18 05:29:52 PM PDT 24
Finished Jul 18 05:29:55 PM PDT 24
Peak memory 204788 kb
Host smart-eaad58f0-bee2-44e5-92d8-0120f6dba3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721214048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.721214048
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1740224346
Short name T1044
Test name
Test status
Simulation time 651821846 ps
CPU time 2.54 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:29:55 PM PDT 24
Peak memory 213732 kb
Host smart-65aee621-9500-49ff-8ac1-836ee4f3822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740224346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1740224346
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2998857393
Short name T812
Test name
Test status
Simulation time 685096709 ps
CPU time 3.61 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:29:55 PM PDT 24
Peak memory 238060 kb
Host smart-48167d1d-286e-4ef7-9c19-13521371423b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998857393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2998857393
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2602388856
Short name T122
Test name
Test status
Simulation time 12702861144 ps
CPU time 205.38 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:33:17 PM PDT 24
Peak memory 633420 kb
Host smart-37396b9f-2aa4-4860-a84b-df2c34b45c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602388856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2602388856
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1222593127
Short name T396
Test name
Test status
Simulation time 2056242981 ps
CPU time 60.21 seconds
Started Jul 18 05:29:52 PM PDT 24
Finished Jul 18 05:30:55 PM PDT 24
Peak memory 540196 kb
Host smart-2dfcff2c-e237-49de-aa4c-bcc708f4477e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222593127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1222593127
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.4110166876
Short name T1627
Test name
Test status
Simulation time 193086644 ps
CPU time 0.9 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:29:53 PM PDT 24
Peak memory 205200 kb
Host smart-63563330-a752-4f97-8e39-d52d22d6606e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110166876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.4110166876
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.1375029486
Short name T1503
Test name
Test status
Simulation time 141730409 ps
CPU time 3.77 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:29:57 PM PDT 24
Peak memory 229256 kb
Host smart-63c103f2-153c-4d4f-85ca-ff5bab3c272e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375029486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.1375029486
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2801027053
Short name T1421
Test name
Test status
Simulation time 9982190435 ps
CPU time 120.54 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:31:53 PM PDT 24
Peak memory 1337680 kb
Host smart-f1ce8e06-d189-4b22-a6b7-1bc49ae801d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801027053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2801027053
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.2409502960
Short name T1186
Test name
Test status
Simulation time 5322520122 ps
CPU time 7.7 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:30:00 PM PDT 24
Peak memory 205584 kb
Host smart-7fe3ab44-6c77-4a37-b046-ff24313a6fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409502960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.2409502960
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_override.53823475
Short name T112
Test name
Test status
Simulation time 19484920 ps
CPU time 0.73 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:29:53 PM PDT 24
Peak memory 205236 kb
Host smart-81df91c8-5552-49ba-ad51-ebafc884ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53823475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.53823475
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.2404094831
Short name T1367
Test name
Test status
Simulation time 23413356302 ps
CPU time 137.58 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:32:10 PM PDT 24
Peak memory 213824 kb
Host smart-3160ee16-bcbd-43fb-b844-9d1be41a9b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404094831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2404094831
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.13396108
Short name T214
Test name
Test status
Simulation time 2292262311 ps
CPU time 122.37 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:31:52 PM PDT 24
Peak memory 556232 kb
Host smart-a2964347-0aa3-4fb6-a418-dc5324adeb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13396108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.13396108
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1290856704
Short name T1417
Test name
Test status
Simulation time 6637626928 ps
CPU time 75.53 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:31:08 PM PDT 24
Peak memory 333592 kb
Host smart-9ca1f175-7518-4ef8-bbf1-c6af2d7ddc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290856704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1290856704
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.1959131437
Short name T29
Test name
Test status
Simulation time 53034463643 ps
CPU time 970.94 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 3149140 kb
Host smart-93db7d72-daf9-42ce-97e8-48bff80835d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959131437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.1959131437
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2759985298
Short name T32
Test name
Test status
Simulation time 846323863 ps
CPU time 38.15 seconds
Started Jul 18 05:29:51 PM PDT 24
Finished Jul 18 05:30:33 PM PDT 24
Peak memory 213808 kb
Host smart-709d2bd1-624e-4e5c-b237-4ea5f39569c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759985298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2759985298
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3481317827
Short name T1049
Test name
Test status
Simulation time 1974153702 ps
CPU time 5.54 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:29:58 PM PDT 24
Peak memory 210624 kb
Host smart-5900caa9-70b1-4318-92b7-1aa98af16d6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481317827 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3481317827
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1341963839
Short name T377
Test name
Test status
Simulation time 891405664 ps
CPU time 1.69 seconds
Started Jul 18 05:29:51 PM PDT 24
Finished Jul 18 05:29:56 PM PDT 24
Peak memory 213100 kb
Host smart-8f1e4d35-aca5-408f-b890-fd9637dbc054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341963839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1341963839
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.3075035394
Short name T404
Test name
Test status
Simulation time 2000584769 ps
CPU time 3.15 seconds
Started Jul 18 05:29:51 PM PDT 24
Finished Jul 18 05:29:57 PM PDT 24
Peak memory 205580 kb
Host smart-a694a731-e28f-41ae-9f10-f4973051a58a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075035394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.3075035394
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.3005999587
Short name T289
Test name
Test status
Simulation time 123784135 ps
CPU time 0.84 seconds
Started Jul 18 05:29:47 PM PDT 24
Finished Jul 18 05:29:48 PM PDT 24
Peak memory 205360 kb
Host smart-fd0c7c04-28b4-45c4-a90d-997613e32d38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005999587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.3005999587
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.171400440
Short name T832
Test name
Test status
Simulation time 1018892724 ps
CPU time 5.42 seconds
Started Jul 18 05:29:51 PM PDT 24
Finished Jul 18 05:30:00 PM PDT 24
Peak memory 215376 kb
Host smart-9d7ba791-e24b-4cbb-983b-4096791645ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171400440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.171400440
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3683943628
Short name T639
Test name
Test status
Simulation time 9650500148 ps
CPU time 39.74 seconds
Started Jul 18 05:29:47 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 814824 kb
Host smart-182402d6-4b4d-415a-abeb-ce4a88887ac0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683943628 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3683943628
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.1690540661
Short name T563
Test name
Test status
Simulation time 551538030 ps
CPU time 3.17 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:29:55 PM PDT 24
Peak memory 214112 kb
Host smart-aa9c2fc7-8496-443e-bfd2-dccbd8c44d3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690540661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_acqfull.1690540661
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.2386222896
Short name T884
Test name
Test status
Simulation time 4227241852 ps
CPU time 2.73 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:29:56 PM PDT 24
Peak memory 205920 kb
Host smart-cc00a031-52f3-4509-82ec-71649e90bbfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386222896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.2386222896
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_txstretch.297068106
Short name T1327
Test name
Test status
Simulation time 547700611 ps
CPU time 1.56 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:29:54 PM PDT 24
Peak memory 222272 kb
Host smart-2ed2ad1e-7a6c-4b7e-b7cb-a173aa247f8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297068106 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_nack_txstretch.297068106
Directory /workspace/29.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/29.i2c_target_perf.2442096856
Short name T295
Test name
Test status
Simulation time 392982423 ps
CPU time 3.24 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:29:56 PM PDT 24
Peak memory 220436 kb
Host smart-41bff48f-b342-4d96-b606-0a5a60988e03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442096856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.2442096856
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.3088372795
Short name T1246
Test name
Test status
Simulation time 2326399614 ps
CPU time 2.04 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:29:56 PM PDT 24
Peak memory 205484 kb
Host smart-6d42a497-c535-4113-969c-778f39bc5b0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088372795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.3088372795
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.1031455494
Short name T964
Test name
Test status
Simulation time 528099643 ps
CPU time 7.16 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:29:58 PM PDT 24
Peak memory 213824 kb
Host smart-791b742c-b5d1-4269-8d50-a718822624f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031455494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.1031455494
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.804989162
Short name T272
Test name
Test status
Simulation time 41804384244 ps
CPU time 105.83 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:31:36 PM PDT 24
Peak memory 1183596 kb
Host smart-783f50c0-13ff-4fff-8850-f80a49a0f4e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804989162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_target_stress_all.804989162
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.2704433321
Short name T455
Test name
Test status
Simulation time 1313567122 ps
CPU time 25.97 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:30:20 PM PDT 24
Peak memory 213856 kb
Host smart-03098e9a-7991-4242-a74a-c21b292e8a80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704433321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.2704433321
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.551061199
Short name T1631
Test name
Test status
Simulation time 49140804882 ps
CPU time 512.56 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:38:26 PM PDT 24
Peak memory 3870912 kb
Host smart-58ce4c1f-96ce-44b1-b0a8-6b3bae6e8534
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551061199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.551061199
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.39557324
Short name T870
Test name
Test status
Simulation time 3266018552 ps
CPU time 4.2 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:29:58 PM PDT 24
Peak memory 311000 kb
Host smart-27583d21-7108-4000-ada4-6845fa311081
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39557324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_stretch.39557324
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2227229236
Short name T961
Test name
Test status
Simulation time 987828769 ps
CPU time 6.12 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:29:57 PM PDT 24
Peak memory 221932 kb
Host smart-7795367f-d7f8-4d05-8e75-5d2b84c112a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227229236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2227229236
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.777597666
Short name T1135
Test name
Test status
Simulation time 402811492 ps
CPU time 5.63 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:29:58 PM PDT 24
Peak memory 205324 kb
Host smart-1fd25f09-25bd-4a07-974f-6d79140d54a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777597666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.777597666
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2279542199
Short name T1378
Test name
Test status
Simulation time 17056271 ps
CPU time 0.65 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 204744 kb
Host smart-d0d7aff2-27b5-4ebb-9f2a-f19cd13f87fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279542199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2279542199
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3665416997
Short name T1553
Test name
Test status
Simulation time 200217438 ps
CPU time 2.73 seconds
Started Jul 18 05:26:27 PM PDT 24
Finished Jul 18 05:26:32 PM PDT 24
Peak memory 213748 kb
Host smart-b4c35373-194a-46a2-8114-6b3e91fb390a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665416997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3665416997
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.3549242944
Short name T840
Test name
Test status
Simulation time 1991202627 ps
CPU time 26.58 seconds
Started Jul 18 05:26:18 PM PDT 24
Finished Jul 18 05:26:47 PM PDT 24
Peak memory 321304 kb
Host smart-bf04b5cc-14db-4408-8622-df71f0adca36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549242944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.3549242944
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3427863872
Short name T1317
Test name
Test status
Simulation time 6471800474 ps
CPU time 225.59 seconds
Started Jul 18 05:26:24 PM PDT 24
Finished Jul 18 05:30:14 PM PDT 24
Peak memory 689184 kb
Host smart-ccd8592f-56fd-4c53-9cba-2120821aa92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427863872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3427863872
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2388499950
Short name T86
Test name
Test status
Simulation time 5557396380 ps
CPU time 37.88 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:27:03 PM PDT 24
Peak memory 531868 kb
Host smart-dea188aa-9a0a-4173-912f-76d5e2e03136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388499950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2388499950
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3032260581
Short name T686
Test name
Test status
Simulation time 115938500 ps
CPU time 0.92 seconds
Started Jul 18 05:26:19 PM PDT 24
Finished Jul 18 05:26:22 PM PDT 24
Peak memory 205212 kb
Host smart-62d361e7-97ca-45cc-978e-b96610049b65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032260581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3032260581
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2660424224
Short name T1113
Test name
Test status
Simulation time 179039722 ps
CPU time 8.87 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:36 PM PDT 24
Peak memory 205492 kb
Host smart-441f385b-cb68-4d83-89a0-5ae2d04ab9b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660424224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2660424224
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.784901902
Short name T1740
Test name
Test status
Simulation time 25644798816 ps
CPU time 108.69 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:28:16 PM PDT 24
Peak memory 1227812 kb
Host smart-354961ec-fa95-497e-b18c-c40b4a50daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784901902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.784901902
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.1270589783
Short name T1181
Test name
Test status
Simulation time 514354711 ps
CPU time 12.53 seconds
Started Jul 18 05:26:24 PM PDT 24
Finished Jul 18 05:26:41 PM PDT 24
Peak memory 205452 kb
Host smart-6042ab38-a4f4-41a8-a2d2-b50145c41af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270589783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.1270589783
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_override.738073606
Short name T80
Test name
Test status
Simulation time 16611446 ps
CPU time 0.64 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:28 PM PDT 24
Peak memory 205240 kb
Host smart-fedc7fa6-cb92-4bd1-ab80-0a5549f29073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738073606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.738073606
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2983665603
Short name T867
Test name
Test status
Simulation time 785744901 ps
CPU time 12.04 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:26:40 PM PDT 24
Peak memory 227948 kb
Host smart-341f1865-e461-45a4-8dbb-de14d7fd82ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983665603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2983665603
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.389981220
Short name T288
Test name
Test status
Simulation time 231315187 ps
CPU time 4.6 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:29 PM PDT 24
Peak memory 240608 kb
Host smart-87c8ccf8-2551-4ca8-93f0-5360b0621332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389981220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.389981220
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.441217874
Short name T1188
Test name
Test status
Simulation time 5484357761 ps
CPU time 70.78 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:27:39 PM PDT 24
Peak memory 367776 kb
Host smart-2352b57d-65e7-43f2-9dc5-574b31f8f8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441217874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.441217874
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1928861927
Short name T1433
Test name
Test status
Simulation time 1703106827 ps
CPU time 7.24 seconds
Started Jul 18 05:26:27 PM PDT 24
Finished Jul 18 05:26:37 PM PDT 24
Peak memory 213688 kb
Host smart-84987986-6a33-4b70-aa52-71084dc73ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928861927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1928861927
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2090304215
Short name T174
Test name
Test status
Simulation time 107023072 ps
CPU time 0.87 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 223764 kb
Host smart-60e24bdc-3185-4395-98f9-7001d70091c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090304215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2090304215
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2988773767
Short name T962
Test name
Test status
Simulation time 3246151163 ps
CPU time 4.04 seconds
Started Jul 18 05:26:28 PM PDT 24
Finished Jul 18 05:26:34 PM PDT 24
Peak memory 222036 kb
Host smart-cef9c5bc-b737-4065-9e12-10ddf9d272a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988773767 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2988773767
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1356498011
Short name T418
Test name
Test status
Simulation time 776602604 ps
CPU time 1.24 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 205652 kb
Host smart-1d236b45-1dcd-4ebd-832d-0462bb53d534
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356498011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1356498011
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1836346689
Short name T982
Test name
Test status
Simulation time 1141149128 ps
CPU time 1.17 seconds
Started Jul 18 05:26:29 PM PDT 24
Finished Jul 18 05:26:32 PM PDT 24
Peak memory 205744 kb
Host smart-792b5cc0-4c43-490b-a3c2-00286328d25f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836346689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1836346689
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.811775055
Short name T717
Test name
Test status
Simulation time 427408665 ps
CPU time 2.53 seconds
Started Jul 18 05:26:18 PM PDT 24
Finished Jul 18 05:26:22 PM PDT 24
Peak memory 205640 kb
Host smart-9132201e-d143-4644-a4d3-5b4de3ebe19a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811775055 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.811775055
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.2414762114
Short name T340
Test name
Test status
Simulation time 520039866 ps
CPU time 1.21 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:28 PM PDT 24
Peak memory 205452 kb
Host smart-ef256f00-3733-405f-9729-6097a52d56fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414762114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.2414762114
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.2510569671
Short name T823
Test name
Test status
Simulation time 521350032 ps
CPU time 2.04 seconds
Started Jul 18 05:26:29 PM PDT 24
Finished Jul 18 05:26:32 PM PDT 24
Peak memory 221344 kb
Host smart-7127cb83-2127-4b7b-a630-a2b59e54e8fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510569671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.2510569671
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3578703305
Short name T971
Test name
Test status
Simulation time 717910478 ps
CPU time 4.49 seconds
Started Jul 18 05:26:28 PM PDT 24
Finished Jul 18 05:26:34 PM PDT 24
Peak memory 214796 kb
Host smart-eeb87998-9ca3-4056-9273-23de0e20b1ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578703305 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3578703305
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3605978421
Short name T646
Test name
Test status
Simulation time 2794971898 ps
CPU time 6.73 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:26:34 PM PDT 24
Peak memory 205684 kb
Host smart-985f0725-2771-4c78-b79b-808b90178610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605978421 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3605978421
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.913187748
Short name T1487
Test name
Test status
Simulation time 517966746 ps
CPU time 2.91 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:26:30 PM PDT 24
Peak memory 213864 kb
Host smart-85a1d361-7d4d-40c9-bcb4-465fd3f34fac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913187748 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_nack_acqfull.913187748
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.1540088947
Short name T607
Test name
Test status
Simulation time 622823844 ps
CPU time 2.89 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:30 PM PDT 24
Peak memory 205596 kb
Host smart-dd360afa-92f0-4bb1-9bb4-d820d13f7ae7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540088947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.1540088947
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_txstretch.2989546177
Short name T1100
Test name
Test status
Simulation time 130157497 ps
CPU time 1.49 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:26:29 PM PDT 24
Peak memory 222432 kb
Host smart-12199b73-d5ae-43b6-b71f-904bfe0f1d5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989546177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_nack_txstretch.2989546177
Directory /workspace/3.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/3.i2c_target_perf.3097069510
Short name T580
Test name
Test status
Simulation time 1430293911 ps
CPU time 5.21 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:31 PM PDT 24
Peak memory 213824 kb
Host smart-38cc9892-ebe3-4c9b-834b-fbea9eac7d3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097069510 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.3097069510
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.2073544099
Short name T354
Test name
Test status
Simulation time 462121059 ps
CPU time 2.12 seconds
Started Jul 18 05:26:19 PM PDT 24
Finished Jul 18 05:26:23 PM PDT 24
Peak memory 205332 kb
Host smart-d8e6b921-cac4-4fb3-86b6-7e3a9bb42ed4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073544099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_smbus_maxlen.2073544099
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.847065431
Short name T1684
Test name
Test status
Simulation time 731189659 ps
CPU time 11.72 seconds
Started Jul 18 05:26:29 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 221896 kb
Host smart-740ab82f-2228-4ce9-af6b-d41b897fa0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847065431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.847065431
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.2605677484
Short name T1640
Test name
Test status
Simulation time 40353026671 ps
CPU time 1157.37 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 4378316 kb
Host smart-93c45b91-680a-48a1-83de-d9086293715f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605677484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.2605677484
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1608358412
Short name T385
Test name
Test status
Simulation time 4544511503 ps
CPU time 29 seconds
Started Jul 18 05:26:29 PM PDT 24
Finished Jul 18 05:26:59 PM PDT 24
Peak memory 213840 kb
Host smart-f488b1a5-dbcd-492b-b295-d285e5dcbf57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608358412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1608358412
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3016571632
Short name T636
Test name
Test status
Simulation time 48865750234 ps
CPU time 1169.02 seconds
Started Jul 18 05:26:27 PM PDT 24
Finished Jul 18 05:45:59 PM PDT 24
Peak memory 7400708 kb
Host smart-9daac269-e48a-40ae-8819-64038a4d714f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016571632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3016571632
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.29929534
Short name T1248
Test name
Test status
Simulation time 2642882150 ps
CPU time 9.48 seconds
Started Jul 18 05:26:27 PM PDT 24
Finished Jul 18 05:26:39 PM PDT 24
Peak memory 333272 kb
Host smart-e71c1165-2b1d-47ef-9bc8-ccd381233055
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29929534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_stretch.29929534
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2138574237
Short name T600
Test name
Test status
Simulation time 5530548871 ps
CPU time 6.67 seconds
Started Jul 18 05:26:17 PM PDT 24
Finished Jul 18 05:26:24 PM PDT 24
Peak memory 222220 kb
Host smart-85904dcf-cdd1-48d8-a637-c5ca7becb064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138574237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2138574237
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.1339829741
Short name T1098
Test name
Test status
Simulation time 75523119 ps
CPU time 1.7 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 205596 kb
Host smart-c1f3d43b-0232-4da6-ae37-e6a5ece55093
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339829741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.1339829741
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1856853160
Short name T1642
Test name
Test status
Simulation time 45083028 ps
CPU time 0.63 seconds
Started Jul 18 05:30:06 PM PDT 24
Finished Jul 18 05:30:10 PM PDT 24
Peak memory 204696 kb
Host smart-426fb9f8-d3f3-4b42-977d-23cbc1aa6415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856853160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1856853160
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1531143531
Short name T1409
Test name
Test status
Simulation time 65258402 ps
CPU time 1.7 seconds
Started Jul 18 05:30:05 PM PDT 24
Finished Jul 18 05:30:10 PM PDT 24
Peak memory 213728 kb
Host smart-8af359c5-88c6-4073-b4bf-04f0a8746494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531143531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1531143531
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1048826347
Short name T270
Test name
Test status
Simulation time 1876816738 ps
CPU time 17.11 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:30:09 PM PDT 24
Peak memory 264632 kb
Host smart-13b20fa2-ba43-470e-81d7-4e9d814f3eb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048826347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1048826347
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2749481476
Short name T818
Test name
Test status
Simulation time 10130952509 ps
CPU time 80.27 seconds
Started Jul 18 05:29:48 PM PDT 24
Finished Jul 18 05:31:12 PM PDT 24
Peak memory 389132 kb
Host smart-846241d1-6fd9-426b-82cb-b5415adbfcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749481476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2749481476
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2192322311
Short name T1343
Test name
Test status
Simulation time 10192464882 ps
CPU time 191.81 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:33:06 PM PDT 24
Peak memory 818496 kb
Host smart-c6c5d401-ab10-4965-b780-e89526837cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192322311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2192322311
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2895754182
Short name T1419
Test name
Test status
Simulation time 117677379 ps
CPU time 1.17 seconds
Started Jul 18 05:29:46 PM PDT 24
Finished Jul 18 05:29:48 PM PDT 24
Peak memory 205368 kb
Host smart-bad82c9f-002f-4cbc-9830-7f0c3926b12b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895754182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2895754182
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1846249736
Short name T997
Test name
Test status
Simulation time 782168002 ps
CPU time 4.6 seconds
Started Jul 18 05:29:51 PM PDT 24
Finished Jul 18 05:29:59 PM PDT 24
Peak memory 205484 kb
Host smart-4953dd85-1124-407d-8baf-49d5072ec121
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846249736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1846249736
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1673848425
Short name T1272
Test name
Test status
Simulation time 12317111390 ps
CPU time 74.17 seconds
Started Jul 18 05:29:49 PM PDT 24
Finished Jul 18 05:31:06 PM PDT 24
Peak memory 883512 kb
Host smart-93e47885-1568-4c87-934b-006db88407fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673848425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1673848425
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.3959622891
Short name T241
Test name
Test status
Simulation time 543487200 ps
CPU time 8.48 seconds
Started Jul 18 05:30:06 PM PDT 24
Finished Jul 18 05:30:18 PM PDT 24
Peak memory 205476 kb
Host smart-9e2555f4-978b-4202-85f0-31d7bacbdd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959622891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3959622891
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.661216371
Short name T246
Test name
Test status
Simulation time 96589201 ps
CPU time 1.5 seconds
Started Jul 18 05:30:01 PM PDT 24
Finished Jul 18 05:30:04 PM PDT 24
Peak memory 219948 kb
Host smart-e5592c51-6718-439e-a884-3bd0023d6298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661216371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.661216371
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3125906859
Short name T118
Test name
Test status
Simulation time 28211362 ps
CPU time 0.72 seconds
Started Jul 18 05:29:51 PM PDT 24
Finished Jul 18 05:29:55 PM PDT 24
Peak memory 205200 kb
Host smart-e5c94670-c2b4-4556-8ab8-88b34d57e0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125906859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3125906859
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2737650361
Short name T309
Test name
Test status
Simulation time 7044886831 ps
CPU time 15.84 seconds
Started Jul 18 05:29:51 PM PDT 24
Finished Jul 18 05:30:10 PM PDT 24
Peak memory 234668 kb
Host smart-185e4342-c1df-4e2a-8d42-2201399a518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737650361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2737650361
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.427708889
Short name T1230
Test name
Test status
Simulation time 170079929 ps
CPU time 3.81 seconds
Started Jul 18 05:30:06 PM PDT 24
Finished Jul 18 05:30:15 PM PDT 24
Peak memory 234740 kb
Host smart-d35b9686-20db-4acc-af07-d98340b04865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427708889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.427708889
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1309720747
Short name T650
Test name
Test status
Simulation time 12696633983 ps
CPU time 21.24 seconds
Started Jul 18 05:29:52 PM PDT 24
Finished Jul 18 05:30:16 PM PDT 24
Peak memory 335548 kb
Host smart-a20f7eb0-695d-47f2-ad61-2570188321f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309720747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1309720747
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2865381540
Short name T14
Test name
Test status
Simulation time 8462162924 ps
CPU time 578.41 seconds
Started Jul 18 05:30:02 PM PDT 24
Finished Jul 18 05:39:43 PM PDT 24
Peak memory 902612 kb
Host smart-7816adad-8d22-4853-81ac-0cbd7421b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865381540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2865381540
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2495037400
Short name T520
Test name
Test status
Simulation time 846884275 ps
CPU time 39.38 seconds
Started Jul 18 05:29:50 PM PDT 24
Finished Jul 18 05:30:33 PM PDT 24
Peak memory 213976 kb
Host smart-14571b6a-bba5-4e22-8077-26124c1d0455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495037400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2495037400
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2371066816
Short name T1269
Test name
Test status
Simulation time 1173542934 ps
CPU time 6.05 seconds
Started Jul 18 05:30:03 PM PDT 24
Finished Jul 18 05:30:12 PM PDT 24
Peak memory 213968 kb
Host smart-01112f11-aaf1-47b0-b051-ef68bf6f30c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371066816 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2371066816
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.3888105423
Short name T914
Test name
Test status
Simulation time 207355116 ps
CPU time 1.34 seconds
Started Jul 18 05:30:04 PM PDT 24
Finished Jul 18 05:30:09 PM PDT 24
Peak memory 205596 kb
Host smart-72301d94-af66-4a55-bdf5-b68513dfb776
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888105423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.3888105423
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2981385888
Short name T221
Test name
Test status
Simulation time 213261096 ps
CPU time 1.33 seconds
Started Jul 18 05:30:04 PM PDT 24
Finished Jul 18 05:30:08 PM PDT 24
Peak memory 205692 kb
Host smart-b19fb3de-7e6e-44b7-9132-2ff3354cb3c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981385888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2981385888
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.2482132048
Short name T466
Test name
Test status
Simulation time 2741296446 ps
CPU time 2.68 seconds
Started Jul 18 05:30:02 PM PDT 24
Finished Jul 18 05:30:07 PM PDT 24
Peak memory 205708 kb
Host smart-6daa3142-ca0b-4361-bfed-9d0b45f3d309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482132048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.2482132048
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.3450618411
Short name T449
Test name
Test status
Simulation time 142746182 ps
CPU time 1.48 seconds
Started Jul 18 05:30:06 PM PDT 24
Finished Jul 18 05:30:11 PM PDT 24
Peak memory 205392 kb
Host smart-899151f9-ce92-4087-a4c3-e503fd63f544
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450618411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.3450618411
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.3014781268
Short name T1291
Test name
Test status
Simulation time 1006266849 ps
CPU time 5.5 seconds
Started Jul 18 05:30:02 PM PDT 24
Finished Jul 18 05:30:10 PM PDT 24
Peak memory 222132 kb
Host smart-90b193b1-b808-42b4-bac7-38364f72ef1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014781268 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.3014781268
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1306703919
Short name T1095
Test name
Test status
Simulation time 3754094159 ps
CPU time 2.85 seconds
Started Jul 18 05:30:04 PM PDT 24
Finished Jul 18 05:30:10 PM PDT 24
Peak memory 205720 kb
Host smart-5d1033c8-6e82-48a5-b4a8-f0bf2b48214e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306703919 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1306703919
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.3828596358
Short name T1550
Test name
Test status
Simulation time 3968069568 ps
CPU time 2.99 seconds
Started Jul 18 05:30:01 PM PDT 24
Finished Jul 18 05:30:05 PM PDT 24
Peak memory 213816 kb
Host smart-983cc3b2-b790-4b13-84c0-11acc913b2a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828596358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_acqfull.3828596358
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.1557563777
Short name T574
Test name
Test status
Simulation time 549524950 ps
CPU time 2.69 seconds
Started Jul 18 05:30:03 PM PDT 24
Finished Jul 18 05:30:09 PM PDT 24
Peak memory 206132 kb
Host smart-ff91c28f-83df-4aa1-a65a-485bde20124c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557563777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.1557563777
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_txstretch.3765955243
Short name T1124
Test name
Test status
Simulation time 620647204 ps
CPU time 1.38 seconds
Started Jul 18 05:30:07 PM PDT 24
Finished Jul 18 05:30:14 PM PDT 24
Peak memory 222084 kb
Host smart-27af55ac-c329-41ed-8486-5ec80b12aed4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765955243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_nack_txstretch.3765955243
Directory /workspace/30.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/30.i2c_target_perf.3856995306
Short name T381
Test name
Test status
Simulation time 3700249200 ps
CPU time 5.22 seconds
Started Jul 18 05:30:01 PM PDT 24
Finished Jul 18 05:30:07 PM PDT 24
Peak memory 213916 kb
Host smart-e1b633e0-d575-4e24-b3ae-39dbfd21f29e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856995306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.3856995306
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.1777757100
Short name T846
Test name
Test status
Simulation time 508345621 ps
CPU time 2.27 seconds
Started Jul 18 05:30:01 PM PDT 24
Finished Jul 18 05:30:05 PM PDT 24
Peak memory 205416 kb
Host smart-644890a0-d974-44ff-ab74-892d837bee78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777757100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_smbus_maxlen.1777757100
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1365339994
Short name T626
Test name
Test status
Simulation time 3095696520 ps
CPU time 7.23 seconds
Started Jul 18 05:30:00 PM PDT 24
Finished Jul 18 05:30:08 PM PDT 24
Peak memory 214020 kb
Host smart-7df88b64-4d81-4f2d-b5dd-8ff8b00eb938
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365339994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1365339994
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.1084918968
Short name T1094
Test name
Test status
Simulation time 7140102689 ps
CPU time 40.88 seconds
Started Jul 18 05:30:03 PM PDT 24
Finished Jul 18 05:30:46 PM PDT 24
Peak memory 230916 kb
Host smart-2a38be97-9cc2-4169-ad53-a5ee597c5913
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084918968 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.1084918968
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.4196842811
Short name T632
Test name
Test status
Simulation time 493057583 ps
CPU time 20.5 seconds
Started Jul 18 05:30:01 PM PDT 24
Finished Jul 18 05:30:24 PM PDT 24
Peak memory 205544 kb
Host smart-8a78b3a8-5617-4d28-96f6-f254da735bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196842811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.4196842811
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1902875104
Short name T54
Test name
Test status
Simulation time 49616341355 ps
CPU time 149.71 seconds
Started Jul 18 05:30:03 PM PDT 24
Finished Jul 18 05:32:35 PM PDT 24
Peak memory 1935568 kb
Host smart-06f3ff99-117a-43ec-a6fe-2946b9d6ad31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902875104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1902875104
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2679019487
Short name T1305
Test name
Test status
Simulation time 1201794569 ps
CPU time 9.12 seconds
Started Jul 18 05:30:07 PM PDT 24
Finished Jul 18 05:30:21 PM PDT 24
Peak memory 302164 kb
Host smart-7584015b-282c-4543-a245-9df09038ad7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679019487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2679019487
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2640921304
Short name T826
Test name
Test status
Simulation time 6275097700 ps
CPU time 7.66 seconds
Started Jul 18 05:30:05 PM PDT 24
Finished Jul 18 05:30:16 PM PDT 24
Peak memory 213828 kb
Host smart-a29d92b9-ccf8-42d8-ab1c-5118406a9f4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640921304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2640921304
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.1105044094
Short name T1201
Test name
Test status
Simulation time 76223739 ps
CPU time 1.75 seconds
Started Jul 18 05:30:03 PM PDT 24
Finished Jul 18 05:30:07 PM PDT 24
Peak memory 205644 kb
Host smart-14bed1d1-2ecb-4316-b74a-11f9520b0218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105044094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.1105044094
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1029617037
Short name T1324
Test name
Test status
Simulation time 28397459 ps
CPU time 0.64 seconds
Started Jul 18 05:30:16 PM PDT 24
Finished Jul 18 05:30:19 PM PDT 24
Peak memory 204788 kb
Host smart-74327e2f-24ec-4dbf-84be-18fadc5e91a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029617037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1029617037
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1935757477
Short name T25
Test name
Test status
Simulation time 344756968 ps
CPU time 3.34 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:25 PM PDT 24
Peak memory 230992 kb
Host smart-f23c98b5-1215-448d-ade1-553d971a4222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935757477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1935757477
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.691457498
Short name T1700
Test name
Test status
Simulation time 791009876 ps
CPU time 21.31 seconds
Started Jul 18 05:30:03 PM PDT 24
Finished Jul 18 05:30:26 PM PDT 24
Peak memory 295232 kb
Host smart-9bb6db1a-c714-43fb-b34c-a5d7a71e57ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691457498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.691457498
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2352885406
Short name T1516
Test name
Test status
Simulation time 2759178029 ps
CPU time 163.13 seconds
Started Jul 18 05:30:07 PM PDT 24
Finished Jul 18 05:32:55 PM PDT 24
Peak memory 432256 kb
Host smart-61b2ce1a-ff83-4739-a34a-69d454cd8e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352885406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2352885406
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2361304007
Short name T726
Test name
Test status
Simulation time 2299069945 ps
CPU time 162.8 seconds
Started Jul 18 05:30:06 PM PDT 24
Finished Jul 18 05:32:52 PM PDT 24
Peak memory 732980 kb
Host smart-483a8d45-4743-41b3-9ac9-9691965719d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361304007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2361304007
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2934577092
Short name T1119
Test name
Test status
Simulation time 119272741 ps
CPU time 1.05 seconds
Started Jul 18 05:30:07 PM PDT 24
Finished Jul 18 05:30:13 PM PDT 24
Peak memory 205240 kb
Host smart-c9e7b9e9-4b20-4a0d-9d0d-cd27497eb356
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934577092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2934577092
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1178743121
Short name T1303
Test name
Test status
Simulation time 1085474208 ps
CPU time 5.58 seconds
Started Jul 18 05:30:01 PM PDT 24
Finished Jul 18 05:30:08 PM PDT 24
Peak memory 205488 kb
Host smart-8479e0b3-4e74-4f69-95e2-dc62efaaa34a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178743121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1178743121
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.4181116725
Short name T1108
Test name
Test status
Simulation time 19719419469 ps
CPU time 138.74 seconds
Started Jul 18 05:30:02 PM PDT 24
Finished Jul 18 05:32:23 PM PDT 24
Peak memory 1359960 kb
Host smart-db338ce4-75ad-4e09-a620-548aed811ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181116725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4181116725
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2293052605
Short name T1105
Test name
Test status
Simulation time 709872130 ps
CPU time 10.9 seconds
Started Jul 18 05:30:16 PM PDT 24
Finished Jul 18 05:30:29 PM PDT 24
Peak memory 205528 kb
Host smart-417c1327-6686-432a-913a-f6af480d01d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293052605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2293052605
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_override.2392420329
Short name T115
Test name
Test status
Simulation time 70441117 ps
CPU time 0.76 seconds
Started Jul 18 05:30:04 PM PDT 24
Finished Jul 18 05:30:08 PM PDT 24
Peak memory 205236 kb
Host smart-a80db7a0-12aa-44a8-ad3b-a0d1119dd8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392420329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2392420329
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.898913524
Short name T1408
Test name
Test status
Simulation time 7073205171 ps
CPU time 63.48 seconds
Started Jul 18 05:30:04 PM PDT 24
Finished Jul 18 05:31:11 PM PDT 24
Peak memory 213672 kb
Host smart-6cf855b6-7001-45ba-a424-02a7186a8a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898913524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.898913524
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.1454457564
Short name T1454
Test name
Test status
Simulation time 251370347 ps
CPU time 4.32 seconds
Started Jul 18 05:30:07 PM PDT 24
Finished Jul 18 05:30:16 PM PDT 24
Peak memory 221616 kb
Host smart-f98ccf1c-c049-469d-938e-255c26e529ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454457564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.1454457564
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2324682842
Short name T1483
Test name
Test status
Simulation time 5052174777 ps
CPU time 19.03 seconds
Started Jul 18 05:30:06 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 318756 kb
Host smart-ac2a4615-c334-47fc-a92f-294f07bf8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324682842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2324682842
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.2203227360
Short name T716
Test name
Test status
Simulation time 749454412 ps
CPU time 32.42 seconds
Started Jul 18 05:30:16 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 213740 kb
Host smart-ae9ab0f5-5bfd-4a5c-b6bf-163b993acee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203227360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.2203227360
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1634519843
Short name T709
Test name
Test status
Simulation time 18623647349 ps
CPU time 6.28 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:30 PM PDT 24
Peak memory 219804 kb
Host smart-5c6b4eaa-05b7-41d3-8f31-98f07306a045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634519843 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1634519843
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1633147295
Short name T562
Test name
Test status
Simulation time 319851177 ps
CPU time 1.22 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:30:29 PM PDT 24
Peak memory 205580 kb
Host smart-dddbb18a-53e5-409d-a281-9e396b1ebe53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633147295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1633147295
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2176301297
Short name T1434
Test name
Test status
Simulation time 243868307 ps
CPU time 1.44 seconds
Started Jul 18 05:30:17 PM PDT 24
Finished Jul 18 05:30:20 PM PDT 24
Peak memory 205660 kb
Host smart-3a2e8edc-07a2-4890-bf0e-9af40cfca113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176301297 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2176301297
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.3766068050
Short name T1166
Test name
Test status
Simulation time 2314281439 ps
CPU time 1.93 seconds
Started Jul 18 05:30:17 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 205684 kb
Host smart-e6b7ba59-b821-4394-a492-f64cec5e0569
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766068050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.3766068050
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.1866049860
Short name T277
Test name
Test status
Simulation time 771869106 ps
CPU time 1.21 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:27 PM PDT 24
Peak memory 205420 kb
Host smart-6f84f2c5-6693-47ac-bb56-5069d0a9c5ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866049860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.1866049860
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.2020582936
Short name T959
Test name
Test status
Simulation time 1253274953 ps
CPU time 1.51 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:23 PM PDT 24
Peak memory 204336 kb
Host smart-477ec6c6-231b-493c-91d4-f9fc5f0b6711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020582936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.2020582936
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3011435438
Short name T1675
Test name
Test status
Simulation time 712459495 ps
CPU time 4.73 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:30 PM PDT 24
Peak memory 215496 kb
Host smart-3f35935b-b05d-447b-a4ca-05ee27eb5213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011435438 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3011435438
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1883753299
Short name T408
Test name
Test status
Simulation time 2330744303 ps
CPU time 5.49 seconds
Started Jul 18 05:30:18 PM PDT 24
Finished Jul 18 05:30:26 PM PDT 24
Peak memory 205492 kb
Host smart-325ac804-1a34-40d2-9ee4-ed74f4172f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883753299 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1883753299
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.3158775444
Short name T1318
Test name
Test status
Simulation time 2167195092 ps
CPU time 2.82 seconds
Started Jul 18 05:30:23 PM PDT 24
Finished Jul 18 05:30:32 PM PDT 24
Peak memory 213848 kb
Host smart-79e0210a-d1af-4506-bba2-58d6bdb68f72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158775444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_nack_acqfull.3158775444
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.986416484
Short name T48
Test name
Test status
Simulation time 1042667304 ps
CPU time 2.45 seconds
Started Jul 18 05:30:18 PM PDT 24
Finished Jul 18 05:30:22 PM PDT 24
Peak memory 205656 kb
Host smart-08f0336b-7e28-440d-8ba6-1da4bcf090c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986416484 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.986416484
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_txstretch.132179054
Short name T1220
Test name
Test status
Simulation time 135391216 ps
CPU time 1.36 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:26 PM PDT 24
Peak memory 222232 kb
Host smart-0f719d1c-360b-40cf-98f6-3bab2c4c2f6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132179054 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_nack_txstretch.132179054
Directory /workspace/31.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/31.i2c_target_perf.1176610858
Short name T414
Test name
Test status
Simulation time 729159459 ps
CPU time 5.1 seconds
Started Jul 18 05:30:17 PM PDT 24
Finished Jul 18 05:30:24 PM PDT 24
Peak memory 213876 kb
Host smart-99b2c3dd-e252-4f55-b8dd-a397ab277db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176610858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.1176610858
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.2992450323
Short name T159
Test name
Test status
Simulation time 2226258052 ps
CPU time 2.42 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:23 PM PDT 24
Peak memory 205424 kb
Host smart-4587ba17-755d-44dc-ac62-50a8f639cfcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992450323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.2992450323
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2876917769
Short name T1287
Test name
Test status
Simulation time 430652360 ps
CPU time 7.57 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 213768 kb
Host smart-f5f0739f-bd50-4787-b823-699af0ed5b02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876917769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2876917769
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.638199276
Short name T1610
Test name
Test status
Simulation time 48519642392 ps
CPU time 1614.3 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:57:22 PM PDT 24
Peak memory 5223452 kb
Host smart-e1dca0b1-fcd3-44f4-83a0-14f2c0f696a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638199276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.i2c_target_stress_all.638199276
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2795123417
Short name T384
Test name
Test status
Simulation time 1706480371 ps
CPU time 13.33 seconds
Started Jul 18 05:30:23 PM PDT 24
Finished Jul 18 05:30:42 PM PDT 24
Peak memory 205548 kb
Host smart-19bb11c5-a7be-40ec-8f97-f21f455cc07c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795123417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2795123417
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2893375922
Short name T657
Test name
Test status
Simulation time 25335797795 ps
CPU time 14.62 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:39 PM PDT 24
Peak memory 326032 kb
Host smart-6146b6c9-19b6-4834-853a-d4a06f541db0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893375922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2893375922
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1819581058
Short name T1322
Test name
Test status
Simulation time 4525236898 ps
CPU time 32.52 seconds
Started Jul 18 05:30:17 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 686220 kb
Host smart-b33ba888-295c-465a-a946-553a3ed4a9fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819581058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1819581058
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.588588083
Short name T1173
Test name
Test status
Simulation time 1008337177 ps
CPU time 6 seconds
Started Jul 18 05:30:16 PM PDT 24
Finished Jul 18 05:30:24 PM PDT 24
Peak memory 222012 kb
Host smart-aeed3080-3c21-4310-9e20-8f052a34005b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588588083 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.588588083
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.427282132
Short name T1063
Test name
Test status
Simulation time 67180403 ps
CPU time 1.51 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:25 PM PDT 24
Peak memory 205636 kb
Host smart-56ed322e-24d3-4ce4-884f-20a4035f2ca5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427282132 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.427282132
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.4167291811
Short name T440
Test name
Test status
Simulation time 27333618 ps
CPU time 0.64 seconds
Started Jul 18 05:30:23 PM PDT 24
Finished Jul 18 05:30:29 PM PDT 24
Peak memory 204408 kb
Host smart-94f64af6-0afd-4a47-9e67-feb1048e8c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167291811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.4167291811
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3745830383
Short name T671
Test name
Test status
Simulation time 61267813 ps
CPU time 1.8 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:25 PM PDT 24
Peak memory 213772 kb
Host smart-4e399c74-12a5-494e-8bf9-ecb1e0d08de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745830383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3745830383
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.4017173284
Short name T1268
Test name
Test status
Simulation time 581782423 ps
CPU time 15.45 seconds
Started Jul 18 05:30:17 PM PDT 24
Finished Jul 18 05:30:34 PM PDT 24
Peak memory 265328 kb
Host smart-115c4a6a-e788-42fa-af22-f4d04af95b69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017173284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.4017173284
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.4080746236
Short name T540
Test name
Test status
Simulation time 4048340356 ps
CPU time 309.19 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:35:37 PM PDT 24
Peak memory 947144 kb
Host smart-3ba63930-2d26-4aa3-91cd-785f653b9b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080746236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.4080746236
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1377740945
Short name T1200
Test name
Test status
Simulation time 3322051041 ps
CPU time 112.21 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:32:15 PM PDT 24
Peak memory 596140 kb
Host smart-14832595-ac5c-4364-9b95-6d0251977bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377740945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1377740945
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3409330584
Short name T1102
Test name
Test status
Simulation time 204591315 ps
CPU time 1.14 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:25 PM PDT 24
Peak memory 205500 kb
Host smart-c0b945ca-a395-468b-8879-858372259a7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409330584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3409330584
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1212138152
Short name T1337
Test name
Test status
Simulation time 695925232 ps
CPU time 9.58 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:31 PM PDT 24
Peak memory 205552 kb
Host smart-5acada87-c498-4645-b344-e7f5ca63241b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212138152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1212138152
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2163215980
Short name T124
Test name
Test status
Simulation time 5153142443 ps
CPU time 155.65 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:33:01 PM PDT 24
Peak memory 1401760 kb
Host smart-4b0a2c2d-d496-4b82-93ba-07c4466ff4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163215980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2163215980
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1565746571
Short name T1717
Test name
Test status
Simulation time 555317097 ps
CPU time 23.04 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:50 PM PDT 24
Peak memory 205528 kb
Host smart-f2d02a6c-ee31-484c-83c1-892cbabc9c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565746571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1565746571
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.2428781463
Short name T1667
Test name
Test status
Simulation time 84214668 ps
CPU time 0.69 seconds
Started Jul 18 05:30:18 PM PDT 24
Finished Jul 18 05:30:20 PM PDT 24
Peak memory 205192 kb
Host smart-020ed007-ca72-4b5c-b1df-2ac0b5c8849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428781463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.2428781463
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1202132535
Short name T1686
Test name
Test status
Simulation time 674800268 ps
CPU time 7.04 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 224936 kb
Host smart-b4079952-6beb-49b9-862f-6390c3a15dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202132535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1202132535
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.1688476131
Short name T322
Test name
Test status
Simulation time 230554836 ps
CPU time 1.56 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:25 PM PDT 24
Peak memory 205384 kb
Host smart-8f078d82-10d0-4a34-934a-797a1309ce94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688476131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.1688476131
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2798526021
Short name T1079
Test name
Test status
Simulation time 1337142799 ps
CPU time 27.95 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:52 PM PDT 24
Peak memory 388080 kb
Host smart-d286b85c-b0d9-41fe-aced-766830079852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798526021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2798526021
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3708869992
Short name T299
Test name
Test status
Simulation time 395708194 ps
CPU time 17.24 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:39 PM PDT 24
Peak memory 213788 kb
Host smart-83e8d3c5-3d41-4e27-9a6d-d230414e982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708869992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3708869992
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.3169484401
Short name T862
Test name
Test status
Simulation time 6327938762 ps
CPU time 5.13 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:30:33 PM PDT 24
Peak memory 213872 kb
Host smart-6d251755-36ad-416f-b48c-d2bec90a1209
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169484401 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3169484401
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3070909250
Short name T1646
Test name
Test status
Simulation time 490134019 ps
CPU time 1.1 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 205492 kb
Host smart-0066cf1e-d541-4078-81d3-0f7a0e84bfa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070909250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3070909250
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1891390959
Short name T361
Test name
Test status
Simulation time 167056460 ps
CPU time 1.07 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:30:29 PM PDT 24
Peak memory 205444 kb
Host smart-b76fc43b-3f2d-41af-8d5c-5360adc90acf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891390959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1891390959
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.1090395704
Short name T1355
Test name
Test status
Simulation time 507832175 ps
CPU time 2.38 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:29 PM PDT 24
Peak memory 205600 kb
Host smart-98ce1180-baaf-4d1e-b353-e5dfecdf9720
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090395704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.1090395704
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.4041150486
Short name T828
Test name
Test status
Simulation time 847326947 ps
CPU time 6.2 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:32 PM PDT 24
Peak memory 215040 kb
Host smart-9c1510f4-ce07-402d-b2f4-25f39404b16e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041150486 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.4041150486
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.3836572267
Short name T1460
Test name
Test status
Simulation time 11303996279 ps
CPU time 4.84 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:27 PM PDT 24
Peak memory 271884 kb
Host smart-cfd5dd77-987d-429b-8788-c556e1d9704b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836572267 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3836572267
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.162439294
Short name T1423
Test name
Test status
Simulation time 1117570794 ps
CPU time 3.12 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:30:31 PM PDT 24
Peak memory 213780 kb
Host smart-c8035a49-8d90-4a24-afc5-baf8f824bd42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162439294 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_nack_acqfull.162439294
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.886063698
Short name T372
Test name
Test status
Simulation time 2028148054 ps
CPU time 2.5 seconds
Started Jul 18 05:30:38 PM PDT 24
Finished Jul 18 05:30:43 PM PDT 24
Peak memory 205604 kb
Host smart-06fe6689-a448-4cf8-9016-956d9a41930d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886063698 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.886063698
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.3452539247
Short name T1710
Test name
Test status
Simulation time 566785074 ps
CPU time 4.21 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:30:32 PM PDT 24
Peak memory 213832 kb
Host smart-c03e6556-daeb-4706-9d7d-5027767caaab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452539247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.3452539247
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.3923643038
Short name T720
Test name
Test status
Simulation time 552149066 ps
CPU time 2.48 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 205388 kb
Host smart-59a55966-d472-4d42-8d07-fdff872c8ec4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923643038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_smbus_maxlen.3923643038
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.447110412
Short name T1543
Test name
Test status
Simulation time 9994614144 ps
CPU time 14.88 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:37 PM PDT 24
Peak memory 213996 kb
Host smart-fd06b086-69ae-45a0-b0c3-fa07a397a773
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447110412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.447110412
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.271219596
Short name T1260
Test name
Test status
Simulation time 50942091628 ps
CPU time 74.93 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:31:42 PM PDT 24
Peak memory 568740 kb
Host smart-f6e45c63-d1b1-4658-a904-142b77ce1ba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271219596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.i2c_target_stress_all.271219596
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3581349738
Short name T1380
Test name
Test status
Simulation time 6543685830 ps
CPU time 7.6 seconds
Started Jul 18 05:30:18 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 215840 kb
Host smart-12209462-70c0-4cd8-96c3-08da53334c62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581349738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3581349738
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.2279588811
Short name T1092
Test name
Test status
Simulation time 7784582796 ps
CPU time 14.39 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:41 PM PDT 24
Peak memory 205436 kb
Host smart-46bc2f7f-a182-47ed-9fd7-ff7d6a520223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279588811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.2279588811
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1295858496
Short name T1304
Test name
Test status
Simulation time 3190516898 ps
CPU time 13.66 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:36 PM PDT 24
Peak memory 358068 kb
Host smart-2cf08a71-334a-48b7-9968-f9629547d7be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295858496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1295858496
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1842527113
Short name T530
Test name
Test status
Simulation time 2009905305 ps
CPU time 6.67 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:31 PM PDT 24
Peak memory 222008 kb
Host smart-ce474855-30dc-4d4f-8c2b-799590b2fd79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842527113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1842527113
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.192477245
Short name T589
Test name
Test status
Simulation time 93359419 ps
CPU time 2.08 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:24 PM PDT 24
Peak memory 205600 kb
Host smart-31c7d1c1-a276-49aa-b080-3d4e1f450370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192477245 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.192477245
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3456956358
Short name T992
Test name
Test status
Simulation time 23294764 ps
CPU time 0.64 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 204732 kb
Host smart-62dc15e1-d5f8-4fb2-829e-c04caae61a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456956358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3456956358
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.4206482220
Short name T1215
Test name
Test status
Simulation time 504950438 ps
CPU time 9.25 seconds
Started Jul 18 05:30:26 PM PDT 24
Finished Jul 18 05:30:39 PM PDT 24
Peak memory 319132 kb
Host smart-489c70e1-30ee-4aec-b184-d302a88b88d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206482220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.4206482220
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.445403427
Short name T21
Test name
Test status
Simulation time 2550893306 ps
CPU time 72.55 seconds
Started Jul 18 05:30:25 PM PDT 24
Finished Jul 18 05:31:43 PM PDT 24
Peak memory 523740 kb
Host smart-f379b368-857a-4c57-939b-71deea88cc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445403427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.445403427
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2590955793
Short name T1422
Test name
Test status
Simulation time 17325409413 ps
CPU time 202.4 seconds
Started Jul 18 05:30:26 PM PDT 24
Finished Jul 18 05:33:53 PM PDT 24
Peak memory 853592 kb
Host smart-7ec9470f-402b-40c2-8635-6d0a0e5e2c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590955793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2590955793
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.129027863
Short name T1229
Test name
Test status
Simulation time 330239584 ps
CPU time 0.84 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:27 PM PDT 24
Peak memory 205256 kb
Host smart-251e7b4e-4eed-4dbd-8d92-b0a06ee5a2e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129027863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.129027863
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1343852762
Short name T486
Test name
Test status
Simulation time 849113595 ps
CPU time 12.3 seconds
Started Jul 18 05:30:34 PM PDT 24
Finished Jul 18 05:30:47 PM PDT 24
Peak memory 249524 kb
Host smart-64bad63c-fec7-4583-8f66-c9fcb71decfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343852762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1343852762
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2676194245
Short name T106
Test name
Test status
Simulation time 2799245653 ps
CPU time 57.87 seconds
Started Jul 18 05:30:28 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 835676 kb
Host smart-a77143d7-d8dd-4a70-b50c-4f02957ccd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676194245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2676194245
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2352863204
Short name T240
Test name
Test status
Simulation time 4263000483 ps
CPU time 9.91 seconds
Started Jul 18 05:30:27 PM PDT 24
Finished Jul 18 05:30:41 PM PDT 24
Peak memory 205512 kb
Host smart-f5268e1a-a557-4144-8e8e-99eee0de9329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352863204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2352863204
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.3066131944
Short name T110
Test name
Test status
Simulation time 27725682 ps
CPU time 0.69 seconds
Started Jul 18 05:30:28 PM PDT 24
Finished Jul 18 05:30:32 PM PDT 24
Peak memory 205192 kb
Host smart-391a46c6-17af-440f-84e7-87b68195b62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066131944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3066131944
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1635374296
Short name T499
Test name
Test status
Simulation time 477265369 ps
CPU time 2.31 seconds
Started Jul 18 05:30:26 PM PDT 24
Finished Jul 18 05:30:33 PM PDT 24
Peak memory 227652 kb
Host smart-a69ea938-c6fb-4e67-82af-fdee03210f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635374296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1635374296
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.2114867628
Short name T821
Test name
Test status
Simulation time 2459284593 ps
CPU time 92.53 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:31:55 PM PDT 24
Peak memory 223900 kb
Host smart-fb38ee9a-a78f-46bb-be46-156ea448bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114867628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.2114867628
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.1227102505
Short name T282
Test name
Test status
Simulation time 1762307548 ps
CPU time 42.02 seconds
Started Jul 18 05:30:28 PM PDT 24
Finished Jul 18 05:31:13 PM PDT 24
Peak memory 262280 kb
Host smart-8eeb4f38-8ba2-451d-a4af-74bd1fadc318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227102505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.1227102505
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1362196459
Short name T954
Test name
Test status
Simulation time 3648238395 ps
CPU time 43.36 seconds
Started Jul 18 05:30:40 PM PDT 24
Finished Jul 18 05:31:26 PM PDT 24
Peak memory 214788 kb
Host smart-7eeea227-4bdc-467c-8991-3e2841b4a7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362196459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1362196459
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3645726666
Short name T1676
Test name
Test status
Simulation time 1050425268 ps
CPU time 5.83 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 222048 kb
Host smart-16a8c31f-353a-4256-8afb-502958524e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645726666 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3645726666
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3457778357
Short name T1538
Test name
Test status
Simulation time 335634455 ps
CPU time 0.9 seconds
Started Jul 18 05:30:27 PM PDT 24
Finished Jul 18 05:30:31 PM PDT 24
Peak memory 205460 kb
Host smart-863cee15-b031-4f25-9e87-60e842f20c6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457778357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3457778357
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1285455151
Short name T942
Test name
Test status
Simulation time 336781673 ps
CPU time 1.22 seconds
Started Jul 18 05:30:36 PM PDT 24
Finished Jul 18 05:30:38 PM PDT 24
Peak memory 205980 kb
Host smart-549a9504-dfa3-40c5-ab44-f79b78867437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285455151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1285455151
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.1480630791
Short name T825
Test name
Test status
Simulation time 446714630 ps
CPU time 2.5 seconds
Started Jul 18 05:30:37 PM PDT 24
Finished Jul 18 05:30:41 PM PDT 24
Peak memory 205612 kb
Host smart-d2448a1f-8b2e-4ee4-99bc-7f55cf31d247
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480630791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.1480630791
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.2383669316
Short name T1093
Test name
Test status
Simulation time 438382882 ps
CPU time 1.32 seconds
Started Jul 18 05:30:33 PM PDT 24
Finished Jul 18 05:30:35 PM PDT 24
Peak memory 205396 kb
Host smart-2a2cfab7-1cae-4dca-bc9a-79afdbd458fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383669316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.2383669316
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.4031083366
Short name T665
Test name
Test status
Simulation time 19469206829 ps
CPU time 5.68 seconds
Started Jul 18 05:30:28 PM PDT 24
Finished Jul 18 05:30:37 PM PDT 24
Peak memory 221896 kb
Host smart-141bc94a-907f-4c0a-8a9f-7eb7431450d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031083366 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.4031083366
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2014947032
Short name T1279
Test name
Test status
Simulation time 25890422531 ps
CPU time 805.58 seconds
Started Jul 18 05:30:40 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 4732864 kb
Host smart-c94bc1a0-bc97-4aa7-8283-06f48c2bb250
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014947032 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2014947032
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.2837870690
Short name T578
Test name
Test status
Simulation time 490670488 ps
CPU time 2.84 seconds
Started Jul 18 05:30:25 PM PDT 24
Finished Jul 18 05:30:33 PM PDT 24
Peak memory 213804 kb
Host smart-513ce958-e280-4d25-930f-c260c7a72903
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837870690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.2837870690
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.383286986
Short name T1099
Test name
Test status
Simulation time 952077913 ps
CPU time 2.83 seconds
Started Jul 18 05:30:23 PM PDT 24
Finished Jul 18 05:30:32 PM PDT 24
Peak memory 205628 kb
Host smart-351b212d-68d2-4af2-a5c3-939a4e50f08a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383286986 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.383286986
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3101827977
Short name T1690
Test name
Test status
Simulation time 5058852936 ps
CPU time 4.72 seconds
Started Jul 18 05:30:39 PM PDT 24
Finished Jul 18 05:30:46 PM PDT 24
Peak memory 221972 kb
Host smart-d74c255d-39b1-425d-baa2-f19aec26dc7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101827977 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3101827977
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.4187916013
Short name T161
Test name
Test status
Simulation time 554337666 ps
CPU time 2.33 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:26 PM PDT 24
Peak memory 205396 kb
Host smart-e1624a26-4f42-437b-abaf-a052f1711f02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187916013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.4187916013
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.2035882473
Short name T902
Test name
Test status
Simulation time 2154861832 ps
CPU time 33.26 seconds
Started Jul 18 05:30:25 PM PDT 24
Finished Jul 18 05:31:03 PM PDT 24
Peak memory 218096 kb
Host smart-c307b3b2-dfa3-47d5-901c-ee39823cc8cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035882473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.2035882473
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.2197232899
Short name T1672
Test name
Test status
Simulation time 21215800428 ps
CPU time 215.69 seconds
Started Jul 18 05:30:25 PM PDT 24
Finished Jul 18 05:34:06 PM PDT 24
Peak memory 2007740 kb
Host smart-c107dd95-1fa3-43b0-bf41-86cd8a3a222f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197232899 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.2197232899
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1678744806
Short name T572
Test name
Test status
Simulation time 1214968009 ps
CPU time 56.8 seconds
Started Jul 18 05:30:35 PM PDT 24
Finished Jul 18 05:31:32 PM PDT 24
Peak memory 214076 kb
Host smart-aeeb6cfc-1fe7-4dfd-8ce5-fea2622ff12c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678744806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1678744806
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2950034046
Short name T670
Test name
Test status
Simulation time 28158599759 ps
CPU time 7.52 seconds
Started Jul 18 05:30:31 PM PDT 24
Finished Jul 18 05:30:40 PM PDT 24
Peak memory 213892 kb
Host smart-2a1c274f-afd6-433d-acbf-d3ce24fca986
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950034046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2950034046
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2163040266
Short name T79
Test name
Test status
Simulation time 1436709434 ps
CPU time 29.02 seconds
Started Jul 18 05:30:25 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 340020 kb
Host smart-01f04076-0d79-4058-bde9-e921953f0f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163040266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2163040266
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1710997288
Short name T424
Test name
Test status
Simulation time 4651846994 ps
CPU time 6 seconds
Started Jul 18 05:30:25 PM PDT 24
Finished Jul 18 05:30:36 PM PDT 24
Peak memory 213904 kb
Host smart-e35d1484-1dc2-4841-94c2-730a248456cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710997288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1710997288
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.354164785
Short name T755
Test name
Test status
Simulation time 216909091 ps
CPU time 2.95 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 205588 kb
Host smart-a51a6baa-635e-4c8a-8e03-481059e3c993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354164785 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.354164785
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3065890747
Short name T328
Test name
Test status
Simulation time 40179730 ps
CPU time 0.65 seconds
Started Jul 18 05:30:42 PM PDT 24
Finished Jul 18 05:30:45 PM PDT 24
Peak memory 204904 kb
Host smart-cbf581d8-f57b-4886-8a6f-7ea8b1eb96c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065890747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3065890747
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3478019568
Short name T24
Test name
Test status
Simulation time 617572297 ps
CPU time 2.15 seconds
Started Jul 18 05:30:23 PM PDT 24
Finished Jul 18 05:30:31 PM PDT 24
Peak memory 213240 kb
Host smart-4a4b2c08-1911-468a-95e4-bc7e180d0c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478019568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3478019568
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3534391063
Short name T504
Test name
Test status
Simulation time 1084852292 ps
CPU time 5.2 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:30 PM PDT 24
Peak memory 259776 kb
Host smart-8770e82a-1f10-4068-8206-0200a4a89e39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534391063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3534391063
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2035266994
Short name T1084
Test name
Test status
Simulation time 15411126346 ps
CPU time 121.48 seconds
Started Jul 18 05:30:19 PM PDT 24
Finished Jul 18 05:32:23 PM PDT 24
Peak memory 718252 kb
Host smart-d789847e-9409-4d28-88d1-1f80194c7d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035266994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2035266994
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3963479818
Short name T453
Test name
Test status
Simulation time 1722147617 ps
CPU time 58.94 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:31:24 PM PDT 24
Peak memory 634796 kb
Host smart-a05cd4fa-9930-4a49-9803-b146d9bfd302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963479818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3963479818
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.1379501082
Short name T1284
Test name
Test status
Simulation time 363567472 ps
CPU time 1.13 seconds
Started Jul 18 05:30:20 PM PDT 24
Finished Jul 18 05:30:26 PM PDT 24
Peak memory 205440 kb
Host smart-092e1b73-069c-4490-94de-856495ba9102
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379501082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.1379501082
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.459775084
Short name T1335
Test name
Test status
Simulation time 3466246103 ps
CPU time 238.76 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:34:26 PM PDT 24
Peak memory 1067620 kb
Host smart-80edd506-21c6-4cd7-9569-39feb94d2568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459775084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.459775084
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.4168802240
Short name T243
Test name
Test status
Simulation time 465266246 ps
CPU time 5.85 seconds
Started Jul 18 05:30:43 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 205460 kb
Host smart-d16079c9-82e2-4135-8aa6-1778bcbfe9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168802240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.4168802240
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.135297984
Short name T1368
Test name
Test status
Simulation time 152079413 ps
CPU time 0.67 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:26 PM PDT 24
Peak memory 205236 kb
Host smart-e8d17412-5c73-4be0-8e6f-a618d1871aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135297984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.135297984
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.2525733441
Short name T304
Test name
Test status
Simulation time 190045664 ps
CPU time 2.83 seconds
Started Jul 18 05:30:27 PM PDT 24
Finished Jul 18 05:30:33 PM PDT 24
Peak memory 221780 kb
Host smart-bca75142-35b7-4bc6-804c-b557282bb806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525733441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.2525733441
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.1895430431
Short name T741
Test name
Test status
Simulation time 6216007806 ps
CPU time 20.51 seconds
Started Jul 18 05:30:21 PM PDT 24
Finished Jul 18 05:30:47 PM PDT 24
Peak memory 295576 kb
Host smart-abe8ee7b-aa1f-4dc4-90dc-ff1b5ac105c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895430431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1895430431
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.1748646150
Short name T913
Test name
Test status
Simulation time 1675326180 ps
CPU time 13.8 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:30:42 PM PDT 24
Peak memory 214884 kb
Host smart-bbfeaaf3-032c-4a39-ba18-2ad506632472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748646150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1748646150
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.4094835830
Short name T422
Test name
Test status
Simulation time 3437767297 ps
CPU time 4.77 seconds
Started Jul 18 05:30:37 PM PDT 24
Finished Jul 18 05:30:43 PM PDT 24
Peak memory 217864 kb
Host smart-d46152cd-b67e-42f1-a65c-70a9c7e1edbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094835830 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.4094835830
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2546602662
Short name T1013
Test name
Test status
Simulation time 760073281 ps
CPU time 1.56 seconds
Started Jul 18 05:30:40 PM PDT 24
Finished Jul 18 05:30:44 PM PDT 24
Peak memory 205688 kb
Host smart-6643b652-2cad-4e16-a452-a569ca2f6ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546602662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2546602662
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3670219956
Short name T712
Test name
Test status
Simulation time 566343934 ps
CPU time 0.9 seconds
Started Jul 18 05:30:46 PM PDT 24
Finished Jul 18 05:30:50 PM PDT 24
Peak memory 204372 kb
Host smart-acb81577-e86c-4e16-a081-0d54f2c1b585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670219956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3670219956
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.39779035
Short name T538
Test name
Test status
Simulation time 590407002 ps
CPU time 3.07 seconds
Started Jul 18 05:30:49 PM PDT 24
Finished Jul 18 05:30:54 PM PDT 24
Peak memory 205632 kb
Host smart-8cbb045b-60de-412e-af99-a2e82e16a4de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39779035 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.39779035
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.3024611195
Short name T1319
Test name
Test status
Simulation time 598668210 ps
CPU time 1.44 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:48 PM PDT 24
Peak memory 205424 kb
Host smart-f796caad-9d20-4b0d-8d11-6a990c125051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024611195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.3024611195
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.551772439
Short name T134
Test name
Test status
Simulation time 260998768 ps
CPU time 1.89 seconds
Started Jul 18 05:30:40 PM PDT 24
Finished Jul 18 05:30:44 PM PDT 24
Peak memory 213804 kb
Host smart-33006721-0420-477f-997f-424aa39427b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551772439 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.i2c_target_hrst.551772439
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3518608297
Short name T5
Test name
Test status
Simulation time 1281937854 ps
CPU time 8.18 seconds
Started Jul 18 05:30:41 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 223232 kb
Host smart-b6b7de97-a13c-42eb-adb1-dcc2233616d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518608297 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3518608297
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.3676249180
Short name T892
Test name
Test status
Simulation time 11326306602 ps
CPU time 189.06 seconds
Started Jul 18 05:30:36 PM PDT 24
Finished Jul 18 05:33:46 PM PDT 24
Peak memory 2773168 kb
Host smart-3601aca0-a9da-4e81-9ad4-6a1421adb894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676249180 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.3676249180
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.1508392279
Short name T412
Test name
Test status
Simulation time 4834296319 ps
CPU time 3.23 seconds
Started Jul 18 05:30:36 PM PDT 24
Finished Jul 18 05:30:41 PM PDT 24
Peak memory 213908 kb
Host smart-2e05aa6e-5991-4f3d-9ea9-9020c3a354f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508392279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.1508392279
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.3903822416
Short name T1299
Test name
Test status
Simulation time 549047008 ps
CPU time 2.59 seconds
Started Jul 18 05:30:34 PM PDT 24
Finished Jul 18 05:30:37 PM PDT 24
Peak memory 205636 kb
Host smart-94462671-8b4e-4295-b2b7-3f92e223e4e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903822416 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.3903822416
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.3371767417
Short name T1665
Test name
Test status
Simulation time 2676190737 ps
CPU time 4.34 seconds
Started Jul 18 05:30:39 PM PDT 24
Finished Jul 18 05:30:45 PM PDT 24
Peak memory 222004 kb
Host smart-ed328ee6-aea0-4e9a-8116-14f91ea5e9b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371767417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.3371767417
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.1667064911
Short name T1208
Test name
Test status
Simulation time 2236647194 ps
CPU time 2.39 seconds
Started Jul 18 05:30:38 PM PDT 24
Finished Jul 18 05:30:42 PM PDT 24
Peak memory 205460 kb
Host smart-2ffa7a87-7929-4e33-a35b-6a87dc6a1823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667064911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_smbus_maxlen.1667064911
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.291153307
Short name T1471
Test name
Test status
Simulation time 4272565015 ps
CPU time 34.09 seconds
Started Jul 18 05:30:22 PM PDT 24
Finished Jul 18 05:31:02 PM PDT 24
Peak memory 213916 kb
Host smart-27c46200-11bc-4ef6-8354-88d936ff9636
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291153307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.291153307
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.120413036
Short name T937
Test name
Test status
Simulation time 36168391806 ps
CPU time 597.4 seconds
Started Jul 18 05:30:39 PM PDT 24
Finished Jul 18 05:40:38 PM PDT 24
Peak memory 3827020 kb
Host smart-e66d8c5b-e80d-4bdc-b3bd-f0cfd4726d19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120413036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_target_stress_all.120413036
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.854761173
Short name T1597
Test name
Test status
Simulation time 3966458030 ps
CPU time 15.15 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:31:03 PM PDT 24
Peak memory 223236 kb
Host smart-9c50f755-e411-49ba-a700-4afb2f87943e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854761173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.854761173
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.3491832879
Short name T1251
Test name
Test status
Simulation time 16466902533 ps
CPU time 27.83 seconds
Started Jul 18 05:30:28 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 205376 kb
Host smart-fb10b0ca-fcf2-41ce-b5df-559f6ecb6332
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491832879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.3491832879
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.455312844
Short name T458
Test name
Test status
Simulation time 3525478366 ps
CPU time 7.15 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:31:04 PM PDT 24
Peak memory 283512 kb
Host smart-9f986ae3-b72a-4e41-8118-9621861679c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455312844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.455312844
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.172989507
Short name T1534
Test name
Test status
Simulation time 1323191903 ps
CPU time 7.23 seconds
Started Jul 18 05:30:35 PM PDT 24
Finished Jul 18 05:30:43 PM PDT 24
Peak memory 213788 kb
Host smart-fb566466-dab6-4a8e-b7a6-fe446e51bb3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172989507 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.172989507
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.268803831
Short name T1110
Test name
Test status
Simulation time 156979653 ps
CPU time 2.15 seconds
Started Jul 18 05:30:36 PM PDT 24
Finished Jul 18 05:30:39 PM PDT 24
Peak memory 205580 kb
Host smart-61202663-ed3f-44d9-b0c9-57d564c7a724
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268803831 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.268803831
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2394645709
Short name T1511
Test name
Test status
Simulation time 18349852 ps
CPU time 0.64 seconds
Started Jul 18 05:30:47 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 204740 kb
Host smart-28ca01f4-a786-421c-8c94-bc3b471f3630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394645709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2394645709
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.466790485
Short name T1590
Test name
Test status
Simulation time 459653576 ps
CPU time 1.75 seconds
Started Jul 18 05:30:36 PM PDT 24
Finished Jul 18 05:30:39 PM PDT 24
Peak memory 213828 kb
Host smart-1497a22b-c52d-4738-8792-76efa9c2b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466790485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.466790485
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3626807382
Short name T847
Test name
Test status
Simulation time 1392574731 ps
CPU time 17.35 seconds
Started Jul 18 05:30:36 PM PDT 24
Finished Jul 18 05:30:55 PM PDT 24
Peak memory 250644 kb
Host smart-9d51cbf5-5598-47e8-ad21-0a757d3d0ebb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626807382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3626807382
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3309174198
Short name T1155
Test name
Test status
Simulation time 6695809027 ps
CPU time 52.27 seconds
Started Jul 18 05:30:37 PM PDT 24
Finished Jul 18 05:31:30 PM PDT 24
Peak memory 492048 kb
Host smart-24035791-d800-4122-a089-c880e5d0276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309174198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3309174198
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3312178611
Short name T346
Test name
Test status
Simulation time 1519752018 ps
CPU time 106.29 seconds
Started Jul 18 05:30:46 PM PDT 24
Finished Jul 18 05:32:36 PM PDT 24
Peak memory 581376 kb
Host smart-98ef1e1d-3a60-4c45-8688-b1a62d18251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312178611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3312178611
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1433076034
Short name T1193
Test name
Test status
Simulation time 1259722103 ps
CPU time 1.15 seconds
Started Jul 18 05:30:40 PM PDT 24
Finished Jul 18 05:30:43 PM PDT 24
Peak memory 205216 kb
Host smart-041a00c6-1f1a-4383-b8b3-1c3891de938d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433076034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1433076034
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1600154332
Short name T487
Test name
Test status
Simulation time 286716610 ps
CPU time 8.77 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:30:57 PM PDT 24
Peak memory 232056 kb
Host smart-12a76a3f-78b6-4e03-a94e-17031cdeab5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600154332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1600154332
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2755641762
Short name T588
Test name
Test status
Simulation time 3567431652 ps
CPU time 97.27 seconds
Started Jul 18 05:30:41 PM PDT 24
Finished Jul 18 05:32:20 PM PDT 24
Peak memory 1066484 kb
Host smart-0c134892-6eba-4ece-b68a-d2fc83c9b378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755641762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2755641762
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.243972571
Short name T1683
Test name
Test status
Simulation time 1634355659 ps
CPU time 17.31 seconds
Started Jul 18 05:30:46 PM PDT 24
Finished Jul 18 05:31:07 PM PDT 24
Peak memory 205440 kb
Host smart-e4c64409-7aae-474f-bd9f-00830bfe9f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243972571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.243972571
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.333835870
Short name T1728
Test name
Test status
Simulation time 20280981 ps
CPU time 0.68 seconds
Started Jul 18 05:30:33 PM PDT 24
Finished Jul 18 05:30:34 PM PDT 24
Peak memory 205216 kb
Host smart-8dcbfe1e-f134-417d-95fd-6d1f8684b763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333835870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.333835870
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.3892398991
Short name T831
Test name
Test status
Simulation time 28649712569 ps
CPU time 292.93 seconds
Started Jul 18 05:30:42 PM PDT 24
Finished Jul 18 05:35:37 PM PDT 24
Peak memory 1115040 kb
Host smart-fb1620b7-b8c5-42a4-81b0-f39f67da208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892398991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3892398991
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.1075373178
Short name T1045
Test name
Test status
Simulation time 395938272 ps
CPU time 2.16 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:49 PM PDT 24
Peak memory 227652 kb
Host smart-9d5aba3a-9d44-443c-b61e-db777281e590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075373178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.1075373178
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3274704949
Short name T1479
Test name
Test status
Simulation time 1760903463 ps
CPU time 39.9 seconds
Started Jul 18 05:30:34 PM PDT 24
Finished Jul 18 05:31:14 PM PDT 24
Peak memory 262044 kb
Host smart-1339787c-00bd-4fc5-be64-81d3e21934a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274704949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3274704949
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.866571736
Short name T565
Test name
Test status
Simulation time 1264815569 ps
CPU time 16.65 seconds
Started Jul 18 05:30:46 PM PDT 24
Finished Jul 18 05:31:06 PM PDT 24
Peak memory 221772 kb
Host smart-8d0e6a8a-d020-4963-ba63-a4bdc69af589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866571736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.866571736
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2477611073
Short name T737
Test name
Test status
Simulation time 11314247186 ps
CPU time 7.27 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:54 PM PDT 24
Peak memory 213872 kb
Host smart-c57e4882-fd2a-4af2-889e-c106843619e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477611073 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2477611073
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2833984661
Short name T331
Test name
Test status
Simulation time 179078618 ps
CPU time 1.13 seconds
Started Jul 18 05:30:46 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 213588 kb
Host smart-e412241c-def1-40a7-a10b-cff455789dbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833984661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2833984661
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2334519158
Short name T138
Test name
Test status
Simulation time 448734940 ps
CPU time 1.41 seconds
Started Jul 18 05:30:43 PM PDT 24
Finished Jul 18 05:30:48 PM PDT 24
Peak memory 205588 kb
Host smart-dc67651c-ccc0-409b-95ac-0dcba96a3e03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334519158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2334519158
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.406099696
Short name T834
Test name
Test status
Simulation time 862199264 ps
CPU time 1.88 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:30:50 PM PDT 24
Peak memory 205396 kb
Host smart-b19e9b53-63cb-4cb4-b3b4-c1b4b2da0fcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406099696 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.406099696
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.680199821
Short name T715
Test name
Test status
Simulation time 698151021 ps
CPU time 1.51 seconds
Started Jul 18 05:30:47 PM PDT 24
Finished Jul 18 05:30:52 PM PDT 24
Peak memory 205400 kb
Host smart-88051413-83da-4705-a202-f46f2ceb4112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680199821 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.680199821
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3982459938
Short name T625
Test name
Test status
Simulation time 964877299 ps
CPU time 3.63 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:50 PM PDT 24
Peak memory 213792 kb
Host smart-76d0d764-06ba-48de-8752-9efc82bd7023
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982459938 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3982459938
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.1363242562
Short name T990
Test name
Test status
Simulation time 11007782200 ps
CPU time 9.58 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:56 PM PDT 24
Peak memory 401460 kb
Host smart-b75a48b8-e521-4d79-9bbd-fede3937c919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363242562 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.1363242562
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.1331109461
Short name T730
Test name
Test status
Simulation time 795763686 ps
CPU time 2.44 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:49 PM PDT 24
Peak memory 213868 kb
Host smart-7a40836a-c0b4-4fca-8e92-efb547139709
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331109461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_nack_acqfull.1331109461
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.3927323663
Short name T1233
Test name
Test status
Simulation time 1250350620 ps
CPU time 2.68 seconds
Started Jul 18 05:30:43 PM PDT 24
Finished Jul 18 05:30:48 PM PDT 24
Peak memory 205780 kb
Host smart-b8861713-7636-4a35-9af7-b4537f98d996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927323663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.3927323663
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_txstretch.1539884767
Short name T1452
Test name
Test status
Simulation time 301252320 ps
CPU time 1.41 seconds
Started Jul 18 05:30:40 PM PDT 24
Finished Jul 18 05:30:43 PM PDT 24
Peak memory 222300 kb
Host smart-7be3908b-e349-4eca-ab6c-5a0afe1ce4a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539884767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_nack_txstretch.1539884767
Directory /workspace/35.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/35.i2c_target_perf.2115678755
Short name T529
Test name
Test status
Simulation time 829966820 ps
CPU time 5.64 seconds
Started Jul 18 05:30:46 PM PDT 24
Finished Jul 18 05:30:55 PM PDT 24
Peak memory 221016 kb
Host smart-81909b27-4eac-404d-89ff-11c022a47545
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115678755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.2115678755
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.2091221090
Short name T1358
Test name
Test status
Simulation time 651701235 ps
CPU time 2.16 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 205576 kb
Host smart-0a852988-337c-4090-a450-a7f67c3e4265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091221090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_smbus_maxlen.2091221090
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3138563987
Short name T463
Test name
Test status
Simulation time 1530181611 ps
CPU time 23.98 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:31:11 PM PDT 24
Peak memory 221964 kb
Host smart-a94f2707-3b12-4fa0-a1a5-9b8f218b271e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138563987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3138563987
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3308880284
Short name T425
Test name
Test status
Simulation time 1025707459 ps
CPU time 9.66 seconds
Started Jul 18 05:30:42 PM PDT 24
Finished Jul 18 05:30:54 PM PDT 24
Peak memory 205908 kb
Host smart-c1d4ae46-79ee-4c29-9247-2e140aacdf0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308880284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3308880284
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2459627715
Short name T979
Test name
Test status
Simulation time 17629249236 ps
CPU time 5.74 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:52 PM PDT 24
Peak memory 205684 kb
Host smart-07907e81-32d4-4c60-a1c3-418995358652
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459627715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2459627715
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.4056580494
Short name T948
Test name
Test status
Simulation time 4103803668 ps
CPU time 167.51 seconds
Started Jul 18 05:30:43 PM PDT 24
Finished Jul 18 05:33:33 PM PDT 24
Peak memory 915712 kb
Host smart-ecbb95c9-4123-490b-b52e-53257ae0fa55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056580494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.4056580494
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3245784157
Short name T363
Test name
Test status
Simulation time 3248342398 ps
CPU time 7.35 seconds
Started Jul 18 05:30:42 PM PDT 24
Finished Jul 18 05:30:52 PM PDT 24
Peak memory 222044 kb
Host smart-4da21a7e-03b2-4f79-8941-72f794ad4ffa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245784157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3245784157
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2382441334
Short name T938
Test name
Test status
Simulation time 372439201 ps
CPU time 5.11 seconds
Started Jul 18 05:30:47 PM PDT 24
Finished Jul 18 05:30:55 PM PDT 24
Peak memory 205592 kb
Host smart-784906f0-fd0e-4f77-9864-ee4dbb460585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382441334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2382441334
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3188075402
Short name T1204
Test name
Test status
Simulation time 16990619 ps
CPU time 0.63 seconds
Started Jul 18 05:30:55 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 204884 kb
Host smart-eea0f474-14ea-4d91-9e04-c5eb1b9a6657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188075402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3188075402
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2598761706
Short name T719
Test name
Test status
Simulation time 1277226664 ps
CPU time 4.44 seconds
Started Jul 18 05:30:48 PM PDT 24
Finished Jul 18 05:30:55 PM PDT 24
Peak memory 250724 kb
Host smart-53db2627-1f47-4dd3-a5fb-9d12ee460218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598761706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2598761706
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.950070933
Short name T280
Test name
Test status
Simulation time 583737754 ps
CPU time 14.83 seconds
Started Jul 18 05:30:48 PM PDT 24
Finished Jul 18 05:31:05 PM PDT 24
Peak memory 263648 kb
Host smart-3fbc27f8-9bb2-4648-a20c-5a7cc9c2b7d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950070933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.950070933
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2432528252
Short name T895
Test name
Test status
Simulation time 33412062995 ps
CPU time 151.4 seconds
Started Jul 18 05:30:49 PM PDT 24
Finished Jul 18 05:33:23 PM PDT 24
Peak memory 425648 kb
Host smart-ebf42433-ca4a-4aa1-a21e-3d1f4137517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432528252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2432528252
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.4178331324
Short name T1203
Test name
Test status
Simulation time 6758577776 ps
CPU time 103.61 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:32:32 PM PDT 24
Peak memory 575324 kb
Host smart-9f0da991-83c8-4e87-bc78-c1e5d10bd43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178331324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.4178331324
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.794108482
Short name T555
Test name
Test status
Simulation time 146961496 ps
CPU time 0.86 seconds
Started Jul 18 05:30:37 PM PDT 24
Finished Jul 18 05:30:40 PM PDT 24
Peak memory 205256 kb
Host smart-7bd13a44-6872-4f74-adc4-f81e6140e193
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794108482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fm
t.794108482
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2943285866
Short name T1604
Test name
Test status
Simulation time 766764773 ps
CPU time 4.35 seconds
Started Jul 18 05:30:48 PM PDT 24
Finished Jul 18 05:30:55 PM PDT 24
Peak memory 205472 kb
Host smart-094136fb-16f3-42bd-b4a5-052bc7393592
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943285866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2943285866
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2126185087
Short name T701
Test name
Test status
Simulation time 3540145755 ps
CPU time 228.79 seconds
Started Jul 18 05:30:41 PM PDT 24
Finished Jul 18 05:34:32 PM PDT 24
Peak memory 1049188 kb
Host smart-67181a04-e83f-4f64-9c01-94bbc555b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126185087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2126185087
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.3768768003
Short name T1618
Test name
Test status
Simulation time 572235698 ps
CPU time 24.5 seconds
Started Jul 18 05:30:39 PM PDT 24
Finished Jul 18 05:31:06 PM PDT 24
Peak memory 205480 kb
Host smart-360d3b27-19d3-4112-8e71-ddc3c45cb1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768768003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3768768003
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.509564963
Short name T1466
Test name
Test status
Simulation time 29698091 ps
CPU time 0.73 seconds
Started Jul 18 05:30:38 PM PDT 24
Finished Jul 18 05:30:41 PM PDT 24
Peak memory 205216 kb
Host smart-07965555-8d29-49a1-b059-e07df579faab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509564963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.509564963
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3283301260
Short name T416
Test name
Test status
Simulation time 6507971870 ps
CPU time 44.66 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:31:33 PM PDT 24
Peak memory 255632 kb
Host smart-afbe41b7-d863-4ef1-b9c9-d7d730286eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283301260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3283301260
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.547106359
Short name T1404
Test name
Test status
Simulation time 787184608 ps
CPU time 1.5 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:30:49 PM PDT 24
Peak memory 215684 kb
Host smart-28dc6814-439b-4bfc-9a28-97dea58807e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547106359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.547106359
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.3893804834
Short name T795
Test name
Test status
Simulation time 3036449277 ps
CPU time 75.77 seconds
Started Jul 18 05:30:39 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 380412 kb
Host smart-0decc487-07a0-4f23-a212-c3f259368f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893804834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.3893804834
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1865734494
Short name T1474
Test name
Test status
Simulation time 13084142517 ps
CPU time 34.71 seconds
Started Jul 18 05:30:45 PM PDT 24
Finished Jul 18 05:31:23 PM PDT 24
Peak memory 213816 kb
Host smart-f11b2dfd-7b6d-466d-8bdf-7238ec929258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865734494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1865734494
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1163351471
Short name T1065
Test name
Test status
Simulation time 4170348282 ps
CPU time 5.18 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:31:00 PM PDT 24
Peak memory 214084 kb
Host smart-7be16859-bf06-4f25-be4e-ba5a232fafde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163351471 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1163351471
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.183926917
Short name T1068
Test name
Test status
Simulation time 224663563 ps
CPU time 1.05 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:30:56 PM PDT 24
Peak memory 205292 kb
Host smart-f783010e-1825-41f6-8f18-5257a4273767
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183926917 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.183926917
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1057182673
Short name T1527
Test name
Test status
Simulation time 213196435 ps
CPU time 1.17 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:30:56 PM PDT 24
Peak memory 205280 kb
Host smart-27089ffc-be9a-4de9-ba74-c5f0533468ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057182673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1057182673
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.723198944
Short name T796
Test name
Test status
Simulation time 272202741 ps
CPU time 1.95 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:49 PM PDT 24
Peak memory 205412 kb
Host smart-4c6c28eb-aa07-4077-8f0f-a2ed043a8910
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723198944 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.723198944
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.555680690
Short name T1196
Test name
Test status
Simulation time 214941865 ps
CPU time 1.08 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:30:48 PM PDT 24
Peak memory 205396 kb
Host smart-e0425f41-bf39-4ff2-815a-3a1521225e73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555680690 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.555680690
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3608624552
Short name T1628
Test name
Test status
Simulation time 2045586348 ps
CPU time 2.73 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:30:57 PM PDT 24
Peak memory 213876 kb
Host smart-d234d0b1-86a1-4469-8f69-51a4e69211b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608624552 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3608624552
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.4048784472
Short name T1054
Test name
Test status
Simulation time 20778282344 ps
CPU time 146.38 seconds
Started Jul 18 05:30:38 PM PDT 24
Finished Jul 18 05:33:06 PM PDT 24
Peak memory 1728616 kb
Host smart-47d64164-b878-4a75-bff0-5a0aa46ef850
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048784472 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.4048784472
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.342772622
Short name T1430
Test name
Test status
Simulation time 1286119244 ps
CPU time 2.99 seconds
Started Jul 18 05:31:00 PM PDT 24
Finished Jul 18 05:31:05 PM PDT 24
Peak memory 213800 kb
Host smart-bdc862a9-bd8c-4a16-aece-20bdac3b7bb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342772622 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_nack_acqfull.342772622
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.3133189798
Short name T1122
Test name
Test status
Simulation time 1022253325 ps
CPU time 2.7 seconds
Started Jul 18 05:30:58 PM PDT 24
Finished Jul 18 05:31:04 PM PDT 24
Peak memory 205600 kb
Host smart-a36ed606-c8e2-4c0d-9b0a-2ddd9adcb13f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133189798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.3133189798
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_txstretch.2613100963
Short name T1477
Test name
Test status
Simulation time 520188735 ps
CPU time 1.4 seconds
Started Jul 18 05:30:51 PM PDT 24
Finished Jul 18 05:30:55 PM PDT 24
Peak memory 222216 kb
Host smart-db9f2d45-81c7-48a1-9d80-d49ed410fd41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613100963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_nack_txstretch.2613100963
Directory /workspace/36.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/36.i2c_target_perf.2869544908
Short name T829
Test name
Test status
Simulation time 1081301231 ps
CPU time 3.99 seconds
Started Jul 18 05:30:39 PM PDT 24
Finished Jul 18 05:30:45 PM PDT 24
Peak memory 213880 kb
Host smart-454eb437-654c-4a2a-84de-16b3075e5cb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869544908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.2869544908
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.2090667421
Short name T586
Test name
Test status
Simulation time 735430013 ps
CPU time 2.05 seconds
Started Jul 18 05:30:59 PM PDT 24
Finished Jul 18 05:31:04 PM PDT 24
Peak memory 205380 kb
Host smart-402b9eb5-ae38-42bf-b5b5-6382fa828ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090667421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.2090667421
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.4060021924
Short name T1745
Test name
Test status
Simulation time 1217238817 ps
CPU time 17.79 seconds
Started Jul 18 05:30:49 PM PDT 24
Finished Jul 18 05:31:09 PM PDT 24
Peak memory 213504 kb
Host smart-fec7ee3e-c1d6-4fff-9797-60d15d1475af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060021924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.4060021924
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.3097278811
Short name T1468
Test name
Test status
Simulation time 26893024157 ps
CPU time 1189.83 seconds
Started Jul 18 05:30:38 PM PDT 24
Finished Jul 18 05:50:30 PM PDT 24
Peak memory 5640524 kb
Host smart-fccb2363-964c-4023-aec7-09f9bd16643c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097278811 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.3097278811
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.354064852
Short name T452
Test name
Test status
Simulation time 3921681615 ps
CPU time 19.05 seconds
Started Jul 18 05:30:44 PM PDT 24
Finished Jul 18 05:31:06 PM PDT 24
Peak memory 221992 kb
Host smart-69ac13ba-74c4-4e9a-8f2b-0f2b19c830c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354064852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.354064852
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.759872618
Short name T389
Test name
Test status
Simulation time 15157177579 ps
CPU time 28.99 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:31:24 PM PDT 24
Peak memory 205688 kb
Host smart-4ae184ec-78cc-4653-925e-ae120a204727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759872618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.759872618
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.915518443
Short name T722
Test name
Test status
Simulation time 510556563 ps
CPU time 14.65 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:31:09 PM PDT 24
Peak memory 259760 kb
Host smart-d1526d62-72f8-411a-9800-236afa430bf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915518443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.915518443
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.3662722549
Short name T903
Test name
Test status
Simulation time 5311889071 ps
CPU time 7.09 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:31:02 PM PDT 24
Peak memory 222064 kb
Host smart-e7dcd49a-a671-4a18-9b5e-93d04f308655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662722549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.3662722549
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.742675899
Short name T53
Test name
Test status
Simulation time 164898079 ps
CPU time 3.24 seconds
Started Jul 18 05:30:55 PM PDT 24
Finished Jul 18 05:31:01 PM PDT 24
Peak memory 205636 kb
Host smart-ba842b0e-b274-4a62-86e8-b70401ae5e7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742675899 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.742675899
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.1309569993
Short name T165
Test name
Test status
Simulation time 31526114 ps
CPU time 0.63 seconds
Started Jul 18 05:30:54 PM PDT 24
Finished Jul 18 05:30:58 PM PDT 24
Peak memory 204792 kb
Host smart-4fe7d53c-5096-48b4-b0e5-be35db2c8890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309569993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1309569993
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1373895983
Short name T528
Test name
Test status
Simulation time 138480561 ps
CPU time 1.62 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:58 PM PDT 24
Peak memory 213848 kb
Host smart-a6746714-542b-44fb-89e9-582b54f03722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373895983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1373895983
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.2413420618
Short name T1185
Test name
Test status
Simulation time 570121542 ps
CPU time 5.5 seconds
Started Jul 18 05:30:59 PM PDT 24
Finished Jul 18 05:31:08 PM PDT 24
Peak memory 253508 kb
Host smart-0594fc6c-8a85-4809-bf87-25797c2d3c85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413420618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.2413420618
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.575527006
Short name T432
Test name
Test status
Simulation time 7492210618 ps
CPU time 51.89 seconds
Started Jul 18 05:30:51 PM PDT 24
Finished Jul 18 05:31:46 PM PDT 24
Peak memory 363208 kb
Host smart-dc7292c5-9538-4f89-9e71-79e424e38a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575527006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.575527006
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1173608076
Short name T651
Test name
Test status
Simulation time 8799925618 ps
CPU time 159.61 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:33:35 PM PDT 24
Peak memory 724412 kb
Host smart-4151ea59-9426-4fa5-bb09-534e45ed5ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173608076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1173608076
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.4118365760
Short name T774
Test name
Test status
Simulation time 135799422 ps
CPU time 1.33 seconds
Started Jul 18 05:30:59 PM PDT 24
Finished Jul 18 05:31:03 PM PDT 24
Peak memory 205404 kb
Host smart-0c1f7448-b8e5-4c7e-8f7c-0314fad928f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118365760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.4118365760
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.122613518
Short name T1152
Test name
Test status
Simulation time 417853514 ps
CPU time 8.51 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:31:03 PM PDT 24
Peak memory 205468 kb
Host smart-1083085f-bc14-449e-8a2e-48a1b1eaf57f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122613518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
122613518
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3086415768
Short name T614
Test name
Test status
Simulation time 12503236729 ps
CPU time 208.05 seconds
Started Jul 18 05:30:59 PM PDT 24
Finished Jul 18 05:34:30 PM PDT 24
Peak memory 949188 kb
Host smart-60c1c404-bda6-4bdc-b1ac-aafd9416697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086415768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3086415768
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.1469330826
Short name T1142
Test name
Test status
Simulation time 5142320096 ps
CPU time 7.83 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:31:03 PM PDT 24
Peak memory 205796 kb
Host smart-5c66af75-0fa4-4edd-9a2a-d87daf64d598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469330826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1469330826
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_override.140186426
Short name T474
Test name
Test status
Simulation time 40682697 ps
CPU time 0.68 seconds
Started Jul 18 05:30:56 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 205216 kb
Host smart-f0cf33ba-7430-4475-bbcc-71f2da72b3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140186426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.140186426
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.751298055
Short name T1666
Test name
Test status
Simulation time 47430851880 ps
CPU time 941.98 seconds
Started Jul 18 05:30:56 PM PDT 24
Finished Jul 18 05:46:41 PM PDT 24
Peak memory 221764 kb
Host smart-f209181a-084d-4f77-8a4a-56983caec1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751298055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.751298055
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.4149997128
Short name T1617
Test name
Test status
Simulation time 229691548 ps
CPU time 2.91 seconds
Started Jul 18 05:30:59 PM PDT 24
Finished Jul 18 05:31:05 PM PDT 24
Peak memory 205444 kb
Host smart-76202044-7e29-404e-b469-17e7748ea4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149997128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.4149997128
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1096165083
Short name T721
Test name
Test status
Simulation time 1563393893 ps
CPU time 21.89 seconds
Started Jul 18 05:30:50 PM PDT 24
Finished Jul 18 05:31:15 PM PDT 24
Peak memory 287512 kb
Host smart-97424d62-96c1-47bc-8664-80d778fdd1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096165083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1096165083
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.747499004
Short name T596
Test name
Test status
Simulation time 1082957782 ps
CPU time 12.79 seconds
Started Jul 18 05:30:51 PM PDT 24
Finished Jul 18 05:31:06 PM PDT 24
Peak memory 213764 kb
Host smart-6e449ec6-7a63-47c7-a34d-77e06befa6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747499004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.747499004
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1066892912
Short name T477
Test name
Test status
Simulation time 1525016412 ps
CPU time 4.43 seconds
Started Jul 18 05:30:57 PM PDT 24
Finished Jul 18 05:31:04 PM PDT 24
Peak memory 221944 kb
Host smart-3dc04fab-b8ff-427b-a91a-05b702988471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066892912 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1066892912
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3959004042
Short name T889
Test name
Test status
Simulation time 202015623 ps
CPU time 1.2 seconds
Started Jul 18 05:30:57 PM PDT 24
Finished Jul 18 05:31:01 PM PDT 24
Peak memory 205360 kb
Host smart-92a8ea05-c9c7-4c87-b5fa-3c0994d602e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959004042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3959004042
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.150315843
Short name T995
Test name
Test status
Simulation time 133052724 ps
CPU time 1.01 seconds
Started Jul 18 05:30:58 PM PDT 24
Finished Jul 18 05:31:02 PM PDT 24
Peak memory 205408 kb
Host smart-404d514e-5144-4dca-9e4a-896a816cc199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150315843 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_fifo_reset_tx.150315843
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.2117534905
Short name T1008
Test name
Test status
Simulation time 392984990 ps
CPU time 2.48 seconds
Started Jul 18 05:30:55 PM PDT 24
Finished Jul 18 05:31:01 PM PDT 24
Peak memory 205832 kb
Host smart-bcbd4f52-38ad-4cb8-a258-2cd9f76ea17c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117534905 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.2117534905
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.2198600744
Short name T1217
Test name
Test status
Simulation time 119370039 ps
CPU time 1.22 seconds
Started Jul 18 05:30:54 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 205416 kb
Host smart-d3e5ce78-ea80-4c9e-b68d-257102942c33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198600744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.2198600744
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1674768822
Short name T1688
Test name
Test status
Simulation time 147539930 ps
CPU time 1.39 seconds
Started Jul 18 05:30:50 PM PDT 24
Finished Jul 18 05:30:54 PM PDT 24
Peak memory 215232 kb
Host smart-dd503f2a-c351-4288-b11c-034b0ac34dfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674768822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1674768822
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3259272463
Short name T1498
Test name
Test status
Simulation time 1174118609 ps
CPU time 5.59 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:31:00 PM PDT 24
Peak memory 216404 kb
Host smart-8a6e13e7-3db4-440c-b7c8-aa6043a72de3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259272463 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3259272463
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.797406429
Short name T1473
Test name
Test status
Simulation time 13568442321 ps
CPU time 28.12 seconds
Started Jul 18 05:30:51 PM PDT 24
Finished Jul 18 05:31:21 PM PDT 24
Peak memory 629048 kb
Host smart-d3aa4846-721f-4c26-833c-f7359605966d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797406429 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.797406429
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.1850665245
Short name T1362
Test name
Test status
Simulation time 1664624123 ps
CPU time 2.86 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 214020 kb
Host smart-61a5ac27-5a41-41b0-94c7-6641811db71a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850665245 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.1850665245
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.3892669805
Short name T49
Test name
Test status
Simulation time 1061625256 ps
CPU time 2.64 seconds
Started Jul 18 05:30:55 PM PDT 24
Finished Jul 18 05:31:01 PM PDT 24
Peak memory 205652 kb
Host smart-55b39f21-aa54-48fa-aae4-d2ed80dd76e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892669805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.3892669805
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.1998313860
Short name T660
Test name
Test status
Simulation time 421597305 ps
CPU time 3.14 seconds
Started Jul 18 05:31:02 PM PDT 24
Finished Jul 18 05:31:07 PM PDT 24
Peak memory 213832 kb
Host smart-ce70ceb0-4122-4799-8692-724716433094
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998313860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.1998313860
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.79408387
Short name T630
Test name
Test status
Simulation time 792987699 ps
CPU time 2.03 seconds
Started Jul 18 05:30:57 PM PDT 24
Finished Jul 18 05:31:02 PM PDT 24
Peak memory 205440 kb
Host smart-d3586d91-7eae-415b-8587-9e7cdf43749a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79408387 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_target_smbus_maxlen.79408387
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2442200223
Short name T1039
Test name
Test status
Simulation time 4193583734 ps
CPU time 33.12 seconds
Started Jul 18 05:30:57 PM PDT 24
Finished Jul 18 05:31:34 PM PDT 24
Peak memory 213856 kb
Host smart-5ff48b6d-8a59-49f4-9b80-a7b82d3ed891
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442200223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2442200223
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.3308365485
Short name T1162
Test name
Test status
Simulation time 23810600653 ps
CPU time 38.01 seconds
Started Jul 18 05:30:55 PM PDT 24
Finished Jul 18 05:31:36 PM PDT 24
Peak memory 507060 kb
Host smart-fd6bc84b-53c1-4e0d-87f3-cbbb1431c86b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308365485 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.3308365485
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1478849528
Short name T1183
Test name
Test status
Simulation time 3185818209 ps
CPU time 37.89 seconds
Started Jul 18 05:30:52 PM PDT 24
Finished Jul 18 05:31:33 PM PDT 24
Peak memory 213920 kb
Host smart-16ddac32-88c3-4217-b79d-546dff03437e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478849528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1478849528
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.2949734454
Short name T1062
Test name
Test status
Simulation time 50988650541 ps
CPU time 1619.67 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:57:56 PM PDT 24
Peak memory 7883960 kb
Host smart-7348e30f-8f32-42dd-b867-7baf6c1e7d28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949734454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.2949734454
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3593135255
Short name T676
Test name
Test status
Simulation time 3040177489 ps
CPU time 18.7 seconds
Started Jul 18 05:30:51 PM PDT 24
Finished Jul 18 05:31:12 PM PDT 24
Peak memory 526764 kb
Host smart-f39a9e4e-b7bc-44e7-a644-106a1af528f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593135255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3593135255
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.4172976764
Short name T1701
Test name
Test status
Simulation time 2765106722 ps
CPU time 7.82 seconds
Started Jul 18 05:30:54 PM PDT 24
Finished Jul 18 05:31:05 PM PDT 24
Peak memory 222092 kb
Host smart-f4f5ad27-a829-4bcd-b64b-d154b9160dbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172976764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.4172976764
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.1769553810
Short name T403
Test name
Test status
Simulation time 178686275 ps
CPU time 3.25 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:31:00 PM PDT 24
Peak memory 205660 kb
Host smart-9ccf91cf-9103-4520-a6a3-b8680ee8d3bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769553810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.1769553810
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3514310926
Short name T1755
Test name
Test status
Simulation time 18210284 ps
CPU time 0.64 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:28 PM PDT 24
Peak memory 204704 kb
Host smart-5204e062-8bba-4c9a-8c6d-d2c3538c4d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514310926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3514310926
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2358847639
Short name T1517
Test name
Test status
Simulation time 1382760922 ps
CPU time 6.69 seconds
Started Jul 18 05:31:00 PM PDT 24
Finished Jul 18 05:31:09 PM PDT 24
Peak memory 277664 kb
Host smart-18b7b3cb-2fa5-4e1d-915a-9bd3a68c33e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358847639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2358847639
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2570204234
Short name T1637
Test name
Test status
Simulation time 12144982461 ps
CPU time 211.44 seconds
Started Jul 18 05:30:55 PM PDT 24
Finished Jul 18 05:34:29 PM PDT 24
Peak memory 612908 kb
Host smart-49bf3a21-d908-4bf2-8e98-0ba3a567e689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570204234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2570204234
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1353392652
Short name T696
Test name
Test status
Simulation time 1676795319 ps
CPU time 110.39 seconds
Started Jul 18 05:30:56 PM PDT 24
Finished Jul 18 05:32:49 PM PDT 24
Peak memory 542640 kb
Host smart-87a0ea72-42fd-4432-9ef2-d03d5427e9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353392652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1353392652
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3219318427
Short name T911
Test name
Test status
Simulation time 141008828 ps
CPU time 1.11 seconds
Started Jul 18 05:31:06 PM PDT 24
Finished Jul 18 05:31:08 PM PDT 24
Peak memory 205252 kb
Host smart-06dd1055-4d2b-416a-94a2-d19dfb2c666a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219318427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3219318427
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1614504577
Short name T1211
Test name
Test status
Simulation time 271877225 ps
CPU time 3.81 seconds
Started Jul 18 05:30:57 PM PDT 24
Finished Jul 18 05:31:04 PM PDT 24
Peak memory 226532 kb
Host smart-1b37a0c0-c56f-4709-8a1c-27159f673caa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614504577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1614504577
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1137300554
Short name T1577
Test name
Test status
Simulation time 3592913048 ps
CPU time 82.27 seconds
Started Jul 18 05:30:51 PM PDT 24
Finished Jul 18 05:32:16 PM PDT 24
Peak memory 1064088 kb
Host smart-133821ee-bf40-4af3-9c47-c4dea995fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137300554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1137300554
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.153583702
Short name T1568
Test name
Test status
Simulation time 571242307 ps
CPU time 7.91 seconds
Started Jul 18 05:31:00 PM PDT 24
Finished Jul 18 05:31:10 PM PDT 24
Peak memory 205504 kb
Host smart-06ce4dbd-ed96-417a-8e45-ea34048a6397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153583702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.153583702
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1338045758
Short name T1723
Test name
Test status
Simulation time 302053153 ps
CPU time 1.45 seconds
Started Jul 18 05:31:01 PM PDT 24
Finished Jul 18 05:31:05 PM PDT 24
Peak memory 205516 kb
Host smart-d9c63003-2a9e-436d-87b5-7bc391652068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338045758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1338045758
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3663125786
Short name T681
Test name
Test status
Simulation time 27458093 ps
CPU time 0.67 seconds
Started Jul 18 05:31:00 PM PDT 24
Finished Jul 18 05:31:03 PM PDT 24
Peak memory 205232 kb
Host smart-1548d739-e1f2-4c9e-a8b0-f2d7cdaf92d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663125786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3663125786
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.500917480
Short name T1420
Test name
Test status
Simulation time 12480689624 ps
CPU time 98.26 seconds
Started Jul 18 05:30:59 PM PDT 24
Finished Jul 18 05:32:40 PM PDT 24
Peak memory 878548 kb
Host smart-59f726bb-6fba-487a-841e-4492f031a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500917480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.500917480
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.755498339
Short name T541
Test name
Test status
Simulation time 279402640 ps
CPU time 1.67 seconds
Started Jul 18 05:31:00 PM PDT 24
Finished Jul 18 05:31:04 PM PDT 24
Peak memory 205420 kb
Host smart-a2788358-c1f0-482c-b9f0-ce4359dacf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755498339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.755498339
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.2450278907
Short name T612
Test name
Test status
Simulation time 1245438154 ps
CPU time 62.31 seconds
Started Jul 18 05:30:55 PM PDT 24
Finished Jul 18 05:32:00 PM PDT 24
Peak memory 405596 kb
Host smart-0fe5c817-93ed-43b8-a963-db74614fb24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450278907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2450278907
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.4046558120
Short name T633
Test name
Test status
Simulation time 627472233 ps
CPU time 11.86 seconds
Started Jul 18 05:31:36 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 216332 kb
Host smart-60a54c55-ef04-4280-a97b-7c781bdad557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046558120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.4046558120
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.946846575
Short name T351
Test name
Test status
Simulation time 1729513875 ps
CPU time 4.6 seconds
Started Jul 18 05:30:58 PM PDT 24
Finished Jul 18 05:31:06 PM PDT 24
Peak memory 217848 kb
Host smart-6718edb3-bbb8-455f-9576-9e6aede54876
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946846575 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.946846575
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1105267493
Short name T1533
Test name
Test status
Simulation time 1255036766 ps
CPU time 1.49 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:58 PM PDT 24
Peak memory 205616 kb
Host smart-80ae25dd-d115-4662-80dc-ff174642e557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105267493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1105267493
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3969113695
Short name T1131
Test name
Test status
Simulation time 601624161 ps
CPU time 1.38 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:58 PM PDT 24
Peak memory 205440 kb
Host smart-3a70479f-e2b6-4f8b-ba31-4cdf664f1497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969113695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3969113695
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.1727257460
Short name T865
Test name
Test status
Simulation time 2270164111 ps
CPU time 2.93 seconds
Started Jul 18 05:30:57 PM PDT 24
Finished Jul 18 05:31:03 PM PDT 24
Peak memory 205576 kb
Host smart-f24187ea-bfa3-4972-be42-38459958174a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727257460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.1727257460
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.2901312702
Short name T1373
Test name
Test status
Simulation time 170613482 ps
CPU time 1.63 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 205456 kb
Host smart-cc1d1e58-d465-4649-a166-39eebb0ada94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901312702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.2901312702
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.961328965
Short name T1470
Test name
Test status
Simulation time 1340725386 ps
CPU time 7.55 seconds
Started Jul 18 05:30:58 PM PDT 24
Finished Jul 18 05:31:09 PM PDT 24
Peak memory 217700 kb
Host smart-ad6c7b3f-bced-41c2-9c5a-21d43a04c425
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961328965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.961328965
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3706751800
Short name T799
Test name
Test status
Simulation time 17598920406 ps
CPU time 415.03 seconds
Started Jul 18 05:30:58 PM PDT 24
Finished Jul 18 05:37:57 PM PDT 24
Peak memory 4299168 kb
Host smart-93ca6933-493f-4253-8ca6-1aadc7e57a1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706751800 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3706751800
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.3507936647
Short name T59
Test name
Test status
Simulation time 987969706 ps
CPU time 2.72 seconds
Started Jul 18 05:31:20 PM PDT 24
Finished Jul 18 05:31:23 PM PDT 24
Peak memory 213868 kb
Host smart-d816ff4d-6c2f-4516-a7a1-af1abfa0d30e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507936647 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_acqfull.3507936647
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.3794594528
Short name T1394
Test name
Test status
Simulation time 956985404 ps
CPU time 2.56 seconds
Started Jul 18 05:31:21 PM PDT 24
Finished Jul 18 05:31:25 PM PDT 24
Peak memory 205624 kb
Host smart-ce0d6696-f528-45ad-bba3-0ebcff5583eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794594528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.3794594528
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_txstretch.320197631
Short name T620
Test name
Test status
Simulation time 144777132 ps
CPU time 1.44 seconds
Started Jul 18 05:31:29 PM PDT 24
Finished Jul 18 05:31:32 PM PDT 24
Peak memory 222248 kb
Host smart-c132cb4d-6c51-42cd-ad77-63c7f16821be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320197631 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_nack_txstretch.320197631
Directory /workspace/38.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/38.i2c_target_perf.2054831808
Short name T663
Test name
Test status
Simulation time 695171147 ps
CPU time 5.01 seconds
Started Jul 18 05:30:58 PM PDT 24
Finished Jul 18 05:31:07 PM PDT 24
Peak memory 214384 kb
Host smart-56fb2c68-f4b2-4a12-b40b-417152b69bea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054831808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.2054831808
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.2283370329
Short name T568
Test name
Test status
Simulation time 468785657 ps
CPU time 2.29 seconds
Started Jul 18 05:31:21 PM PDT 24
Finished Jul 18 05:31:24 PM PDT 24
Peak memory 205420 kb
Host smart-caea6092-a2d2-408d-b82c-ae42b9bf71e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283370329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_smbus_maxlen.2283370329
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1203557737
Short name T680
Test name
Test status
Simulation time 3336400691 ps
CPU time 12.12 seconds
Started Jul 18 05:30:58 PM PDT 24
Finished Jul 18 05:31:13 PM PDT 24
Peak memory 213904 kb
Host smart-1e687d1f-d017-483a-a079-13ab6e8ad5ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203557737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1203557737
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.3997460674
Short name T797
Test name
Test status
Simulation time 59947108551 ps
CPU time 313.73 seconds
Started Jul 18 05:30:59 PM PDT 24
Finished Jul 18 05:36:16 PM PDT 24
Peak memory 1250312 kb
Host smart-9962390e-1320-45dc-93fc-974d3a6acda4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997460674 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_stress_all.3997460674
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3479572249
Short name T1192
Test name
Test status
Simulation time 4050867679 ps
CPU time 64.89 seconds
Started Jul 18 05:30:58 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 217804 kb
Host smart-61510a65-924d-489b-8cab-dccdfcff0c67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479572249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3479572249
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.3867481957
Short name T771
Test name
Test status
Simulation time 58937254662 ps
CPU time 2419.23 seconds
Started Jul 18 05:31:02 PM PDT 24
Finished Jul 18 06:11:23 PM PDT 24
Peak memory 9634704 kb
Host smart-53ad788c-18fe-4c93-b758-807728e31f3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867481957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.3867481957
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.2304899714
Short name T1379
Test name
Test status
Simulation time 829912443 ps
CPU time 1.74 seconds
Started Jul 18 05:30:53 PM PDT 24
Finished Jul 18 05:30:59 PM PDT 24
Peak memory 205476 kb
Host smart-c44602a1-abd0-4a98-85fb-1b600442ae48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304899714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.2304899714
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.542536160
Short name T1660
Test name
Test status
Simulation time 2941814774 ps
CPU time 7.25 seconds
Started Jul 18 05:31:01 PM PDT 24
Finished Jul 18 05:31:10 PM PDT 24
Peak memory 222056 kb
Host smart-80c11e3c-5331-4667-86e6-efbcf513bb0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542536160 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.542536160
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.2378064896
Short name T1752
Test name
Test status
Simulation time 17815231 ps
CPU time 0.63 seconds
Started Jul 18 05:31:25 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 204836 kb
Host smart-fcd8cacc-38ba-4b1c-a446-9fb39c16b297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378064896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2378064896
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1321121977
Short name T1255
Test name
Test status
Simulation time 110663514 ps
CPU time 2.01 seconds
Started Jul 18 05:31:26 PM PDT 24
Finished Jul 18 05:31:31 PM PDT 24
Peak memory 213784 kb
Host smart-3e64f7ba-54cf-46c0-8e32-258cd50982e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321121977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1321121977
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.4048884620
Short name T698
Test name
Test status
Simulation time 255990626 ps
CPU time 5.37 seconds
Started Jul 18 05:31:29 PM PDT 24
Finished Jul 18 05:31:36 PM PDT 24
Peak memory 243888 kb
Host smart-21948874-3343-4fbe-89d9-e4816c7f70a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048884620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.4048884620
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.1423229188
Short name T23
Test name
Test status
Simulation time 11099969239 ps
CPU time 138.72 seconds
Started Jul 18 05:31:27 PM PDT 24
Finished Jul 18 05:33:49 PM PDT 24
Peak memory 252796 kb
Host smart-e2dac5db-fa56-4248-81ad-1c1305389030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423229188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.1423229188
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2097486356
Short name T897
Test name
Test status
Simulation time 6097600898 ps
CPU time 101.98 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:33:05 PM PDT 24
Peak memory 571492 kb
Host smart-d6f3d171-ae8d-4949-a098-8fe45ebabc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097486356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2097486356
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.2820076450
Short name T635
Test name
Test status
Simulation time 125746627 ps
CPU time 0.81 seconds
Started Jul 18 05:31:21 PM PDT 24
Finished Jul 18 05:31:23 PM PDT 24
Peak memory 205256 kb
Host smart-93e3dc59-8618-4d0b-83ac-68e8b2c77d63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820076450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.2820076450
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3240643281
Short name T592
Test name
Test status
Simulation time 399847440 ps
CPU time 6.65 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:30 PM PDT 24
Peak memory 205452 kb
Host smart-82a21807-bed6-45bc-9dd5-052383b76ce1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240643281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3240643281
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3044725974
Short name T1609
Test name
Test status
Simulation time 5333551447 ps
CPU time 157.98 seconds
Started Jul 18 05:31:25 PM PDT 24
Finished Jul 18 05:34:06 PM PDT 24
Peak memory 818388 kb
Host smart-a38cce55-81e3-4cd8-b113-13ed3e3d628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044725974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3044725974
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2285465574
Short name T231
Test name
Test status
Simulation time 403887003 ps
CPU time 16.62 seconds
Started Jul 18 05:31:23 PM PDT 24
Finished Jul 18 05:31:43 PM PDT 24
Peak memory 205480 kb
Host smart-c2acd57e-b008-44aa-bc74-dfada39a7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285465574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2285465574
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.1125612969
Short name T956
Test name
Test status
Simulation time 138429693 ps
CPU time 2.25 seconds
Started Jul 18 05:31:29 PM PDT 24
Finished Jul 18 05:31:33 PM PDT 24
Peak memory 218856 kb
Host smart-1bc38c96-b535-4dc6-8a7a-d883fdb64367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125612969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1125612969
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.93063311
Short name T85
Test name
Test status
Simulation time 17769403 ps
CPU time 0.68 seconds
Started Jul 18 05:31:20 PM PDT 24
Finished Jul 18 05:31:22 PM PDT 24
Peak memory 205240 kb
Host smart-ee6c06c6-0c67-4ff1-8fca-bc48b7084a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93063311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.93063311
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2080168530
Short name T1020
Test name
Test status
Simulation time 2971693040 ps
CPU time 40.66 seconds
Started Jul 18 05:31:33 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 313732 kb
Host smart-1e61864e-bd95-4c57-9953-ea09fa441cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080168530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2080168530
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.1967373260
Short name T1252
Test name
Test status
Simulation time 2529671680 ps
CPU time 162.23 seconds
Started Jul 18 05:31:27 PM PDT 24
Finished Jul 18 05:34:12 PM PDT 24
Peak memory 802840 kb
Host smart-dfae80a4-4538-46de-8c58-2f8e7ad3c174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967373260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.1967373260
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.130324514
Short name T858
Test name
Test status
Simulation time 20547143410 ps
CPU time 20.72 seconds
Started Jul 18 05:31:23 PM PDT 24
Finished Jul 18 05:31:47 PM PDT 24
Peak memory 331384 kb
Host smart-fb3f8b9b-1a25-475f-a3c7-ab72b59ffdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130324514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.130324514
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1130157926
Short name T736
Test name
Test status
Simulation time 3863110849 ps
CPU time 17.3 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:41 PM PDT 24
Peak memory 222008 kb
Host smart-7f73822d-fa6a-41dd-95c4-fec769492375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130157926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1130157926
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2245832955
Short name T294
Test name
Test status
Simulation time 5315815599 ps
CPU time 5.49 seconds
Started Jul 18 05:31:27 PM PDT 24
Finished Jul 18 05:31:36 PM PDT 24
Peak memory 213908 kb
Host smart-41641340-cd05-4a30-9b9c-ed5814770ae0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245832955 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2245832955
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.449746957
Short name T397
Test name
Test status
Simulation time 800934196 ps
CPU time 1.03 seconds
Started Jul 18 05:31:27 PM PDT 24
Finished Jul 18 05:31:31 PM PDT 24
Peak memory 205408 kb
Host smart-f3d32617-0566-4bb4-a578-27cfa8040697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449746957 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_acq.449746957
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2375208077
Short name T619
Test name
Test status
Simulation time 222344730 ps
CPU time 1 seconds
Started Jul 18 05:31:25 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 205456 kb
Host smart-7906f2cb-b06a-4fbb-9463-37fd51ff0f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375208077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2375208077
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.1335664807
Short name T1529
Test name
Test status
Simulation time 2297086056 ps
CPU time 3.19 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:27 PM PDT 24
Peak memory 205916 kb
Host smart-0070173f-9def-4baa-9eed-88d74ebd748e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335664807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.1335664807
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.3019206449
Short name T941
Test name
Test status
Simulation time 155055591 ps
CPU time 1.46 seconds
Started Jul 18 05:31:25 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 205444 kb
Host smart-33eb34ee-c2df-48c9-b066-29005d08c666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019206449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.3019206449
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1183540063
Short name T1702
Test name
Test status
Simulation time 1189970703 ps
CPU time 6.84 seconds
Started Jul 18 05:31:25 PM PDT 24
Finished Jul 18 05:31:36 PM PDT 24
Peak memory 213924 kb
Host smart-f499777d-371c-44b9-a502-f240a347fe01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183540063 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1183540063
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2284267303
Short name T594
Test name
Test status
Simulation time 21577201332 ps
CPU time 50.32 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 855956 kb
Host smart-e24c0e03-3450-4c5e-8c82-6f264f7c0dd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284267303 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2284267303
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.1105492033
Short name T1289
Test name
Test status
Simulation time 4108229059 ps
CPU time 3.11 seconds
Started Jul 18 05:31:21 PM PDT 24
Finished Jul 18 05:31:25 PM PDT 24
Peak memory 213952 kb
Host smart-be75535a-01c6-4f3f-8aae-91b475e60364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105492033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_nack_acqfull.1105492033
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.1776854660
Short name T609
Test name
Test status
Simulation time 490648322 ps
CPU time 2.21 seconds
Started Jul 18 05:31:21 PM PDT 24
Finished Jul 18 05:31:24 PM PDT 24
Peak memory 205664 kb
Host smart-a60332c3-1f62-44cb-87c8-d1e2525ee5ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776854660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.1776854660
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_txstretch.654347166
Short name T742
Test name
Test status
Simulation time 282271492 ps
CPU time 1.39 seconds
Started Jul 18 05:31:23 PM PDT 24
Finished Jul 18 05:31:27 PM PDT 24
Peak memory 222476 kb
Host smart-5b64ba49-bead-4c67-8681-fcf88c791678
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654347166 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_nack_txstretch.654347166
Directory /workspace/39.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/39.i2c_target_perf.3312722950
Short name T905
Test name
Test status
Simulation time 2204909845 ps
CPU time 3.76 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:27 PM PDT 24
Peak memory 213888 kb
Host smart-515e0458-e600-44f7-b508-fcc0f84492c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312722950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.3312722950
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.2102737134
Short name T762
Test name
Test status
Simulation time 456899170 ps
CPU time 2.27 seconds
Started Jul 18 05:31:27 PM PDT 24
Finished Jul 18 05:31:32 PM PDT 24
Peak memory 205392 kb
Host smart-c97ea66e-a1d1-45f7-b348-7ef270e3cfc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102737134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_smbus_maxlen.2102737134
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.177400112
Short name T869
Test name
Test status
Simulation time 4908168482 ps
CPU time 12.51 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:40 PM PDT 24
Peak memory 213860 kb
Host smart-2c0502d2-631a-4a13-9a4e-5aa6e7cf398c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177400112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_tar
get_smoke.177400112
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.1565154907
Short name T1332
Test name
Test status
Simulation time 6868440861 ps
CPU time 22.4 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 262972 kb
Host smart-c375b1f2-80ed-4f3b-a82e-d1e95f47ef97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565154907 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.1565154907
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1231896567
Short name T810
Test name
Test status
Simulation time 3973704228 ps
CPU time 36.87 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:32:04 PM PDT 24
Peak memory 213848 kb
Host smart-bd96c627-fe0f-469c-9260-1f79e5c790e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231896567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1231896567
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3854510087
Short name T192
Test name
Test status
Simulation time 58462279349 ps
CPU time 613.84 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:41:41 PM PDT 24
Peak memory 4743660 kb
Host smart-28b0d0ad-489c-4aa7-833a-e07fde8f2624
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854510087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3854510087
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3125884870
Short name T604
Test name
Test status
Simulation time 730860708 ps
CPU time 2.33 seconds
Started Jul 18 05:31:21 PM PDT 24
Finished Jul 18 05:31:24 PM PDT 24
Peak memory 205640 kb
Host smart-b084c5fd-9da8-45b2-8281-e3a8db53931b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125884870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3125884870
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1473632170
Short name T1273
Test name
Test status
Simulation time 2773979605 ps
CPU time 6.85 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:31 PM PDT 24
Peak memory 213836 kb
Host smart-f8baa6f1-9e65-47c9-9e73-f8f2e75d360d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473632170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1473632170
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.2407636988
Short name T1727
Test name
Test status
Simulation time 1497014064 ps
CPU time 17.65 seconds
Started Jul 18 05:31:23 PM PDT 24
Finished Jul 18 05:31:43 PM PDT 24
Peak memory 205748 kb
Host smart-b17a7ee2-1752-4cf9-9cb6-63145b4a83f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407636988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.2407636988
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.693471226
Short name T1530
Test name
Test status
Simulation time 41587795 ps
CPU time 0.62 seconds
Started Jul 18 05:26:43 PM PDT 24
Finished Jul 18 05:26:46 PM PDT 24
Peak memory 204820 kb
Host smart-8ea9243c-8343-4e89-be7b-f729965b106d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693471226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.693471226
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.1565631698
Short name T618
Test name
Test status
Simulation time 243371390 ps
CPU time 4.14 seconds
Started Jul 18 05:26:19 PM PDT 24
Finished Jul 18 05:26:25 PM PDT 24
Peak memory 229924 kb
Host smart-807bf8b4-8832-434d-aa0d-a691b4c02396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565631698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1565631698
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1988503769
Short name T81
Test name
Test status
Simulation time 1218901428 ps
CPU time 7.01 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:34 PM PDT 24
Peak memory 270204 kb
Host smart-213e77a3-9211-4c22-b446-65edfbecf6e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988503769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.1988503769
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2282345761
Short name T1476
Test name
Test status
Simulation time 2180696403 ps
CPU time 51.47 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:27:19 PM PDT 24
Peak memory 436524 kb
Host smart-cf22c91c-4174-4859-a553-06790ba36794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282345761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2282345761
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.178289462
Short name T476
Test name
Test status
Simulation time 4358709796 ps
CPU time 168.1 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:29:15 PM PDT 24
Peak memory 750264 kb
Host smart-e772ec5e-ec11-4f74-89d8-8cc13e8d4661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178289462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.178289462
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2076092732
Short name T1154
Test name
Test status
Simulation time 263380272 ps
CPU time 1.21 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:28 PM PDT 24
Peak memory 205408 kb
Host smart-37a3ee6f-6d2a-4e20-8ff9-0c7d0dd8fe9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076092732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2076092732
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3767519593
Short name T1537
Test name
Test status
Simulation time 2657376759 ps
CPU time 9.3 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:34 PM PDT 24
Peak memory 205516 kb
Host smart-ad8de55b-43e3-4830-b7f2-b7648f66c5f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767519593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3767519593
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.288008012
Short name T761
Test name
Test status
Simulation time 15013660224 ps
CPU time 215.45 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:30:03 PM PDT 24
Peak memory 934900 kb
Host smart-2dc9689f-a85c-40e2-900d-b98e67db73a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288008012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.288008012
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2002143683
Short name T773
Test name
Test status
Simulation time 7925054813 ps
CPU time 19.83 seconds
Started Jul 18 05:26:31 PM PDT 24
Finished Jul 18 05:26:52 PM PDT 24
Peak memory 205608 kb
Host smart-ec74fce2-0652-46b0-8f07-0742e7754005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002143683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2002143683
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3159077382
Short name T1265
Test name
Test status
Simulation time 134202075 ps
CPU time 1.85 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:26:29 PM PDT 24
Peak memory 205532 kb
Host smart-41bfcb31-719e-4589-a85a-dbe19d2f1f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159077382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3159077382
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.4197095068
Short name T713
Test name
Test status
Simulation time 17956517 ps
CPU time 0.67 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:24 PM PDT 24
Peak memory 205244 kb
Host smart-45eb225d-8735-455c-8ef9-53e75c1ca0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197095068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.4197095068
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3695571918
Short name T857
Test name
Test status
Simulation time 25274995040 ps
CPU time 267.48 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:30:56 PM PDT 24
Peak memory 1673900 kb
Host smart-5bb3102c-2487-4785-a628-dde793ae7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695571918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3695571918
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.1409349938
Short name T951
Test name
Test status
Simulation time 2057801918 ps
CPU time 10.67 seconds
Started Jul 18 05:26:21 PM PDT 24
Finished Jul 18 05:26:35 PM PDT 24
Peak memory 213556 kb
Host smart-9a7829c8-6ddc-4d16-ab04-062050d69ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409349938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.1409349938
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2376078675
Short name T791
Test name
Test status
Simulation time 22789663416 ps
CPU time 38.85 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:27:06 PM PDT 24
Peak memory 407980 kb
Host smart-a3853b17-4ffc-4785-9350-8db6b5b508ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376078675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2376078675
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.695709499
Short name T925
Test name
Test status
Simulation time 3073263662 ps
CPU time 13.78 seconds
Started Jul 18 05:26:23 PM PDT 24
Finished Jul 18 05:26:41 PM PDT 24
Peak memory 221836 kb
Host smart-0a102d13-afdc-4740-80da-b2a853cfab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695709499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.695709499
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.99290449
Short name T173
Test name
Test status
Simulation time 1015026602 ps
CPU time 0.96 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:26:44 PM PDT 24
Peak memory 224068 kb
Host smart-ec2d1231-51f1-46df-981a-e93c08d39c2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99290449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.99290449
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3289517856
Short name T1636
Test name
Test status
Simulation time 3612145729 ps
CPU time 4.89 seconds
Started Jul 18 05:26:29 PM PDT 24
Finished Jul 18 05:26:35 PM PDT 24
Peak memory 218164 kb
Host smart-369426bc-9d5c-4a19-b3ad-cd2930cfb431
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289517856 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3289517856
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1338199941
Short name T629
Test name
Test status
Simulation time 574083617 ps
CPU time 1.28 seconds
Started Jul 18 05:26:29 PM PDT 24
Finished Jul 18 05:26:31 PM PDT 24
Peak memory 205416 kb
Host smart-20b297e9-3011-4e33-ba89-f33eb1a14af6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338199941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1338199941
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1722606252
Short name T1750
Test name
Test status
Simulation time 233870330 ps
CPU time 1.25 seconds
Started Jul 18 05:26:28 PM PDT 24
Finished Jul 18 05:26:31 PM PDT 24
Peak memory 205404 kb
Host smart-fada3825-f8d9-48dd-a193-0275a667eade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722606252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1722606252
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.2926335326
Short name T1018
Test name
Test status
Simulation time 312846127 ps
CPU time 2.1 seconds
Started Jul 18 05:26:30 PM PDT 24
Finished Jul 18 05:26:33 PM PDT 24
Peak memory 205552 kb
Host smart-feb980e3-2160-4ea5-9c51-1ec61675c2f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926335326 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.2926335326
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.4206398619
Short name T550
Test name
Test status
Simulation time 174574388 ps
CPU time 1.23 seconds
Started Jul 18 05:26:31 PM PDT 24
Finished Jul 18 05:26:33 PM PDT 24
Peak memory 204868 kb
Host smart-ff178909-1902-4e0d-abd9-d86eccdca7f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206398619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.4206398619
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.620915497
Short name T811
Test name
Test status
Simulation time 3178550357 ps
CPU time 4.7 seconds
Started Jul 18 05:26:24 PM PDT 24
Finished Jul 18 05:26:33 PM PDT 24
Peak memory 221868 kb
Host smart-11533337-9c02-406f-93e9-1b886ae94ee2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620915497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.620915497
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1787618080
Short name T1344
Test name
Test status
Simulation time 10913405038 ps
CPU time 59.13 seconds
Started Jul 18 05:26:20 PM PDT 24
Finished Jul 18 05:27:22 PM PDT 24
Peak memory 1041084 kb
Host smart-14851c62-6b39-4213-a993-33d9bf6f0b10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787618080 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1787618080
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.2208998371
Short name T1536
Test name
Test status
Simulation time 525001670 ps
CPU time 2.98 seconds
Started Jul 18 05:26:51 PM PDT 24
Finished Jul 18 05:26:55 PM PDT 24
Peak memory 213804 kb
Host smart-f4d918c2-b522-481e-9a42-18019ddf8d80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208998371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.2208998371
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.186722269
Short name T896
Test name
Test status
Simulation time 1751594876 ps
CPU time 2.52 seconds
Started Jul 18 05:26:34 PM PDT 24
Finished Jul 18 05:26:37 PM PDT 24
Peak memory 205392 kb
Host smart-129fb9c8-7c89-4347-bffb-35bdc95a40db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186722269 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.186722269
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_txstretch.3174174608
Short name T1325
Test name
Test status
Simulation time 143845065 ps
CPU time 1.29 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 222232 kb
Host smart-eb641b55-942a-4a88-8162-9eac1139e717
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174174608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_nack_txstretch.3174174608
Directory /workspace/4.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/4.i2c_target_perf.920818428
Short name T1741
Test name
Test status
Simulation time 1013581071 ps
CPU time 4.1 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:30 PM PDT 24
Peak memory 220844 kb
Host smart-1225d719-3175-431f-b960-7a21c68b0ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920818428 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_perf.920818428
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.1952017009
Short name T912
Test name
Test status
Simulation time 1646198281 ps
CPU time 2.01 seconds
Started Jul 18 05:26:39 PM PDT 24
Finished Jul 18 05:26:45 PM PDT 24
Peak memory 205456 kb
Host smart-36444fe0-2cce-4712-ad3e-d2906966b254
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952017009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_smbus_maxlen.1952017009
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.4290986582
Short name T1648
Test name
Test status
Simulation time 2277663019 ps
CPU time 9.81 seconds
Started Jul 18 05:26:22 PM PDT 24
Finished Jul 18 05:26:37 PM PDT 24
Peak memory 213848 kb
Host smart-af64ce21-8989-410b-bac9-f8ea1d59a8ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290986582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.4290986582
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.2668251153
Short name T1133
Test name
Test status
Simulation time 48040309035 ps
CPU time 627.18 seconds
Started Jul 18 05:26:30 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 3898196 kb
Host smart-bb1e1249-ddbe-42fb-bb63-f440aff260a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668251153 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.2668251153
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3981393931
Short name T921
Test name
Test status
Simulation time 2497709452 ps
CPU time 26.64 seconds
Started Jul 18 05:26:28 PM PDT 24
Finished Jul 18 05:26:56 PM PDT 24
Peak memory 213824 kb
Host smart-6060854f-d249-48cc-bcfd-2d8ea15a0f32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981393931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3981393931
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2153927155
Short name T573
Test name
Test status
Simulation time 26612072991 ps
CPU time 111.61 seconds
Started Jul 18 05:26:24 PM PDT 24
Finished Jul 18 05:28:20 PM PDT 24
Peak memory 1673132 kb
Host smart-9012e495-ff75-4d92-900e-b13c9baabdd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153927155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2153927155
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.670388513
Short name T1275
Test name
Test status
Simulation time 1142054276 ps
CPU time 2.89 seconds
Started Jul 18 05:26:27 PM PDT 24
Finished Jul 18 05:26:33 PM PDT 24
Peak memory 213820 kb
Host smart-04c3517e-1518-4340-b2fc-a310a1607b91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670388513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.670388513
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1115361448
Short name T149
Test name
Test status
Simulation time 1151500065 ps
CPU time 6.81 seconds
Started Jul 18 05:26:24 PM PDT 24
Finished Jul 18 05:26:35 PM PDT 24
Peak memory 231460 kb
Host smart-dce64232-93ab-4a77-b1c8-38b6d1cf826d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115361448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1115361448
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.379103453
Short name T848
Test name
Test status
Simulation time 73809812 ps
CPU time 1.41 seconds
Started Jul 18 05:26:39 PM PDT 24
Finished Jul 18 05:26:45 PM PDT 24
Peak memory 205648 kb
Host smart-f6668492-f583-4899-b75a-09dd0a0cddbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379103453 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.379103453
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.703221474
Short name T401
Test name
Test status
Simulation time 18016587 ps
CPU time 0.73 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:31:47 PM PDT 24
Peak memory 204728 kb
Host smart-01fd0cf6-6e0e-4c47-9eef-ea269222d6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703221474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.703221474
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1978321611
Short name T26
Test name
Test status
Simulation time 288413186 ps
CPU time 1.66 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:26 PM PDT 24
Peak memory 213724 kb
Host smart-703ffbf8-e5de-44a0-b611-b84c15d66267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978321611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1978321611
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.340689810
Short name T855
Test name
Test status
Simulation time 1985643106 ps
CPU time 9.61 seconds
Started Jul 18 05:31:26 PM PDT 24
Finished Jul 18 05:31:39 PM PDT 24
Peak memory 285428 kb
Host smart-5226a5d3-cc2f-4a31-9ceb-cde1ea5c93e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340689810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empt
y.340689810
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.20976145
Short name T1038
Test name
Test status
Simulation time 2284059169 ps
CPU time 146.98 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:33:51 PM PDT 24
Peak memory 581340 kb
Host smart-b7646b4f-693c-42fa-be24-c02709e42ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20976145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.20976145
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3463610749
Short name T886
Test name
Test status
Simulation time 4672018805 ps
CPU time 71.29 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:32:38 PM PDT 24
Peak memory 720572 kb
Host smart-00c11bd0-9678-4150-8eba-7d86ba88decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463610749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3463610749
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3314045959
Short name T224
Test name
Test status
Simulation time 515954229 ps
CPU time 1.28 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:25 PM PDT 24
Peak memory 205428 kb
Host smart-4768f372-fd91-4723-9a5a-77826f775940
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314045959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3314045959
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.399251246
Short name T1508
Test name
Test status
Simulation time 3489391768 ps
CPU time 10.79 seconds
Started Jul 18 05:31:23 PM PDT 24
Finished Jul 18 05:31:37 PM PDT 24
Peak memory 241416 kb
Host smart-69d4fca2-30c7-450a-af47-0ffcd43cf569
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399251246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
399251246
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.116508720
Short name T1746
Test name
Test status
Simulation time 3903171359 ps
CPU time 105.27 seconds
Started Jul 18 05:31:27 PM PDT 24
Finished Jul 18 05:33:16 PM PDT 24
Peak memory 1090408 kb
Host smart-2a30cc2e-e77a-48af-b228-2d4ca95e0a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116508720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.116508720
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.3378930934
Short name T675
Test name
Test status
Simulation time 5158730996 ps
CPU time 25.24 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:53 PM PDT 24
Peak memory 205544 kb
Host smart-a635f2cd-b0c9-43ce-9c3d-61893fc69a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378930934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3378930934
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_override.3515915988
Short name T723
Test name
Test status
Simulation time 18166520 ps
CPU time 0.7 seconds
Started Jul 18 05:31:23 PM PDT 24
Finished Jul 18 05:31:27 PM PDT 24
Peak memory 205184 kb
Host smart-67676177-3ef4-4426-b01f-26c30cb78723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515915988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3515915988
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3238858526
Short name T13
Test name
Test status
Simulation time 13155977329 ps
CPU time 141.3 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:33:44 PM PDT 24
Peak memory 525988 kb
Host smart-8337dea1-a1dc-465c-8e37-0c12dbcf0441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238858526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3238858526
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.1757958587
Short name T837
Test name
Test status
Simulation time 132355347 ps
CPU time 1.37 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:28 PM PDT 24
Peak memory 223128 kb
Host smart-e34a6d37-cd64-4783-960d-55a1511dad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757958587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.1757958587
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.4212291155
Short name T1225
Test name
Test status
Simulation time 3508237989 ps
CPU time 77.77 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:32:41 PM PDT 24
Peak memory 299848 kb
Host smart-66e5f411-647e-4f34-b01e-d4c42d6b8f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212291155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.4212291155
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1732606057
Short name T259
Test name
Test status
Simulation time 54129138660 ps
CPU time 1021.64 seconds
Started Jul 18 05:31:23 PM PDT 24
Finished Jul 18 05:48:28 PM PDT 24
Peak memory 1451580 kb
Host smart-9d75b4bf-ade3-4556-9270-d065e3ad040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732606057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1732606057
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.771778666
Short name T1697
Test name
Test status
Simulation time 2868178920 ps
CPU time 31.21 seconds
Started Jul 18 05:31:21 PM PDT 24
Finished Jul 18 05:31:53 PM PDT 24
Peak memory 213812 kb
Host smart-44f268a9-7cdc-4cee-9aa3-d5d2eff0ca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771778666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.771778666
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.924607075
Short name T290
Test name
Test status
Simulation time 2685695397 ps
CPU time 7.06 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:31 PM PDT 24
Peak memory 222012 kb
Host smart-36561f5a-8747-4668-ac12-c689be3a02e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924607075 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.924607075
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1932613724
Short name T1526
Test name
Test status
Simulation time 489156141 ps
CPU time 1.45 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 205668 kb
Host smart-3ecfcac7-55c1-41ed-af9a-1b80bde74ea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932613724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1932613724
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.4047388214
Short name T523
Test name
Test status
Simulation time 284908201 ps
CPU time 1.52 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 205400 kb
Host smart-afae991a-dc65-410e-be89-6ee736a60887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047388214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.4047388214
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.465902743
Short name T355
Test name
Test status
Simulation time 483659253 ps
CPU time 2.41 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:30 PM PDT 24
Peak memory 205548 kb
Host smart-790acddf-ecb7-4f06-a19d-c10add7a6b82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465902743 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.465902743
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.104472578
Short name T1139
Test name
Test status
Simulation time 207019636 ps
CPU time 1.27 seconds
Started Jul 18 05:31:38 PM PDT 24
Finished Jul 18 05:31:42 PM PDT 24
Peak memory 205436 kb
Host smart-81676924-94ae-4030-9b0a-7d9aa0f838c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104472578 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.104472578
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.4065444797
Short name T682
Test name
Test status
Simulation time 913716016 ps
CPU time 1.76 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:25 PM PDT 24
Peak memory 213804 kb
Host smart-09f037b0-71e8-41b3-9066-9cbb69f4d6f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065444797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.4065444797
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2880183012
Short name T1043
Test name
Test status
Simulation time 14478472527 ps
CPU time 8.42 seconds
Started Jul 18 05:31:27 PM PDT 24
Finished Jul 18 05:31:38 PM PDT 24
Peak memory 232664 kb
Host smart-06325bc1-4893-4b97-99e4-f087c2370476
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880183012 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2880183012
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.1485542907
Short name T622
Test name
Test status
Simulation time 7237719444 ps
CPU time 16.28 seconds
Started Jul 18 05:31:26 PM PDT 24
Finished Jul 18 05:31:45 PM PDT 24
Peak memory 626384 kb
Host smart-8a9f701a-1f5a-4a61-b45b-069112bb7578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485542907 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.1485542907
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.3030567118
Short name T569
Test name
Test status
Simulation time 597343291 ps
CPU time 2.97 seconds
Started Jul 18 05:31:36 PM PDT 24
Finished Jul 18 05:31:41 PM PDT 24
Peak memory 213860 kb
Host smart-9e3df79d-1e9f-4bc1-af63-29f8afc6babb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030567118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_acqfull.3030567118
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.1024896622
Short name T1349
Test name
Test status
Simulation time 1971923591 ps
CPU time 2.47 seconds
Started Jul 18 05:31:38 PM PDT 24
Finished Jul 18 05:31:43 PM PDT 24
Peak memory 205592 kb
Host smart-cacde626-aa45-405a-ac09-d3caef8b7014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024896622 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.1024896622
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.456166768
Short name T1623
Test name
Test status
Simulation time 713958716 ps
CPU time 5.04 seconds
Started Jul 18 05:31:22 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 217540 kb
Host smart-ef3eb905-34b6-4711-a83f-18dc286c1a6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456166768 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_perf.456166768
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.2743360685
Short name T77
Test name
Test status
Simulation time 921487080 ps
CPU time 2.26 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:43 PM PDT 24
Peak memory 205364 kb
Host smart-8e57211a-4bc7-4227-a39a-f396aa843ba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743360685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.2743360685
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3959244378
Short name T794
Test name
Test status
Simulation time 1693222353 ps
CPU time 26.98 seconds
Started Jul 18 05:31:26 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 213808 kb
Host smart-daef97f5-e654-425a-b3d6-1628f3773e8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959244378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3959244378
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.334723409
Short name T845
Test name
Test status
Simulation time 32863681721 ps
CPU time 90.71 seconds
Started Jul 18 05:31:25 PM PDT 24
Finished Jul 18 05:32:59 PM PDT 24
Peak memory 910380 kb
Host smart-1fcd5d49-1d8d-45dd-9b1e-e52265f23a74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334723409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.i2c_target_stress_all.334723409
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.201494114
Short name T376
Test name
Test status
Simulation time 8121385520 ps
CPU time 71.04 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:32:39 PM PDT 24
Peak memory 217036 kb
Host smart-5b5be63c-d006-44fd-992e-bc823f3d01c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201494114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_rd.201494114
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3410173206
Short name T1581
Test name
Test status
Simulation time 66251421732 ps
CPU time 326.91 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:36:53 PM PDT 24
Peak memory 2976916 kb
Host smart-f5db29af-acad-4a87-90d5-a7b58357c996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410173206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3410173206
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1630424780
Short name T442
Test name
Test status
Simulation time 199624823 ps
CPU time 1.28 seconds
Started Jul 18 05:31:25 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 205364 kb
Host smart-b65cc30c-4646-4ad2-b702-ee67c3f6ea7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630424780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1630424780
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.321976519
Short name T1725
Test name
Test status
Simulation time 5252100986 ps
CPU time 6.29 seconds
Started Jul 18 05:31:24 PM PDT 24
Finished Jul 18 05:31:33 PM PDT 24
Peak memory 219980 kb
Host smart-aa030c42-9559-43c7-aa3c-36536a3e9fa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321976519 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.321976519
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.94815211
Short name T1461
Test name
Test status
Simulation time 154436028 ps
CPU time 2.6 seconds
Started Jul 18 05:31:46 PM PDT 24
Finished Jul 18 05:31:52 PM PDT 24
Peak memory 205608 kb
Host smart-46555666-bc5e-4360-81a6-fac64cae9696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94815211 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.94815211
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3944146966
Short name T809
Test name
Test status
Simulation time 49090928 ps
CPU time 0.65 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:43 PM PDT 24
Peak memory 204844 kb
Host smart-7b16c4ab-d0f4-45ca-90a8-4cdbb4deaea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944146966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3944146966
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2628347225
Short name T1606
Test name
Test status
Simulation time 84158203 ps
CPU time 1.61 seconds
Started Jul 18 05:31:38 PM PDT 24
Finished Jul 18 05:31:41 PM PDT 24
Peak memory 213760 kb
Host smart-83d7e1cf-3da3-468f-8ae2-a4d9f780648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628347225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2628347225
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3254885247
Short name T1575
Test name
Test status
Simulation time 650892871 ps
CPU time 5.51 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:47 PM PDT 24
Peak memory 257184 kb
Host smart-89783940-5402-4c54-a35c-65dc7bf22714
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254885247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3254885247
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1463931408
Short name T1588
Test name
Test status
Simulation time 2203184279 ps
CPU time 46.69 seconds
Started Jul 18 05:31:43 PM PDT 24
Finished Jul 18 05:32:34 PM PDT 24
Peak memory 343232 kb
Host smart-dea8e8e3-ef94-4de8-bb01-9d61c70ab9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463931408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1463931408
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1257161635
Short name T154
Test name
Test status
Simulation time 10017109444 ps
CPU time 100.81 seconds
Started Jul 18 05:31:44 PM PDT 24
Finished Jul 18 05:33:29 PM PDT 24
Peak memory 881304 kb
Host smart-9b5da8e6-abac-4024-bec3-103c4a7ae05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257161635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1257161635
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.4139684713
Short name T1153
Test name
Test status
Simulation time 1803959863 ps
CPU time 1.39 seconds
Started Jul 18 05:31:40 PM PDT 24
Finished Jul 18 05:31:44 PM PDT 24
Peak memory 205380 kb
Host smart-83c15440-cf8f-4a0d-853c-cb7139bc0dbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139684713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.4139684713
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1658190575
Short name T40
Test name
Test status
Simulation time 1811276452 ps
CPU time 4.95 seconds
Started Jul 18 05:31:47 PM PDT 24
Finished Jul 18 05:31:56 PM PDT 24
Peak memory 237884 kb
Host smart-341c6a0e-825f-4abc-9d16-e5fd7149b9c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658190575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1658190575
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1914354979
Short name T1356
Test name
Test status
Simulation time 17995514647 ps
CPU time 295.14 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:36:39 PM PDT 24
Peak memory 1181576 kb
Host smart-5b38c3ca-3415-4f0c-a17b-7d74d0aa03e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914354979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1914354979
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_override.3192810372
Short name T1567
Test name
Test status
Simulation time 52881630 ps
CPU time 0.7 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:53 PM PDT 24
Peak memory 205188 kb
Host smart-33ba60e1-806e-48e6-aa8b-e83e4a90a930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192810372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3192810372
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3284457569
Short name T395
Test name
Test status
Simulation time 7155894296 ps
CPU time 23.77 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:32:17 PM PDT 24
Peak memory 205516 kb
Host smart-23408156-85ea-4417-9da0-fc1344a64bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284457569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3284457569
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.472926481
Short name T279
Test name
Test status
Simulation time 85675502 ps
CPU time 2.2 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:31:47 PM PDT 24
Peak memory 229912 kb
Host smart-9fa2426b-dc83-4adc-938d-9dd1934ae139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472926481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.472926481
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3166034242
Short name T534
Test name
Test status
Simulation time 1702864045 ps
CPU time 81.05 seconds
Started Jul 18 05:31:35 PM PDT 24
Finished Jul 18 05:32:58 PM PDT 24
Peak memory 338852 kb
Host smart-28fb747d-47e5-46db-b801-c849c6dd9821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166034242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3166034242
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3817455225
Short name T544
Test name
Test status
Simulation time 1428992095 ps
CPU time 33.61 seconds
Started Jul 18 05:31:38 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 213768 kb
Host smart-2fd04f32-4fe8-470e-9ea0-9798e43baead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817455225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3817455225
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3369286032
Short name T57
Test name
Test status
Simulation time 966653913 ps
CPU time 4.51 seconds
Started Jul 18 05:31:38 PM PDT 24
Finished Jul 18 05:31:45 PM PDT 24
Peak memory 213820 kb
Host smart-f01a6aeb-297a-4b8a-9684-fa465e180d26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369286032 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3369286032
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.4188299269
Short name T1123
Test name
Test status
Simulation time 307580457 ps
CPU time 1.25 seconds
Started Jul 18 05:31:43 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 205572 kb
Host smart-7c506f6b-0381-4bb7-a7fd-10dafa53e462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188299269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.4188299269
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1416001816
Short name T883
Test name
Test status
Simulation time 763830370 ps
CPU time 1.55 seconds
Started Jul 18 05:31:38 PM PDT 24
Finished Jul 18 05:31:41 PM PDT 24
Peak memory 205604 kb
Host smart-72af850e-0687-489d-a576-9955ede10b64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416001816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1416001816
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.3862985307
Short name T1629
Test name
Test status
Simulation time 66891724 ps
CPU time 0.85 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:42 PM PDT 24
Peak memory 205396 kb
Host smart-437ce9f6-c402-4869-bc3a-aeb3db46ae63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862985307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.3862985307
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.3758191060
Short name T1234
Test name
Test status
Simulation time 134323508 ps
CPU time 1.54 seconds
Started Jul 18 05:31:38 PM PDT 24
Finished Jul 18 05:31:41 PM PDT 24
Peak memory 205468 kb
Host smart-7bca16c1-c453-44df-ab1e-976206b7d3ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758191060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3758191060
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3831820354
Short name T585
Test name
Test status
Simulation time 1126151525 ps
CPU time 2.51 seconds
Started Jul 18 05:31:40 PM PDT 24
Finished Jul 18 05:31:45 PM PDT 24
Peak memory 213784 kb
Host smart-c933d6ee-f901-4479-b954-0135f9eb242a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831820354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3831820354
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.549803941
Short name T378
Test name
Test status
Simulation time 3356488536 ps
CPU time 5.59 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:47 PM PDT 24
Peak memory 222120 kb
Host smart-78047ce8-0531-499c-8ba0-7dbd8f4cea2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549803941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.549803941
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3383636943
Short name T560
Test name
Test status
Simulation time 24481628293 ps
CPU time 680.67 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:43:03 PM PDT 24
Peak memory 4468088 kb
Host smart-0a568f9c-81c6-44af-9268-91a0f2b238a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383636943 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3383636943
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.1883202532
Short name T576
Test name
Test status
Simulation time 596956936 ps
CPU time 2.95 seconds
Started Jul 18 05:31:35 PM PDT 24
Finished Jul 18 05:31:38 PM PDT 24
Peak memory 213900 kb
Host smart-b7124215-555f-449b-b40d-52a6331b7866
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883202532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_acqfull.1883202532
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.1890709883
Short name T1557
Test name
Test status
Simulation time 1454891334 ps
CPU time 2.8 seconds
Started Jul 18 05:31:37 PM PDT 24
Finished Jul 18 05:31:42 PM PDT 24
Peak memory 205596 kb
Host smart-75c6b48d-d321-4870-9775-23c67de0e7b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890709883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.1890709883
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_txstretch.2729264143
Short name T62
Test name
Test status
Simulation time 246235945 ps
CPU time 1.52 seconds
Started Jul 18 05:31:40 PM PDT 24
Finished Jul 18 05:31:44 PM PDT 24
Peak memory 222404 kb
Host smart-2cd2b6d0-8fdd-4ea5-bffd-b07fb5d30f29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729264143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_nack_txstretch.2729264143
Directory /workspace/41.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/41.i2c_target_perf.1126257995
Short name T695
Test name
Test status
Simulation time 790696773 ps
CPU time 5.67 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:31:50 PM PDT 24
Peak memory 217912 kb
Host smart-ec2faf91-018c-4520-9f16-3abdd0c93906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126257995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.1126257995
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.1950969422
Short name T127
Test name
Test status
Simulation time 421059950 ps
CPU time 2.25 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 205640 kb
Host smart-d2ff88ed-77cb-432e-9f1e-23c669f08e62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950969422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.1950969422
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.1125210196
Short name T1706
Test name
Test status
Simulation time 1419191586 ps
CPU time 10.92 seconds
Started Jul 18 05:31:36 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 213864 kb
Host smart-6c8595f7-e6ad-4739-8657-0797786f844d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125210196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.1125210196
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.416280187
Short name T252
Test name
Test status
Simulation time 86817813883 ps
CPU time 114.33 seconds
Started Jul 18 05:31:37 PM PDT 24
Finished Jul 18 05:33:33 PM PDT 24
Peak memory 1061104 kb
Host smart-445a8758-648a-450e-b45d-2a47d9dcd231
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416280187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_target_stress_all.416280187
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.225741154
Short name T84
Test name
Test status
Simulation time 336898020 ps
CPU time 6.67 seconds
Started Jul 18 05:31:36 PM PDT 24
Finished Jul 18 05:31:44 PM PDT 24
Peak memory 205652 kb
Host smart-f8074aa3-dcb6-4fae-85fb-4a274ec5c263
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225741154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.225741154
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1999146246
Short name T1393
Test name
Test status
Simulation time 8287358033 ps
CPU time 5.32 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 205688 kb
Host smart-fc7f15fc-f7cc-4caa-9c35-2ff3e960edb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999146246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1999146246
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2737693010
Short name T816
Test name
Test status
Simulation time 443052713 ps
CPU time 2.14 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:44 PM PDT 24
Peak memory 215924 kb
Host smart-0cda40c1-0baf-40b8-8e02-a62a9148e95e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737693010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2737693010
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2907615958
Short name T417
Test name
Test status
Simulation time 4858048261 ps
CPU time 6.94 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:31:53 PM PDT 24
Peak memory 238468 kb
Host smart-35b759f0-9734-41de-bb6a-0b3bfe300185
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907615958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2907615958
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.341674873
Short name T490
Test name
Test status
Simulation time 650605966 ps
CPU time 7.34 seconds
Started Jul 18 05:31:36 PM PDT 24
Finished Jul 18 05:31:45 PM PDT 24
Peak memory 205572 kb
Host smart-2d3504ec-663c-4e14-9da6-14cee03feb8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341674873 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.341674873
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.578361796
Short name T1495
Test name
Test status
Simulation time 16818109 ps
CPU time 0.66 seconds
Started Jul 18 05:31:53 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 204864 kb
Host smart-3df94fa0-2dd7-44cf-8657-868a2bd91b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578361796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.578361796
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2932517865
Short name T1209
Test name
Test status
Simulation time 320580270 ps
CPU time 4.17 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:31:58 PM PDT 24
Peak memory 213716 kb
Host smart-f5e591c7-9823-44cd-8550-991b39f201b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932517865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2932517865
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.176570907
Short name T1221
Test name
Test status
Simulation time 648354398 ps
CPU time 3.96 seconds
Started Jul 18 05:31:37 PM PDT 24
Finished Jul 18 05:31:42 PM PDT 24
Peak memory 243212 kb
Host smart-5e8cdb3e-3c49-4c03-85c7-9ba778554117
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176570907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.176570907
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.215136841
Short name T1366
Test name
Test status
Simulation time 3520185885 ps
CPU time 255.01 seconds
Started Jul 18 05:31:38 PM PDT 24
Finished Jul 18 05:35:55 PM PDT 24
Peak memory 687504 kb
Host smart-c136b037-da99-4193-883f-b2404b3cddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215136841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.215136841
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1714310499
Short name T838
Test name
Test status
Simulation time 42093558722 ps
CPU time 204.58 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:35:11 PM PDT 24
Peak memory 835984 kb
Host smart-625e1412-3620-48cf-b4f6-67ad3185d292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714310499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1714310499
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2237748570
Short name T225
Test name
Test status
Simulation time 406380571 ps
CPU time 1.21 seconds
Started Jul 18 05:31:40 PM PDT 24
Finished Jul 18 05:31:44 PM PDT 24
Peak memory 205216 kb
Host smart-40723425-6167-49a3-9e5c-2723a6a1473d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237748570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2237748570
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1758267714
Short name T1625
Test name
Test status
Simulation time 848775407 ps
CPU time 6.26 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:48 PM PDT 24
Peak memory 249200 kb
Host smart-a1598863-f61b-430b-a971-8b0cb3656270
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758267714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1758267714
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3807667466
Short name T1280
Test name
Test status
Simulation time 19833802544 ps
CPU time 147.79 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:34:09 PM PDT 24
Peak memory 1377288 kb
Host smart-b1dd6a5d-0466-470c-ba4d-d80d487c34c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807667466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3807667466
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3610271959
Short name T1634
Test name
Test status
Simulation time 433028589 ps
CPU time 3.01 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:55 PM PDT 24
Peak memory 205436 kb
Host smart-99cf622e-d63e-4df5-903c-38273d4521bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610271959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3610271959
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.1132590418
Short name T113
Test name
Test status
Simulation time 95270626 ps
CPU time 0.7 seconds
Started Jul 18 05:31:45 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 205184 kb
Host smart-b3b63c3b-c068-4aea-9df3-7998bb4b03a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132590418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1132590418
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3702678001
Short name T443
Test name
Test status
Simulation time 31267459841 ps
CPU time 437 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:39:02 PM PDT 24
Peak memory 213804 kb
Host smart-8d595999-a759-48ba-84e3-d52171be4b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702678001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3702678001
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.2919311550
Short name T492
Test name
Test status
Simulation time 161090884 ps
CPU time 3.02 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 205644 kb
Host smart-e8fb7e40-cd23-4b37-917f-3adfdc31a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919311550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.2919311550
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3739486744
Short name T1177
Test name
Test status
Simulation time 2902732959 ps
CPU time 21.62 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:32:07 PM PDT 24
Peak memory 305308 kb
Host smart-d90c0a44-dc7c-4020-a513-63b575a492e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739486744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3739486744
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.206856726
Short name T557
Test name
Test status
Simulation time 6156427907 ps
CPU time 12.99 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 221884 kb
Host smart-85c46858-3f16-4240-891a-4ee0ec34e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206856726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.206856726
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1552168359
Short name T1035
Test name
Test status
Simulation time 990495677 ps
CPU time 5.43 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:58 PM PDT 24
Peak memory 213800 kb
Host smart-970a164e-f31d-476e-bbe3-5901842702e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552168359 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1552168359
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.642388635
Short name T763
Test name
Test status
Simulation time 162025699 ps
CPU time 0.98 seconds
Started Jul 18 05:31:40 PM PDT 24
Finished Jul 18 05:31:43 PM PDT 24
Peak memory 205376 kb
Host smart-06287aa2-8e29-470f-965b-3b1ca1f1486a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642388635 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.642388635
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1910371158
Short name T1448
Test name
Test status
Simulation time 227859358 ps
CPU time 1.69 seconds
Started Jul 18 05:31:47 PM PDT 24
Finished Jul 18 05:31:53 PM PDT 24
Peak memory 205600 kb
Host smart-832e88d0-fd60-4e08-a1d7-2e4c2a7d5cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910371158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1910371158
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.2928614151
Short name T357
Test name
Test status
Simulation time 1421827092 ps
CPU time 2.1 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:31:48 PM PDT 24
Peak memory 205540 kb
Host smart-ba485660-d244-4181-959b-b780f771e34d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928614151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.2928614151
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.2664142289
Short name T785
Test name
Test status
Simulation time 668214739 ps
CPU time 1.62 seconds
Started Jul 18 05:31:52 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 205240 kb
Host smart-4af8176c-aedd-4036-a1b0-474466ebb375
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664142289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.2664142289
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1141433939
Short name T1085
Test name
Test status
Simulation time 368278774 ps
CPU time 1.9 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:54 PM PDT 24
Peak memory 213948 kb
Host smart-03bb6b3d-ba47-4bf4-b88b-a8b98ee182aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141433939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1141433939
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3362742181
Short name T429
Test name
Test status
Simulation time 1165247258 ps
CPU time 6.48 seconds
Started Jul 18 05:31:47 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 219620 kb
Host smart-ea7b70d7-5c6b-41ce-a91d-6b5d9dcf2b13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362742181 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.3362742181
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1145653652
Short name T1671
Test name
Test status
Simulation time 5668613158 ps
CPU time 61.61 seconds
Started Jul 18 05:31:47 PM PDT 24
Finished Jul 18 05:32:52 PM PDT 24
Peak memory 1474840 kb
Host smart-37ce3280-0685-4a5b-95f9-4e634c0dbd6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145653652 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1145653652
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.2333521797
Short name T1156
Test name
Test status
Simulation time 1086719111 ps
CPU time 2.77 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:31:56 PM PDT 24
Peak memory 213728 kb
Host smart-06249963-3b88-44f8-9bbb-d5e48c5381f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333521797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.2333521797
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.2215345705
Short name T409
Test name
Test status
Simulation time 2340293845 ps
CPU time 2.76 seconds
Started Jul 18 05:31:52 PM PDT 24
Finished Jul 18 05:31:59 PM PDT 24
Peak memory 205476 kb
Host smart-75368ce9-f843-4beb-848b-78ba9566e5cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215345705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.2215345705
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_txstretch.2268007576
Short name T45
Test name
Test status
Simulation time 292624165 ps
CPU time 1.36 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:31:46 PM PDT 24
Peak memory 222296 kb
Host smart-caa5db48-4b69-4984-9989-c11f29a202a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268007576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_nack_txstretch.2268007576
Directory /workspace/42.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/42.i2c_target_perf.3000112263
Short name T1320
Test name
Test status
Simulation time 961943150 ps
CPU time 5.86 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:58 PM PDT 24
Peak memory 221948 kb
Host smart-e3b9584d-4330-4f79-85eb-a688e24174dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000112263 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.3000112263
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.2305375622
Short name T1695
Test name
Test status
Simulation time 1722239075 ps
CPU time 2.26 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:31:55 PM PDT 24
Peak memory 205364 kb
Host smart-9da3fc14-47a5-414c-bb49-2332f45ee9ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305375622 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_smbus_maxlen.2305375622
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.121805934
Short name T1295
Test name
Test status
Simulation time 1152398927 ps
CPU time 17.9 seconds
Started Jul 18 05:31:37 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 209224 kb
Host smart-b99bc9f8-3195-42c0-839e-83dcefa5bd39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121805934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.121805934
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.3581277113
Short name T732
Test name
Test status
Simulation time 54945884339 ps
CPU time 838.56 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:45:52 PM PDT 24
Peak memory 4804164 kb
Host smart-38fe3463-8918-4b62-8749-d084c6591fac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581277113 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.3581277113
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.942898781
Short name T532
Test name
Test status
Simulation time 7722893764 ps
CPU time 58.36 seconds
Started Jul 18 05:31:52 PM PDT 24
Finished Jul 18 05:32:54 PM PDT 24
Peak memory 217612 kb
Host smart-95fea029-40b5-4cae-805a-f147e69b24aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942898781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.942898781
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3765098573
Short name T1523
Test name
Test status
Simulation time 56918581284 ps
CPU time 231.9 seconds
Started Jul 18 05:31:54 PM PDT 24
Finished Jul 18 05:35:48 PM PDT 24
Peak memory 2301396 kb
Host smart-14485f67-ee59-4a0b-b24c-9a86101f56d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765098573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3765098573
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2454823525
Short name T952
Test name
Test status
Simulation time 4561059525 ps
CPU time 6.29 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:32:00 PM PDT 24
Peak memory 222008 kb
Host smart-1ff647b4-783b-43bc-8450-31fe83dbf738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454823525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2454823525
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.886071522
Short name T1172
Test name
Test status
Simulation time 387491931 ps
CPU time 4.95 seconds
Started Jul 18 05:31:52 PM PDT 24
Finished Jul 18 05:32:00 PM PDT 24
Peak memory 205604 kb
Host smart-7913c024-8b75-4be2-93a0-a2048a1b43af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886071522 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.886071522
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1177865436
Short name T488
Test name
Test status
Simulation time 61901397 ps
CPU time 0.64 seconds
Started Jul 18 05:31:52 PM PDT 24
Finished Jul 18 05:31:56 PM PDT 24
Peak memory 204860 kb
Host smart-5ef06563-137c-47f2-a4b0-7de9a26558c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177865436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1177865436
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2671163739
Short name T705
Test name
Test status
Simulation time 875272163 ps
CPU time 1.82 seconds
Started Jul 18 05:31:40 PM PDT 24
Finished Jul 18 05:31:45 PM PDT 24
Peak memory 213748 kb
Host smart-2fbab0ae-f16c-409c-8800-d79c6204e086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671163739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2671163739
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.78585958
Short name T434
Test name
Test status
Simulation time 1047739927 ps
CPU time 7 seconds
Started Jul 18 05:31:44 PM PDT 24
Finished Jul 18 05:31:55 PM PDT 24
Peak memory 265756 kb
Host smart-6a5d0536-048b-44a4-a3a3-1eb008807050
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78585958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty
.78585958
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1183917961
Short name T140
Test name
Test status
Simulation time 1742551795 ps
CPU time 44.39 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:32:30 PM PDT 24
Peak memory 301128 kb
Host smart-5e30a897-d3e0-4180-a6db-dd9129dc3768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183917961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1183917961
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1860198050
Short name T1281
Test name
Test status
Simulation time 19196453836 ps
CPU time 72.87 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:32:58 PM PDT 24
Peak memory 756460 kb
Host smart-6008c1c7-38e3-4c41-bab7-b72bc72bc8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860198050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1860198050
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.1547139333
Short name T966
Test name
Test status
Simulation time 477327506 ps
CPU time 1.06 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:31:54 PM PDT 24
Peak memory 205196 kb
Host smart-a6ffc507-2c68-4146-8d1a-4e4c2adca7f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547139333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.1547139333
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1959569995
Short name T1593
Test name
Test status
Simulation time 417243089 ps
CPU time 11.4 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:32:04 PM PDT 24
Peak memory 205472 kb
Host smart-54c39f1b-2f9a-49e5-9baf-e1f90a2090b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959569995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1959569995
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3926621109
Short name T370
Test name
Test status
Simulation time 13809095914 ps
CPU time 99.7 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:33:26 PM PDT 24
Peak memory 1068416 kb
Host smart-632212f3-6c5e-4b5d-a0fb-aefafde07c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926621109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3926621109
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3321867802
Short name T238
Test name
Test status
Simulation time 361722926 ps
CPU time 14.7 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 205372 kb
Host smart-dac58d8b-6e46-4dde-99f4-980defede8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321867802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3321867802
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.1208634752
Short name T1655
Test name
Test status
Simulation time 20172822 ps
CPU time 0.67 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:43 PM PDT 24
Peak memory 205204 kb
Host smart-f0f9a9be-5857-4dba-bb31-895fadc7b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208634752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1208634752
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.3977413050
Short name T973
Test name
Test status
Simulation time 700100153 ps
CPU time 8.39 seconds
Started Jul 18 05:31:47 PM PDT 24
Finished Jul 18 05:31:59 PM PDT 24
Peak memory 220200 kb
Host smart-834cc6aa-173c-42f2-8be3-d7e0127244ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977413050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3977413050
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.3137634401
Short name T784
Test name
Test status
Simulation time 125182589 ps
CPU time 4.87 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:31:50 PM PDT 24
Peak memory 213572 kb
Host smart-c15860ce-2db9-42ec-97c2-98509bb2e1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137634401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.3137634401
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2015687042
Short name T1692
Test name
Test status
Simulation time 11465636023 ps
CPU time 21.96 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:32:15 PM PDT 24
Peak memory 311632 kb
Host smart-61135377-b737-4bcb-95da-b8d27b4d5cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015687042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2015687042
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.935962904
Short name T491
Test name
Test status
Simulation time 1139485245 ps
CPU time 25.66 seconds
Started Jul 18 05:31:45 PM PDT 24
Finished Jul 18 05:32:15 PM PDT 24
Peak memory 213808 kb
Host smart-12631291-f89e-4abd-aca5-eafe3844797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935962904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.935962904
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.892387837
Short name T1283
Test name
Test status
Simulation time 808327331 ps
CPU time 4.5 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:31:51 PM PDT 24
Peak memory 214092 kb
Host smart-508ac02e-2429-4b51-8cfc-eb3564219142
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892387837 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.892387837
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1802982218
Short name T1241
Test name
Test status
Simulation time 284704823 ps
CPU time 1.19 seconds
Started Jul 18 05:31:43 PM PDT 24
Finished Jul 18 05:31:48 PM PDT 24
Peak memory 205724 kb
Host smart-62e14662-402b-450c-b9dd-dbf225464525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802982218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1802982218
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2951401274
Short name T335
Test name
Test status
Simulation time 201201404 ps
CPU time 1.27 seconds
Started Jul 18 05:31:53 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 205636 kb
Host smart-7d444e4f-6409-4497-affc-2e97e41ae126
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951401274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2951401274
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.1634875480
Short name T919
Test name
Test status
Simulation time 2967018141 ps
CPU time 2.69 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:56 PM PDT 24
Peak memory 205632 kb
Host smart-f2538e9c-2ffb-445f-b0dc-019a75b7fc0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634875480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.1634875480
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.1138506283
Short name T658
Test name
Test status
Simulation time 91231553 ps
CPU time 1.01 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:31:55 PM PDT 24
Peak memory 205408 kb
Host smart-a5ab29a9-53ff-468d-ab0b-4d00eee3dcb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138506283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.1138506283
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2407022498
Short name T1348
Test name
Test status
Simulation time 329706236 ps
CPU time 1.48 seconds
Started Jul 18 05:31:47 PM PDT 24
Finished Jul 18 05:31:53 PM PDT 24
Peak memory 205616 kb
Host smart-3e0a859a-4512-41a7-b2f4-38ec065eaf40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407022498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2407022498
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1099636421
Short name T1680
Test name
Test status
Simulation time 14010691054 ps
CPU time 5.06 seconds
Started Jul 18 05:31:43 PM PDT 24
Finished Jul 18 05:31:52 PM PDT 24
Peak memory 216252 kb
Host smart-5e571002-83f5-4122-a958-1f6cc0ad4d49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099636421 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1099636421
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.811880962
Short name T1169
Test name
Test status
Simulation time 13708544234 ps
CPU time 258.49 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:36:12 PM PDT 24
Peak memory 3276188 kb
Host smart-dcf00178-1950-4ca8-b750-9bc3e543fd74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811880962 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.811880962
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.2559601708
Short name T1507
Test name
Test status
Simulation time 466982132 ps
CPU time 2.6 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:54 PM PDT 24
Peak memory 213816 kb
Host smart-b9ce8eb1-34c9-41b8-b0bc-e8bc1388d0e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559601708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.2559601708
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.3930875788
Short name T475
Test name
Test status
Simulation time 941187868 ps
CPU time 2.36 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:54 PM PDT 24
Peak memory 205496 kb
Host smart-f1fb60c0-45db-44f7-901f-cb2e534ab0fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930875788 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.3930875788
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_txstretch.3193769258
Short name T697
Test name
Test status
Simulation time 522563704 ps
CPU time 1.56 seconds
Started Jul 18 05:31:54 PM PDT 24
Finished Jul 18 05:31:58 PM PDT 24
Peak memory 222168 kb
Host smart-be2e866e-bf38-4090-9834-6749b49bb21e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193769258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_nack_txstretch.3193769258
Directory /workspace/43.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/43.i2c_target_perf.3577244779
Short name T1436
Test name
Test status
Simulation time 622168890 ps
CPU time 4.57 seconds
Started Jul 18 05:31:39 PM PDT 24
Finished Jul 18 05:31:46 PM PDT 24
Peak memory 221984 kb
Host smart-eb9a5188-bc7c-4fb0-a33e-7fc02fd6c0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577244779 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.3577244779
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.4071237327
Short name T380
Test name
Test status
Simulation time 675055576 ps
CPU time 1.89 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:31:55 PM PDT 24
Peak memory 204908 kb
Host smart-4d5a82f7-b502-47c4-810d-87fc8d09285f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071237327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_smbus_maxlen.4071237327
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1508831352
Short name T661
Test name
Test status
Simulation time 3013642160 ps
CPU time 10.99 seconds
Started Jul 18 05:31:47 PM PDT 24
Finished Jul 18 05:32:02 PM PDT 24
Peak memory 213884 kb
Host smart-25f5507a-38b4-4adf-9b0e-8beaf2d13822
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508831352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1508831352
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.2769321461
Short name T1566
Test name
Test status
Simulation time 70267550842 ps
CPU time 239.85 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:35:52 PM PDT 24
Peak memory 2312612 kb
Host smart-b2c40c57-c71a-4f16-a3de-43a371978194
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769321461 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.2769321461
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.544050805
Short name T1739
Test name
Test status
Simulation time 1008091606 ps
CPU time 18.35 seconds
Started Jul 18 05:31:43 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 221640 kb
Host smart-f2e23b8f-5c17-45d2-a5d6-e1899e4e0537
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544050805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.544050805
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3169924200
Short name T662
Test name
Test status
Simulation time 49569608928 ps
CPU time 434.71 seconds
Started Jul 18 05:31:43 PM PDT 24
Finished Jul 18 05:39:02 PM PDT 24
Peak memory 3709228 kb
Host smart-357f4af2-cc91-4ba5-8e82-9fff43f19495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169924200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3169924200
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.3694983803
Short name T1316
Test name
Test status
Simulation time 2869385011 ps
CPU time 135.18 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:34:00 PM PDT 24
Peak memory 833032 kb
Host smart-9fcefb3e-8a9e-49f9-9651-4fdc1d563532
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694983803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.3694983803
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3669163817
Short name T1179
Test name
Test status
Simulation time 1537441777 ps
CPU time 7.65 seconds
Started Jul 18 05:31:40 PM PDT 24
Finished Jul 18 05:31:51 PM PDT 24
Peak memory 218744 kb
Host smart-1182bbaf-0e2f-4ab4-863f-89378db1b527
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669163817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3669163817
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.2916213377
Short name T989
Test name
Test status
Simulation time 103506916 ps
CPU time 2.24 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:31:54 PM PDT 24
Peak memory 205576 kb
Host smart-4ec1dd3e-8054-4dcb-8e21-a8db2a70295b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916213377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.2916213377
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2449094775
Short name T1267
Test name
Test status
Simulation time 18613745 ps
CPU time 0.64 seconds
Started Jul 18 05:32:01 PM PDT 24
Finished Jul 18 05:32:03 PM PDT 24
Peak memory 204756 kb
Host smart-79df0070-2156-4b55-bc75-a31b4eca4736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449094775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2449094775
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1245333736
Short name T1528
Test name
Test status
Simulation time 360479433 ps
CPU time 1.64 seconds
Started Jul 18 05:31:42 PM PDT 24
Finished Jul 18 05:31:48 PM PDT 24
Peak memory 213956 kb
Host smart-98eb17db-7718-4238-b4b0-2479a814e583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245333736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1245333736
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1158080177
Short name T505
Test name
Test status
Simulation time 782276040 ps
CPU time 5.52 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:31:59 PM PDT 24
Peak memory 268388 kb
Host smart-ef1f8706-005a-48ba-af4c-abebfe652c6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158080177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1158080177
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2859213907
Short name T908
Test name
Test status
Simulation time 12319860413 ps
CPU time 157.13 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:34:30 PM PDT 24
Peak memory 453924 kb
Host smart-6ab2bf55-6f5a-4dea-9d51-1937e5fff6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859213907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2859213907
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.552395854
Short name T856
Test name
Test status
Simulation time 20355272978 ps
CPU time 91.96 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:33:26 PM PDT 24
Peak memory 460844 kb
Host smart-939fd9b7-b5b3-472a-a142-8f134f101ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552395854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.552395854
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3247707086
Short name T516
Test name
Test status
Simulation time 566544309 ps
CPU time 1.22 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:31:54 PM PDT 24
Peak memory 205180 kb
Host smart-9d99c082-f58a-45cc-b8bd-1a46eea068b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247707086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3247707086
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.278220045
Short name T1116
Test name
Test status
Simulation time 947208621 ps
CPU time 11.5 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 244556 kb
Host smart-0ca96ebf-b24d-495b-9b99-ecee839c9af7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278220045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
278220045
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.604008783
Short name T101
Test name
Test status
Simulation time 6027612879 ps
CPU time 64.69 seconds
Started Jul 18 05:31:52 PM PDT 24
Finished Jul 18 05:33:01 PM PDT 24
Peak memory 943648 kb
Host smart-127915cc-1375-497f-a389-506ce8f4756a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604008783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.604008783
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3608062983
Short name T229
Test name
Test status
Simulation time 609082577 ps
CPU time 10.07 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:15 PM PDT 24
Peak memory 205480 kb
Host smart-c8fa8dad-901d-4e3f-83cf-55628cd48d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608062983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3608062983
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_override.1382765169
Short name T1224
Test name
Test status
Simulation time 16727662 ps
CPU time 0.72 seconds
Started Jul 18 05:31:53 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 205196 kb
Host smart-60dd9a25-1b80-46a0-8c00-2aed5c93af3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382765169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1382765169
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.235351875
Short name T1297
Test name
Test status
Simulation time 22860751617 ps
CPU time 21.06 seconds
Started Jul 18 05:31:48 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 332924 kb
Host smart-76be87db-7cb8-4f05-8803-2fbfb5a878e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235351875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.235351875
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.1000074150
Short name T445
Test name
Test status
Simulation time 263021617 ps
CPU time 1.59 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:31:55 PM PDT 24
Peak memory 205400 kb
Host smart-1d543de4-28f8-4fa7-af2b-0f2fb8b0050e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000074150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.1000074150
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2953010554
Short name T306
Test name
Test status
Simulation time 2473613167 ps
CPU time 19.22 seconds
Started Jul 18 05:31:50 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 299156 kb
Host smart-a9aca6de-989d-44bf-9bf1-20095cc84ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953010554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2953010554
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.3130248944
Short name T31
Test name
Test status
Simulation time 49392012822 ps
CPU time 874.21 seconds
Started Jul 18 05:31:41 PM PDT 24
Finished Jul 18 05:46:20 PM PDT 24
Peak memory 2028144 kb
Host smart-87122924-3672-410b-9975-b3457bfa32b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130248944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.3130248944
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1793555276
Short name T980
Test name
Test status
Simulation time 1412892268 ps
CPU time 11.38 seconds
Started Jul 18 05:31:53 PM PDT 24
Finished Jul 18 05:32:08 PM PDT 24
Peak memory 221492 kb
Host smart-db222ff4-e19e-450c-82a2-aab54197accb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793555276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1793555276
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3381863082
Short name T292
Test name
Test status
Simulation time 4175145005 ps
CPU time 5.09 seconds
Started Jul 18 05:31:56 PM PDT 24
Finished Jul 18 05:32:03 PM PDT 24
Peak memory 218612 kb
Host smart-e1c2fb5e-ba3c-411b-9727-863b70e3a768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381863082 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3381863082
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.658264511
Short name T1459
Test name
Test status
Simulation time 488799628 ps
CPU time 1.91 seconds
Started Jul 18 05:31:45 PM PDT 24
Finished Jul 18 05:31:51 PM PDT 24
Peak memory 205880 kb
Host smart-7483142c-0e9c-4847-bf72-82fe04500d82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658264511 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.658264511
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2604883440
Short name T7
Test name
Test status
Simulation time 440220481 ps
CPU time 1.6 seconds
Started Jul 18 05:31:44 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 212496 kb
Host smart-4d5f44da-6674-47ef-a14c-7f39dc51a33f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604883440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2604883440
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.2054435853
Short name T1129
Test name
Test status
Simulation time 1235914986 ps
CPU time 3.04 seconds
Started Jul 18 05:31:55 PM PDT 24
Finished Jul 18 05:32:00 PM PDT 24
Peak memory 205588 kb
Host smart-22d6c534-2786-47b1-a697-943f903b54e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054435853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.2054435853
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.2794426135
Short name T969
Test name
Test status
Simulation time 507602564 ps
CPU time 1.13 seconds
Started Jul 18 05:31:56 PM PDT 24
Finished Jul 18 05:31:59 PM PDT 24
Peak memory 205460 kb
Host smart-283917e0-36a4-44f8-b184-83ac71d932b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794426135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.2794426135
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3743820537
Short name T133
Test name
Test status
Simulation time 738195159 ps
CPU time 2.67 seconds
Started Jul 18 05:31:57 PM PDT 24
Finished Jul 18 05:32:01 PM PDT 24
Peak memory 213880 kb
Host smart-6e1a112d-0bae-42f2-b0ad-96f879f7a437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743820537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3743820537
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1571774390
Short name T509
Test name
Test status
Simulation time 651529126 ps
CPU time 4.04 seconds
Started Jul 18 05:31:51 PM PDT 24
Finished Jul 18 05:31:59 PM PDT 24
Peak memory 215348 kb
Host smart-260fcd19-d9da-4b4e-96b7-242bc6709dd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571774390 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1571774390
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3366965819
Short name T978
Test name
Test status
Simulation time 7554165380 ps
CPU time 4.68 seconds
Started Jul 18 05:31:51 PM PDT 24
Finished Jul 18 05:32:00 PM PDT 24
Peak memory 205036 kb
Host smart-709f431b-351e-481e-bcec-7781c6e15319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366965819 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3366965819
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.981108519
Short name T1218
Test name
Test status
Simulation time 474874556 ps
CPU time 2.58 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:08 PM PDT 24
Peak memory 213788 kb
Host smart-c2f333d6-e07e-4dd9-bb02-c92d7c48da1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981108519 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_nack_acqfull.981108519
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.429103434
Short name T615
Test name
Test status
Simulation time 1013516935 ps
CPU time 2.37 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:15 PM PDT 24
Peak memory 205376 kb
Host smart-8aaae630-8688-434c-83e4-22e36b022aaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429103434 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.429103434
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_txstretch.2964052445
Short name T157
Test name
Test status
Simulation time 148141624 ps
CPU time 1.66 seconds
Started Jul 18 05:31:57 PM PDT 24
Finished Jul 18 05:32:00 PM PDT 24
Peak memory 222428 kb
Host smart-5641a16e-2bb7-4261-950e-5f69c602dfcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964052445 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_nack_txstretch.2964052445
Directory /workspace/44.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/44.i2c_target_perf.1535768436
Short name T1426
Test name
Test status
Simulation time 1414449550 ps
CPU time 3.92 seconds
Started Jul 18 05:31:43 PM PDT 24
Finished Jul 18 05:31:51 PM PDT 24
Peak memory 218892 kb
Host smart-72cc5583-10ae-4a00-bf33-207075df01e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535768436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.1535768436
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.3415546597
Short name T521
Test name
Test status
Simulation time 614090876 ps
CPU time 2.21 seconds
Started Jul 18 05:31:58 PM PDT 24
Finished Jul 18 05:32:02 PM PDT 24
Peak memory 205396 kb
Host smart-194c5157-4dc7-464c-b02f-81c1471c9602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415546597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_smbus_maxlen.3415546597
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3462109075
Short name T1722
Test name
Test status
Simulation time 2309837666 ps
CPU time 12.14 seconds
Started Jul 18 05:31:49 PM PDT 24
Finished Jul 18 05:32:05 PM PDT 24
Peak memory 213784 kb
Host smart-0c2af6df-35ff-4c80-b36a-84279519fa2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462109075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3462109075
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.2671675355
Short name T356
Test name
Test status
Simulation time 30498123054 ps
CPU time 616.53 seconds
Started Jul 18 05:31:57 PM PDT 24
Finished Jul 18 05:42:16 PM PDT 24
Peak memory 4031536 kb
Host smart-e1474062-0a87-4830-bbcf-1bd7ef3e1d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671675355 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_stress_all.2671675355
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3227908686
Short name T1127
Test name
Test status
Simulation time 2902305745 ps
CPU time 65.29 seconds
Started Jul 18 05:31:51 PM PDT 24
Finished Jul 18 05:33:00 PM PDT 24
Peak memory 217804 kb
Host smart-a05e840d-7de1-4418-bda6-c2330d41385a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227908686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3227908686
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.687476286
Short name T120
Test name
Test status
Simulation time 34681220002 ps
CPU time 389.81 seconds
Started Jul 18 05:31:51 PM PDT 24
Finished Jul 18 05:38:25 PM PDT 24
Peak memory 3696028 kb
Host smart-aa9d9804-8f03-41b6-b7fc-cc322c4e5444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687476286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.687476286
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3346157235
Short name T1416
Test name
Test status
Simulation time 4244614210 ps
CPU time 96.55 seconds
Started Jul 18 05:31:46 PM PDT 24
Finished Jul 18 05:33:27 PM PDT 24
Peak memory 1152228 kb
Host smart-0f99829b-c7b7-4748-9413-baccfd159c86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346157235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3346157235
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2545359099
Short name T341
Test name
Test status
Simulation time 1133942923 ps
CPU time 6.65 seconds
Started Jul 18 05:31:53 PM PDT 24
Finished Jul 18 05:32:03 PM PDT 24
Peak memory 213800 kb
Host smart-c74c5519-325a-4d6d-93e5-298a492db38e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545359099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2545359099
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.590130396
Short name T1259
Test name
Test status
Simulation time 74000543 ps
CPU time 1.36 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 205564 kb
Host smart-06f4f6ec-9fba-4553-ba24-f130b40b1966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590130396 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.590130396
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.4164659574
Short name T1046
Test name
Test status
Simulation time 48389277 ps
CPU time 0.67 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:05 PM PDT 24
Peak memory 204732 kb
Host smart-442b5c04-c54d-4f83-8afc-5c709e721834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164659574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.4164659574
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2592468338
Short name T28
Test name
Test status
Simulation time 782950219 ps
CPU time 1.89 seconds
Started Jul 18 05:32:11 PM PDT 24
Finished Jul 18 05:32:15 PM PDT 24
Peak memory 215392 kb
Host smart-a51149a0-675c-4fea-a4e9-a4af688e67ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592468338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2592468338
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3694262983
Short name T765
Test name
Test status
Simulation time 352727136 ps
CPU time 19.09 seconds
Started Jul 18 05:32:07 PM PDT 24
Finished Jul 18 05:32:28 PM PDT 24
Peak memory 282700 kb
Host smart-99b3de06-3839-47cf-ba39-0cfe2abf8210
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694262983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3694262983
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1356873548
Short name T38
Test name
Test status
Simulation time 7066296480 ps
CPU time 233.1 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:36:04 PM PDT 24
Peak memory 704600 kb
Host smart-807ee246-53b8-4847-8159-73febd337243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356873548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1356873548
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.242710476
Short name T949
Test name
Test status
Simulation time 2138934561 ps
CPU time 59.67 seconds
Started Jul 18 05:32:00 PM PDT 24
Finished Jul 18 05:33:01 PM PDT 24
Peak memory 688884 kb
Host smart-6d9c8bef-d9a6-4bc8-a1de-18d0704b4505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242710476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.242710476
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.281656295
Short name T1608
Test name
Test status
Simulation time 646455689 ps
CPU time 1.31 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:07 PM PDT 24
Peak memory 205408 kb
Host smart-2ad76b64-e6e1-4853-874a-083c848f3d44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281656295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.281656295
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3607742642
Short name T1237
Test name
Test status
Simulation time 716968482 ps
CPU time 10.31 seconds
Started Jul 18 05:31:59 PM PDT 24
Finished Jul 18 05:32:11 PM PDT 24
Peak memory 205524 kb
Host smart-97e0ddb1-ad83-40d1-88bc-092d6e066acc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607742642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3607742642
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2365621981
Short name T426
Test name
Test status
Simulation time 5228628220 ps
CPU time 163.43 seconds
Started Jul 18 05:32:02 PM PDT 24
Finished Jul 18 05:34:47 PM PDT 24
Peak memory 1508744 kb
Host smart-bea6b79b-24c9-47a8-8d76-16f9afa471b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365621981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2365621981
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1924527578
Short name T667
Test name
Test status
Simulation time 492393295 ps
CPU time 9.81 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:23 PM PDT 24
Peak memory 205272 kb
Host smart-4c06e577-9308-423a-bdb1-9bb5adaa6b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924527578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1924527578
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2346810975
Short name T11
Test name
Test status
Simulation time 225073354 ps
CPU time 1.19 seconds
Started Jul 18 05:32:08 PM PDT 24
Finished Jul 18 05:32:10 PM PDT 24
Peak memory 213740 kb
Host smart-c3d7a890-33d5-4792-a3ad-05ccb3d405f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346810975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2346810975
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1665914020
Short name T685
Test name
Test status
Simulation time 70462030 ps
CPU time 0.68 seconds
Started Jul 18 05:31:59 PM PDT 24
Finished Jul 18 05:32:01 PM PDT 24
Peak memory 205192 kb
Host smart-97e012fd-73b1-48fd-bfad-9eb0128d8909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665914020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1665914020
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3551187039
Short name T967
Test name
Test status
Simulation time 7049584559 ps
CPU time 104.78 seconds
Started Jul 18 05:31:58 PM PDT 24
Finished Jul 18 05:33:44 PM PDT 24
Peak memory 1067076 kb
Host smart-1a25b6c7-67e4-4b4e-bf95-cdbb6b3c32e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551187039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3551187039
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.1181485232
Short name T1696
Test name
Test status
Simulation time 201488734 ps
CPU time 3.39 seconds
Started Jul 18 05:32:11 PM PDT 24
Finished Jul 18 05:32:17 PM PDT 24
Peak memory 230996 kb
Host smart-06f41dfe-d92e-4306-a7d0-8256ac0e6d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181485232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1181485232
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3848851636
Short name T1216
Test name
Test status
Simulation time 2264850616 ps
CPU time 103.51 seconds
Started Jul 18 05:31:55 PM PDT 24
Finished Jul 18 05:33:40 PM PDT 24
Peak memory 365112 kb
Host smart-41aaf475-b426-481b-b478-8b7b23d090e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848851636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3848851636
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.3113199194
Short name T923
Test name
Test status
Simulation time 3759798510 ps
CPU time 18.23 seconds
Started Jul 18 05:32:08 PM PDT 24
Finished Jul 18 05:32:27 PM PDT 24
Peak memory 220748 kb
Host smart-c210418f-6938-4355-8596-6edf05716f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113199194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3113199194
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.96910514
Short name T391
Test name
Test status
Simulation time 1261274229 ps
CPU time 6.22 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:11 PM PDT 24
Peak memory 215764 kb
Host smart-7a139c41-6cf9-43ad-9200-39c09c581be8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96910514 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.96910514
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3281592713
Short name T1157
Test name
Test status
Simulation time 201824385 ps
CPU time 1.22 seconds
Started Jul 18 05:31:58 PM PDT 24
Finished Jul 18 05:32:00 PM PDT 24
Peak memory 205460 kb
Host smart-c414da70-7f46-4bce-9f85-1ddf81f090d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281592713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3281592713
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1080533261
Short name T1165
Test name
Test status
Simulation time 435196419 ps
CPU time 1.54 seconds
Started Jul 18 05:31:59 PM PDT 24
Finished Jul 18 05:32:02 PM PDT 24
Peak memory 209060 kb
Host smart-496a3442-06f8-431c-aa43-502fc7ab49a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080533261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1080533261
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.1798719728
Short name T770
Test name
Test status
Simulation time 1956701326 ps
CPU time 2.37 seconds
Started Jul 18 05:32:00 PM PDT 24
Finished Jul 18 05:32:04 PM PDT 24
Peak memory 205588 kb
Host smart-0dbf9ddd-9548-4a16-b1f8-b2bb4d8b1acd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798719728 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.1798719728
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.244401219
Short name T976
Test name
Test status
Simulation time 556849685 ps
CPU time 1.37 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:13 PM PDT 24
Peak memory 205456 kb
Host smart-36a30039-bb66-45fe-beab-2c7d3046bb11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244401219 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.244401219
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1552640811
Short name T1658
Test name
Test status
Simulation time 589696806 ps
CPU time 1.42 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:12 PM PDT 24
Peak memory 205616 kb
Host smart-287d3077-49dc-48a6-9994-b5b01e218fee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552640811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1552640811
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.878183133
Short name T362
Test name
Test status
Simulation time 692577352 ps
CPU time 3.86 seconds
Started Jul 18 05:32:08 PM PDT 24
Finished Jul 18 05:32:13 PM PDT 24
Peak memory 214524 kb
Host smart-42fb79c7-8c2a-4a46-9033-42d49b902ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878183133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_intr_smoke.878183133
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3076896806
Short name T1015
Test name
Test status
Simulation time 20907828113 ps
CPU time 177.82 seconds
Started Jul 18 05:32:00 PM PDT 24
Finished Jul 18 05:34:59 PM PDT 24
Peak memory 2556424 kb
Host smart-3d92426f-da7c-4f15-9f53-292046b58e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076896806 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3076896806
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.1793388572
Short name T957
Test name
Test status
Simulation time 465202210 ps
CPU time 2.69 seconds
Started Jul 18 05:32:11 PM PDT 24
Finished Jul 18 05:32:16 PM PDT 24
Peak memory 213784 kb
Host smart-bab56f7e-1bb3-4a36-b30c-475c3b6e2623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793388572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_nack_acqfull.1793388572
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.1679349253
Short name T1647
Test name
Test status
Simulation time 1660532130 ps
CPU time 2.43 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 205672 kb
Host smart-7af8b327-8d02-40b0-ba6c-0f9624f2cf45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679349253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.1679349253
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.3248449759
Short name T890
Test name
Test status
Simulation time 880738843 ps
CPU time 6.48 seconds
Started Jul 18 05:31:59 PM PDT 24
Finished Jul 18 05:32:07 PM PDT 24
Peak memory 221948 kb
Host smart-840f234b-6346-43c8-8d9a-475af54fac7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248449759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.3248449759
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.2695629954
Short name T918
Test name
Test status
Simulation time 430034608 ps
CPU time 2.01 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:15 PM PDT 24
Peak memory 205280 kb
Host smart-74005e51-ceee-47e1-bbd5-058dad6c777d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695629954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_smbus_maxlen.2695629954
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1780058952
Short name T1082
Test name
Test status
Simulation time 1193142689 ps
CPU time 18.16 seconds
Started Jul 18 05:31:59 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 213808 kb
Host smart-0cdd08ad-7445-49df-9a26-2442ef5ee6be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780058952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1780058952
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.899429514
Short name T1734
Test name
Test status
Simulation time 45068772992 ps
CPU time 189.71 seconds
Started Jul 18 05:32:02 PM PDT 24
Finished Jul 18 05:35:13 PM PDT 24
Peak memory 1302060 kb
Host smart-3c97412c-a546-44ab-9b4a-a9a363375f3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899429514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_target_stress_all.899429514
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.444683846
Short name T1199
Test name
Test status
Simulation time 904584465 ps
CPU time 15.73 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:27 PM PDT 24
Peak memory 230092 kb
Host smart-8224328e-5ddc-4c2c-82d3-820b9be10882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444683846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.444683846
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2613247649
Short name T1720
Test name
Test status
Simulation time 44715236207 ps
CPU time 320.78 seconds
Started Jul 18 05:32:07 PM PDT 24
Finished Jul 18 05:37:29 PM PDT 24
Peak memory 3127460 kb
Host smart-f39dcb52-3ae1-4fad-a704-a0a1672f518e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613247649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2613247649
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2173794844
Short name T446
Test name
Test status
Simulation time 1129470534 ps
CPU time 2.1 seconds
Started Jul 18 05:32:04 PM PDT 24
Finished Jul 18 05:32:09 PM PDT 24
Peak memory 213552 kb
Host smart-2520dba0-d924-42bc-b1b0-8e30db7b58ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173794844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2173794844
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2708358762
Short name T1298
Test name
Test status
Simulation time 2790486646 ps
CPU time 6.88 seconds
Started Jul 18 05:31:55 PM PDT 24
Finished Jul 18 05:32:04 PM PDT 24
Peak memory 222040 kb
Host smart-51db47f1-052f-4795-a2a3-39f57e4bf764
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708358762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2708358762
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.2357908597
Short name T1668
Test name
Test status
Simulation time 119227683 ps
CPU time 2.79 seconds
Started Jul 18 05:31:58 PM PDT 24
Finished Jul 18 05:32:03 PM PDT 24
Peak memory 205604 kb
Host smart-bafe225e-634a-4375-b1da-a9bb44e83c2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357908597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.2357908597
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.320733281
Short name T1372
Test name
Test status
Simulation time 37886058 ps
CPU time 0.64 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:07 PM PDT 24
Peak memory 205264 kb
Host smart-2f86fced-347b-41e8-9f80-955ede6dd873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320733281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.320733281
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1033334329
Short name T710
Test name
Test status
Simulation time 548806691 ps
CPU time 2.26 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:32:20 PM PDT 24
Peak memory 220976 kb
Host smart-b947bcac-21e2-4b4e-8664-ecae10be95ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033334329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1033334329
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3045061092
Short name T653
Test name
Test status
Simulation time 1437298813 ps
CPU time 8.52 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:21 PM PDT 24
Peak memory 280020 kb
Host smart-a1011d14-4f52-4320-be36-a96862eb4bf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045061092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3045061092
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.2683948457
Short name T379
Test name
Test status
Simulation time 35432359281 ps
CPU time 105.95 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:34:03 PM PDT 24
Peak memory 456000 kb
Host smart-10fb5154-c0eb-4ea2-8e06-c8624ddb84a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683948457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2683948457
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1630614858
Short name T659
Test name
Test status
Simulation time 3554151738 ps
CPU time 122.82 seconds
Started Jul 18 05:32:01 PM PDT 24
Finished Jul 18 05:34:04 PM PDT 24
Peak memory 637368 kb
Host smart-3cfafd8e-c2dc-49ca-8401-ec956150db57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630614858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1630614858
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2137870817
Short name T1467
Test name
Test status
Simulation time 156955951 ps
CPU time 3.38 seconds
Started Jul 18 05:32:01 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 205540 kb
Host smart-fc9814fe-5f39-4216-a180-4cc59c96434f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137870817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2137870817
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1226264976
Short name T99
Test name
Test status
Simulation time 14280935203 ps
CPU time 69.69 seconds
Started Jul 18 05:32:11 PM PDT 24
Finished Jul 18 05:33:23 PM PDT 24
Peak memory 892752 kb
Host smart-98277d82-018f-495d-82d0-f657cd1521bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226264976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1226264976
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1914823724
Short name T2
Test name
Test status
Simulation time 331957852 ps
CPU time 4.49 seconds
Started Jul 18 05:31:59 PM PDT 24
Finished Jul 18 05:32:05 PM PDT 24
Peak memory 205588 kb
Host smart-5922e167-52a4-4d0e-8b41-afe8e10ca1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914823724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1914823724
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.1403686428
Short name T1602
Test name
Test status
Simulation time 87138563 ps
CPU time 1.33 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 205544 kb
Host smart-ea206e7f-8d15-44c6-a2ed-69587b582d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403686428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.1403686428
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3413693439
Short name T757
Test name
Test status
Simulation time 27967900 ps
CPU time 0.75 seconds
Started Jul 18 05:32:01 PM PDT 24
Finished Jul 18 05:32:03 PM PDT 24
Peak memory 205172 kb
Host smart-9380b47e-6f14-43f6-81c7-5c3c6dbd3b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413693439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3413693439
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.847679659
Short name T738
Test name
Test status
Simulation time 29165163574 ps
CPU time 1074.22 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:50:14 PM PDT 24
Peak memory 205632 kb
Host smart-1eeb3980-f67f-4017-bde0-90e120555fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847679659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.847679659
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.701361327
Short name T1354
Test name
Test status
Simulation time 652139286 ps
CPU time 10.51 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 253868 kb
Host smart-74806f88-5b7a-48cf-b3db-45c198a2a83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701361327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.701361327
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3019574526
Short name T1202
Test name
Test status
Simulation time 2124144994 ps
CPU time 34.71 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:39 PM PDT 24
Peak memory 412668 kb
Host smart-11876f63-fb56-452f-855d-3651023155a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019574526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3019574526
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2086514202
Short name T160
Test name
Test status
Simulation time 4353156976 ps
CPU time 16.04 seconds
Started Jul 18 05:32:08 PM PDT 24
Finished Jul 18 05:32:25 PM PDT 24
Peak memory 229420 kb
Host smart-a3468b90-d345-4d3e-b5cf-ea6ec9bc4f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086514202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2086514202
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.245140473
Short name T1388
Test name
Test status
Simulation time 4360078984 ps
CPU time 5.17 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 218560 kb
Host smart-282b7eed-72d5-4c31-a66b-c893d4072693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245140473 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.245140473
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2764348893
Short name T787
Test name
Test status
Simulation time 477972327 ps
CPU time 1.11 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 205416 kb
Host smart-87ce51b9-0162-440f-8016-18289cf15a1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764348893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2764348893
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2298064449
Short name T1484
Test name
Test status
Simulation time 580533002 ps
CPU time 1.26 seconds
Started Jul 18 05:32:08 PM PDT 24
Finished Jul 18 05:32:11 PM PDT 24
Peak memory 209596 kb
Host smart-65f66cbc-c96b-4560-93d8-c8c43bbb05a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298064449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2298064449
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.493612287
Short name T733
Test name
Test status
Simulation time 797829051 ps
CPU time 2.19 seconds
Started Jul 18 05:32:08 PM PDT 24
Finished Jul 18 05:32:12 PM PDT 24
Peak memory 205436 kb
Host smart-04f63534-3749-493f-897b-00271c711563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493612287 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.493612287
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.2614156205
Short name T1491
Test name
Test status
Simulation time 630912590 ps
CPU time 1.27 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:21 PM PDT 24
Peak memory 205436 kb
Host smart-b03cdec7-0c3d-44a1-b240-c23241b6e0f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614156205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.2614156205
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1424772346
Short name T1075
Test name
Test status
Simulation time 2546476139 ps
CPU time 2.22 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:32:20 PM PDT 24
Peak memory 213880 kb
Host smart-8adef930-b657-4e76-b811-ff884efbcb51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424772346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1424772346
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3116186132
Short name T1282
Test name
Test status
Simulation time 1162587971 ps
CPU time 6.46 seconds
Started Jul 18 05:31:58 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 217792 kb
Host smart-8b00e1db-5b71-4746-9b16-29f700b5f39e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116186132 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3116186132
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2386675721
Short name T1164
Test name
Test status
Simulation time 3203867820 ps
CPU time 7.53 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:19 PM PDT 24
Peak memory 205704 kb
Host smart-ba58c5e8-c3e1-47b9-ade8-6eb83ffa4177
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386675721 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2386675721
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.479230322
Short name T50
Test name
Test status
Simulation time 827229365 ps
CPU time 2.74 seconds
Started Jul 18 05:32:02 PM PDT 24
Finished Jul 18 05:32:07 PM PDT 24
Peak memory 213852 kb
Host smart-3d1b067e-a901-4805-b242-5408d88c6e77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479230322 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_nack_acqfull.479230322
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.1460586433
Short name T144
Test name
Test status
Simulation time 366829173 ps
CPU time 2.45 seconds
Started Jul 18 05:31:58 PM PDT 24
Finished Jul 18 05:32:02 PM PDT 24
Peak memory 205644 kb
Host smart-0955a847-7191-4bad-9b37-c525b1a13a32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460586433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.1460586433
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_txstretch.77213638
Short name T806
Test name
Test status
Simulation time 153236941 ps
CPU time 1.65 seconds
Started Jul 18 05:32:08 PM PDT 24
Finished Jul 18 05:32:10 PM PDT 24
Peak memory 222364 kb
Host smart-89510cb0-4b74-4040-a91a-8f53415c8f9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77213638 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_txstretch.77213638
Directory /workspace/46.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/46.i2c_target_perf.936802096
Short name T126
Test name
Test status
Simulation time 3668420128 ps
CPU time 6.33 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 223000 kb
Host smart-5b11b3fa-85aa-4060-97ec-0a390244978f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936802096 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_perf.936802096
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.1097675615
Short name T1118
Test name
Test status
Simulation time 442993284 ps
CPU time 2.17 seconds
Started Jul 18 05:32:02 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 205440 kb
Host smart-76299bc9-6fbf-490a-b002-935a2dd382e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097675615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_smbus_maxlen.1097675615
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.3675339672
Short name T987
Test name
Test status
Simulation time 913032155 ps
CPU time 13.9 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:26 PM PDT 24
Peak memory 213860 kb
Host smart-0123f644-a04a-4516-b1d4-3d96e16bd46b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675339672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.3675339672
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.3846478199
Short name T271
Test name
Test status
Simulation time 55819003115 ps
CPU time 1563.84 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:58:17 PM PDT 24
Peak memory 5943200 kb
Host smart-b4273209-f04c-46e6-a504-a7ffa61c2f3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846478199 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.3846478199
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.2137171844
Short name T998
Test name
Test status
Simulation time 1509665311 ps
CPU time 5.95 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 205560 kb
Host smart-60dcd95e-fe88-47cf-8949-b2ebbea18611
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137171844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.2137171844
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.4174283385
Short name T1445
Test name
Test status
Simulation time 31219637513 ps
CPU time 40.29 seconds
Started Jul 18 05:32:36 PM PDT 24
Finished Jul 18 05:33:17 PM PDT 24
Peak memory 761704 kb
Host smart-bcc6ca29-1897-44b0-be04-321a05e2dfd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174283385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.4174283385
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2758676521
Short name T513
Test name
Test status
Simulation time 1224425195 ps
CPU time 4.38 seconds
Started Jul 18 05:32:14 PM PDT 24
Finished Jul 18 05:32:20 PM PDT 24
Peak memory 249392 kb
Host smart-8769239e-ab47-4ab0-8590-be46642d28ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758676521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2758676521
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2883818745
Short name T1258
Test name
Test status
Simulation time 4990214811 ps
CPU time 6.54 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:19 PM PDT 24
Peak memory 213964 kb
Host smart-dd996254-6c0b-440d-bcfa-aa523d596c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883818745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2883818745
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.2781953193
Short name T583
Test name
Test status
Simulation time 219178311 ps
CPU time 3.6 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:23 PM PDT 24
Peak memory 205604 kb
Host smart-0f8974d8-0c23-4685-b162-849c48959b84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781953193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.2781953193
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.556947144
Short name T994
Test name
Test status
Simulation time 22898298 ps
CPU time 0.64 seconds
Started Jul 18 05:32:18 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 204712 kb
Host smart-5325e1ce-8742-4b7b-8992-a6d251aad60a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556947144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.556947144
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.77329686
Short name T1382
Test name
Test status
Simulation time 53532379 ps
CPU time 1.52 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:20 PM PDT 24
Peak memory 213844 kb
Host smart-a8559ad9-a05c-4282-bad9-7850f3440e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77329686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.77329686
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.217009976
Short name T1730
Test name
Test status
Simulation time 944028986 ps
CPU time 5.14 seconds
Started Jul 18 05:31:59 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 265168 kb
Host smart-3f0f0650-6cae-44e9-bf50-5e9ff6dbf365
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217009976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.217009976
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2358198194
Short name T1244
Test name
Test status
Simulation time 33481819140 ps
CPU time 62.35 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:33:07 PM PDT 24
Peak memory 365816 kb
Host smart-fc3c691e-a589-4550-a671-f13ed20a10c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358198194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2358198194
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1291168951
Short name T1112
Test name
Test status
Simulation time 9868704688 ps
CPU time 42.96 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:56 PM PDT 24
Peak memory 598960 kb
Host smart-8128cb35-5c16-4139-af70-62ae842facf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291168951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1291168951
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3632399424
Short name T353
Test name
Test status
Simulation time 161331030 ps
CPU time 1.21 seconds
Started Jul 18 05:31:58 PM PDT 24
Finished Jul 18 05:32:01 PM PDT 24
Peak memory 205244 kb
Host smart-c8bb7576-9d39-4af5-bbdd-6e2e03bf95dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632399424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3632399424
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3296560825
Short name T343
Test name
Test status
Simulation time 732009233 ps
CPU time 4.51 seconds
Started Jul 18 05:32:01 PM PDT 24
Finished Jul 18 05:32:06 PM PDT 24
Peak memory 238072 kb
Host smart-821935eb-a0b0-4acc-8133-43ade6117384
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296560825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3296560825
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.3762759801
Short name T672
Test name
Test status
Simulation time 17273109465 ps
CPU time 176.52 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:35:09 PM PDT 24
Peak memory 894320 kb
Host smart-a378aa70-0948-47fc-a7ed-1d4f9aa87414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762759801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.3762759801
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.4121412318
Short name T1546
Test name
Test status
Simulation time 1226469863 ps
CPU time 20.48 seconds
Started Jul 18 05:32:15 PM PDT 24
Finished Jul 18 05:32:36 PM PDT 24
Peak memory 205520 kb
Host smart-f27d2cae-44fc-49a9-9f9c-b581087ff4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121412318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.4121412318
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.2953754372
Short name T1413
Test name
Test status
Simulation time 82961683 ps
CPU time 0.67 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:05 PM PDT 24
Peak memory 205244 kb
Host smart-3042a080-3fd3-4fa3-a769-ecb56e99420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953754372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2953754372
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3177643418
Short name T807
Test name
Test status
Simulation time 7098529830 ps
CPU time 281.54 seconds
Started Jul 18 05:32:11 PM PDT 24
Finished Jul 18 05:36:55 PM PDT 24
Peak memory 223688 kb
Host smart-31178357-68e3-4bef-8ff6-16949f522f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177643418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3177643418
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.1359843543
Short name T1490
Test name
Test status
Simulation time 279059202 ps
CPU time 1.87 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:21 PM PDT 24
Peak memory 217052 kb
Host smart-fbeab5f7-9d63-4c86-b2f2-d20e36ac6d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359843543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.1359843543
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1766131263
Short name T926
Test name
Test status
Simulation time 5657507468 ps
CPU time 25.75 seconds
Started Jul 18 05:32:11 PM PDT 24
Finished Jul 18 05:32:39 PM PDT 24
Peak memory 299196 kb
Host smart-ebcbfcc0-c544-446d-ae44-6156f3966112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766131263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1766131263
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.795076623
Short name T41
Test name
Test status
Simulation time 1762063087 ps
CPU time 7.55 seconds
Started Jul 18 05:32:02 PM PDT 24
Finished Jul 18 05:32:11 PM PDT 24
Peak memory 220968 kb
Host smart-f28c9173-847b-4371-b462-7fc4e50942d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795076623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.795076623
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2943013515
Short name T1415
Test name
Test status
Simulation time 1256224659 ps
CPU time 6 seconds
Started Jul 18 05:32:15 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 209756 kb
Host smart-8a57455a-cf49-4f7b-96ef-1461901238d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943013515 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2943013515
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1923300547
Short name T1555
Test name
Test status
Simulation time 1099553241 ps
CPU time 1.16 seconds
Started Jul 18 05:32:32 PM PDT 24
Finished Jul 18 05:32:33 PM PDT 24
Peak memory 205624 kb
Host smart-f133218b-7bd6-4c96-b249-90588ccf428e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923300547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1923300547
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.3494163067
Short name T1270
Test name
Test status
Simulation time 159082947 ps
CPU time 1.53 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 205404 kb
Host smart-09763f29-b91b-4883-99c4-ee01647d8f88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494163067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.3494163067
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.145028387
Short name T1245
Test name
Test status
Simulation time 356289214 ps
CPU time 1.54 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:15 PM PDT 24
Peak memory 205412 kb
Host smart-7c9285d2-f593-4960-a44b-a9cb830973b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145028387 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.145028387
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.2639215486
Short name T866
Test name
Test status
Simulation time 440656435 ps
CPU time 1.68 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 213796 kb
Host smart-f97abb3b-296a-4132-a5ed-45bdbe55c759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639215486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.2639215486
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2421330002
Short name T64
Test name
Test status
Simulation time 3799914356 ps
CPU time 4.46 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:10 PM PDT 24
Peak memory 214996 kb
Host smart-8e3b796a-f0c7-41de-8c03-8cd05e1e3d85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421330002 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2421330002
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2091346785
Short name T822
Test name
Test status
Simulation time 15355744554 ps
CPU time 23.22 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 05:32:34 PM PDT 24
Peak memory 528264 kb
Host smart-dee4f135-f7ee-4ef1-a291-461387df705d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091346785 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2091346785
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.362022152
Short name T904
Test name
Test status
Simulation time 3285426899 ps
CPU time 2.5 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:21 PM PDT 24
Peak memory 214160 kb
Host smart-96a6f632-6a1d-4cd1-8bd9-32178ef43257
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362022152 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_nack_acqfull.362022152
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.3792505316
Short name T382
Test name
Test status
Simulation time 1789550075 ps
CPU time 2.38 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:32:25 PM PDT 24
Peak memory 205728 kb
Host smart-74828100-c088-4284-ad1b-36e1537dd8ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792505316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.3792505316
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_txstretch.3775509425
Short name T752
Test name
Test status
Simulation time 267424518 ps
CPU time 1.5 seconds
Started Jul 18 05:32:15 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 222448 kb
Host smart-7acd49c0-5873-490c-a678-55d9beecc3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775509425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_nack_txstretch.3775509425
Directory /workspace/47.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/47.i2c_target_perf.2132812038
Short name T1502
Test name
Test status
Simulation time 3608571662 ps
CPU time 5.1 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 223272 kb
Host smart-20a3f3b5-0c6b-458f-8253-2828fad229a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132812038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.2132812038
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.1569417759
Short name T1288
Test name
Test status
Simulation time 438485647 ps
CPU time 2.12 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:14 PM PDT 24
Peak memory 205184 kb
Host smart-ce7af364-e2b5-4101-94ac-8e571bee983c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569417759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_smbus_maxlen.1569417759
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.4036131794
Short name T1140
Test name
Test status
Simulation time 6873104148 ps
CPU time 35.9 seconds
Started Jul 18 05:32:04 PM PDT 24
Finished Jul 18 05:32:43 PM PDT 24
Peak memory 213900 kb
Host smart-6cdcd1ec-1db9-425a-ad82-bc903372dbd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036131794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.4036131794
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.2935350712
Short name T514
Test name
Test status
Simulation time 52783118987 ps
CPU time 2495.8 seconds
Started Jul 18 05:32:09 PM PDT 24
Finished Jul 18 06:13:48 PM PDT 24
Peak memory 10093560 kb
Host smart-02e4be15-1c96-43a0-8251-70015c1e9112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935350712 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.2935350712
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2107369392
Short name T162
Test name
Test status
Simulation time 766004102 ps
CPU time 2.75 seconds
Started Jul 18 05:32:03 PM PDT 24
Finished Jul 18 05:32:07 PM PDT 24
Peak memory 205520 kb
Host smart-605ee71a-be07-48aa-8d8e-3bee99208347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107369392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2107369392
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.691835303
Short name T1614
Test name
Test status
Simulation time 22831952486 ps
CPU time 23.41 seconds
Started Jul 18 05:32:10 PM PDT 24
Finished Jul 18 05:32:36 PM PDT 24
Peak memory 377800 kb
Host smart-7893a13a-bed9-4903-85b6-78435c63863a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691835303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.691835303
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.60866877
Short name T339
Test name
Test status
Simulation time 4114531252 ps
CPU time 23.62 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:32:42 PM PDT 24
Peak memory 544720 kb
Host smart-c08111d3-9b22-40c3-b1e2-723941fe47f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60866877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_stretch.60866877
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2092182802
Short name T411
Test name
Test status
Simulation time 4752319381 ps
CPU time 6.85 seconds
Started Jul 18 05:32:02 PM PDT 24
Finished Jul 18 05:32:10 PM PDT 24
Peak memory 213980 kb
Host smart-32bc63ec-1cb5-47d9-bc74-6987271a7922
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092182802 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2092182802
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.1154454407
Short name T767
Test name
Test status
Simulation time 147042800 ps
CPU time 2.25 seconds
Started Jul 18 05:32:14 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 205604 kb
Host smart-6c8464c7-bda6-4ddd-9d9d-cfe9cc084d52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154454407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.1154454407
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1352013484
Short name T1431
Test name
Test status
Simulation time 105347443 ps
CPU time 0.63 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:32:26 PM PDT 24
Peak memory 204720 kb
Host smart-04e9eae8-731b-466e-bd3a-3b97a43b8fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352013484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1352013484
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1074797099
Short name T645
Test name
Test status
Simulation time 1127493078 ps
CPU time 3.32 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:32:29 PM PDT 24
Peak memory 213732 kb
Host smart-3b9fa441-3879-428f-a693-bb7aeea57ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074797099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1074797099
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2211024523
Short name T437
Test name
Test status
Simulation time 637807863 ps
CPU time 5.5 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:32:23 PM PDT 24
Peak memory 271016 kb
Host smart-09863a48-25dc-495b-93d9-2666c225e543
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211024523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2211024523
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3040235747
Short name T945
Test name
Test status
Simulation time 3630600791 ps
CPU time 89.44 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:33:49 PM PDT 24
Peak memory 513620 kb
Host smart-cf93d60a-9a6a-49b8-8c4b-fd72646a0262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040235747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3040235747
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.759123735
Short name T1401
Test name
Test status
Simulation time 16090486277 ps
CPU time 211.9 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:35:57 PM PDT 24
Peak memory 847248 kb
Host smart-3baa8625-ebb3-4a8c-a28c-3d874e9edc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759123735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.759123735
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.413472387
Short name T1518
Test name
Test status
Simulation time 355530527 ps
CPU time 0.94 seconds
Started Jul 18 05:32:20 PM PDT 24
Finished Jul 18 05:32:24 PM PDT 24
Peak memory 205268 kb
Host smart-16140f2f-e6ae-49c6-9a5c-f81d86bb5ac4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413472387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.413472387
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.4137195051
Short name T844
Test name
Test status
Simulation time 279207263 ps
CPU time 13.45 seconds
Started Jul 18 05:32:24 PM PDT 24
Finished Jul 18 05:32:40 PM PDT 24
Peak memory 205536 kb
Host smart-3ab0d83c-e6ee-4d9d-98dd-a7bbb60dd304
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137195051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.4137195051
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1444290040
Short name T153
Test name
Test status
Simulation time 88695950663 ps
CPU time 181.33 seconds
Started Jul 18 05:41:53 PM PDT 24
Finished Jul 18 05:45:07 PM PDT 24
Peak memory 1565316 kb
Host smart-7e41c911-25e4-46cb-9c90-442ed7a960ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444290040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1444290040
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2022596394
Short name T1630
Test name
Test status
Simulation time 286072101 ps
CPU time 2.35 seconds
Started Jul 18 05:32:24 PM PDT 24
Finished Jul 18 05:32:29 PM PDT 24
Peak memory 213680 kb
Host smart-70ec3620-e4ef-45ca-a371-c379c9e75775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022596394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2022596394
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.1491120707
Short name T1574
Test name
Test status
Simulation time 58022443 ps
CPU time 0.73 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 205260 kb
Host smart-5db9445d-e42a-4fa3-8b00-461c6d89ee88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491120707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.1491120707
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1513851185
Short name T36
Test name
Test status
Simulation time 784974762 ps
CPU time 36.22 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:33:01 PM PDT 24
Peak memory 313248 kb
Host smart-96af8671-9c71-485b-968f-a17c8a767170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513851185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1513851185
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.416608425
Short name T286
Test name
Test status
Simulation time 294888742 ps
CPU time 1.54 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:32:23 PM PDT 24
Peak memory 205432 kb
Host smart-c73451c4-992e-44ca-88d5-dba8271dd82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416608425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.416608425
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.4097135454
Short name T935
Test name
Test status
Simulation time 4311294664 ps
CPU time 20.53 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:32:43 PM PDT 24
Peak memory 287620 kb
Host smart-79093828-6757-4f5d-b0f1-2fa9e76d67cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097135454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.4097135454
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3607502492
Short name T316
Test name
Test status
Simulation time 13501300959 ps
CPU time 15.75 seconds
Started Jul 18 05:32:18 PM PDT 24
Finished Jul 18 05:32:37 PM PDT 24
Peak memory 221472 kb
Host smart-86a60dd9-21de-4efb-88f5-c1704a5af0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607502492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3607502492
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2656635563
Short name T58
Test name
Test status
Simulation time 3889728194 ps
CPU time 6.3 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:32:32 PM PDT 24
Peak memory 218056 kb
Host smart-68c6be1a-7785-484b-839d-b1ea2d7bab5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656635563 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2656635563
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.831416305
Short name T1101
Test name
Test status
Simulation time 186343844 ps
CPU time 1.3 seconds
Started Jul 18 05:32:18 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 205404 kb
Host smart-6f728690-bf70-4d81-9482-aa2b5943898a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831416305 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.831416305
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2693057577
Short name T1398
Test name
Test status
Simulation time 249923464 ps
CPU time 1.47 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:32:27 PM PDT 24
Peak memory 205644 kb
Host smart-30b6d2a1-5a71-4f28-8e89-f37e5205b82e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693057577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2693057577
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.1628402666
Short name T1758
Test name
Test status
Simulation time 3937170519 ps
CPU time 3.18 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:32:21 PM PDT 24
Peak memory 205700 kb
Host smart-5f8a336a-4bab-44c2-a453-5c066871467f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628402666 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.1628402666
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.2361703882
Short name T970
Test name
Test status
Simulation time 105274373 ps
CPU time 1.36 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 205436 kb
Host smart-e9e6333d-1ad9-4515-ba1f-755bd9cf6c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361703882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.2361703882
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.4250001806
Short name T1565
Test name
Test status
Simulation time 488879929 ps
CPU time 1.47 seconds
Started Jul 18 05:32:20 PM PDT 24
Finished Jul 18 05:32:25 PM PDT 24
Peak memory 205608 kb
Host smart-7740c37f-0377-44d1-b4ba-eba99dccb4b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250001806 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.4250001806
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.443327759
Short name T1435
Test name
Test status
Simulation time 1466334050 ps
CPU time 7.03 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:27 PM PDT 24
Peak memory 222028 kb
Host smart-1a29983f-f048-4a43-9d4c-0c416812d8ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443327759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.443327759
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2123861256
Short name T1312
Test name
Test status
Simulation time 10210091312 ps
CPU time 6.23 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:32:32 PM PDT 24
Peak memory 205720 kb
Host smart-66335fe9-7f97-4f61-ae3c-13bd8175888b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123861256 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2123861256
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.999775927
Short name T145
Test name
Test status
Simulation time 6120218394 ps
CPU time 2.78 seconds
Started Jul 18 05:32:20 PM PDT 24
Finished Jul 18 05:32:26 PM PDT 24
Peak memory 213964 kb
Host smart-1e774019-8a19-4371-835f-550170b47ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999775927 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_nack_acqfull.999775927
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.2982153652
Short name T567
Test name
Test status
Simulation time 494672893 ps
CPU time 2.79 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:22 PM PDT 24
Peak memory 205628 kb
Host smart-7b0a46ff-6a2b-405f-81c4-6f163f92a566
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982153652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.2982153652
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.3667663877
Short name T673
Test name
Test status
Simulation time 1266012066 ps
CPU time 5.46 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:32:28 PM PDT 24
Peak memory 220472 kb
Host smart-c6ed92ce-d83a-49b8-870c-9d9845e5094c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667663877 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.3667663877
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.82067296
Short name T605
Test name
Test status
Simulation time 740867563 ps
CPU time 2.35 seconds
Started Jul 18 05:32:20 PM PDT 24
Finished Jul 18 05:32:25 PM PDT 24
Peak memory 205392 kb
Host smart-6b284d3a-789a-4a8c-9430-64b7646bba90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82067296 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_target_smbus_maxlen.82067296
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.3178485972
Short name T1622
Test name
Test status
Simulation time 918924913 ps
CPU time 29.62 seconds
Started Jul 18 05:32:34 PM PDT 24
Finished Jul 18 05:33:04 PM PDT 24
Peak memory 213844 kb
Host smart-0da6d0b9-445e-4de1-882a-c0e3229ee739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178485972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.3178485972
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.2920165778
Short name T779
Test name
Test status
Simulation time 43851951420 ps
CPU time 1130.97 seconds
Started Jul 18 05:32:20 PM PDT 24
Finished Jul 18 05:51:14 PM PDT 24
Peak memory 4242020 kb
Host smart-084a199e-11c2-4665-bb0e-ecd42fe0516a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920165778 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.2920165778
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.139265023
Short name T1486
Test name
Test status
Simulation time 5573606367 ps
CPU time 63.02 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:33:25 PM PDT 24
Peak memory 218484 kb
Host smart-d2e8d4cd-cb70-4b48-b8cb-7ac498c6ab93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139265023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.139265023
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3059873808
Short name T318
Test name
Test status
Simulation time 36086317519 ps
CPU time 462.02 seconds
Started Jul 18 05:32:18 PM PDT 24
Finished Jul 18 05:40:03 PM PDT 24
Peak memory 4155368 kb
Host smart-1f436de1-56a3-4e07-af4f-2f5dbafd8a82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059873808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3059873808
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3287998866
Short name T1031
Test name
Test status
Simulation time 824788068 ps
CPU time 2.68 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:32:25 PM PDT 24
Peak memory 221748 kb
Host smart-c4820bd6-5f16-4cae-b90d-0ed13e51e778
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287998866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3287998866
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3627261362
Short name T1257
Test name
Test status
Simulation time 1444107843 ps
CPU time 7.13 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:32:32 PM PDT 24
Peak memory 221992 kb
Host smart-4ee13b1d-bb62-4957-bd5f-e3db0afcd8c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627261362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3627261362
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.484313234
Short name T413
Test name
Test status
Simulation time 452332431 ps
CPU time 6.32 seconds
Started Jul 18 05:32:16 PM PDT 24
Finished Jul 18 05:32:23 PM PDT 24
Peak memory 205584 kb
Host smart-7247d9cc-3712-4e81-a3ca-2b54a2e7651a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484313234 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.484313234
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.3004005915
Short name T1029
Test name
Test status
Simulation time 17526667 ps
CPU time 0.66 seconds
Started Jul 18 05:32:41 PM PDT 24
Finished Jul 18 05:32:43 PM PDT 24
Peak memory 204772 kb
Host smart-5b731087-b8fe-4e45-9b3b-980d1481e006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004005915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3004005915
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3650574801
Short name T881
Test name
Test status
Simulation time 945056240 ps
CPU time 4.49 seconds
Started Jul 18 05:32:18 PM PDT 24
Finished Jul 18 05:32:25 PM PDT 24
Peak memory 249712 kb
Host smart-66944508-18f2-4f46-b1fa-eaf4e3d8564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650574801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3650574801
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2973229404
Short name T910
Test name
Test status
Simulation time 610268214 ps
CPU time 15.86 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:32:38 PM PDT 24
Peak memory 270492 kb
Host smart-5abd6418-0645-44c2-833b-ce7223edd7f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973229404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2973229404
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.465958374
Short name T1167
Test name
Test status
Simulation time 7299645899 ps
CPU time 96.29 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:33:55 PM PDT 24
Peak memory 590312 kb
Host smart-98250785-1ff2-4535-8ea6-71a74901d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465958374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.465958374
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.977705549
Short name T1412
Test name
Test status
Simulation time 2516823305 ps
CPU time 186.23 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:35:32 PM PDT 24
Peak memory 771904 kb
Host smart-590a1e88-456b-4d53-bda0-eff85cf568d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977705549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.977705549
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3941669461
Short name T1757
Test name
Test status
Simulation time 153422631 ps
CPU time 0.87 seconds
Started Jul 18 05:32:20 PM PDT 24
Finished Jul 18 05:32:24 PM PDT 24
Peak memory 205264 kb
Host smart-893c476c-1ad7-4605-97e5-68a5b9c02347
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941669461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3941669461
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2038608312
Short name T1705
Test name
Test status
Simulation time 966580246 ps
CPU time 14.53 seconds
Started Jul 18 05:32:21 PM PDT 24
Finished Jul 18 05:32:39 PM PDT 24
Peak memory 258000 kb
Host smart-58b77863-6881-491c-9160-b9768389717e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038608312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2038608312
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2134392007
Short name T1583
Test name
Test status
Simulation time 31488104431 ps
CPU time 75.63 seconds
Started Jul 18 05:32:21 PM PDT 24
Finished Jul 18 05:33:39 PM PDT 24
Peak memory 876944 kb
Host smart-96c7e266-367b-4770-9626-73be8f552c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134392007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2134392007
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.2074055651
Short name T1114
Test name
Test status
Simulation time 446213409 ps
CPU time 17.55 seconds
Started Jul 18 05:32:45 PM PDT 24
Finished Jul 18 05:33:07 PM PDT 24
Peak memory 205468 kb
Host smart-ba4a20e4-056c-4bf7-8b8d-fd5e379ab800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074055651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.2074055651
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1910285383
Short name T68
Test name
Test status
Simulation time 113000150 ps
CPU time 2.27 seconds
Started Jul 18 05:32:45 PM PDT 24
Finished Jul 18 05:32:52 PM PDT 24
Peak memory 221684 kb
Host smart-39c983af-46d3-4375-9a24-e526a94883ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910285383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1910285383
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3476053411
Short name T1002
Test name
Test status
Simulation time 44187600 ps
CPU time 0.73 seconds
Started Jul 18 05:32:23 PM PDT 24
Finished Jul 18 05:32:26 PM PDT 24
Peak memory 205188 kb
Host smart-04853320-39a6-433e-a8ec-1f0e83570919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476053411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3476053411
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1561469685
Short name T1500
Test name
Test status
Simulation time 2623343496 ps
CPU time 28.14 seconds
Started Jul 18 05:32:17 PM PDT 24
Finished Jul 18 05:32:48 PM PDT 24
Peak memory 225612 kb
Host smart-895366e7-c4de-4dc3-9cec-e91ca5cc4634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561469685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1561469685
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.2812392277
Short name T345
Test name
Test status
Simulation time 77012561 ps
CPU time 1.42 seconds
Started Jul 18 05:32:19 PM PDT 24
Finished Jul 18 05:32:24 PM PDT 24
Peak memory 225836 kb
Host smart-09a18aee-3c9d-4c9f-aba3-5b1e6129e53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812392277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.2812392277
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2432010527
Short name T1592
Test name
Test status
Simulation time 3290929315 ps
CPU time 22 seconds
Started Jul 18 05:32:18 PM PDT 24
Finished Jul 18 05:32:43 PM PDT 24
Peak memory 288540 kb
Host smart-8df54c44-31fe-4480-8496-b0cf20b3c3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432010527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2432010527
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.1733520532
Short name T643
Test name
Test status
Simulation time 1137735270 ps
CPU time 25.53 seconds
Started Jul 18 05:32:20 PM PDT 24
Finished Jul 18 05:32:49 PM PDT 24
Peak memory 213716 kb
Host smart-c3d05722-d727-4571-b0ba-a9bfa1d1b0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733520532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.1733520532
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.4125589224
Short name T885
Test name
Test status
Simulation time 1166793972 ps
CPU time 5.67 seconds
Started Jul 18 05:32:44 PM PDT 24
Finished Jul 18 05:32:54 PM PDT 24
Peak memory 222016 kb
Host smart-710b7bed-956c-4c1f-aa7d-e22401171000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125589224 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.4125589224
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.4265883292
Short name T531
Test name
Test status
Simulation time 1118351570 ps
CPU time 1.36 seconds
Started Jul 18 05:32:42 PM PDT 24
Finished Jul 18 05:32:45 PM PDT 24
Peak memory 205664 kb
Host smart-f6f1e193-e656-4871-b517-e3b61891f050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265883292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.4265883292
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2749945835
Short name T364
Test name
Test status
Simulation time 601449071 ps
CPU time 1.3 seconds
Started Jul 18 05:32:45 PM PDT 24
Finished Jul 18 05:32:52 PM PDT 24
Peak memory 205580 kb
Host smart-51566f17-3766-4fc4-9312-1cdd3af49f81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749945835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2749945835
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.1684869628
Short name T1653
Test name
Test status
Simulation time 1079304652 ps
CPU time 2.96 seconds
Started Jul 18 05:32:43 PM PDT 24
Finished Jul 18 05:32:48 PM PDT 24
Peak memory 205612 kb
Host smart-6b44d4be-8db5-43ef-a876-dde8a94ca92e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684869628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.1684869628
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.3355341184
Short name T724
Test name
Test status
Simulation time 582301741 ps
CPU time 1.28 seconds
Started Jul 18 05:32:43 PM PDT 24
Finished Jul 18 05:32:47 PM PDT 24
Peak memory 205468 kb
Host smart-71cf39a9-27d7-4372-8077-24a4ea329dd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355341184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.3355341184
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.802409196
Short name T65
Test name
Test status
Simulation time 599370701 ps
CPU time 3.95 seconds
Started Jul 18 05:32:43 PM PDT 24
Finished Jul 18 05:32:48 PM PDT 24
Peak memory 213804 kb
Host smart-66cd4f2c-3caf-4fa3-9714-37ac58481ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802409196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.802409196
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.3200762913
Short name T1206
Test name
Test status
Simulation time 14094081775 ps
CPU time 297.81 seconds
Started Jul 18 05:32:42 PM PDT 24
Finished Jul 18 05:37:42 PM PDT 24
Peak memory 3547632 kb
Host smart-bf21c70a-bc64-4d83-a4ee-cf803b5fc0e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200762913 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.3200762913
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.3827151222
Short name T718
Test name
Test status
Simulation time 474215043 ps
CPU time 2.5 seconds
Started Jul 18 05:32:43 PM PDT 24
Finished Jul 18 05:32:47 PM PDT 24
Peak memory 213848 kb
Host smart-846468ed-02cc-4cbf-bfec-e14b11ca827c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827151222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_nack_acqfull.3827151222
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.1162260684
Short name T1381
Test name
Test status
Simulation time 1536497276 ps
CPU time 2.39 seconds
Started Jul 18 05:32:44 PM PDT 24
Finished Jul 18 05:32:51 PM PDT 24
Peak memory 205596 kb
Host smart-d7964dd7-130f-484c-910e-d3e020942ae4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162260684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.1162260684
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_txstretch.3486607286
Short name T1059
Test name
Test status
Simulation time 658202286 ps
CPU time 1.62 seconds
Started Jul 18 05:32:43 PM PDT 24
Finished Jul 18 05:32:46 PM PDT 24
Peak memory 222568 kb
Host smart-e8f78989-7ebf-4e15-86eb-a40168a37c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486607286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_nack_txstretch.3486607286
Directory /workspace/49.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/49.i2c_target_perf.1021127423
Short name T394
Test name
Test status
Simulation time 1091940736 ps
CPU time 4.03 seconds
Started Jul 18 05:32:43 PM PDT 24
Finished Jul 18 05:32:50 PM PDT 24
Peak memory 213888 kb
Host smart-3f27ad7d-9dba-4d30-9149-702e01de856e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021127423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.1021127423
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.3429709210
Short name T1120
Test name
Test status
Simulation time 2157480317 ps
CPU time 2.06 seconds
Started Jul 18 05:32:45 PM PDT 24
Finished Jul 18 05:32:52 PM PDT 24
Peak memory 205484 kb
Host smart-c0929d20-23aa-4c3b-b5a7-3c89666a08e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429709210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.3429709210
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3352155665
Short name T1238
Test name
Test status
Simulation time 898570968 ps
CPU time 12.91 seconds
Started Jul 18 05:32:45 PM PDT 24
Finished Jul 18 05:33:03 PM PDT 24
Peak memory 213876 kb
Host smart-cb49d0f2-090d-40b9-96d5-a7a423ed4fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352155665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3352155665
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.3168965650
Short name T1481
Test name
Test status
Simulation time 24531184809 ps
CPU time 70.19 seconds
Started Jul 18 05:32:43 PM PDT 24
Finished Jul 18 05:33:55 PM PDT 24
Peak memory 907548 kb
Host smart-2b5f513f-c18a-4f66-9332-0a0d1a640612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168965650 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_stress_all.3168965650
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.543375576
Short name T739
Test name
Test status
Simulation time 357834494 ps
CPU time 16.13 seconds
Started Jul 18 05:32:49 PM PDT 24
Finished Jul 18 05:33:12 PM PDT 24
Peak memory 205652 kb
Host smart-25eaeb53-8e68-4d52-85f8-65124b337707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543375576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.543375576
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1786411473
Short name T1689
Test name
Test status
Simulation time 11765482727 ps
CPU time 20.85 seconds
Started Jul 18 05:32:45 PM PDT 24
Finished Jul 18 05:33:11 PM PDT 24
Peak memory 205732 kb
Host smart-9a6daf29-2774-4989-aaab-b756e756e690
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786411473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1786411473
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.3369710380
Short name T4
Test name
Test status
Simulation time 2930222817 ps
CPU time 6.05 seconds
Started Jul 18 05:32:47 PM PDT 24
Finished Jul 18 05:33:01 PM PDT 24
Peak memory 265676 kb
Host smart-203fa864-1e2e-49d9-aeb9-37faa01484da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369710380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.3369710380
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1258395107
Short name T454
Test name
Test status
Simulation time 1485791934 ps
CPU time 7 seconds
Started Jul 18 05:32:44 PM PDT 24
Finished Jul 18 05:32:53 PM PDT 24
Peak memory 218768 kb
Host smart-f33aebdb-3dcb-4975-bc9e-fd1efa9b4148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258395107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1258395107
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.3525203160
Short name T407
Test name
Test status
Simulation time 571696034 ps
CPU time 7.9 seconds
Started Jul 18 05:32:44 PM PDT 24
Finished Jul 18 05:32:56 PM PDT 24
Peak memory 205600 kb
Host smart-f19bb6f2-bea1-45b9-be22-33bb573b71bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525203160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.3525203160
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3762610632
Short name T166
Test name
Test status
Simulation time 41750894 ps
CPU time 0.61 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:39 PM PDT 24
Peak memory 204760 kb
Host smart-f69f15d3-9f0b-402b-9146-3a85cacf18ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762610632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3762610632
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2617470546
Short name T1514
Test name
Test status
Simulation time 505637394 ps
CPU time 9.78 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:49 PM PDT 24
Peak memory 213724 kb
Host smart-f351a09b-2bca-49ac-8638-31b3c6bf00c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617470546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2617470546
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.863878133
Short name T595
Test name
Test status
Simulation time 610120005 ps
CPU time 15.45 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:26:59 PM PDT 24
Peak memory 251412 kb
Host smart-4b9bea04-9b47-40b2-9577-d8579d5da9e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863878133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.863878133
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2088162264
Short name T1277
Test name
Test status
Simulation time 2407657239 ps
CPU time 73.42 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:27:52 PM PDT 24
Peak memory 556444 kb
Host smart-3cc43681-f452-4852-84d0-b6f8ae06ad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088162264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2088162264
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.4218315678
Short name T805
Test name
Test status
Simulation time 17059750261 ps
CPU time 193.58 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:29:51 PM PDT 24
Peak memory 803504 kb
Host smart-ad7687a2-6acc-4f07-b8f7-61660377a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218315678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.4218315678
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3510239020
Short name T627
Test name
Test status
Simulation time 149923319 ps
CPU time 1.16 seconds
Started Jul 18 05:26:34 PM PDT 24
Finished Jul 18 05:26:37 PM PDT 24
Peak memory 205264 kb
Host smart-fc9a855d-970f-4405-abbe-917f456f20ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510239020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3510239020
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1437403969
Short name T218
Test name
Test status
Simulation time 599761782 ps
CPU time 9.39 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 205452 kb
Host smart-49aff7bd-0659-41e5-8912-0bf11a16a69c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437403969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1437403969
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1258920395
Short name T868
Test name
Test status
Simulation time 10855208104 ps
CPU time 175.08 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:29:35 PM PDT 24
Peak memory 1562024 kb
Host smart-17f0f284-18d5-4d74-aece-b6d240cb1f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258920395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1258920395
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2603578247
Short name T1222
Test name
Test status
Simulation time 3985739436 ps
CPU time 20.4 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:27:03 PM PDT 24
Peak memory 205800 kb
Host smart-b0081f29-0ae4-40ef-bd9d-74b1cc98852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603578247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2603578247
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_override.1410458677
Short name T1300
Test name
Test status
Simulation time 41778041 ps
CPU time 0.76 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 205188 kb
Host smart-d8377d84-e6e4-431b-a00e-3f55aac1a788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410458677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1410458677
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1486906120
Short name T317
Test name
Test status
Simulation time 6682103177 ps
CPU time 24.53 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:27:06 PM PDT 24
Peak memory 213664 kb
Host smart-3287ab8b-b9e1-4b80-a592-1796c50c1c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486906120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1486906120
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.3568161489
Short name T631
Test name
Test status
Simulation time 763996039 ps
CPU time 7.94 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:26:49 PM PDT 24
Peak memory 205404 kb
Host smart-fc76639a-b8d7-4d91-bdb8-049685c5d0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568161489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.3568161489
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2823209513
Short name T1716
Test name
Test status
Simulation time 3005582772 ps
CPU time 74.78 seconds
Started Jul 18 05:26:40 PM PDT 24
Finished Jul 18 05:27:59 PM PDT 24
Peak memory 380848 kb
Host smart-f5d23d4f-d453-44f4-a81a-a483cb56ce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823209513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2823209513
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2516686322
Short name T1064
Test name
Test status
Simulation time 6626614050 ps
CPU time 17.12 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:56 PM PDT 24
Peak memory 220032 kb
Host smart-275de2eb-c60f-4aa4-83c2-26a49b281a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516686322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2516686322
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.4262339597
Short name T624
Test name
Test status
Simulation time 1432726365 ps
CPU time 6.91 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 222016 kb
Host smart-00362822-52a0-4856-b8fe-a7776a774d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262339597 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.4262339597
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.4160230274
Short name T1285
Test name
Test status
Simulation time 802450381 ps
CPU time 1.46 seconds
Started Jul 18 05:26:51 PM PDT 24
Finished Jul 18 05:26:54 PM PDT 24
Peak memory 205536 kb
Host smart-129aa856-d047-42f6-9c94-675382473e47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160230274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.4160230274
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.693502184
Short name T545
Test name
Test status
Simulation time 202414487 ps
CPU time 0.82 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:40 PM PDT 24
Peak memory 205460 kb
Host smart-f9707f00-b778-45fb-bfaa-c11559082bff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693502184 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.693502184
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.641375480
Short name T1339
Test name
Test status
Simulation time 1047787702 ps
CPU time 2.64 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:26:45 PM PDT 24
Peak memory 205612 kb
Host smart-911132db-4c26-427f-942a-fd54953ac0b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641375480 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.641375480
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.2035506590
Short name T756
Test name
Test status
Simulation time 117767749 ps
CPU time 1.21 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:26:44 PM PDT 24
Peak memory 205468 kb
Host smart-2e319fa0-5cff-42ad-bab6-fc942fbc5dc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035506590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.2035506590
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3886086515
Short name T958
Test name
Test status
Simulation time 1464120150 ps
CPU time 7.69 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:26:50 PM PDT 24
Peak memory 230716 kb
Host smart-08271dde-06d6-4cf0-9fde-5dedf2216a87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886086515 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3886086515
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3926484943
Short name T1736
Test name
Test status
Simulation time 12342729288 ps
CPU time 15.43 seconds
Started Jul 18 05:26:41 PM PDT 24
Finished Jul 18 05:27:01 PM PDT 24
Peak memory 384200 kb
Host smart-96268a6c-a4b0-4542-a36d-436669f67e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926484943 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3926484943
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.3261876413
Short name T1659
Test name
Test status
Simulation time 648450791 ps
CPU time 3.11 seconds
Started Jul 18 05:26:41 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 214068 kb
Host smart-b096b953-be5e-4b1b-9ae6-2f1f9f19667f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261876413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_nack_acqfull.3261876413
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.352463896
Short name T1308
Test name
Test status
Simulation time 2138892233 ps
CPU time 2.54 seconds
Started Jul 18 05:26:40 PM PDT 24
Finished Jul 18 05:26:47 PM PDT 24
Peak memory 205660 kb
Host smart-14fa383f-cde1-42dc-a9ae-809189bcaea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352463896 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.352463896
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_txstretch.1922068139
Short name T648
Test name
Test status
Simulation time 500977467 ps
CPU time 1.52 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:40 PM PDT 24
Peak memory 222792 kb
Host smart-b7965281-35d7-4854-a9eb-44ba28a89156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922068139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_nack_txstretch.1922068139
Directory /workspace/5.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/5.i2c_target_perf.3669499394
Short name T1219
Test name
Test status
Simulation time 1573111319 ps
CPU time 4.95 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 213808 kb
Host smart-5a6503f5-c7b0-4d32-93cd-17500a32a7b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669499394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.3669499394
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.3110213454
Short name T1103
Test name
Test status
Simulation time 416720409 ps
CPU time 2.32 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:44 PM PDT 24
Peak memory 205476 kb
Host smart-d36e641f-c830-4351-b073-70d947d6b010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110213454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_smbus_maxlen.3110213454
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.510447871
Short name T689
Test name
Test status
Simulation time 4379814811 ps
CPU time 12 seconds
Started Jul 18 05:26:41 PM PDT 24
Finished Jul 18 05:26:57 PM PDT 24
Peak memory 217156 kb
Host smart-cfa06515-da81-4d8c-848a-5b4abd8471b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510447871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.510447871
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3159645844
Short name T1306
Test name
Test status
Simulation time 555928228 ps
CPU time 3.7 seconds
Started Jul 18 05:26:40 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 205796 kb
Host smart-d95c738e-74b9-4c13-8057-49e83e8ce0ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159645844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3159645844
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1955606100
Short name T699
Test name
Test status
Simulation time 31287638607 ps
CPU time 251.06 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 2892668 kb
Host smart-5574ba7f-6e3f-4c19-b7cf-2cacb5f69eef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955606100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1955606100
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.533249264
Short name T387
Test name
Test status
Simulation time 4902280094 ps
CPU time 4.76 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 230532 kb
Host smart-4cf80238-8da9-476f-a9b3-97a4587399d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533249264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_ta
rget_stretch.533249264
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1809885631
Short name T988
Test name
Test status
Simulation time 12969183156 ps
CPU time 7.1 seconds
Started Jul 18 05:26:40 PM PDT 24
Finished Jul 18 05:26:51 PM PDT 24
Peak memory 219204 kb
Host smart-11389f38-9c67-4aa8-bdde-d6b8000ad4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809885631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1809885631
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.2094923201
Short name T1391
Test name
Test status
Simulation time 38771996 ps
CPU time 1.12 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:41 PM PDT 24
Peak memory 205584 kb
Host smart-ddaaa7e5-900a-4d1a-ace8-d17f72a07bb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094923201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.2094923201
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2948982333
Short name T1584
Test name
Test status
Simulation time 38077485 ps
CPU time 0.66 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 204708 kb
Host smart-7aca6d69-a7aa-4b9e-8409-800070cc52b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948982333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2948982333
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.281829716
Short name T1330
Test name
Test status
Simulation time 119579885 ps
CPU time 1.74 seconds
Started Jul 18 05:26:35 PM PDT 24
Finished Jul 18 05:26:39 PM PDT 24
Peak memory 213784 kb
Host smart-4e8bc27c-6f4b-4d91-928d-3353dbfd2a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281829716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.281829716
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.406928851
Short name T984
Test name
Test status
Simulation time 404262422 ps
CPU time 7.22 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 289216 kb
Host smart-f170463c-070f-4752-be93-d4e69dc7aae6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406928851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.406928851
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3079739558
Short name T1639
Test name
Test status
Simulation time 2268012421 ps
CPU time 112.81 seconds
Started Jul 18 05:26:40 PM PDT 24
Finished Jul 18 05:28:37 PM PDT 24
Peak memory 348776 kb
Host smart-12dea802-1c59-45f0-8e47-ddc9f368c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079739558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3079739558
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.474571822
Short name T406
Test name
Test status
Simulation time 10795517942 ps
CPU time 44.04 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:27:27 PM PDT 24
Peak memory 529876 kb
Host smart-b4597d65-3da5-42fa-b52a-22880063334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474571822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.474571822
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2301174005
Short name T1301
Test name
Test status
Simulation time 261169665 ps
CPU time 4.1 seconds
Started Jul 18 05:26:42 PM PDT 24
Finished Jul 18 05:26:50 PM PDT 24
Peak memory 228344 kb
Host smart-54268152-6fe1-4d4d-a0a1-888537bab887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301174005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2301174005
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2290873471
Short name T1649
Test name
Test status
Simulation time 3606121899 ps
CPU time 71.23 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:27:50 PM PDT 24
Peak memory 998408 kb
Host smart-de374ff8-2071-4055-946e-b07367f64628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290873471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2290873471
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3288797518
Short name T674
Test name
Test status
Simulation time 353217893 ps
CPU time 15.56 seconds
Started Jul 18 05:27:09 PM PDT 24
Finished Jul 18 05:27:29 PM PDT 24
Peak memory 205568 kb
Host smart-22b5abc3-5592-4067-9cf2-33a2374886ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288797518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3288797518
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3825811060
Short name T1205
Test name
Test status
Simulation time 83474207 ps
CPU time 1.43 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:09 PM PDT 24
Peak memory 213652 kb
Host smart-015efb1d-9510-47b2-af0b-e4fee7ad005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825811060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3825811060
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.470760161
Short name T69
Test name
Test status
Simulation time 31757003 ps
CPU time 0.68 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 205216 kb
Host smart-2c24f206-696c-4055-aeaf-8b6608ae557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470760161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.470760161
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3099199306
Short name T1673
Test name
Test status
Simulation time 276339211 ps
CPU time 11.37 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:52 PM PDT 24
Peak memory 235340 kb
Host smart-20886c31-ea41-4322-ab9a-461c3f38bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099199306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3099199306
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.549438748
Short name T78
Test name
Test status
Simulation time 189112534 ps
CPU time 1.06 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 222760 kb
Host smart-dc2db7b2-fc93-4da6-b0d3-94314beee879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549438748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.549438748
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1445466041
Short name T1138
Test name
Test status
Simulation time 1567005609 ps
CPU time 82.35 seconds
Started Jul 18 05:26:39 PM PDT 24
Finished Jul 18 05:28:06 PM PDT 24
Peak memory 381976 kb
Host smart-371fee89-1ed3-4cc3-81b0-8d89f05855dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445466041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1445466041
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.8095174
Short name T524
Test name
Test status
Simulation time 889573353 ps
CPU time 17.09 seconds
Started Jul 18 05:26:36 PM PDT 24
Finished Jul 18 05:26:56 PM PDT 24
Peak memory 221748 kb
Host smart-6be19c3b-2827-44c4-866d-e8ad8461873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8095174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.8095174
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.317563457
Short name T928
Test name
Test status
Simulation time 1297755964 ps
CPU time 6.58 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:15 PM PDT 24
Peak memory 213860 kb
Host smart-c51f3e09-1c2b-4522-bc5f-ff907009438a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317563457 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.317563457
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2692420149
Short name T222
Test name
Test status
Simulation time 195624278 ps
CPU time 1.42 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 205392 kb
Host smart-862b6443-47b2-43ac-aa6c-31a8c89bac81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692420149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2692420149
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.609224260
Short name T1496
Test name
Test status
Simulation time 160444704 ps
CPU time 1.14 seconds
Started Jul 18 05:26:51 PM PDT 24
Finished Jul 18 05:26:53 PM PDT 24
Peak memory 205428 kb
Host smart-fe24d444-cdd8-42e3-a9a3-52bc1d0e0056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609224260 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.609224260
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.3018614710
Short name T642
Test name
Test status
Simulation time 492492405 ps
CPU time 2.88 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 205612 kb
Host smart-e6ef2f5f-fdcc-4539-9b55-4e4d84933657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018614710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.3018614710
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.3423379189
Short name T640
Test name
Test status
Simulation time 137370220 ps
CPU time 1.13 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 205380 kb
Host smart-0698a97d-f20c-411e-bef5-f35446b65040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423379189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.3423379189
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.399740661
Short name T1239
Test name
Test status
Simulation time 1900807173 ps
CPU time 6 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:47 PM PDT 24
Peak memory 219268 kb
Host smart-e09deb6c-b3f0-485f-b22a-905e6cf722ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399740661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.399740661
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.513137203
Short name T753
Test name
Test status
Simulation time 17119075855 ps
CPU time 19.68 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:27:01 PM PDT 24
Peak memory 444616 kb
Host smart-ade08a07-2537-4fc1-8ea3-f07e43fa0f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513137203 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.513137203
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.4153122714
Short name T51
Test name
Test status
Simulation time 1878480646 ps
CPU time 2.96 seconds
Started Jul 18 05:27:10 PM PDT 24
Finished Jul 18 05:27:16 PM PDT 24
Peak memory 213856 kb
Host smart-de778cd8-ad46-47f0-8048-4a63a1c5035f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153122714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_nack_acqfull.4153122714
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.2302556584
Short name T1263
Test name
Test status
Simulation time 1910597455 ps
CPU time 2.54 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:09 PM PDT 24
Peak memory 205632 kb
Host smart-830ec9ae-125e-4fb1-81af-9a0cf659cae7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302556584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.2302556584
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_txstretch.981040925
Short name T155
Test name
Test status
Simulation time 144642911 ps
CPU time 1.41 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:09 PM PDT 24
Peak memory 222064 kb
Host smart-9e4b50c7-429b-4c52-9da6-6a0ea7ce68ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981040925 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_nack_txstretch.981040925
Directory /workspace/6.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/6.i2c_target_perf.367546576
Short name T348
Test name
Test status
Simulation time 2215146503 ps
CPU time 4.36 seconds
Started Jul 18 05:27:02 PM PDT 24
Finished Jul 18 05:27:08 PM PDT 24
Peak memory 216008 kb
Host smart-45d8b501-b2bb-46c3-959f-0877297b9d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367546576 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_perf.367546576
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.3139663455
Short name T333
Test name
Test status
Simulation time 572076993 ps
CPU time 2.58 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:11 PM PDT 24
Peak memory 205380 kb
Host smart-522307a3-a9b3-43cb-9ded-ba96d873b948
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139663455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_smbus_maxlen.3139663455
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3698825142
Short name T1563
Test name
Test status
Simulation time 13561332945 ps
CPU time 10.77 seconds
Started Jul 18 05:26:40 PM PDT 24
Finished Jul 18 05:26:55 PM PDT 24
Peak memory 213856 kb
Host smart-16163129-52df-4ace-8fbb-2a4275af8675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698825142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3698825142
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.2102259197
Short name T610
Test name
Test status
Simulation time 31795289823 ps
CPU time 779.3 seconds
Started Jul 18 05:27:03 PM PDT 24
Finished Jul 18 05:40:05 PM PDT 24
Peak memory 3933572 kb
Host smart-41e35ede-96e3-459f-b085-4b7cfd58b261
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102259197 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.2102259197
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.493320967
Short name T1544
Test name
Test status
Simulation time 1643610209 ps
CPU time 33.98 seconds
Started Jul 18 05:26:39 PM PDT 24
Finished Jul 18 05:27:17 PM PDT 24
Peak memory 213896 kb
Host smart-a182a42f-8161-49ee-9a93-7a98859471b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493320967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_rd.493320967
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3356564380
Short name T1025
Test name
Test status
Simulation time 39031394887 ps
CPU time 662.11 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:37:43 PM PDT 24
Peak memory 4869048 kb
Host smart-3c52b213-c667-478a-908c-fb7b5bcfce90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356564380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3356564380
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2286827305
Short name T1190
Test name
Test status
Simulation time 1742488249 ps
CPU time 43.18 seconds
Started Jul 18 05:26:38 PM PDT 24
Finished Jul 18 05:27:26 PM PDT 24
Peak memory 419612 kb
Host smart-ef6b1108-9b74-425d-8fc0-bbe3df134d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286827305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2286827305
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2612673414
Short name T1641
Test name
Test status
Simulation time 2410456413 ps
CPU time 6.57 seconds
Started Jul 18 05:26:37 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 221768 kb
Host smart-faaef5f0-0ab7-46ba-9c67-5ba03b8fc045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612673414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2612673414
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.3821197311
Short name T933
Test name
Test status
Simulation time 153119293 ps
CPU time 3.45 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:10 PM PDT 24
Peak memory 204108 kb
Host smart-c9a86152-d7c3-4ad3-b30e-0dc2b81ca057
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821197311 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.3821197311
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1886819742
Short name T553
Test name
Test status
Simulation time 44588203 ps
CPU time 0.66 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 204888 kb
Host smart-017d867b-9de9-479a-9810-0f62c0854480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886819742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1886819742
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1785583381
Short name T744
Test name
Test status
Simulation time 293250272 ps
CPU time 2.33 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 213756 kb
Host smart-68e42735-d0cf-4356-b73c-1b930b798bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785583381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1785583381
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.166036038
Short name T312
Test name
Test status
Simulation time 2610412962 ps
CPU time 9.37 seconds
Started Jul 18 05:27:02 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 289480 kb
Host smart-b85a9219-629f-43ac-9bd0-b837ce8596e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166036038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.166036038
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2221166510
Short name T1738
Test name
Test status
Simulation time 13026715009 ps
CPU time 107.78 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:28:54 PM PDT 24
Peak memory 729488 kb
Host smart-6233d356-f686-44b5-ab80-a046c9ab19e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221166510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2221166510
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2590940370
Short name T1754
Test name
Test status
Simulation time 2921922667 ps
CPU time 102.44 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:28:52 PM PDT 24
Peak memory 783464 kb
Host smart-3da55589-cdb0-494b-9057-311d83849b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590940370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2590940370
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.997590410
Short name T33
Test name
Test status
Simulation time 146734019 ps
CPU time 1.09 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:08 PM PDT 24
Peak memory 205196 kb
Host smart-6e205029-a85a-4246-81a5-1625d1d519b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997590410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.997590410
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3928194775
Short name T999
Test name
Test status
Simulation time 584292618 ps
CPU time 4.18 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:15 PM PDT 24
Peak memory 229992 kb
Host smart-b0a1ecfe-be10-4d79-8de7-9d534bee9bfc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928194775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3928194775
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3488331801
Short name T814
Test name
Test status
Simulation time 14243868331 ps
CPU time 238.06 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:31:09 PM PDT 24
Peak memory 1002664 kb
Host smart-f98610cb-e768-477f-a68a-2d9d797d6bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488331801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3488331801
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.416889916
Short name T1585
Test name
Test status
Simulation time 737858054 ps
CPU time 2.5 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 205472 kb
Host smart-72e6c3b1-39c3-4f3e-b791-e73c9b694da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416889916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.416889916
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.2570505104
Short name T1387
Test name
Test status
Simulation time 473271894 ps
CPU time 1.92 seconds
Started Jul 18 05:27:09 PM PDT 24
Finished Jul 18 05:27:15 PM PDT 24
Peak memory 213712 kb
Host smart-735aa966-1635-420b-957b-1c5fca209f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570505104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.2570505104
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1023208110
Short name T423
Test name
Test status
Simulation time 26519115 ps
CPU time 0.69 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:10 PM PDT 24
Peak memory 205416 kb
Host smart-6e174a39-755f-49d1-bff6-6922d4f114d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023208110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1023208110
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1890409619
Short name T215
Test name
Test status
Simulation time 3792851033 ps
CPU time 25.83 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:34 PM PDT 24
Peak memory 495060 kb
Host smart-a06bbe61-285c-49b0-9642-b9b6b6e2e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890409619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1890409619
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.4088822245
Short name T678
Test name
Test status
Simulation time 32734781 ps
CPU time 1.85 seconds
Started Jul 18 05:27:02 PM PDT 24
Finished Jul 18 05:27:05 PM PDT 24
Peak memory 224016 kb
Host smart-77bc6153-7576-4973-b0e5-0c1c3e2a0d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088822245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.4088822245
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.1271207995
Short name T1504
Test name
Test status
Simulation time 1001617805 ps
CPU time 19.44 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:30 PM PDT 24
Peak memory 282152 kb
Host smart-b581de55-409a-4da7-896d-5c4aff0e0dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271207995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1271207995
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2314961865
Short name T652
Test name
Test status
Simulation time 777431803 ps
CPU time 12.33 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:21 PM PDT 24
Peak memory 219708 kb
Host smart-b4c19952-d21f-4dd8-8dc4-a9e663346dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314961865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2314961865
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1627515585
Short name T1545
Test name
Test status
Simulation time 4232395099 ps
CPU time 6.25 seconds
Started Jul 18 05:27:10 PM PDT 24
Finished Jul 18 05:27:20 PM PDT 24
Peak memory 213912 kb
Host smart-937d5973-d698-41e9-8c3e-d3a40de3917e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627515585 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1627515585
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.582373325
Short name T1223
Test name
Test status
Simulation time 651440362 ps
CPU time 1.01 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:08 PM PDT 24
Peak memory 205644 kb
Host smart-d203f2a7-3d2b-4e5a-ae4a-4bb4e4e32189
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582373325 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.582373325
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1232526832
Short name T1599
Test name
Test status
Simulation time 716135466 ps
CPU time 1.49 seconds
Started Jul 18 05:27:07 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 205640 kb
Host smart-cdacc88d-fedc-401e-b052-7ddb07c8819d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232526832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1232526832
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.4205521573
Short name T374
Test name
Test status
Simulation time 431493998 ps
CPU time 2.38 seconds
Started Jul 18 05:27:08 PM PDT 24
Finished Jul 18 05:27:15 PM PDT 24
Peak memory 205576 kb
Host smart-333a4387-f0ae-4a7a-925d-ce6230d6a6c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205521573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.4205521573
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.411976464
Short name T666
Test name
Test status
Simulation time 208868507 ps
CPU time 1.1 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 205424 kb
Host smart-5ed49876-19b9-4445-b5fb-02194b7839a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411976464 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.411976464
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2293917117
Short name T1012
Test name
Test status
Simulation time 1606072495 ps
CPU time 5.18 seconds
Started Jul 18 05:27:02 PM PDT 24
Finished Jul 18 05:27:09 PM PDT 24
Peak memory 213868 kb
Host smart-e721e323-2536-4cbc-9e57-82893501541d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293917117 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2293917117
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2843566011
Short name T285
Test name
Test status
Simulation time 22109331703 ps
CPU time 176.46 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:30:08 PM PDT 24
Peak memory 2654548 kb
Host smart-eeafadbd-a5a1-4fc2-ae2e-66443d09d78f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843566011 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2843566011
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.4077089418
Short name T623
Test name
Test status
Simulation time 1851651266 ps
CPU time 2.76 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:14 PM PDT 24
Peak memory 213780 kb
Host smart-17355f28-4077-490f-a651-750737b9112b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077089418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_acqfull.4077089418
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.1426092900
Short name T1735
Test name
Test status
Simulation time 5655556349 ps
CPU time 2.76 seconds
Started Jul 18 05:27:03 PM PDT 24
Finished Jul 18 05:27:08 PM PDT 24
Peak memory 205512 kb
Host smart-7eb79942-cbaa-465b-8c74-128e11e976a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426092900 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.1426092900
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_txstretch.3358096236
Short name T156
Test name
Test status
Simulation time 142289809 ps
CPU time 1.39 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:10 PM PDT 24
Peak memory 222416 kb
Host smart-4a6ad153-149d-4eab-9a1e-e9da50f135c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358096236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_nack_txstretch.3358096236
Directory /workspace/7.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/7.i2c_target_perf.2234227293
Short name T764
Test name
Test status
Simulation time 552999584 ps
CPU time 4.61 seconds
Started Jul 18 05:27:08 PM PDT 24
Finished Jul 18 05:27:17 PM PDT 24
Peak memory 219424 kb
Host smart-e758f57b-4ade-4e55-ba36-b314e5ab53d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234227293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.2234227293
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.935559275
Short name T708
Test name
Test status
Simulation time 889768240 ps
CPU time 2.15 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:11 PM PDT 24
Peak memory 205396 kb
Host smart-544f1164-d89e-412e-a1dd-dca9b3f692ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935559275 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_smbus_maxlen.935559275
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2061616209
Short name T558
Test name
Test status
Simulation time 1395260081 ps
CPU time 11.38 seconds
Started Jul 18 05:27:01 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 213808 kb
Host smart-05c021a8-4f17-4d54-8d65-ee0d4faa1d49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061616209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2061616209
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.3596104712
Short name T617
Test name
Test status
Simulation time 4339119995 ps
CPU time 24.12 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:34 PM PDT 24
Peak memory 222564 kb
Host smart-a844e841-af09-4fa0-8f31-01223860cbd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596104712 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.3596104712
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3995780578
Short name T1638
Test name
Test status
Simulation time 2325966834 ps
CPU time 5.93 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:14 PM PDT 24
Peak memory 205644 kb
Host smart-dadf46cd-822f-49b5-b1a6-91f8d6f027e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995780578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3995780578
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3422769148
Short name T1619
Test name
Test status
Simulation time 45964206757 ps
CPU time 1121.02 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:45:53 PM PDT 24
Peak memory 6709300 kb
Host smart-168ee7ce-e622-4e40-892e-317eaaed3f31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422769148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3422769148
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.655407104
Short name T1243
Test name
Test status
Simulation time 3653278342 ps
CPU time 88.65 seconds
Started Jul 18 05:27:01 PM PDT 24
Finished Jul 18 05:28:31 PM PDT 24
Peak memory 634532 kb
Host smart-678a90c9-99f4-4fd1-a3ef-0d032759594c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655407104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_ta
rget_stretch.655407104
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.602238448
Short name T1719
Test name
Test status
Simulation time 2243808012 ps
CPU time 6.07 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 222004 kb
Host smart-f49460bd-9cfa-4dff-a279-c702ca3713d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602238448 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.602238448
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.3836432122
Short name T1554
Test name
Test status
Simulation time 187491827 ps
CPU time 2.71 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:14 PM PDT 24
Peak memory 205584 kb
Host smart-72288f27-26fe-4c02-8ff6-a3b9ad871318
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836432122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.3836432122
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.466119970
Short name T1579
Test name
Test status
Simulation time 42965146 ps
CPU time 0.64 seconds
Started Jul 18 05:27:03 PM PDT 24
Finished Jul 18 05:27:06 PM PDT 24
Peak memory 204808 kb
Host smart-265f02fc-4233-41e5-9489-4ecccba2a304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466119970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.466119970
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1281649573
Short name T1121
Test name
Test status
Simulation time 307603432 ps
CPU time 2.59 seconds
Started Jul 18 05:27:14 PM PDT 24
Finished Jul 18 05:27:18 PM PDT 24
Peak memory 205544 kb
Host smart-c61d5030-05d8-4ab8-bc46-c11ca8ab7020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281649573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1281649573
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2796453975
Short name T1576
Test name
Test status
Simulation time 471536710 ps
CPU time 11.37 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:20 PM PDT 24
Peak memory 309404 kb
Host smart-960a84a2-a11b-4e42-b796-aa031b0e930d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796453975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2796453975
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2250549377
Short name T1405
Test name
Test status
Simulation time 6560790837 ps
CPU time 88.25 seconds
Started Jul 18 05:27:08 PM PDT 24
Finished Jul 18 05:28:41 PM PDT 24
Peak memory 489744 kb
Host smart-68ea35d5-8e64-4a22-a363-08dad644ff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250549377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2250549377
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.858663761
Short name T1180
Test name
Test status
Simulation time 3758559885 ps
CPU time 65.29 seconds
Started Jul 18 05:27:10 PM PDT 24
Finished Jul 18 05:28:19 PM PDT 24
Peak memory 676460 kb
Host smart-d08741fb-fed2-4bf4-868d-cf9d9786eddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858663761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.858663761
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2840738654
Short name T1644
Test name
Test status
Simulation time 112206993 ps
CPU time 1.07 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:11 PM PDT 24
Peak memory 205216 kb
Host smart-dbad943a-ad7d-40b9-9a68-90cf2bc20741
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840738654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2840738654
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2791061060
Short name T1510
Test name
Test status
Simulation time 794889947 ps
CPU time 11.73 seconds
Started Jul 18 05:27:07 PM PDT 24
Finished Jul 18 05:27:24 PM PDT 24
Peak memory 246044 kb
Host smart-f3491f58-b660-4c14-8694-a84f0705aa9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791061060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2791061060
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3532405540
Short name T1513
Test name
Test status
Simulation time 3261136413 ps
CPU time 184.82 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:30:15 PM PDT 24
Peak memory 867924 kb
Host smart-688dfc71-344c-4546-a927-0892f514125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532405540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3532405540
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2336549742
Short name T1571
Test name
Test status
Simulation time 2216038148 ps
CPU time 8.93 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:17 PM PDT 24
Peak memory 205608 kb
Host smart-5f41dc8f-bcf2-4bc1-8de1-e954bda72420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336549742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2336549742
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.650642302
Short name T1505
Test name
Test status
Simulation time 227296021 ps
CPU time 1.25 seconds
Started Jul 18 05:27:10 PM PDT 24
Finished Jul 18 05:27:15 PM PDT 24
Peak memory 213808 kb
Host smart-31a7868d-412f-4bbd-abb4-b5b776671e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650642302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.650642302
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2126986053
Short name T1458
Test name
Test status
Simulation time 38743975 ps
CPU time 0.67 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 205264 kb
Host smart-9d65ccc4-784a-47e5-ba7d-eb5e8e0956ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126986053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2126986053
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2708314955
Short name T929
Test name
Test status
Simulation time 27863143406 ps
CPU time 136.52 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 324120 kb
Host smart-c185e7ca-6de1-4ac8-aa1d-85c96e9da6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708314955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2708314955
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.2676924075
Short name T148
Test name
Test status
Simulation time 225130651 ps
CPU time 1.62 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:11 PM PDT 24
Peak memory 205400 kb
Host smart-72d4750b-d768-449b-94e2-656443cb1234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676924075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.2676924075
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2578788240
Short name T1060
Test name
Test status
Simulation time 19825139267 ps
CPU time 32.21 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:41 PM PDT 24
Peak memory 345504 kb
Host smart-871c7bd8-187b-4c11-b1df-59f514b1026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578788240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2578788240
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1667336222
Short name T256
Test name
Test status
Simulation time 13915399212 ps
CPU time 799.77 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:40:30 PM PDT 24
Peak memory 2958244 kb
Host smart-8c8dc6f3-75d7-44cc-9e22-5a482d8e3d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667336222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1667336222
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3165954059
Short name T747
Test name
Test status
Simulation time 1456484302 ps
CPU time 14.76 seconds
Started Jul 18 05:27:09 PM PDT 24
Finished Jul 18 05:27:28 PM PDT 24
Peak memory 215824 kb
Host smart-28644de6-0137-49b5-9911-05c1dc5f9fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165954059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3165954059
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.807020862
Short name T833
Test name
Test status
Simulation time 657078884 ps
CPU time 3.79 seconds
Started Jul 18 05:27:09 PM PDT 24
Finished Jul 18 05:27:17 PM PDT 24
Peak memory 213920 kb
Host smart-18ffe259-a0dd-4309-ab15-0ea45e2f6e01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807020862 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.807020862
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3839505446
Short name T1440
Test name
Test status
Simulation time 149439663 ps
CPU time 1.09 seconds
Started Jul 18 05:27:07 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 205420 kb
Host smart-1ec14772-cacf-4cad-acfd-254602c29efe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839505446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3839505446
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3862445192
Short name T564
Test name
Test status
Simulation time 661806350 ps
CPU time 1.06 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 213832 kb
Host smart-52e25315-d7ae-4cd7-9967-c3201401d320
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862445192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3862445192
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.1366733439
Short name T347
Test name
Test status
Simulation time 1669175211 ps
CPU time 2.81 seconds
Started Jul 18 05:27:07 PM PDT 24
Finished Jul 18 05:27:15 PM PDT 24
Peak memory 205784 kb
Host smart-fab966df-f04c-4693-8e53-26d48a9c1b66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366733439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.1366733439
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.2943905199
Short name T1147
Test name
Test status
Simulation time 1839905330 ps
CPU time 1.19 seconds
Started Jul 18 05:27:09 PM PDT 24
Finished Jul 18 05:27:14 PM PDT 24
Peak memory 205376 kb
Host smart-7ebe7642-1ecb-4edf-a1a0-fb493e41e679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943905199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.2943905199
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3665647931
Short name T851
Test name
Test status
Simulation time 653022398 ps
CPU time 3.1 seconds
Started Jul 18 05:27:11 PM PDT 24
Finished Jul 18 05:27:17 PM PDT 24
Peak memory 213892 kb
Host smart-68a57488-b8a2-418e-a8d0-ad8486ca4ece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665647931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3665647931
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2515044836
Short name T498
Test name
Test status
Simulation time 2274967943 ps
CPU time 3.77 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 222032 kb
Host smart-ed7c365b-7b7b-4568-9c73-20cfaaf6c113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515044836 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2515044836
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3293076991
Short name T1070
Test name
Test status
Simulation time 5795993074 ps
CPU time 10.68 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:20 PM PDT 24
Peak memory 474172 kb
Host smart-4d153984-b84e-480c-879b-f043d4b6b7ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293076991 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3293076991
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.3725962398
Short name T853
Test name
Test status
Simulation time 2200385952 ps
CPU time 3.1 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:10 PM PDT 24
Peak memory 213880 kb
Host smart-332afc7b-cc1d-44ee-ae6f-ac15ebbf87c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725962398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.3725962398
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.814251544
Short name T1493
Test name
Test status
Simulation time 2116033512 ps
CPU time 2.55 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:09 PM PDT 24
Peak memory 205676 kb
Host smart-daee6257-d762-4ccb-83eb-89a64b955ebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814251544 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.814251544
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.1356258975
Short name T283
Test name
Test status
Simulation time 549864384 ps
CPU time 4.42 seconds
Started Jul 18 05:27:11 PM PDT 24
Finished Jul 18 05:27:19 PM PDT 24
Peak memory 216840 kb
Host smart-1422a6bb-4231-4379-b010-f7d87c4b023b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356258975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.1356258975
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.1274631077
Short name T766
Test name
Test status
Simulation time 4645017709 ps
CPU time 2.19 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:12 PM PDT 24
Peak memory 205464 kb
Host smart-d69ede97-24ad-4270-a9ed-10ff071dbece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274631077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.1274631077
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1521681360
Short name T358
Test name
Test status
Simulation time 2939318165 ps
CPU time 7.91 seconds
Started Jul 18 05:27:16 PM PDT 24
Finished Jul 18 05:27:24 PM PDT 24
Peak memory 213860 kb
Host smart-430ab02e-f979-4a13-b111-4bd1126145d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521681360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1521681360
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.3368562244
Short name T255
Test name
Test status
Simulation time 55272822237 ps
CPU time 43.95 seconds
Started Jul 18 05:27:12 PM PDT 24
Finished Jul 18 05:27:58 PM PDT 24
Peak memory 358880 kb
Host smart-31009205-c1aa-47fc-85c0-39883d373307
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368562244 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.3368562244
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.262057158
Short name T566
Test name
Test status
Simulation time 6809785104 ps
CPU time 23 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:33 PM PDT 24
Peak memory 230388 kb
Host smart-041f77de-50c9-4a7a-8d3c-bb5680738fc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262057158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.262057158
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3627642885
Short name T1061
Test name
Test status
Simulation time 9476895993 ps
CPU time 20.8 seconds
Started Jul 18 05:27:14 PM PDT 24
Finished Jul 18 05:27:36 PM PDT 24
Peak memory 205648 kb
Host smart-918c0c15-edd7-44f5-94eb-e40dbdd07f3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627642885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3627642885
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3256212966
Short name T1106
Test name
Test status
Simulation time 2187478506 ps
CPU time 13.56 seconds
Started Jul 18 05:27:12 PM PDT 24
Finished Jul 18 05:27:28 PM PDT 24
Peak memory 260112 kb
Host smart-5435b26f-b546-4f99-8069-356fa73fed47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256212966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3256212966
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2319706652
Short name T1501
Test name
Test status
Simulation time 1323433144 ps
CPU time 7.64 seconds
Started Jul 18 05:27:06 PM PDT 24
Finished Jul 18 05:27:19 PM PDT 24
Peak memory 222016 kb
Host smart-8ff2e6e9-8a48-4077-9c41-1f4f0261e3ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319706652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2319706652
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.395656894
Short name T392
Test name
Test status
Simulation time 273209554 ps
CPU time 3.67 seconds
Started Jul 18 05:27:10 PM PDT 24
Finished Jul 18 05:27:17 PM PDT 24
Peak memory 205648 kb
Host smart-fa0662e5-385b-4a45-bb0f-236bb508a227
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395656894 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.395656894
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2692936019
Short name T1678
Test name
Test status
Simulation time 17244447 ps
CPU time 0.68 seconds
Started Jul 18 05:27:25 PM PDT 24
Finished Jul 18 05:27:26 PM PDT 24
Peak memory 204756 kb
Host smart-607f2690-e002-471d-8497-f84c4efaab60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692936019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2692936019
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2647778815
Short name T1626
Test name
Test status
Simulation time 717309901 ps
CPU time 3.28 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:40 PM PDT 24
Peak memory 234012 kb
Host smart-00930cb5-032e-43b6-b6a1-ab690cd97682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647778815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2647778815
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.715490497
Short name T291
Test name
Test status
Simulation time 3270149768 ps
CPU time 10.42 seconds
Started Jul 18 05:27:04 PM PDT 24
Finished Jul 18 05:27:17 PM PDT 24
Peak memory 320244 kb
Host smart-ac3525b3-7f81-46da-bcc8-9a736294d4ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715490497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.715490497
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3050312006
Short name T1189
Test name
Test status
Simulation time 11576867991 ps
CPU time 88.55 seconds
Started Jul 18 05:27:08 PM PDT 24
Finished Jul 18 05:28:41 PM PDT 24
Peak memory 553460 kb
Host smart-061c6a28-aad9-4d7a-ad27-937fad4fa89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050312006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3050312006
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1627354595
Short name T603
Test name
Test status
Simulation time 18257092512 ps
CPU time 136.58 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:29:27 PM PDT 24
Peak memory 662404 kb
Host smart-dbf25903-6f5d-4e96-8e8c-bb3262f06eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627354595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1627354595
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2693472041
Short name T35
Test name
Test status
Simulation time 386274722 ps
CPU time 0.99 seconds
Started Jul 18 05:27:03 PM PDT 24
Finished Jul 18 05:27:07 PM PDT 24
Peak memory 205236 kb
Host smart-4e0d04c0-107c-4b40-89aa-60518fe3d2fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693472041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2693472041
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1677373084
Short name T547
Test name
Test status
Simulation time 337538607 ps
CPU time 8.81 seconds
Started Jul 18 05:27:05 PM PDT 24
Finished Jul 18 05:27:19 PM PDT 24
Peak memory 232924 kb
Host smart-d801fa2a-a167-49ff-8dd9-2d6d78414b28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677373084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1677373084
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.442722041
Short name T100
Test name
Test status
Simulation time 11308663175 ps
CPU time 60.33 seconds
Started Jul 18 05:27:07 PM PDT 24
Finished Jul 18 05:28:12 PM PDT 24
Peak memory 884024 kb
Host smart-91b0e3c7-1648-40ca-8849-20c498416e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442722041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.442722041
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1374362487
Short name T1535
Test name
Test status
Simulation time 484850518 ps
CPU time 20.1 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:27:52 PM PDT 24
Peak memory 205472 kb
Host smart-1c3e9960-883a-4ed1-aa2c-9dbfbf79e6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374362487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1374362487
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.2041127080
Short name T1370
Test name
Test status
Simulation time 17979427 ps
CPU time 0.73 seconds
Started Jul 18 05:27:03 PM PDT 24
Finished Jul 18 05:27:06 PM PDT 24
Peak memory 205220 kb
Host smart-7de75137-b098-4cf2-9c1b-5f35484ae153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041127080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2041127080
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2535786660
Short name T559
Test name
Test status
Simulation time 4985086104 ps
CPU time 57.41 seconds
Started Jul 18 05:27:30 PM PDT 24
Finished Jul 18 05:28:30 PM PDT 24
Peak memory 223700 kb
Host smart-5f70f892-aa01-4532-a38c-02171b259b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535786660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2535786660
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.171680697
Short name T438
Test name
Test status
Simulation time 113819730 ps
CPU time 2.33 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:37 PM PDT 24
Peak memory 221208 kb
Host smart-452360fe-9a8b-4b12-bcf8-631809f7ca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171680697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.171680697
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.4023000782
Short name T1021
Test name
Test status
Simulation time 5450972637 ps
CPU time 18.43 seconds
Started Jul 18 05:27:09 PM PDT 24
Finished Jul 18 05:27:32 PM PDT 24
Peak memory 279300 kb
Host smart-dbce6849-c538-444d-b938-f0abb7a797b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023000782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.4023000782
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.3058296536
Short name T783
Test name
Test status
Simulation time 2287631780 ps
CPU time 25.38 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 213788 kb
Host smart-5cf4d5cf-7c2a-4e2d-8d10-9a00b3dabfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058296536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3058296536
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1758792668
Short name T326
Test name
Test status
Simulation time 1930814642 ps
CPU time 5.78 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:27:43 PM PDT 24
Peak memory 214520 kb
Host smart-81714196-399f-43ed-a251-06aa3d8b5f7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758792668 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1758792668
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3586907844
Short name T462
Test name
Test status
Simulation time 160413411 ps
CPU time 1.12 seconds
Started Jul 18 05:27:23 PM PDT 24
Finished Jul 18 05:27:25 PM PDT 24
Peak memory 205472 kb
Host smart-0b3ee497-c939-4fb3-afba-67e6f84e189d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586907844 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3586907844
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2884281716
Short name T1242
Test name
Test status
Simulation time 496751192 ps
CPU time 1.79 seconds
Started Jul 18 05:27:24 PM PDT 24
Finished Jul 18 05:27:27 PM PDT 24
Peak memory 214192 kb
Host smart-5524f453-b51a-440a-b5e2-231b98865d97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884281716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2884281716
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.1438393083
Short name T1726
Test name
Test status
Simulation time 1464748734 ps
CPU time 2.04 seconds
Started Jul 18 05:27:24 PM PDT 24
Finished Jul 18 05:27:27 PM PDT 24
Peak memory 205392 kb
Host smart-5b7fa560-0626-48ef-92de-1ba00b0d9f79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438393083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.1438393083
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.668643318
Short name T608
Test name
Test status
Simulation time 300632200 ps
CPU time 1.02 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:34 PM PDT 24
Peak memory 205416 kb
Host smart-df6ca1bf-5825-44e5-af5f-7b23d6555944
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668643318 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.668643318
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1144448784
Short name T1439
Test name
Test status
Simulation time 4645526261 ps
CPU time 2.51 seconds
Started Jul 18 05:27:24 PM PDT 24
Finished Jul 18 05:27:28 PM PDT 24
Peak memory 213856 kb
Host smart-98015e79-7a69-4270-9a10-51805db12bb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144448784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1144448784
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2694843780
Short name T63
Test name
Test status
Simulation time 2936665132 ps
CPU time 5.2 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:43 PM PDT 24
Peak memory 220312 kb
Host smart-994f8231-e630-4a72-846b-579297122d09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694843780 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2694843780
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.778895669
Short name T55
Test name
Test status
Simulation time 15849145592 ps
CPU time 197.59 seconds
Started Jul 18 05:27:24 PM PDT 24
Finished Jul 18 05:30:42 PM PDT 24
Peak memory 2265964 kb
Host smart-5ee04baf-3589-43e2-8cb4-0fe7b5ef355f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778895669 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.778895669
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.3401000355
Short name T1006
Test name
Test status
Simulation time 545464876 ps
CPU time 2.64 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:41 PM PDT 24
Peak memory 213864 kb
Host smart-acca65dd-8ae6-4df0-bf10-ffcbcdaea883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401000355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.3401000355
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.3994143691
Short name T1089
Test name
Test status
Simulation time 2041883746 ps
CPU time 2.82 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:27:32 PM PDT 24
Peak memory 205644 kb
Host smart-52c79efd-76d2-4a66-9d3d-fa7ff075decc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994143691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3994143691
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_txstretch.1715883830
Short name T1661
Test name
Test status
Simulation time 540942092 ps
CPU time 1.62 seconds
Started Jul 18 05:27:27 PM PDT 24
Finished Jul 18 05:27:31 PM PDT 24
Peak memory 222460 kb
Host smart-204b92ed-88c5-4325-a37e-4f954fbb4922
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715883830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_nack_txstretch.1715883830
Directory /workspace/9.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/9.i2c_target_perf.770275948
Short name T1570
Test name
Test status
Simulation time 717491570 ps
CPU time 5.8 seconds
Started Jul 18 05:27:32 PM PDT 24
Finished Jul 18 05:27:42 PM PDT 24
Peak memory 222024 kb
Host smart-2685f847-267b-46d2-aa60-37c4cd0fa101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770275948 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_perf.770275948
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.70693175
Short name T1418
Test name
Test status
Simulation time 670483118 ps
CPU time 2.35 seconds
Started Jul 18 05:27:23 PM PDT 24
Finished Jul 18 05:27:26 PM PDT 24
Peak memory 205424 kb
Host smart-e3012442-6600-4c36-acad-56fa1d272a60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70693175 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_target_smbus_maxlen.70693175
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2096270335
Short name T73
Test name
Test status
Simulation time 1689879405 ps
CPU time 10.73 seconds
Started Jul 18 05:27:34 PM PDT 24
Finished Jul 18 05:27:49 PM PDT 24
Peak memory 213876 kb
Host smart-219100bf-219e-4f00-9336-40c890577ab5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096270335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2096270335
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.3207601354
Short name T1731
Test name
Test status
Simulation time 146903087572 ps
CPU time 103 seconds
Started Jul 18 05:27:23 PM PDT 24
Finished Jul 18 05:29:07 PM PDT 24
Peak memory 784708 kb
Host smart-55b8da95-5837-4c79-9bc2-bfffff9a88af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207601354 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.3207601354
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.824660911
Short name T872
Test name
Test status
Simulation time 2401026819 ps
CPU time 55.8 seconds
Started Jul 18 05:27:33 PM PDT 24
Finished Jul 18 05:28:33 PM PDT 24
Peak memory 218136 kb
Host smart-cfbae687-7f7a-4ea7-960b-edc3e2329347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824660911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.824660911
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.3888877643
Short name T593
Test name
Test status
Simulation time 12068735336 ps
CPU time 25.7 seconds
Started Jul 18 05:27:26 PM PDT 24
Finished Jul 18 05:27:54 PM PDT 24
Peak memory 205916 kb
Host smart-3713eee1-e279-4393-81ba-17e1e7aa7196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888877643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.3888877643
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.63427996
Short name T472
Test name
Test status
Simulation time 1777739901 ps
CPU time 5.37 seconds
Started Jul 18 05:27:28 PM PDT 24
Finished Jul 18 05:27:35 PM PDT 24
Peak memory 267548 kb
Host smart-f8b53205-2e58-4a6f-87f9-4097016b49e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63427996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_stretch.63427996
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3829085185
Short name T473
Test name
Test status
Simulation time 1202896276 ps
CPU time 6.81 seconds
Started Jul 18 05:27:26 PM PDT 24
Finished Jul 18 05:27:34 PM PDT 24
Peak memory 221156 kb
Host smart-6d563786-6bb9-4481-affb-629c7355663b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829085185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3829085185
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.1820894909
Short name T1414
Test name
Test status
Simulation time 81456424 ps
CPU time 1.98 seconds
Started Jul 18 05:27:31 PM PDT 24
Finished Jul 18 05:27:36 PM PDT 24
Peak memory 205600 kb
Host smart-463f7253-8b13-437e-9c16-85cd659a2a11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820894909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.1820894909
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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