Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	758687	1			T1	2		T2	3		T3	456
all_values[1]	758687	1			T1	2		T2	3		T3	456
all_values[2]	758687	1			T1	2		T2	3		T3	456
all_values[3]	758687	1			T1	2		T2	3		T3	456
all_values[4]	758687	1			T1	2		T2	3		T3	456
all_values[5]	758687	1			T1	2		T2	3		T3	456
all_values[6]	758687	1			T1	2		T2	3		T3	456
all_values[7]	758687	1			T1	2		T2	3		T3	456
all_values[8]	758687	1			T1	2		T2	3		T3	456
all_values[9]	758687	1			T1	2		T2	3		T3	456
all_values[10]	758687	1			T1	2		T2	3		T3	456
all_values[11]	758687	1			T1	2		T2	3		T3	456
all_values[12]	758687	1			T1	2		T2	3		T3	456
all_values[13]	758687	1			T1	2		T2	3		T3	456
all_values[14]	758687	1			T1	2		T2	3		T3	456

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9383086

1

T1

30

T2

39

T3

6200

auto[1]

1997219

1

T2

6

T3

640

T4

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10624544

1

T1

30

T2

45

T3

6840

auto[1]

755761

1

T19

471594

T106

185

T152

4991

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	106943	1			T1	2		T2	1		T3	359
all_values[0]	auto[0]	auto[1]	6509	1			T106	10		T153	26		T238	1438
all_values[0]	auto[1]	auto[0]	632941	1			T2	2		T3	97		T4	2
all_values[0]	auto[1]	auto[1]	12294	1			T106	4		T153	5		T238	187
all_values[1]	auto[0]	auto[0]	702835	1			T1	2		T2	3		T3	456
all_values[1]	auto[0]	auto[1]	55225	1			T19	36237		T106	12		T152	355
all_values[1]	auto[1]	auto[0]	421	1			T15	26		T161	13		T268	3
all_values[1]	auto[1]	auto[1]	206	1			T19	40		T106	1		T152	2
all_values[2]	auto[0]	auto[0]	703070	1			T1	2		T2	3		T3	456
all_values[2]	auto[0]	auto[1]	55253	1			T19	36275		T106	12		T152	355
all_values[2]	auto[1]	auto[0]	193	1			T4	1		T5	1		T143	1
all_values[2]	auto[1]	auto[1]	171	1			T19	1		T106	1		T152	2
all_values[3]	auto[0]	auto[0]	740029	1			T1	2		T2	3		T3	456
all_values[3]	auto[0]	auto[1]	18448	1			T106	15		T152	353		T153	26
all_values[3]	auto[1]	auto[1]	210	1			T152	4		T153	6		T238	4
all_values[4]	auto[0]	auto[0]	703752	1			T1	2		T2	3		T3	456
all_values[4]	auto[0]	auto[1]	54736	1			T19	36274		T106	13		T152	354
all_values[4]	auto[1]	auto[0]	17	1			T21	2		T144	1		T25	1
all_values[4]	auto[1]	auto[1]	182	1			T19	1		T106	2		T152	3
all_values[5]	auto[0]	auto[0]	703260	1			T1	2		T2	3		T3	456
all_values[5]	auto[0]	auto[1]	55237	1			T19	36273		T106	13		T152	355
all_values[5]	auto[1]	auto[1]	190	1			T19	2		T152	1		T153	5
all_values[6]	auto[0]	auto[0]	703259	1			T1	2		T2	3		T3	456
all_values[6]	auto[0]	auto[1]	55238	1			T19	36273		T106	13		T152	353
all_values[6]	auto[1]	auto[1]	190	1			T19	4		T106	2		T152	4
all_values[7]	auto[0]	auto[0]	677420	1			T1	2		T2	2		T3	372
all_values[7]	auto[0]	auto[1]	52989	1			T19	35578		T106	14		T152	317
all_values[7]	auto[1]	auto[0]	25851	1			T2	1		T3	84		T6	148
all_values[7]	auto[1]	auto[1]	2427	1			T19	699		T152	40		T153	7
all_values[8]	auto[0]	auto[0]	703260	1			T1	2		T2	3		T3	456
all_values[8]	auto[0]	auto[1]	55256	1			T19	36273		T106	14		T152	356
all_values[8]	auto[1]	auto[1]	171	1			T19	3		T106	1		T152	1
all_values[9]	auto[0]	auto[0]	182677	1			T1	2		T2	2		T3	448
all_values[9]	auto[0]	auto[1]	10884	1			T19	3062		T106	13		T152	336
all_values[9]	auto[1]	auto[0]	520579	1			T2	1		T3	8		T6	9
all_values[9]	auto[1]	auto[1]	44547	1			T19	33215		T152	19		T153	5
all_values[10]	auto[0]	auto[0]	703853	1			T1	2		T2	3		T3	456
all_values[10]	auto[0]	auto[1]	54678	1			T19	36274		T106	13		T152	354
all_values[10]	auto[1]	auto[1]	156	1			T19	3		T106	2		T152	2
all_values[11]	auto[0]	auto[0]	2413	1			T1	2		T2	1		T3	5
all_values[11]	auto[0]	auto[1]	395	1			T19	43		T152	8		T153	26
all_values[11]	auto[1]	auto[0]	700859	1			T2	2		T3	451		T4	2
all_values[11]	auto[1]	auto[1]	55020	1			T19	36234		T152	349		T153	4
all_values[12]	auto[0]	auto[0]	703221	1			T1	2		T2	3		T3	456
all_values[12]	auto[0]	auto[1]	55250	1			T19	36276		T106	12		T152	355
all_values[12]	auto[1]	auto[0]	64	1			T51	1		T65	1		T66	1
all_values[12]	auto[1]	auto[1]	152	1			T19	1		T106	3		T152	1
all_values[13]	auto[0]	auto[0]	703277	1			T1	2		T2	3		T3	456
all_values[13]	auto[0]	auto[1]	55228	1			T19	36273		T152	353		T153	28
all_values[13]	auto[1]	auto[1]	182	1			T19	4		T152	3		T153	4
all_values[14]	auto[0]	auto[0]	704350	1			T1	2		T2	3		T3	456
all_values[14]	auto[0]	auto[1]	54141	1			T19	36273		T106	11		T152	355
all_values[14]	auto[1]	auto[1]	196	1			T19	3		T106	4		T152	1