Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	758687	1			T1	2		T2	3		T3	456
all_pins[1]	758687	1			T1	2		T2	3		T3	456
all_pins[2]	758687	1			T1	2		T2	3		T3	456
all_pins[3]	758687	1			T1	2		T2	3		T3	456
all_pins[4]	758687	1			T1	2		T2	3		T3	456
all_pins[5]	758687	1			T1	2		T2	3		T3	456
all_pins[6]	758687	1			T1	2		T2	3		T3	456
all_pins[7]	758687	1			T1	2		T2	3		T3	456
all_pins[8]	758687	1			T1	2		T2	3		T3	456
all_pins[9]	758687	1			T1	2		T2	3		T3	456
all_pins[10]	758687	1			T1	2		T2	3		T3	456
all_pins[11]	758687	1			T1	2		T2	3		T3	456
all_pins[12]	758687	1			T1	2		T2	3		T3	456
all_pins[13]	758687	1			T1	2		T2	3		T3	456
all_pins[14]	758687	1			T1	2		T2	3		T3	456

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9389334	1			T1	30		T2	39		T3	6194
values[0x1]	1990971	1			T2	6		T3	646		T4	3
transitions[0x0=>0x1]	1990091	1			T2	6		T3	646		T4	3
transitions[0x1=>0x0]	1988780	1			T2	5		T3	645		T4	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	117059	1			T1	2		T2	1		T3	359
all_pins[0]	values[0x1]	641628	1			T2	2		T3	97		T4	2
all_pins[0]	transitions[0x0=>0x1]	641077	1			T2	2		T3	97		T4	2
all_pins[0]	transitions[0x1=>0x0]	70	1			T153	2		T36	5		T238	2
all_pins[1]	values[0x0]	758066	1			T1	2		T2	3		T3	456
all_pins[1]	values[0x1]	621	1			T15	37		T161	13		T19	47
all_pins[1]	transitions[0x0=>0x1]	598	1			T15	37		T161	13		T19	47
all_pins[1]	transitions[0x1=>0x0]	113	1			T5	1		T143	1		T273	1
all_pins[2]	values[0x0]	758551	1			T1	2		T2	3		T3	456
all_pins[2]	values[0x1]	136	1			T5	1		T143	1		T273	1
all_pins[2]	transitions[0x0=>0x1]	112	1			T5	1		T143	1		T273	1
all_pins[2]	transitions[0x1=>0x0]	81	1			T152	2		T153	1		T238	1
all_pins[3]	values[0x0]	758582	1			T1	2		T2	3		T3	456
all_pins[3]	values[0x1]	105	1			T152	4		T153	2		T238	2
all_pins[3]	transitions[0x0=>0x1]	79	1			T152	4		T153	2		T238	2
all_pins[3]	transitions[0x1=>0x0]	102	1			T21	2		T144	1		T25	1
all_pins[4]	values[0x0]	758559	1			T1	2		T2	3		T3	456
all_pins[4]	values[0x1]	128	1			T21	2		T144	1		T25	1
all_pins[4]	transitions[0x0=>0x1]	108	1			T21	2		T144	1		T25	1
all_pins[4]	transitions[0x1=>0x0]	73	1			T152	1		T274	1		T237	3
all_pins[5]	values[0x0]	758594	1			T1	2		T2	3		T3	456
all_pins[5]	values[0x1]	93	1			T152	1		T238	1		T274	1
all_pins[5]	transitions[0x0=>0x1]	68	1			T237	3		T127	2		T275	2
all_pins[5]	transitions[0x1=>0x0]	70	1			T19	3		T106	2		T152	1
all_pins[6]	values[0x0]	758592	1			T1	2		T2	3		T3	456
all_pins[6]	values[0x1]	95	1			T19	3		T106	2		T152	2
all_pins[6]	transitions[0x0=>0x1]	71	1			T19	2		T106	2		T153	1
all_pins[6]	transitions[0x1=>0x0]	30905	1			T2	1		T3	90		T6	160
all_pins[7]	values[0x0]	727758	1			T1	2		T2	2		T3	366
all_pins[7]	values[0x1]	30929	1			T2	1		T3	90		T6	160
all_pins[7]	transitions[0x0=>0x1]	30905	1			T2	1		T3	90		T6	160
all_pins[7]	transitions[0x1=>0x0]	77	1			T19	2		T106	1		T153	4
all_pins[8]	values[0x0]	758586	1			T1	2		T2	3		T3	456
all_pins[8]	values[0x1]	101	1			T19	2		T106	1		T153	4
all_pins[8]	transitions[0x0=>0x1]	76	1			T106	1		T153	3		T238	3
all_pins[8]	transitions[0x1=>0x0]	565038	1			T2	1		T3	8		T5	1
all_pins[9]	values[0x0]	193624	1			T1	2		T2	2		T3	448
all_pins[9]	values[0x1]	565063	1			T2	1		T3	8		T5	1
all_pins[9]	transitions[0x0=>0x1]	565049	1			T2	1		T3	8		T5	1
all_pins[9]	transitions[0x1=>0x0]	60	1			T19	1		T106	2		T152	1
all_pins[10]	values[0x0]	758613	1			T1	2		T2	3		T3	456
all_pins[10]	values[0x1]	74	1			T19	3		T106	2		T152	1
all_pins[10]	transitions[0x0=>0x1]	54	1			T19	1		T106	1		T153	2
all_pins[10]	transitions[0x1=>0x0]	751656	1			T2	2		T3	451		T4	1
all_pins[11]	values[0x0]	7011	1			T1	2		T2	1		T3	5
all_pins[11]	values[0x1]	751676	1			T2	2		T3	451		T4	1
all_pins[11]	transitions[0x0=>0x1]	751643	1			T2	2		T3	451		T4	1
all_pins[11]	transitions[0x1=>0x0]	104	1			T51	1		T65	1		T66	1
all_pins[12]	values[0x0]	758550	1			T1	2		T2	3		T3	456
all_pins[12]	values[0x1]	137	1			T51	1		T65	1		T66	1
all_pins[12]	transitions[0x0=>0x1]	122	1			T51	1		T65	1		T66	1
all_pins[12]	transitions[0x1=>0x0]	69	1			T19	2		T152	1		T274	1
all_pins[13]	values[0x0]	758603	1			T1	2		T2	3		T3	456
all_pins[13]	values[0x1]	84	1			T19	2		T152	1		T274	1
all_pins[13]	transitions[0x0=>0x1]	64	1			T19	1		T274	1		T127	1
all_pins[13]	transitions[0x1=>0x0]	81	1			T106	3		T153	1		T238	1
all_pins[14]	values[0x0]	758586	1			T1	2		T2	3		T3	456
all_pins[14]	values[0x1]	101	1			T19	1		T106	3		T152	1
all_pins[14]	transitions[0x0=>0x1]	65	1			T19	1		T106	1		T238	1
all_pins[14]	transitions[0x1=>0x0]	640281	1			T2	1		T3	96		T4	1