Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	401	1			T19	4		T106	4		T152	4
all_values[1]	401	1			T19	4		T106	4		T152	4
all_values[2]	401	1			T19	4		T106	4		T152	4
all_values[3]	401	1			T19	4		T106	4		T152	4
all_values[4]	401	1			T19	4		T106	4		T152	4
all_values[5]	401	1			T19	4		T106	4		T152	4
all_values[6]	401	1			T19	4		T106	4		T152	4
all_values[7]	401	1			T19	4		T106	4		T152	4
all_values[8]	401	1			T19	4		T106	4		T152	4
all_values[9]	401	1			T19	4		T106	4		T152	4
all_values[10]	401	1			T19	4		T106	4		T152	4
all_values[11]	401	1			T19	4		T106	4		T152	4
all_values[12]	401	1			T19	4		T106	4		T152	4
all_values[13]	401	1			T19	4		T106	4		T152	4
all_values[14]	401	1			T19	4		T106	4		T152	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3205

1

T19

40

T106

20

T152

18

auto[1]

2810

1

T19

20

T106

40

T152

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947

1

T19

15

T106

18

T152

11

auto[1]

5068

1

T19

45

T106

42

T152

49

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3524

1

T19

36

T106

38

T152

35

auto[1]

2491

1

T19

24

T106

22

T152

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	37	1			T19	3		T153	2		T275	2
all_values[0]	auto[0]	auto[0]	auto[1]	88	1			T106	1		T153	2		T238	4
all_values[0]	auto[0]	auto[1]	auto[0]	22	1			T19	1		T106	1		T152	4
all_values[0]	auto[0]	auto[1]	auto[1]	91	1			T238	1		T274	1		T237	2
all_values[0]	auto[1]	auto[0]	auto[1]	89	1			T106	1		T153	1		T238	2
all_values[0]	auto[1]	auto[1]	auto[1]	74	1			T106	1		T153	2		T127	2
all_values[1]	auto[0]	auto[0]	auto[0]	31	1			T238	1		T275	5		T276	1
all_values[1]	auto[0]	auto[0]	auto[1]	95	1			T19	1		T106	1		T152	1
all_values[1]	auto[0]	auto[1]	auto[0]	26	1			T106	2		T237	3		T275	3
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T152	1		T153	1		T238	1
all_values[1]	auto[1]	auto[0]	auto[1]	103	1			T19	3		T106	1		T152	1
all_values[1]	auto[1]	auto[1]	auto[1]	65	1			T152	1		T238	2		T274	2
all_values[2]	auto[0]	auto[0]	auto[0]	37	1			T19	1		T106	1		T153	1
all_values[2]	auto[0]	auto[0]	auto[1]	74	1			T19	2		T127	4		T275	4
all_values[2]	auto[0]	auto[1]	auto[0]	29	1			T106	1		T274	2		T237	2
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T106	1		T152	2		T153	2
all_values[2]	auto[1]	auto[0]	auto[1]	96	1			T19	1		T153	3		T238	3
all_values[2]	auto[1]	auto[1]	auto[1]	75	1			T106	1		T152	2		T153	1
all_values[3]	auto[0]	auto[0]	auto[0]	36	1			T19	3		T153	1		T274	4
all_values[3]	auto[0]	auto[0]	auto[1]	91	1			T153	3		T238	1		T237	2
all_values[3]	auto[0]	auto[1]	auto[0]	16	1			T19	1		T127	1		T276	1
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T106	2		T152	3		T238	3
all_values[3]	auto[1]	auto[0]	auto[1]	88	1			T153	2		T238	1		T237	2
all_values[3]	auto[1]	auto[1]	auto[1]	88	1			T106	2		T152	1		T153	1
all_values[4]	auto[0]	auto[0]	auto[0]	34	1			T19	1		T153	1		T275	1
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T19	1		T152	1		T153	1
all_values[4]	auto[0]	auto[1]	auto[0]	28	1			T19	1		T153	1		T238	1
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T106	2		T153	3		T238	2
all_values[4]	auto[1]	auto[0]	auto[1]	85	1			T152	2		T237	2		T127	1
all_values[4]	auto[1]	auto[1]	auto[1]	80	1			T19	1		T106	2		T152	1
all_values[5]	auto[0]	auto[0]	auto[0]	35	1			T19	1		T153	2		T127	1
all_values[5]	auto[0]	auto[0]	auto[1]	90	1			T19	1		T106	1		T152	2
all_values[5]	auto[0]	auto[1]	auto[0]	28	1			T19	1		T106	2		T152	1
all_values[5]	auto[0]	auto[1]	auto[1]	83	1			T238	1		T274	1		T237	3
all_values[5]	auto[1]	auto[0]	auto[1]	87	1			T106	1		T153	2		T238	1
all_values[5]	auto[1]	auto[1]	auto[1]	78	1			T19	1		T152	1		T238	2
all_values[6]	auto[0]	auto[0]	auto[0]	36	1			T238	1		T276	2		T277	1
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T19	1		T106	1		T152	1
all_values[6]	auto[0]	auto[1]	auto[0]	23	1			T237	1		T127	1		T128	1
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T19	1		T106	1		T153	1
all_values[6]	auto[1]	auto[0]	auto[1]	95	1			T19	2		T152	1		T153	1
all_values[6]	auto[1]	auto[1]	auto[1]	79	1			T106	2		T152	2		T153	1
all_values[7]	auto[0]	auto[0]	auto[0]	39	1			T153	1		T238	4		T275	1
all_values[7]	auto[0]	auto[0]	auto[1]	81	1			T19	2		T106	2		T153	1
all_values[7]	auto[0]	auto[1]	auto[0]	31	1			T106	1		T238	1		T237	2
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T152	1		T274	2		T237	3
all_values[7]	auto[1]	auto[0]	auto[1]	87	1			T19	2		T153	5		T238	1
all_values[7]	auto[1]	auto[1]	auto[1]	86	1			T106	1		T152	3		T274	1
all_values[8]	auto[0]	auto[0]	auto[0]	32	1			T19	1		T276	1		T129	2
all_values[8]	auto[0]	auto[0]	auto[1]	77	1			T106	2		T152	1		T274	2
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T237	1		T127	1		T23	1
all_values[8]	auto[0]	auto[1]	auto[1]	101	1			T19	1		T152	2		T153	3
all_values[8]	auto[1]	auto[0]	auto[1]	79	1			T19	2		T153	2		T274	1
all_values[8]	auto[1]	auto[1]	auto[1]	84	1			T106	2		T152	1		T153	2
all_values[9]	auto[0]	auto[0]	auto[0]	38	1			T106	1		T152	1		T238	5
all_values[9]	auto[0]	auto[0]	auto[1]	82	1			T19	1		T106	1		T153	2
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T106	1		T152	1		T278	1
all_values[9]	auto[0]	auto[1]	auto[1]	98	1			T19	1		T152	1		T153	2
all_values[9]	auto[1]	auto[0]	auto[1]	97	1			T19	2		T106	1		T153	1
all_values[9]	auto[1]	auto[1]	auto[1]	67	1			T152	1		T153	2		T127	2
all_values[10]	auto[0]	auto[0]	auto[0]	35	1			T238	1		T279	4		T277	2
all_values[10]	auto[0]	auto[0]	auto[1]	92	1			T152	1		T153	3		T274	1
all_values[10]	auto[0]	auto[1]	auto[0]	34	1			T152	1		T274	1		T127	1
all_values[10]	auto[0]	auto[1]	auto[1]	84	1			T19	1		T106	2		T238	3
all_values[10]	auto[1]	auto[0]	auto[1]	94	1			T19	1		T152	1		T153	3
all_values[10]	auto[1]	auto[1]	auto[1]	62	1			T19	2		T106	2		T152	1
all_values[11]	auto[0]	auto[0]	auto[0]	38	1			T106	1		T153	2		T275	1
all_values[11]	auto[0]	auto[0]	auto[1]	86	1			T19	1		T238	1		T274	2
all_values[11]	auto[0]	auto[1]	auto[0]	23	1			T106	3		T153	1		T237	1
all_values[11]	auto[0]	auto[1]	auto[1]	82	1			T152	2		T153	2		T238	1
all_values[11]	auto[1]	auto[0]	auto[1]	96	1			T19	1		T238	2		T237	2
all_values[11]	auto[1]	auto[1]	auto[1]	76	1			T19	2		T152	2		T153	2
all_values[12]	auto[0]	auto[0]	auto[0]	41	1			T153	1		T274	1		T279	1
all_values[12]	auto[0]	auto[0]	auto[1]	97	1			T19	1		T152	2		T153	2
all_values[12]	auto[0]	auto[1]	auto[0]	39	1			T152	1		T238	1		T275	3
all_values[12]	auto[0]	auto[1]	auto[1]	72	1			T19	2		T106	1		T153	1
all_values[12]	auto[1]	auto[0]	auto[1]	78	1			T19	1		T152	1		T153	2
all_values[12]	auto[1]	auto[1]	auto[1]	74	1			T106	3		T153	1		T238	1
all_values[13]	auto[0]	auto[0]	auto[0]	38	1			T106	3		T153	1		T238	2
all_values[13]	auto[0]	auto[0]	auto[1]	95	1			T19	1		T152	1		T153	1
all_values[13]	auto[0]	auto[1]	auto[0]	30	1			T106	1		T152	1		T238	2
all_values[13]	auto[0]	auto[1]	auto[1]	75	1			T19	2		T153	1		T237	2
all_values[13]	auto[1]	auto[0]	auto[1]	89	1			T19	1		T152	1		T153	2
all_values[13]	auto[1]	auto[1]	auto[1]	74	1			T152	1		T153	2		T238	1
all_values[14]	auto[0]	auto[0]	auto[0]	41	1			T19	1		T238	2		T274	4
all_values[14]	auto[0]	auto[0]	auto[1]	86	1			T19	1		T153	2		T127	6
all_values[14]	auto[0]	auto[1]	auto[0]	23	1			T152	1		T237	1		T279	3
all_values[14]	auto[0]	auto[1]	auto[1]	85	1			T106	2		T152	2		T153	3
all_values[14]	auto[1]	auto[0]	auto[1]	95	1			T106	1		T153	1		T238	2
all_values[14]	auto[1]	auto[1]	auto[1]	71	1			T19	2		T106	1		T152	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal