Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	679460	1			T1	2		T2	1		T3	3
all_values[1]	679460	1			T1	2		T2	1		T3	3
all_values[2]	679460	1			T1	2		T2	1		T3	3
all_values[3]	679460	1			T1	2		T2	1		T3	3
all_values[4]	679460	1			T1	2		T2	1		T3	3
all_values[5]	679460	1			T1	2		T2	1		T3	3
all_values[6]	679460	1			T1	2		T2	1		T3	3
all_values[7]	679460	1			T1	2		T2	1		T3	3
all_values[8]	679460	1			T1	2		T2	1		T3	3
all_values[9]	679460	1			T1	2		T2	1		T3	3
all_values[10]	679460	1			T1	2		T2	1		T3	3
all_values[11]	679460	1			T1	2		T2	1		T3	3
all_values[12]	679460	1			T1	2		T2	1		T3	3
all_values[13]	679460	1			T1	2		T2	1		T3	3
all_values[14]	679460	1			T1	2		T2	1		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8412057

1

T1

26

T2

15

T3

39

auto[1]

1779843

1

T1

4

T3

6

T4

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10008682

1

T1

30

T2

15

T3

45

auto[1]

183218

1

T182

159370

T117

72

T183

202

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	107648	1			T2	1		T3	1		T6	17
all_values[0]	auto[0]	auto[1]	955	1			T182	17		T243	5		T244	19
all_values[0]	auto[1]	auto[0]	559602	1			T1	2		T3	2		T4	4
all_values[0]	auto[1]	auto[1]	11255	1			T182	10607		T183	12		T243	3
all_values[1]	auto[0]	auto[0]	666839	1			T1	2		T2	1		T3	3
all_values[1]	auto[0]	auto[1]	12056	1			T182	10608		T117	3		T183	11
all_values[1]	auto[1]	auto[0]	421	1			T30	1		T278	49		T279	6
all_values[1]	auto[1]	auto[1]	144	1			T182	16		T117	1		T183	3
all_values[2]	auto[0]	auto[0]	667052	1			T1	2		T2	1		T3	3
all_values[2]	auto[0]	auto[1]	12083	1			T182	10620		T117	4		T183	11
all_values[2]	auto[1]	auto[0]	187	1			T7	1		T164	1		T166	2
all_values[2]	auto[1]	auto[1]	138	1			T182	6		T117	1		T183	2
all_values[3]	auto[0]	auto[0]	667257	1			T1	2		T2	1		T3	3
all_values[3]	auto[0]	auto[1]	12063	1			T182	10623		T117	2		T183	8
all_values[3]	auto[1]	auto[1]	140	1			T182	3		T117	4		T183	5
all_values[4]	auto[0]	auto[0]	667237	1			T1	2		T2	1		T3	3
all_values[4]	auto[0]	auto[1]	12084	1			T182	10623		T117	4		T183	8
all_values[4]	auto[1]	auto[0]	9	1			T275	1		T24	2		T271	1
all_values[4]	auto[1]	auto[1]	130	1			T182	3		T117	2		T183	6
all_values[5]	auto[0]	auto[0]	667237	1			T1	2		T2	1		T3	3
all_values[5]	auto[0]	auto[1]	12069	1			T182	10620		T117	3		T183	8
all_values[5]	auto[1]	auto[1]	154	1			T182	4		T117	3		T183	6
all_values[6]	auto[0]	auto[0]	667227	1			T1	2		T2	1		T3	3
all_values[6]	auto[0]	auto[1]	12048	1			T182	10617		T117	4		T183	9
all_values[6]	auto[1]	auto[1]	185	1			T182	9		T117	2		T183	5
all_values[7]	auto[0]	auto[0]	641306	1			T1	2		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	11664	1			T182	10529		T183	9		T243	7
all_values[7]	auto[1]	auto[0]	25951	1			T3	1		T6	8		T8	1
all_values[7]	auto[1]	auto[1]	539	1			T182	94		T183	4		T243	2
all_values[8]	auto[0]	auto[0]	667259	1			T1	2		T2	1		T3	3
all_values[8]	auto[0]	auto[1]	12030	1			T182	10619		T117	2		T183	6
all_values[8]	auto[1]	auto[1]	171	1			T182	5		T117	3		T183	8
all_values[9]	auto[0]	auto[0]	174510	1			T1	2		T2	1		T3	2
all_values[9]	auto[0]	auto[1]	1680	1			T182	247		T117	2		T183	7
all_values[9]	auto[1]	auto[0]	492748	1			T3	1		T4	1		T6	4
all_values[9]	auto[1]	auto[1]	10522	1			T182	10375		T117	4		T183	7
all_values[10]	auto[0]	auto[0]	667242	1			T1	2		T2	1		T3	3
all_values[10]	auto[0]	auto[1]	12081	1			T182	10620		T117	5		T183	12
all_values[10]	auto[1]	auto[1]	137	1			T182	5		T117	1		T183	2
all_values[11]	auto[0]	auto[0]	2379	1			T2	1		T3	1		T6	4
all_values[11]	auto[0]	auto[1]	216	1			T182	18		T243	5		T244	19
all_values[11]	auto[1]	auto[0]	664866	1			T1	2		T3	2		T4	4
all_values[11]	auto[1]	auto[1]	11999	1			T182	10608		T117	6		T183	13
all_values[12]	auto[0]	auto[0]	667174	1			T1	2		T2	1		T3	3
all_values[12]	auto[0]	auto[1]	12078	1			T182	10623		T117	4		T183	8
all_values[12]	auto[1]	auto[0]	59	1			T54	1		T56	1		T71	1
all_values[12]	auto[1]	auto[1]	149	1			T182	3		T117	2		T183	5
all_values[13]	auto[0]	auto[0]	667230	1			T1	2		T2	1		T3	3
all_values[13]	auto[0]	auto[1]	12062	1			T182	10622		T117	2		T183	5
all_values[13]	auto[1]	auto[1]	168	1			T182	3		T117	4		T183	8
all_values[14]	auto[0]	auto[0]	667242	1			T1	2		T2	1		T3	3
all_values[14]	auto[0]	auto[1]	12049	1			T182	10620		T117	2		T183	8
all_values[14]	auto[1]	auto[1]	169	1			T182	3		T117	2		T183	6