Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	679460	1			T1	2		T2	1		T3	3
all_pins[1]	679460	1			T1	2		T2	1		T3	3
all_pins[2]	679460	1			T1	2		T2	1		T3	3
all_pins[3]	679460	1			T1	2		T2	1		T3	3
all_pins[4]	679460	1			T1	2		T2	1		T3	3
all_pins[5]	679460	1			T1	2		T2	1		T3	3
all_pins[6]	679460	1			T1	2		T2	1		T3	3
all_pins[7]	679460	1			T1	2		T2	1		T3	3
all_pins[8]	679460	1			T1	2		T2	1		T3	3
all_pins[9]	679460	1			T1	2		T2	1		T3	3
all_pins[10]	679460	1			T1	2		T2	1		T3	3
all_pins[11]	679460	1			T1	2		T2	1		T3	3
all_pins[12]	679460	1			T1	2		T2	1		T3	3
all_pins[13]	679460	1			T1	2		T2	1		T3	3
all_pins[14]	679460	1			T1	2		T2	1		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8418205	1			T1	26		T2	15		T3	39
values[0x1]	1773695	1			T1	4		T3	6		T4	9
transitions[0x0=>0x1]	1772879	1			T1	4		T3	6		T4	9
transitions[0x1=>0x0]	1771578	1			T1	3		T3	5		T4	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	112055	1			T2	1		T3	1		T6	74
all_pins[0]	values[0x1]	567405	1			T1	2		T3	2		T4	4
all_pins[0]	transitions[0x0=>0x1]	566862	1			T1	2		T3	2		T4	4
all_pins[0]	transitions[0x1=>0x0]	50	1			T277	1		T182	1		T117	1
all_pins[1]	values[0x0]	678867	1			T1	2		T2	1		T3	3
all_pins[1]	values[0x1]	593	1			T30	1		T278	54		T279	8
all_pins[1]	transitions[0x0=>0x1]	578	1			T30	1		T278	54		T279	8
all_pins[1]	transitions[0x1=>0x0]	102	1			T7	1		T291	1		T292	1
all_pins[2]	values[0x0]	679343	1			T1	2		T2	1		T3	3
all_pins[2]	values[0x1]	117	1			T7	1		T291	1		T292	1
all_pins[2]	transitions[0x0=>0x1]	104	1			T7	1		T291	1		T292	1
all_pins[2]	transitions[0x1=>0x0]	59	1			T182	2		T117	2		T183	3
all_pins[3]	values[0x0]	679388	1			T1	2		T2	1		T3	3
all_pins[3]	values[0x1]	72	1			T182	3		T117	2		T183	3
all_pins[3]	transitions[0x0=>0x1]	52	1			T182	2		T117	1		T183	3
all_pins[3]	transitions[0x1=>0x0]	57	1			T275	1		T24	2		T293	1
all_pins[4]	values[0x0]	679383	1			T1	2		T2	1		T3	3
all_pins[4]	values[0x1]	77	1			T275	1		T24	2		T293	1
all_pins[4]	transitions[0x0=>0x1]	56	1			T275	1		T24	2		T293	1
all_pins[4]	transitions[0x1=>0x0]	63	1			T182	2		T117	2		T183	3
all_pins[5]	values[0x0]	679376	1			T1	2		T2	1		T3	3
all_pins[5]	values[0x1]	84	1			T182	2		T117	3		T183	4
all_pins[5]	transitions[0x0=>0x1]	65	1			T182	2		T117	2		T183	2
all_pins[5]	transitions[0x1=>0x0]	65	1			T182	2		T183	1		T243	3
all_pins[6]	values[0x0]	679376	1			T1	2		T2	1		T3	3
all_pins[6]	values[0x1]	84	1			T182	2		T117	1		T183	3
all_pins[6]	transitions[0x0=>0x1]	69	1			T182	2		T117	1		T183	3
all_pins[6]	transitions[0x1=>0x0]	28659	1			T3	1		T8	1		T10	1
all_pins[7]	values[0x0]	650786	1			T1	2		T2	1		T3	2
all_pins[7]	values[0x1]	28674	1			T3	1		T8	1		T10	1
all_pins[7]	transitions[0x0=>0x1]	28649	1			T3	1		T8	1		T10	1
all_pins[7]	transitions[0x1=>0x0]	65	1			T182	3		T117	3		T183	3
all_pins[8]	values[0x0]	679370	1			T1	2		T2	1		T3	3
all_pins[8]	values[0x1]	90	1			T182	3		T117	3		T183	4
all_pins[8]	transitions[0x0=>0x1]	78	1			T182	3		T117	3		T183	4
all_pins[8]	transitions[0x1=>0x0]	503193	1			T3	1		T4	1		T6	4
all_pins[9]	values[0x0]	176255	1			T1	2		T2	1		T3	2
all_pins[9]	values[0x1]	503205	1			T3	1		T4	1		T6	4
all_pins[9]	transitions[0x0=>0x1]	503188	1			T3	1		T4	1		T6	4
all_pins[9]	transitions[0x1=>0x0]	64	1			T182	3		T117	1		T183	1
all_pins[10]	values[0x0]	679379	1			T1	2		T2	1		T3	3
all_pins[10]	values[0x1]	81	1			T182	3		T117	1		T183	1
all_pins[10]	transitions[0x0=>0x1]	60	1			T182	1		T117	1		T183	1
all_pins[10]	transitions[0x1=>0x0]	672888	1			T1	2		T3	2		T4	4
all_pins[11]	values[0x0]	6551	1			T2	1		T3	1		T6	74
all_pins[11]	values[0x1]	672909	1			T1	2		T3	2		T4	4
all_pins[11]	transitions[0x0=>0x1]	672884	1			T1	2		T3	2		T4	4
all_pins[11]	transitions[0x1=>0x0]	105	1			T54	1		T56	1		T71	1
all_pins[12]	values[0x0]	679330	1			T1	2		T2	1		T3	3
all_pins[12]	values[0x1]	130	1			T54	1		T56	1		T71	1
all_pins[12]	transitions[0x0=>0x1]	115	1			T54	1		T56	1		T71	1
all_pins[12]	transitions[0x1=>0x0]	70	1			T117	2		T183	7		T243	1
all_pins[13]	values[0x0]	679375	1			T1	2		T2	1		T3	3
all_pins[13]	values[0x1]	85	1			T117	3		T183	7		T243	1
all_pins[13]	transitions[0x0=>0x1]	61	1			T117	3		T183	3		T243	1
all_pins[13]	transitions[0x1=>0x0]	65	1			T182	2		T183	2		T243	1
all_pins[14]	values[0x0]	679371	1			T1	2		T2	1		T3	3
all_pins[14]	values[0x1]	89	1			T182	2		T183	6		T243	1
all_pins[14]	transitions[0x0=>0x1]	58	1			T182	1		T183	2		T294	2
all_pins[14]	transitions[0x1=>0x0]	566073	1			T1	1		T3	1		T4	3