Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	351	1			T182	11		T117	4		T183	11
all_values[1]	351	1			T182	11		T117	4		T183	11
all_values[2]	351	1			T182	11		T117	4		T183	11
all_values[3]	351	1			T182	11		T117	4		T183	11
all_values[4]	351	1			T182	11		T117	4		T183	11
all_values[5]	351	1			T182	11		T117	4		T183	11
all_values[6]	351	1			T182	11		T117	4		T183	11
all_values[7]	351	1			T182	11		T117	4		T183	11
all_values[8]	351	1			T182	11		T117	4		T183	11
all_values[9]	351	1			T182	11		T117	4		T183	11
all_values[10]	351	1			T182	11		T117	4		T183	11
all_values[11]	351	1			T182	11		T117	4		T183	11
all_values[12]	351	1			T182	11		T117	4		T183	11
all_values[13]	351	1			T182	11		T117	4		T183	11
all_values[14]	351	1			T182	11		T117	4		T183	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2717

1

T182

79

T117

28

T183

82

auto[1]

2548

1

T182

86

T117

32

T183

83

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

828

1

T182

20

T117

14

T183

8

auto[1]

4437

1

T182

145

T117

46

T183

157

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3135

1

T182

107

T117

37

T183

104

auto[1]

2130

1

T182

58

T117

23

T183

61

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1			T117	2		T183	1		T243	1
all_values[0]	auto[0]	auto[0]	auto[1]	66	1			T182	5		T183	1		T244	6
all_values[0]	auto[0]	auto[1]	auto[0]	28	1			T182	2		T117	2		T183	1
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T183	4		T243	3		T244	7
all_values[0]	auto[1]	auto[0]	auto[1]	84	1			T182	3		T183	2		T243	1
all_values[0]	auto[1]	auto[1]	auto[1]	63	1			T182	1		T183	2		T243	2
all_values[1]	auto[0]	auto[0]	auto[0]	33	1			T244	1		T294	1		T295	2
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T182	2		T183	4		T243	1
all_values[1]	auto[0]	auto[1]	auto[0]	35	1			T182	2		T117	2		T243	1
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T182	3		T117	1		T183	4
all_values[1]	auto[1]	auto[0]	auto[1]	72	1			T182	3		T244	4		T295	1
all_values[1]	auto[1]	auto[1]	auto[1]	60	1			T182	1		T117	1		T183	3
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T117	1		T130	2		T296	3
all_values[2]	auto[0]	auto[0]	auto[1]	92	1			T182	1		T183	3		T243	3
all_values[2]	auto[0]	auto[1]	auto[0]	19	1			T183	1		T297	1		T294	2
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T182	4		T117	2		T183	5
all_values[2]	auto[1]	auto[0]	auto[1]	78	1			T182	1		T117	1		T243	2
all_values[2]	auto[1]	auto[1]	auto[1]	60	1			T182	5		T183	2		T243	1
all_values[3]	auto[0]	auto[0]	auto[0]	33	1			T130	2		T298	1		T299	1
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T182	4		T117	1		T183	5
all_values[3]	auto[0]	auto[1]	auto[0]	32	1			T183	1		T296	4		T300	1
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T182	2		T183	1		T243	3
all_values[3]	auto[1]	auto[0]	auto[1]	64	1			T182	1		T117	1		T183	2
all_values[3]	auto[1]	auto[1]	auto[1]	73	1			T182	4		T117	2		T183	2
all_values[4]	auto[0]	auto[0]	auto[0]	35	1			T244	1		T130	2		T296	4
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T182	5		T117	1		T183	3
all_values[4]	auto[0]	auto[1]	auto[0]	22	1			T129	2		T294	1		T301	1
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T182	3		T117	1		T183	2
all_values[4]	auto[1]	auto[0]	auto[1]	61	1			T182	1		T117	1		T183	3
all_values[4]	auto[1]	auto[1]	auto[1]	69	1			T182	2		T117	1		T183	3
all_values[5]	auto[0]	auto[0]	auto[0]	31	1			T129	1		T302	2		T300	1
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T182	4		T183	2		T243	3
all_values[5]	auto[0]	auto[1]	auto[0]	17	1			T182	2		T129	1		T294	1
all_values[5]	auto[0]	auto[1]	auto[1]	89	1			T182	2		T117	2		T183	3
all_values[5]	auto[1]	auto[0]	auto[1]	61	1			T182	2		T183	2		T243	1
all_values[5]	auto[1]	auto[1]	auto[1]	84	1			T182	1		T117	2		T183	4
all_values[6]	auto[0]	auto[0]	auto[0]	20	1			T297	1		T295	2		T130	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T182	4		T117	2		T183	3
all_values[6]	auto[0]	auto[1]	auto[0]	18	1			T243	1		T302	2		T130	1
all_values[6]	auto[0]	auto[1]	auto[1]	68	1			T182	1		T183	5		T243	2
all_values[6]	auto[1]	auto[0]	auto[1]	82	1			T182	4		T183	1		T243	1
all_values[6]	auto[1]	auto[1]	auto[1]	80	1			T182	2		T117	2		T183	2
all_values[7]	auto[0]	auto[0]	auto[0]	33	1			T182	3		T117	4		T294	1
all_values[7]	auto[0]	auto[0]	auto[1]	72	1			T182	1		T183	5		T243	1
all_values[7]	auto[0]	auto[1]	auto[0]	31	1			T183	1		T244	1		T302	1
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T182	4		T183	1		T243	2
all_values[7]	auto[1]	auto[0]	auto[1]	70	1			T182	1		T183	2		T243	2
all_values[7]	auto[1]	auto[1]	auto[1]	62	1			T182	2		T183	2		T243	2
all_values[8]	auto[0]	auto[0]	auto[0]	39	1			T182	2		T117	1		T297	1
all_values[8]	auto[0]	auto[0]	auto[1]	66	1			T182	4		T183	3		T243	2
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T296	2		T303	1		T301	2
all_values[8]	auto[0]	auto[1]	auto[1]	71	1			T182	1		T117	1		T183	3
all_values[8]	auto[1]	auto[0]	auto[1]	76	1			T182	2		T117	1		T183	4
all_values[8]	auto[1]	auto[1]	auto[1]	71	1			T182	2		T117	1		T183	1
all_values[9]	auto[0]	auto[0]	auto[0]	41	1			T182	1		T297	1		T294	1
all_values[9]	auto[0]	auto[0]	auto[1]	72	1			T117	2		T183	3		T243	2
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T182	3		T243	4		T294	1
all_values[9]	auto[0]	auto[1]	auto[1]	75	1			T182	6		T183	2		T244	8
all_values[9]	auto[1]	auto[0]	auto[1]	78	1			T182	1		T117	2		T183	3
all_values[9]	auto[1]	auto[1]	auto[1]	59	1			T183	3		T243	1		T244	3
all_values[10]	auto[0]	auto[0]	auto[0]	39	1			T182	1		T297	1		T294	1
all_values[10]	auto[0]	auto[0]	auto[1]	74	1			T182	2		T183	7		T243	1
all_values[10]	auto[0]	auto[1]	auto[0]	14	1			T244	1		T303	2		T304	1
all_values[10]	auto[0]	auto[1]	auto[1]	87	1			T182	3		T117	3		T183	2
all_values[10]	auto[1]	auto[0]	auto[1]	63	1			T182	3		T183	1		T244	3
all_values[10]	auto[1]	auto[1]	auto[1]	74	1			T182	2		T117	1		T183	1
all_values[11]	auto[0]	auto[0]	auto[0]	26	1			T243	1		T130	1		T298	1
all_values[11]	auto[0]	auto[0]	auto[1]	84	1			T182	1		T117	1		T183	5
all_values[11]	auto[0]	auto[1]	auto[0]	29	1			T183	1		T244	1		T296	1
all_values[11]	auto[0]	auto[1]	auto[1]	77	1			T182	4		T117	2		T183	2
all_values[11]	auto[1]	auto[0]	auto[1]	74	1			T182	2		T117	1		T183	3
all_values[11]	auto[1]	auto[1]	auto[1]	61	1			T182	4		T243	1		T244	5
all_values[12]	auto[0]	auto[0]	auto[0]	23	1			T243	2		T297	2		T302	1
all_values[12]	auto[0]	auto[0]	auto[1]	73	1			T182	2		T117	2		T183	4
all_values[12]	auto[0]	auto[1]	auto[0]	22	1			T183	1		T243	2		T300	1
all_values[12]	auto[0]	auto[1]	auto[1]	84	1			T182	6		T183	1		T244	8
all_values[12]	auto[1]	auto[0]	auto[1]	85	1			T182	2		T183	4		T243	1
all_values[12]	auto[1]	auto[1]	auto[1]	64	1			T182	1		T117	2		T183	1
all_values[13]	auto[0]	auto[0]	auto[0]	24	1			T244	2		T294	1		T130	1
all_values[13]	auto[0]	auto[0]	auto[1]	75	1			T182	4		T183	1		T244	8
all_values[13]	auto[0]	auto[1]	auto[0]	17	1			T182	1		T183	1		T129	1
all_values[13]	auto[0]	auto[1]	auto[1]	84	1			T182	3		T117	1		T183	5
all_values[13]	auto[1]	auto[0]	auto[1]	79	1			T182	1		T183	1		T243	2
all_values[13]	auto[1]	auto[1]	auto[1]	72	1			T182	2		T117	3		T183	3
all_values[14]	auto[0]	auto[0]	auto[0]	38	1			T182	3		T117	2		T243	2
all_values[14]	auto[0]	auto[0]	auto[1]	61	1			T182	2		T117	1		T183	3
all_values[14]	auto[0]	auto[1]	auto[0]	14	1			T129	1		T297	3		T298	1
all_values[14]	auto[0]	auto[1]	auto[1]	87	1			T182	4		T183	4		T243	2
all_values[14]	auto[1]	auto[0]	auto[1]	88	1			T182	1		T117	1		T183	1
all_values[14]	auto[1]	auto[1]	auto[1]	63	1			T182	1		T183	3		T243	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal