Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	642796	1			T1	2		T2	2		T3	4051
all_values[1]	642796	1			T1	2		T2	2		T3	4051
all_values[2]	642796	1			T1	2		T2	2		T3	4051
all_values[3]	642796	1			T1	2		T2	2		T3	4051
all_values[4]	642796	1			T1	2		T2	2		T3	4051
all_values[5]	642796	1			T1	2		T2	2		T3	4051
all_values[6]	642796	1			T1	2		T2	2		T3	4051
all_values[7]	642796	1			T1	2		T2	2		T3	4051
all_values[8]	642796	1			T1	2		T2	2		T3	4051
all_values[9]	642796	1			T1	2		T2	2		T3	4051
all_values[10]	642796	1			T1	2		T2	2		T3	4051
all_values[11]	642796	1			T1	2		T2	2		T3	4051
all_values[12]	642796	1			T1	2		T2	2		T3	4051
all_values[13]	642796	1			T1	2		T2	2		T3	4051
all_values[14]	642796	1			T1	2		T2	2		T3	4051

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7924791

1

T1

26

T2

26

T3

48915

auto[1]

1717149

1

T1

4

T2

4

T3

11850

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9449934

1

T1

30

T2

30

T3

60765

auto[1]

192006

1

T177

64486

T178

278

T179

128

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	86240	1			T3	369		T6	16		T7	23
all_values[0]	auto[0]	auto[1]	675	1			T177	338		T178	10		T179	8
all_values[0]	auto[1]	auto[0]	550011	1			T1	2		T2	2		T3	3682
all_values[0]	auto[1]	auto[1]	5870	1			T177	5523		T178	9		T179	1
all_values[1]	auto[0]	auto[0]	627678	1			T1	2		T2	2		T3	4051
all_values[1]	auto[0]	auto[1]	14785	1			T177	5860		T178	10		T179	5
all_values[1]	auto[1]	auto[0]	192	1			T6	3		T193	1		T287	1
all_values[1]	auto[1]	auto[1]	141	1			T177	1		T178	9		T179	3
all_values[2]	auto[0]	auto[0]	627712	1			T1	2		T2	2		T3	4051
all_values[2]	auto[0]	auto[1]	14783	1			T177	5861		T178	13		T179	7
all_values[2]	auto[1]	auto[0]	186	1			T8	1		T90	1		T288	1
all_values[2]	auto[1]	auto[1]	115	1			T177	1		T178	4		T179	2
all_values[3]	auto[0]	auto[0]	633728	1			T1	2		T2	2		T3	4051
all_values[3]	auto[0]	auto[1]	8923	1			T178	7		T179	3		T127	8374
all_values[3]	auto[1]	auto[1]	145	1			T178	12		T179	6		T127	2
all_values[4]	auto[0]	auto[0]	627842	1			T1	2		T2	2		T3	4051
all_values[4]	auto[0]	auto[1]	14803	1			T177	5862		T178	12		T179	5
all_values[4]	auto[1]	auto[0]	21	1			T23	1		T278	1		T264	1
all_values[4]	auto[1]	auto[1]	130	1			T177	1		T178	6		T179	3
all_values[5]	auto[0]	auto[0]	627883	1			T1	2		T2	2		T3	4051
all_values[5]	auto[0]	auto[1]	14756	1			T177	5860		T178	8		T179	3
all_values[5]	auto[1]	auto[1]	157	1			T177	3		T178	11		T179	4
all_values[6]	auto[0]	auto[0]	627879	1			T1	2		T2	2		T3	4051
all_values[6]	auto[0]	auto[1]	14779	1			T177	5859		T178	8		T179	8
all_values[6]	auto[1]	auto[1]	138	1			T177	4		T178	11		T179	1
all_values[7]	auto[0]	auto[0]	610416	1			T1	2		T2	2		T3	3926
all_values[7]	auto[0]	auto[1]	8594	1			T178	8		T179	3		T127	8103
all_values[7]	auto[1]	auto[0]	23313	1			T3	125		T6	46		T7	14
all_values[7]	auto[1]	auto[1]	473	1			T178	10		T179	6		T127	273
all_values[8]	auto[0]	auto[0]	633732	1			T1	2		T2	2		T3	4051
all_values[8]	auto[0]	auto[1]	8907	1			T178	13		T179	4		T127	8374
all_values[8]	auto[1]	auto[1]	157	1			T178	4		T179	5		T127	1
all_values[9]	auto[0]	auto[0]	146892	1			T1	2		T2	2		T3	50
all_values[9]	auto[0]	auto[1]	720	1			T177	76		T178	14		T179	5
all_values[9]	auto[1]	auto[0]	480973	1			T3	4001		T6	13		T7	12
all_values[9]	auto[1]	auto[1]	14211	1			T177	5786		T178	5		T179	2
all_values[10]	auto[0]	auto[0]	633745	1			T1	2		T2	2		T3	4051
all_values[10]	auto[0]	auto[1]	8933	1			T178	15		T179	5		T127	8373
all_values[10]	auto[1]	auto[1]	118	1			T178	4		T179	4		T127	1
all_values[11]	auto[0]	auto[0]	2314	1			T3	9		T6	2		T7	5
all_values[11]	auto[0]	auto[1]	205	1			T178	14		T179	6		T127	18
all_values[11]	auto[1]	auto[0]	625564	1			T1	2		T2	2		T3	4042
all_values[11]	auto[1]	auto[1]	14713	1			T177	5863		T178	5		T179	3
all_values[12]	auto[0]	auto[0]	627809	1			T1	2		T2	2		T3	4051
all_values[12]	auto[0]	auto[1]	14787	1			T177	5861		T178	12		T179	6
all_values[12]	auto[1]	auto[0]	66	1			T68	1		T69	1		T70	1
all_values[12]	auto[1]	auto[1]	134	1			T177	2		T178	7		T179	3
all_values[13]	auto[0]	auto[0]	627882	1			T1	2		T2	2		T3	4051
all_values[13]	auto[0]	auto[1]	14763	1			T177	5860		T178	10		T179	3
all_values[13]	auto[1]	auto[1]	151	1			T177	3		T178	9		T179	6
all_values[14]	auto[0]	auto[0]	627856	1			T1	2		T2	2		T3	4051
all_values[14]	auto[0]	auto[1]	14770	1			T177	5860		T178	9		T179	3
all_values[14]	auto[1]	auto[1]	170	1			T177	2		T178	9		T179	5