Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	642796	1			T1	2		T2	2		T3	4051
all_pins[1]	642796	1			T1	2		T2	2		T3	4051
all_pins[2]	642796	1			T1	2		T2	2		T3	4051
all_pins[3]	642796	1			T1	2		T2	2		T3	4051
all_pins[4]	642796	1			T1	2		T2	2		T3	4051
all_pins[5]	642796	1			T1	2		T2	2		T3	4051
all_pins[6]	642796	1			T1	2		T2	2		T3	4051
all_pins[7]	642796	1			T1	2		T2	2		T3	4051
all_pins[8]	642796	1			T1	2		T2	2		T3	4051
all_pins[9]	642796	1			T1	2		T2	2		T3	4051
all_pins[10]	642796	1			T1	2		T2	2		T3	4051
all_pins[11]	642796	1			T1	2		T2	2		T3	4051
all_pins[12]	642796	1			T1	2		T2	2		T3	4051
all_pins[13]	642796	1			T1	2		T2	2		T3	4051
all_pins[14]	642796	1			T1	2		T2	2		T3	4051

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7931009	1			T1	28		T2	26		T3	48903
values[0x1]	1710931	1			T1	2		T2	4		T3	11862
transitions[0x0=>0x1]	1710407	1			T1	2		T2	4		T3	11862
transitions[0x1=>0x0]	1709104	1			T1	2		T2	3		T3	11861

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	90326	1			T1	1		T3	368		T6	16
all_pins[0]	values[0x1]	552470	1			T1	1		T2	2		T3	3683
all_pins[0]	transitions[0x0=>0x1]	552225	1			T1	1		T2	2		T3	3683
all_pins[0]	transitions[0x1=>0x0]	56	1			T6	3		T178	3		T271	1
all_pins[1]	values[0x0]	642495	1			T1	2		T2	2		T3	4051
all_pins[1]	values[0x1]	301	1			T6	4		T193	1		T287	1
all_pins[1]	transitions[0x0=>0x1]	290	1			T6	4		T193	1		T287	1
all_pins[1]	transitions[0x1=>0x0]	94	1			T90	1		T288	1		T172	1
all_pins[2]	values[0x0]	642691	1			T1	2		T2	2		T3	4051
all_pins[2]	values[0x1]	105	1			T90	1		T288	1		T172	1
all_pins[2]	transitions[0x0=>0x1]	91	1			T90	1		T288	1		T172	1
all_pins[2]	transitions[0x1=>0x0]	59	1			T178	6		T179	1		T246	1
all_pins[3]	values[0x0]	642723	1			T1	2		T2	2		T3	4051
all_pins[3]	values[0x1]	73	1			T178	7		T179	1		T246	1
all_pins[3]	transitions[0x0=>0x1]	51	1			T178	5		T179	1		T246	1
all_pins[3]	transitions[0x1=>0x0]	62	1			T23	1		T278	1		T264	2
all_pins[4]	values[0x0]	642712	1			T1	2		T2	2		T3	4051
all_pins[4]	values[0x1]	84	1			T23	1		T278	1		T264	2
all_pins[4]	transitions[0x0=>0x1]	68	1			T23	1		T278	1		T264	2
all_pins[4]	transitions[0x1=>0x0]	75	1			T177	3		T178	5		T127	2
all_pins[5]	values[0x0]	642705	1			T1	2		T2	2		T3	4051
all_pins[5]	values[0x1]	91	1			T177	3		T178	5		T179	1
all_pins[5]	transitions[0x0=>0x1]	78	1			T177	3		T178	4		T179	1
all_pins[5]	transitions[0x1=>0x0]	56	1			T177	1		T178	9		T246	2
all_pins[6]	values[0x0]	642727	1			T1	2		T2	2		T3	4051
all_pins[6]	values[0x1]	69	1			T177	1		T178	10		T246	2
all_pins[6]	transitions[0x0=>0x1]	51	1			T177	1		T178	4		T294	2
all_pins[6]	transitions[0x1=>0x0]	25832	1			T3	136		T6	48		T7	14
all_pins[7]	values[0x0]	616946	1			T1	2		T2	2		T3	3915
all_pins[7]	values[0x1]	25850	1			T3	136		T6	48		T7	14
all_pins[7]	transitions[0x0=>0x1]	25817	1			T3	136		T6	48		T7	14
all_pins[7]	transitions[0x1=>0x0]	52	1			T178	1		T179	1		T246	2
all_pins[8]	values[0x0]	642711	1			T1	2		T2	2		T3	4051
all_pins[8]	values[0x1]	85	1			T178	3		T179	3		T127	1
all_pins[8]	transitions[0x0=>0x1]	67	1			T178	2		T179	3		T127	1
all_pins[8]	transitions[0x1=>0x0]	495113	1			T3	4001		T6	14		T7	12
all_pins[9]	values[0x0]	147665	1			T1	2		T2	2		T3	50
all_pins[9]	values[0x1]	495131	1			T3	4001		T6	14		T7	12
all_pins[9]	transitions[0x0=>0x1]	495121	1			T3	4001		T6	14		T7	12
all_pins[9]	transitions[0x1=>0x0]	47	1			T178	2		T179	2		T246	4
all_pins[10]	values[0x0]	642739	1			T1	2		T2	2		T3	4051
all_pins[10]	values[0x1]	57	1			T178	4		T179	2		T246	7
all_pins[10]	transitions[0x0=>0x1]	40	1			T178	2		T179	2		T246	5
all_pins[10]	transitions[0x1=>0x0]	636303	1			T1	1		T2	2		T3	4042
all_pins[11]	values[0x0]	6476	1			T1	1		T3	9		T6	2
all_pins[11]	values[0x1]	636320	1			T1	1		T2	2		T3	4042
all_pins[11]	transitions[0x0=>0x1]	636285	1			T1	1		T2	2		T3	4042
all_pins[11]	transitions[0x1=>0x0]	100	1			T68	1		T69	1		T70	1
all_pins[12]	values[0x0]	642661	1			T1	2		T2	2		T3	4051
all_pins[12]	values[0x1]	135	1			T68	1		T69	1		T70	1
all_pins[12]	transitions[0x0=>0x1]	122	1			T68	1		T69	1		T70	1
all_pins[12]	transitions[0x1=>0x0]	60	1			T178	2		T179	2		T127	1
all_pins[13]	values[0x0]	642723	1			T1	2		T2	2		T3	4051
all_pins[13]	values[0x1]	73	1			T178	3		T179	2		T127	1
all_pins[13]	transitions[0x0=>0x1]	48	1			T178	2		T127	1		T246	4
all_pins[13]	transitions[0x1=>0x0]	62	1			T177	2		T178	5		T246	4
all_pins[14]	values[0x0]	642709	1			T1	2		T2	2		T3	4051
all_pins[14]	values[0x1]	87	1			T177	2		T178	6		T179	2
all_pins[14]	transitions[0x0=>0x1]	53	1			T177	1		T178	4		T179	2
all_pins[14]	transitions[0x1=>0x0]	551133	1			T1	1		T2	1		T3	3682