Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	327	1			T177	4		T178	15		T179	7
all_values[1]	327	1			T177	4		T178	15		T179	7
all_values[2]	327	1			T177	4		T178	15		T179	7
all_values[3]	327	1			T177	4		T178	15		T179	7
all_values[4]	327	1			T177	4		T178	15		T179	7
all_values[5]	327	1			T177	4		T178	15		T179	7
all_values[6]	327	1			T177	4		T178	15		T179	7
all_values[7]	327	1			T177	4		T178	15		T179	7
all_values[8]	327	1			T177	4		T178	15		T179	7
all_values[9]	327	1			T177	4		T178	15		T179	7
all_values[10]	327	1			T177	4		T178	15		T179	7
all_values[11]	327	1			T177	4		T178	15		T179	7
all_values[12]	327	1			T177	4		T178	15		T179	7
all_values[13]	327	1			T177	4		T178	15		T179	7
all_values[14]	327	1			T177	4		T178	15		T179	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2672

1

T177

28

T178

112

T179

67

auto[1]

2233

1

T177

32

T178

113

T179

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

859

1

T177

23

T178

7

T179

7

auto[1]

4046

1

T177

37

T178

218

T179

98

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2919

1

T177

43

T178

134

T179

59

auto[1]

1986

1

T177

17

T178

91

T179

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	40	1			T177	1		T246	2		T295	1
all_values[0]	auto[0]	auto[0]	auto[1]	63	1			T177	1		T179	1		T246	9
all_values[0]	auto[0]	auto[1]	auto[0]	21	1			T177	1		T127	4		T295	1
all_values[0]	auto[0]	auto[1]	auto[1]	70	1			T178	6		T179	5		T246	4
all_values[0]	auto[1]	auto[0]	auto[1]	81	1			T177	1		T178	6		T179	1
all_values[0]	auto[1]	auto[1]	auto[1]	52	1			T178	3		T246	1		T295	1
all_values[1]	auto[0]	auto[0]	auto[0]	38	1			T177	1		T179	1		T294	1
all_values[1]	auto[0]	auto[0]	auto[1]	66	1			T177	1		T178	4		T179	2
all_values[1]	auto[0]	auto[1]	auto[0]	15	1			T177	1		T127	1		T294	1
all_values[1]	auto[0]	auto[1]	auto[1]	69	1			T178	2		T179	1		T127	1
all_values[1]	auto[1]	auto[0]	auto[1]	82	1			T177	1		T178	7		T179	3
all_values[1]	auto[1]	auto[1]	auto[1]	57	1			T178	2		T127	1		T246	5
all_values[2]	auto[0]	auto[0]	auto[0]	49	1			T178	2		T294	1		T128	1
all_values[2]	auto[0]	auto[0]	auto[1]	60	1			T178	3		T179	3		T127	2
all_values[2]	auto[0]	auto[1]	auto[0]	27	1			T177	1		T296	1		T297	1
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T177	2		T178	6		T179	2
all_values[2]	auto[1]	auto[0]	auto[1]	62	1			T178	1		T179	2		T246	9
all_values[2]	auto[1]	auto[1]	auto[1]	53	1			T177	1		T178	3		T127	1
all_values[3]	auto[0]	auto[0]	auto[0]	38	1			T177	3		T246	2		T298	1
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T178	4		T179	3		T127	2
all_values[3]	auto[0]	auto[1]	auto[0]	13	1			T177	1		T296	1		T299	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T178	2		T127	1		T246	8
all_values[3]	auto[1]	auto[0]	auto[1]	74	1			T178	5		T179	2		T246	5
all_values[3]	auto[1]	auto[1]	auto[1]	65	1			T178	4		T179	2		T127	1
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T178	1		T179	1		T294	1
all_values[4]	auto[0]	auto[0]	auto[1]	89	1			T178	4		T179	3		T127	1
all_values[4]	auto[0]	auto[1]	auto[0]	13	1			T127	1		T294	1		T300	1
all_values[4]	auto[0]	auto[1]	auto[1]	62	1			T177	3		T178	4		T127	1
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T178	5		T179	2		T127	1
all_values[4]	auto[1]	auto[1]	auto[1]	49	1			T177	1		T178	1		T179	1
all_values[5]	auto[0]	auto[0]	auto[0]	38	1			T179	1		T128	1		T295	3
all_values[5]	auto[0]	auto[0]	auto[1]	60	1			T178	7		T179	3		T246	7
all_values[5]	auto[0]	auto[1]	auto[0]	26	1			T179	1		T127	2		T295	1
all_values[5]	auto[0]	auto[1]	auto[1]	65	1			T177	1		T178	2		T127	1
all_values[5]	auto[1]	auto[0]	auto[1]	66	1			T177	1		T178	4		T179	1
all_values[5]	auto[1]	auto[1]	auto[1]	72	1			T177	2		T178	2		T179	1
all_values[6]	auto[0]	auto[0]	auto[0]	44	1			T246	1		T294	1		T128	2
all_values[6]	auto[0]	auto[0]	auto[1]	63	1			T177	3		T178	2		T179	2
all_values[6]	auto[0]	auto[1]	auto[0]	18	1			T129	1		T296	3		T301	1
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T178	7		T179	4		T127	1
all_values[6]	auto[1]	auto[0]	auto[1]	83	1			T178	2		T179	1		T127	1
all_values[6]	auto[1]	auto[1]	auto[1]	42	1			T177	1		T178	4		T127	1
all_values[7]	auto[0]	auto[0]	auto[0]	27	1			T177	1		T178	1		T294	1
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T178	1		T179	1		T127	1
all_values[7]	auto[0]	auto[1]	auto[0]	25	1			T177	3		T297	1		T301	2
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T178	6		T179	2		T127	1
all_values[7]	auto[1]	auto[0]	auto[1]	77	1			T178	2		T179	3		T246	6
all_values[7]	auto[1]	auto[1]	auto[1]	58	1			T178	5		T179	1		T127	2
all_values[8]	auto[0]	auto[0]	auto[0]	40	1			T177	4		T178	2		T246	1
all_values[8]	auto[0]	auto[0]	auto[1]	70	1			T178	5		T127	1		T246	4
all_values[8]	auto[0]	auto[1]	auto[0]	17	1			T127	1		T302	2		T303	3
all_values[8]	auto[0]	auto[1]	auto[1]	67	1			T178	5		T179	1		T127	1
all_values[8]	auto[1]	auto[0]	auto[1]	62	1			T178	2		T179	4		T127	1
all_values[8]	auto[1]	auto[1]	auto[1]	71	1			T178	1		T179	2		T246	3
all_values[9]	auto[0]	auto[0]	auto[0]	30	1			T177	1		T179	1		T298	1
all_values[9]	auto[0]	auto[0]	auto[1]	84	1			T178	4		T179	2		T127	1
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T179	1		T297	1		T304	2
all_values[9]	auto[0]	auto[1]	auto[1]	60	1			T177	1		T178	7		T179	1
all_values[9]	auto[1]	auto[0]	auto[1]	66	1			T178	2		T127	1		T246	4
all_values[9]	auto[1]	auto[1]	auto[1]	68	1			T177	2		T178	2		T179	2
all_values[10]	auto[0]	auto[0]	auto[0]	43	1			T177	1		T127	1		T295	3
all_values[10]	auto[0]	auto[0]	auto[1]	77	1			T178	3		T179	2		T127	1
all_values[10]	auto[0]	auto[1]	auto[0]	23	1			T177	3		T127	1		T295	1
all_values[10]	auto[0]	auto[1]	auto[1]	66	1			T178	8		T179	1		T246	10
all_values[10]	auto[1]	auto[0]	auto[1]	67	1			T178	2		T179	3		T127	1
all_values[10]	auto[1]	auto[1]	auto[1]	51	1			T178	2		T179	1		T246	6
all_values[11]	auto[0]	auto[0]	auto[0]	35	1			T246	2		T294	1		T128	1
all_values[11]	auto[0]	auto[0]	auto[1]	65	1			T178	5		T179	2		T127	1
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T246	1		T128	1		T297	1
all_values[11]	auto[0]	auto[1]	auto[1]	68	1			T177	3		T178	5		T179	2
all_values[11]	auto[1]	auto[0]	auto[1]	71	1			T178	3		T179	2		T127	1
all_values[11]	auto[1]	auto[1]	auto[1]	64	1			T177	1		T178	2		T179	1
all_values[12]	auto[0]	auto[0]	auto[0]	25	1			T246	2		T295	1		T297	1
all_values[12]	auto[0]	auto[0]	auto[1]	60	1			T177	1		T178	4		T179	2
all_values[12]	auto[0]	auto[1]	auto[0]	34	1			T127	1		T246	1		T298	2
all_values[12]	auto[0]	auto[1]	auto[1]	74	1			T177	1		T178	4		T179	2
all_values[12]	auto[1]	auto[0]	auto[1]	76	1			T177	2		T178	5		T179	1
all_values[12]	auto[1]	auto[1]	auto[1]	58	1			T178	2		T179	2		T246	5
all_values[13]	auto[0]	auto[0]	auto[0]	35	1			T246	1		T294	1		T295	3
all_values[13]	auto[0]	auto[0]	auto[1]	68	1			T177	2		T178	6		T179	2
all_values[13]	auto[0]	auto[1]	auto[0]	28	1			T295	1		T297	4		T304	1
all_values[13]	auto[0]	auto[1]	auto[1]	65	1			T178	4		T179	1		T127	1
all_values[13]	auto[1]	auto[0]	auto[1]	71	1			T177	2		T178	3		T179	4
all_values[13]	auto[1]	auto[1]	auto[1]	60	1			T178	2		T127	1		T246	2
all_values[14]	auto[0]	auto[0]	auto[0]	26	1			T177	1		T178	1		T179	1
all_values[14]	auto[0]	auto[0]	auto[1]	58	1			T178	2		T179	1		T127	2
all_values[14]	auto[0]	auto[1]	auto[0]	15	1			T129	1		T296	2		T300	2
all_values[14]	auto[0]	auto[1]	auto[1]	81	1			T177	1		T178	5		T179	1
all_values[14]	auto[1]	auto[0]	auto[1]	78	1			T178	2		T179	4		T127	1
all_values[14]	auto[1]	auto[1]	auto[1]	69	1			T177	2		T178	5		T127	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal