Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	634276	1			T1	294		T2	7		T3	2
all_values[1]	634276	1			T1	294		T2	7		T3	2
all_values[2]	634276	1			T1	294		T2	7		T3	2
all_values[3]	634276	1			T1	294		T2	7		T3	2
all_values[4]	634276	1			T1	294		T2	7		T3	2
all_values[5]	634276	1			T1	294		T2	7		T3	2
all_values[6]	634276	1			T1	294		T2	7		T3	2
all_values[7]	634276	1			T1	294		T2	7		T3	2
all_values[8]	634276	1			T1	294		T2	7		T3	2
all_values[9]	634276	1			T1	294		T2	7		T3	2
all_values[10]	634276	1			T1	294		T2	7		T3	2
all_values[11]	634276	1			T1	294		T2	7		T3	2
all_values[12]	634276	1			T1	294		T2	7		T3	2
all_values[13]	634276	1			T1	294		T2	7		T3	2
all_values[14]	634276	1			T1	294		T2	7		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7852368

1

T1

3738

T2

105

T3

26

auto[1]

1661772

1

T1

672

T3

4

T4

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8701103

1

T1

4410

T2

105

T3

30

auto[1]

813037

1

T191

101429

T24

124642

T25

169232

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	89710	1			T1	2		T2	7		T4	3
all_values[0]	auto[0]	auto[1]	6281	1			T191	513		T24	986		T25	1969
all_values[0]	auto[1]	auto[0]	487115	1			T1	292		T3	2		T4	5
all_values[0]	auto[1]	auto[1]	51170	1			T191	6250		T24	7324		T25	12134
all_values[1]	auto[0]	auto[0]	576475	1			T1	293		T2	7		T3	2
all_values[1]	auto[0]	auto[1]	57310	1			T191	6757		T24	8305		T25	14102
all_values[1]	auto[1]	auto[0]	353	1			T1	1		T12	13		T283	59
all_values[1]	auto[1]	auto[1]	138	1			T191	2		T24	5		T25	1
all_values[2]	auto[0]	auto[0]	590865	1			T1	294		T2	7		T3	2
all_values[2]	auto[0]	auto[1]	43092	1			T191	6757		T24	8305		T128	3754
all_values[2]	auto[1]	auto[0]	192	1			T174	1		T51	1		T249	2
all_values[2]	auto[1]	auto[1]	127	1			T191	5		T24	5		T128	2
all_values[3]	auto[0]	auto[0]	590921	1			T1	294		T2	7		T3	2
all_values[3]	auto[0]	auto[1]	43200	1			T191	6760		T24	8306		T128	3754
all_values[3]	auto[1]	auto[1]	155	1			T191	2		T128	2		T129	1
all_values[4]	auto[0]	auto[0]	576812	1			T1	294		T2	7		T3	2
all_values[4]	auto[0]	auto[1]	57324	1			T191	6760		T24	8308		T25	14100
all_values[4]	auto[1]	auto[0]	13	1			T22	2		T40	1		T284	1
all_values[4]	auto[1]	auto[1]	127	1			T191	3		T24	2		T25	3
all_values[5]	auto[0]	auto[0]	583104	1			T1	294		T2	7		T3	2
all_values[5]	auto[0]	auto[1]	51016	1			T191	6758		T24	8307		T25	14102
all_values[5]	auto[1]	auto[1]	156	1			T191	3		T24	3		T25	1
all_values[6]	auto[0]	auto[0]	591087	1			T1	294		T2	7		T3	2
all_values[6]	auto[0]	auto[1]	43045	1			T191	6758		T24	8303		T128	3754
all_values[6]	auto[1]	auto[1]	144	1			T191	3		T24	6		T128	1
all_values[7]	auto[0]	auto[0]	552486	1			T1	224		T2	7		T3	2
all_values[7]	auto[0]	auto[1]	53594	1			T191	6342		T24	7563		T25	13640
all_values[7]	auto[1]	auto[0]	24310	1			T1	70		T4	1		T7	1
all_values[7]	auto[1]	auto[1]	3886	1			T191	421		T24	747		T25	463
all_values[8]	auto[0]	auto[0]	576803	1			T1	294		T2	7		T3	2
all_values[8]	auto[0]	auto[1]	57308	1			T191	6759		T24	8308		T25	14102
all_values[8]	auto[1]	auto[1]	165	1			T191	4		T24	2		T25	1
all_values[9]	auto[0]	auto[0]	154222	1			T1	277		T2	7		T3	2
all_values[9]	auto[0]	auto[1]	18772	1			T191	1185		T24	2056		T25	9058
all_values[9]	auto[1]	auto[0]	422577	1			T1	17		T4	1		T7	1
all_values[9]	auto[1]	auto[1]	38705	1			T191	5578		T24	6252		T25	5044
all_values[10]	auto[0]	auto[0]	576802	1			T1	294		T2	7		T3	2
all_values[10]	auto[0]	auto[1]	57326	1			T191	6758		T24	8305		T25	14100
all_values[10]	auto[1]	auto[1]	148	1			T191	5		T24	4		T25	2
all_values[11]	auto[0]	auto[0]	2211	1			T1	2		T2	7		T4	3
all_values[11]	auto[0]	auto[1]	260	1			T191	11		T24	2		T25	27
all_values[11]	auto[1]	auto[0]	574614	1			T1	292		T3	2		T4	5
all_values[11]	auto[1]	auto[1]	57191	1			T191	6752		T24	8308		T25	14076
all_values[12]	auto[0]	auto[0]	576747	1			T1	294		T2	7		T3	2
all_values[12]	auto[0]	auto[1]	57339	1			T191	6757		T24	8306		T25	14100
all_values[12]	auto[1]	auto[0]	56	1			T51	1		T52	1		T66	1
all_values[12]	auto[1]	auto[1]	134	1			T191	1		T24	4		T25	2
all_values[13]	auto[0]	auto[0]	576800	1			T1	294		T2	7		T3	2
all_values[13]	auto[0]	auto[1]	57339	1			T191	6758		T24	8308		T25	14099
all_values[13]	auto[1]	auto[1]	137	1			T191	4		T24	2		T25	3
all_values[14]	auto[0]	auto[0]	576828	1			T1	294		T2	7		T3	2
all_values[14]	auto[0]	auto[1]	57289	1			T191	6757		T24	8305		T25	14101
all_values[14]	auto[1]	auto[1]	159	1			T191	6		T24	5		T25	2