Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	634276	1			T1	294		T2	7		T3	2
all_pins[1]	634276	1			T1	294		T2	7		T3	2
all_pins[2]	634276	1			T1	294		T2	7		T3	2
all_pins[3]	634276	1			T1	294		T2	7		T3	2
all_pins[4]	634276	1			T1	294		T2	7		T3	2
all_pins[5]	634276	1			T1	294		T2	7		T3	2
all_pins[6]	634276	1			T1	294		T2	7		T3	2
all_pins[7]	634276	1			T1	294		T2	7		T3	2
all_pins[8]	634276	1			T1	294		T2	7		T3	2
all_pins[9]	634276	1			T1	294		T2	7		T3	2
all_pins[10]	634276	1			T1	294		T2	7		T3	2
all_pins[11]	634276	1			T1	294		T2	7		T3	2
all_pins[12]	634276	1			T1	294		T2	7		T3	2
all_pins[13]	634276	1			T1	294		T2	7		T3	2
all_pins[14]	634276	1			T1	294		T2	7		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7858085	1			T1	3736		T2	105		T3	26
values[0x1]	1656055	1			T1	674		T3	4		T4	12
transitions[0x0=>0x1]	1655315	1			T1	673		T3	4		T4	12
transitions[0x1=>0x0]	1654003	1			T1	672		T3	3		T4	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99410	1			T1	2		T2	7		T4	3
all_pins[0]	values[0x1]	534866	1			T1	292		T3	2		T4	5
all_pins[0]	transitions[0x0=>0x1]	534418	1			T1	291		T3	2		T4	5
all_pins[0]	transitions[0x1=>0x0]	66	1			T280	1		T24	3		T128	1
all_pins[1]	values[0x0]	633762	1			T1	293		T2	7		T3	2
all_pins[1]	values[0x1]	514	1			T1	1		T12	14		T283	69
all_pins[1]	transitions[0x0=>0x1]	494	1			T1	1		T12	14		T283	69
all_pins[1]	transitions[0x1=>0x0]	101	1			T174	1		T287	1		T288	1
all_pins[2]	values[0x0]	634155	1			T1	294		T2	7		T3	2
all_pins[2]	values[0x1]	121	1			T174	1		T287	1		T288	1
all_pins[2]	transitions[0x0=>0x1]	101	1			T174	1		T287	1		T288	1
all_pins[2]	transitions[0x1=>0x0]	54	1			T191	1		T128	1		T129	1
all_pins[3]	values[0x0]	634202	1			T1	294		T2	7		T3	2
all_pins[3]	values[0x1]	74	1			T191	2		T128	1		T129	1
all_pins[3]	transitions[0x0=>0x1]	57	1			T191	2		T128	1		T130	2
all_pins[3]	transitions[0x1=>0x0]	61	1			T22	2		T40	1		T191	2
all_pins[4]	values[0x0]	634198	1			T1	294		T2	7		T3	2
all_pins[4]	values[0x1]	78	1			T22	2		T40	1		T191	2
all_pins[4]	transitions[0x0=>0x1]	59	1			T22	2		T40	1		T191	2
all_pins[4]	transitions[0x1=>0x0]	67	1			T191	2		T24	2		T128	1
all_pins[5]	values[0x0]	634190	1			T1	294		T2	7		T3	2
all_pins[5]	values[0x1]	86	1			T191	2		T24	2		T128	2
all_pins[5]	transitions[0x0=>0x1]	54	1			T24	2		T128	2		T130	2
all_pins[5]	transitions[0x1=>0x0]	55	1			T191	1		T24	3		T129	2
all_pins[6]	values[0x0]	634189	1			T1	294		T2	7		T3	2
all_pins[6]	values[0x1]	87	1			T191	3		T24	3		T129	2
all_pins[6]	transitions[0x0=>0x1]	61	1			T191	1		T24	3		T129	2
all_pins[6]	transitions[0x1=>0x0]	30578	1			T1	72		T4	1		T7	1
all_pins[7]	values[0x0]	603672	1			T1	222		T2	7		T3	2
all_pins[7]	values[0x1]	30604	1			T1	72		T4	1		T7	1
all_pins[7]	transitions[0x0=>0x1]	30581	1			T1	72		T4	1		T7	1
all_pins[7]	transitions[0x1=>0x0]	47	1			T129	2		T130	3		T131	2
all_pins[8]	values[0x0]	634206	1			T1	294		T2	7		T3	2
all_pins[8]	values[0x1]	70	1			T25	1		T129	3		T130	5
all_pins[8]	transitions[0x0=>0x1]	55	1			T25	1		T129	2		T130	3
all_pins[8]	transitions[0x1=>0x0]	461212	1			T1	17		T4	1		T7	1
all_pins[9]	values[0x0]	173049	1			T1	277		T2	7		T3	2
all_pins[9]	values[0x1]	461227	1			T1	17		T4	1		T7	1
all_pins[9]	transitions[0x0=>0x1]	461216	1			T1	17		T4	1		T7	1
all_pins[9]	transitions[0x1=>0x0]	64	1			T191	2		T24	3		T25	1
all_pins[10]	values[0x0]	634201	1			T1	294		T2	7		T3	2
all_pins[10]	values[0x1]	75	1			T191	2		T24	4		T25	1
all_pins[10]	transitions[0x0=>0x1]	52	1			T191	1		T24	2		T25	1
all_pins[10]	transitions[0x1=>0x0]	627960	1			T1	292		T3	2		T4	5
all_pins[11]	values[0x0]	6293	1			T1	2		T2	7		T4	3
all_pins[11]	values[0x1]	627983	1			T1	292		T3	2		T4	5
all_pins[11]	transitions[0x0=>0x1]	627958	1			T1	292		T3	2		T4	5
all_pins[11]	transitions[0x1=>0x0]	101	1			T51	1		T52	1		T66	1
all_pins[12]	values[0x0]	634150	1			T1	294		T2	7		T3	2
all_pins[12]	values[0x1]	126	1			T51	1		T52	1		T66	1
all_pins[12]	transitions[0x0=>0x1]	109	1			T51	1		T52	1		T66	1
all_pins[12]	transitions[0x1=>0x0]	47	1			T191	2		T24	1		T25	1
all_pins[13]	values[0x0]	634212	1			T1	294		T2	7		T3	2
all_pins[13]	values[0x1]	64	1			T191	3		T24	2		T25	1
all_pins[13]	transitions[0x0=>0x1]	48	1			T191	2		T24	2		T25	1
all_pins[13]	transitions[0x1=>0x0]	64	1			T191	2		T128	3		T129	1
all_pins[14]	values[0x0]	634196	1			T1	294		T2	7		T3	2
all_pins[14]	values[0x1]	80	1			T191	3		T128	4		T129	1
all_pins[14]	transitions[0x0=>0x1]	52	1			T191	2		T128	2		T130	3
all_pins[14]	transitions[0x1=>0x0]	533526	1			T1	291		T3	1		T4	4