Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	320	1			T191	7		T24	7		T25	4
all_values[1]	320	1			T191	7		T24	7		T25	4
all_values[2]	320	1			T191	7		T24	7		T25	4
all_values[3]	320	1			T191	7		T24	7		T25	4
all_values[4]	320	1			T191	7		T24	7		T25	4
all_values[5]	320	1			T191	7		T24	7		T25	4
all_values[6]	320	1			T191	7		T24	7		T25	4
all_values[7]	320	1			T191	7		T24	7		T25	4
all_values[8]	320	1			T191	7		T24	7		T25	4
all_values[9]	320	1			T191	7		T24	7		T25	4
all_values[10]	320	1			T191	7		T24	7		T25	4
all_values[11]	320	1			T191	7		T24	7		T25	4
all_values[12]	320	1			T191	7		T24	7		T25	4
all_values[13]	320	1			T191	7		T24	7		T25	4
all_values[14]	320	1			T191	7		T24	7		T25	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2562

1

T191

62

T24

44

T25

30

auto[1]

2238

1

T191

43

T24

61

T25

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

820

1

T191

16

T24

8

T25

16

auto[1]

3980

1

T191

89

T24

97

T25

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2816

1

T191

53

T24

54

T25

40

auto[1]

1984

1

T191

52

T24

51

T25

20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	38	1			T128	1		T130	1		T289	2
all_values[0]	auto[0]	auto[0]	auto[1]	61	1			T191	3		T24	4		T25	2
all_values[0]	auto[0]	auto[1]	auto[0]	24	1			T130	1		T290	1		T291	3
all_values[0]	auto[0]	auto[1]	auto[1]	66	1			T24	1		T128	1		T129	1
all_values[0]	auto[1]	auto[0]	auto[1]	73	1			T191	4		T25	1		T128	2
all_values[0]	auto[1]	auto[1]	auto[1]	58	1			T24	2		T25	1		T129	1
all_values[1]	auto[0]	auto[0]	auto[0]	41	1			T191	2		T128	1		T129	2
all_values[1]	auto[0]	auto[0]	auto[1]	53	1			T191	1		T25	1		T130	6
all_values[1]	auto[0]	auto[1]	auto[0]	27	1			T191	2		T292	2		T132	1
all_values[1]	auto[0]	auto[1]	auto[1]	68	1			T191	1		T24	2		T25	2
all_values[1]	auto[1]	auto[0]	auto[1]	62	1			T191	1		T24	2		T25	1
all_values[1]	auto[1]	auto[1]	auto[1]	69	1			T24	3		T128	1		T129	1
all_values[2]	auto[0]	auto[0]	auto[0]	35	1			T191	1		T25	1		T130	4
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T191	1		T24	1		T128	1
all_values[2]	auto[0]	auto[1]	auto[0]	22	1			T25	3		T131	1		T293	2
all_values[2]	auto[0]	auto[1]	auto[1]	66	1			T24	1		T128	1		T131	3
all_values[2]	auto[1]	auto[0]	auto[1]	71	1			T191	2		T24	3		T128	1
all_values[2]	auto[1]	auto[1]	auto[1]	56	1			T191	3		T24	2		T128	1
all_values[3]	auto[0]	auto[0]	auto[0]	32	1			T191	1		T24	2		T130	1
all_values[3]	auto[0]	auto[0]	auto[1]	68	1			T191	2		T24	2		T128	1
all_values[3]	auto[0]	auto[1]	auto[0]	31	1			T24	2		T25	4		T130	1
all_values[3]	auto[0]	auto[1]	auto[1]	54	1			T191	1		T129	1		T130	2
all_values[3]	auto[1]	auto[0]	auto[1]	80	1			T191	2		T24	1		T128	2
all_values[3]	auto[1]	auto[1]	auto[1]	55	1			T191	1		T128	1		T129	1
all_values[4]	auto[0]	auto[0]	auto[0]	32	1			T130	1		T131	3		T292	1
all_values[4]	auto[0]	auto[0]	auto[1]	70	1			T191	2		T24	3		T25	1
all_values[4]	auto[0]	auto[1]	auto[0]	29	1			T128	1		T130	1		T131	1
all_values[4]	auto[0]	auto[1]	auto[1]	62	1			T191	2		T24	2		T128	1
all_values[4]	auto[1]	auto[0]	auto[1]	75	1			T191	1		T24	1		T25	3
all_values[4]	auto[1]	auto[1]	auto[1]	52	1			T191	2		T24	1		T128	2
all_values[5]	auto[0]	auto[0]	auto[0]	28	1			T191	1		T128	1		T129	2
all_values[5]	auto[0]	auto[0]	auto[1]	63	1			T191	1		T24	1		T128	1
all_values[5]	auto[0]	auto[1]	auto[0]	14	1			T191	1		T129	2		T131	1
all_values[5]	auto[0]	auto[1]	auto[1]	79	1			T191	2		T24	2		T25	3
all_values[5]	auto[1]	auto[0]	auto[1]	69	1			T191	1		T24	2		T25	1
all_values[5]	auto[1]	auto[1]	auto[1]	67	1			T191	1		T24	2		T130	1
all_values[6]	auto[0]	auto[0]	auto[0]	44	1			T191	2		T25	1		T129	1
all_values[6]	auto[0]	auto[0]	auto[1]	49	1			T24	1		T128	1		T130	4
all_values[6]	auto[0]	auto[1]	auto[0]	36	1			T24	1		T25	3		T128	1
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T191	2		T24	1		T129	1
all_values[6]	auto[1]	auto[0]	auto[1]	58	1			T191	1		T24	1		T128	2
all_values[6]	auto[1]	auto[1]	auto[1]	63	1			T191	2		T24	3		T129	1
all_values[7]	auto[0]	auto[0]	auto[0]	23	1			T128	1		T291	2		T294	1
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T24	2		T25	1		T128	1
all_values[7]	auto[0]	auto[1]	auto[0]	16	1			T128	1		T130	2		T131	1
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T191	2		T24	2		T25	1
all_values[7]	auto[1]	auto[0]	auto[1]	88	1			T191	4		T24	2		T25	1
all_values[7]	auto[1]	auto[1]	auto[1]	44	1			T191	1		T24	1		T25	1
all_values[8]	auto[0]	auto[0]	auto[0]	31	1			T130	1		T131	2		T292	1
all_values[8]	auto[0]	auto[0]	auto[1]	61	1			T191	2		T24	1		T25	2
all_values[8]	auto[0]	auto[1]	auto[0]	14	1			T131	2		T295	1		T296	2
all_values[8]	auto[0]	auto[1]	auto[1]	75	1			T191	2		T24	3		T25	1
all_values[8]	auto[1]	auto[0]	auto[1]	80	1			T191	3		T24	1		T128	2
all_values[8]	auto[1]	auto[1]	auto[1]	59	1			T24	2		T25	1		T129	2
all_values[9]	auto[0]	auto[0]	auto[0]	22	1			T24	1		T292	3		T289	3
all_values[9]	auto[0]	auto[0]	auto[1]	63	1			T191	2		T24	1		T25	1
all_values[9]	auto[0]	auto[1]	auto[0]	20	1			T24	1		T25	1		T130	1
all_values[9]	auto[0]	auto[1]	auto[1]	79	1			T191	2		T24	1		T129	3
all_values[9]	auto[1]	auto[0]	auto[1]	73	1			T191	1		T24	1		T25	2
all_values[9]	auto[1]	auto[1]	auto[1]	63	1			T191	2		T24	2		T128	1
all_values[10]	auto[0]	auto[0]	auto[0]	25	1			T128	1		T290	1		T132	1
all_values[10]	auto[0]	auto[0]	auto[1]	72	1			T191	1		T25	1		T128	1
all_values[10]	auto[0]	auto[1]	auto[0]	18	1			T24	1		T25	1		T131	1
all_values[10]	auto[0]	auto[1]	auto[1]	57	1			T191	1		T24	2		T130	4
all_values[10]	auto[1]	auto[0]	auto[1]	73	1			T191	3		T129	2		T130	4
all_values[10]	auto[1]	auto[1]	auto[1]	75	1			T191	2		T24	4		T25	2
all_values[11]	auto[0]	auto[0]	auto[0]	42	1			T130	1		T293	2		T132	1
all_values[11]	auto[0]	auto[0]	auto[1]	56	1			T191	1		T25	2		T129	2
all_values[11]	auto[0]	auto[1]	auto[0]	20	1			T130	1		T132	1		T291	2
all_values[11]	auto[0]	auto[1]	auto[1]	68	1			T24	3		T25	1		T128	2
all_values[11]	auto[1]	auto[0]	auto[1]	71	1			T191	2		T24	2		T25	1
all_values[11]	auto[1]	auto[1]	auto[1]	63	1			T191	4		T24	2		T128	2
all_values[12]	auto[0]	auto[0]	auto[0]	32	1			T191	2		T25	1		T130	1
all_values[12]	auto[0]	auto[0]	auto[1]	67	1			T24	1		T130	3		T131	3
all_values[12]	auto[0]	auto[1]	auto[0]	13	1			T191	3		T128	2		T297	1
all_values[12]	auto[0]	auto[1]	auto[1]	74	1			T191	1		T24	2		T25	1
all_values[12]	auto[1]	auto[0]	auto[1]	71	1			T191	1		T24	1		T25	2
all_values[12]	auto[1]	auto[1]	auto[1]	63	1			T24	3		T128	1		T129	1
all_values[13]	auto[0]	auto[0]	auto[0]	34	1			T191	1		T129	1		T289	1
all_values[13]	auto[0]	auto[0]	auto[1]	76	1			T24	1		T25	1		T128	1
all_values[13]	auto[0]	auto[1]	auto[0]	9	1			T25	1		T293	3		T298	1
all_values[13]	auto[0]	auto[1]	auto[1]	78	1			T191	2		T24	4		T25	1
all_values[13]	auto[1]	auto[0]	auto[1]	72	1			T191	4		T129	2		T130	2
all_values[13]	auto[1]	auto[1]	auto[1]	51	1			T24	2		T25	1		T128	2
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T292	1		T289	5		T293	1
all_values[14]	auto[0]	auto[0]	auto[1]	58	1			T191	2		T24	2		T25	1
all_values[14]	auto[0]	auto[1]	auto[0]	26	1			T131	1		T292	1		T289	2
all_values[14]	auto[0]	auto[1]	auto[1]	64	1			T191	1		T25	1		T128	3
all_values[14]	auto[1]	auto[0]	auto[1]	74	1			T191	4		T24	4		T25	2
all_values[14]	auto[1]	auto[1]	auto[1]	56	1			T24	1		T128	1		T129	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal