Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	646878	1			T1	2		T2	4		T3	2
all_values[1]	646878	1			T1	2		T2	4		T3	2
all_values[2]	646878	1			T1	2		T2	4		T3	2
all_values[3]	646878	1			T1	2		T2	4		T3	2
all_values[4]	646878	1			T1	2		T2	4		T3	2
all_values[5]	646878	1			T1	2		T2	4		T3	2
all_values[6]	646878	1			T1	2		T2	4		T3	2
all_values[7]	646878	1			T1	2		T2	4		T3	2
all_values[8]	646878	1			T1	2		T2	4		T3	2
all_values[9]	646878	1			T1	2		T2	4		T3	2
all_values[10]	646878	1			T1	2		T2	4		T3	2
all_values[11]	646878	1			T1	2		T2	4		T3	2
all_values[12]	646878	1			T1	2		T2	4		T3	2
all_values[13]	646878	1			T1	2		T2	4		T3	2
all_values[14]	646878	1			T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8035781

1

T1

26

T2

51

T3

26

auto[1]

1667389

1

T1

4

T2

9

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9211130

1

T1

30

T2

60

T3

30

auto[1]

492040

1

T17

18251

T39

124

T182

111

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92960	1			T4	473		T9	2		T10	597
all_values[0]	auto[0]	auto[1]	4746	1			T17	8		T43	7		T242	811
all_values[0]	auto[1]	auto[0]	519914	1			T1	2		T2	4		T3	2
all_values[0]	auto[1]	auto[1]	29258	1			T17	1296		T39	9		T43	1
all_values[1]	auto[0]	auto[0]	612638	1			T1	2		T2	4		T3	2
all_values[1]	auto[0]	auto[1]	33840	1			T17	1300		T39	5		T182	6
all_values[1]	auto[1]	auto[0]	233	1			T45	1		T39	14		T264	1
all_values[1]	auto[1]	auto[1]	167	1			T17	3		T39	4		T182	2
all_values[2]	auto[0]	auto[0]	612680	1			T1	2		T2	4		T3	2
all_values[2]	auto[0]	auto[1]	33834	1			T17	1299		T39	6		T182	7
all_values[2]	auto[1]	auto[0]	193	1			T64	1		T164	1		T165	1
all_values[2]	auto[1]	auto[1]	171	1			T17	4		T39	3		T182	2
all_values[3]	auto[0]	auto[0]	612894	1			T1	2		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	33804	1			T17	1303		T39	5		T182	9
all_values[3]	auto[1]	auto[1]	180	1			T39	2		T43	2		T242	2
all_values[4]	auto[0]	auto[0]	613038	1			T1	2		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	33667	1			T17	1300		T39	6		T182	7
all_values[4]	auto[1]	auto[0]	19	1			T24	1		T256	1		T265	1
all_values[4]	auto[1]	auto[1]	154	1			T17	4		T39	2		T182	1
all_values[5]	auto[0]	auto[0]	612882	1			T1	2		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	33818	1			T17	1298		T39	7		T182	9
all_values[5]	auto[1]	auto[1]	178	1			T17	6		T43	2		T242	6
all_values[6]	auto[0]	auto[0]	612880	1			T1	2		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	33793	1			T17	1301		T39	6		T182	8
all_values[6]	auto[1]	auto[1]	205	1			T17	3		T39	2		T182	1
all_values[7]	auto[0]	auto[0]	583666	1			T1	2		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	31471	1			T39	7		T43	2		T242	15656
all_values[7]	auto[1]	auto[0]	30726	1			T4	192		T10	67		T14	1
all_values[7]	auto[1]	auto[1]	1015	1			T39	2		T43	6		T242	254
all_values[8]	auto[0]	auto[0]	612869	1			T1	2		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	33831	1			T17	1298		T39	8		T182	7
all_values[8]	auto[1]	auto[1]	178	1			T17	6		T39	1		T182	1
all_values[9]	auto[0]	auto[0]	200251	1			T1	2		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	6786	1			T17	1296		T39	6		T182	5
all_values[9]	auto[1]	auto[0]	428548	1			T2	1		T4	7		T10	6
all_values[9]	auto[1]	auto[1]	11293	1			T17	8		T39	2		T182	4
all_values[10]	auto[0]	auto[0]	612862	1			T1	2		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	33851	1			T17	1303		T39	3		T182	6
all_values[10]	auto[1]	auto[1]	165	1			T17	1		T39	3		T182	1
all_values[11]	auto[0]	auto[0]	2450	1			T4	3		T9	2		T10	3
all_values[11]	auto[0]	auto[1]	275	1			T17	7		T182	4		T43	6
all_values[11]	auto[1]	auto[0]	610622	1			T1	2		T2	4		T3	2
all_values[11]	auto[1]	auto[1]	33531	1			T17	1297		T39	9		T182	5
all_values[12]	auto[0]	auto[0]	612807	1			T1	2		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	33846	1			T17	1301		T39	7		T182	6
all_values[12]	auto[1]	auto[0]	64	1			T56	1		T57	1		T73	1
all_values[12]	auto[1]	auto[1]	161	1			T17	2		T39	2		T182	2
all_values[13]	auto[0]	auto[0]	612861	1			T1	2		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	33809	1			T17	1300		T39	5		T182	6
all_values[13]	auto[1]	auto[1]	208	1			T17	3		T39	3		T182	3
all_values[14]	auto[0]	auto[0]	613073	1			T1	2		T2	4		T3	2
all_values[14]	auto[0]	auto[1]	33599	1			T17	1299		T39	4		T182	8
all_values[14]	auto[1]	auto[1]	206	1			T17	5		T39	5		T182	1