Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	646878	1			T1	2		T2	4		T3	2
all_pins[1]	646878	1			T1	2		T2	4		T3	2
all_pins[2]	646878	1			T1	2		T2	4		T3	2
all_pins[3]	646878	1			T1	2		T2	4		T3	2
all_pins[4]	646878	1			T1	2		T2	4		T3	2
all_pins[5]	646878	1			T1	2		T2	4		T3	2
all_pins[6]	646878	1			T1	2		T2	4		T3	2
all_pins[7]	646878	1			T1	2		T2	4		T3	2
all_pins[8]	646878	1			T1	2		T2	4		T3	2
all_pins[9]	646878	1			T1	2		T2	4		T3	2
all_pins[10]	646878	1			T1	2		T2	4		T3	2
all_pins[11]	646878	1			T1	2		T2	4		T3	2
all_pins[12]	646878	1			T1	2		T2	4		T3	2
all_pins[13]	646878	1			T1	2		T2	4		T3	2
all_pins[14]	646878	1			T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8040823	1			T1	26		T2	51		T3	26
values[0x1]	1662347	1			T1	4		T2	9		T3	4
transitions[0x0=>0x1]	1661742	1			T1	4		T2	9		T3	4
transitions[0x1=>0x0]	1660425	1			T1	3		T2	8		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100715	1			T4	474		T5	1		T9	2
all_pins[0]	values[0x1]	546163	1			T1	2		T2	4		T3	2
all_pins[0]	transitions[0x0=>0x1]	545866	1			T1	2		T2	4		T3	2
all_pins[0]	transitions[0x1=>0x0]	68	1			T17	2		T39	3		T264	1
all_pins[1]	values[0x0]	646513	1			T1	2		T2	4		T3	2
all_pins[1]	values[0x1]	365	1			T45	1		T17	2		T39	19
all_pins[1]	transitions[0x0=>0x1]	347	1			T45	1		T17	1		T39	19
all_pins[1]	transitions[0x1=>0x0]	112	1			T64	1		T164	1		T165	1
all_pins[2]	values[0x0]	646748	1			T1	2		T2	4		T3	2
all_pins[2]	values[0x1]	130	1			T64	1		T164	1		T165	1
all_pins[2]	transitions[0x0=>0x1]	118	1			T64	1		T164	1		T165	1
all_pins[2]	transitions[0x1=>0x0]	71	1			T27	2		T124	2		T267	3
all_pins[3]	values[0x0]	646795	1			T1	2		T2	4		T3	2
all_pins[3]	values[0x1]	83	1			T27	3		T124	2		T267	3
all_pins[3]	transitions[0x0=>0x1]	66	1			T27	3		T124	2		T267	3
all_pins[3]	transitions[0x1=>0x0]	81	1			T24	1		T17	3		T39	1
all_pins[4]	values[0x0]	646780	1			T1	2		T2	4		T3	2
all_pins[4]	values[0x1]	98	1			T24	1		T17	3		T39	1
all_pins[4]	transitions[0x0=>0x1]	81	1			T24	1		T17	1		T39	1
all_pins[4]	transitions[0x1=>0x0]	81	1			T17	1		T43	1		T242	4
all_pins[5]	values[0x0]	646780	1			T1	2		T2	4		T3	2
all_pins[5]	values[0x1]	98	1			T17	3		T43	1		T242	4
all_pins[5]	transitions[0x0=>0x1]	72	1			T17	3		T43	1		T242	1
all_pins[5]	transitions[0x1=>0x0]	80	1			T17	2		T39	2		T182	1
all_pins[6]	values[0x0]	646772	1			T1	2		T2	4		T3	2
all_pins[6]	values[0x1]	106	1			T17	2		T39	2		T182	1
all_pins[6]	transitions[0x0=>0x1]	89	1			T17	2		T39	2		T182	1
all_pins[6]	transitions[0x1=>0x0]	34360	1			T4	203		T10	69		T14	1
all_pins[7]	values[0x0]	612501	1			T1	2		T2	4		T3	2
all_pins[7]	values[0x1]	34377	1			T4	203		T10	69		T14	1
all_pins[7]	transitions[0x0=>0x1]	34355	1			T4	203		T10	69		T14	1
all_pins[7]	transitions[0x1=>0x0]	64	1			T17	3		T39	1		T182	1
all_pins[8]	values[0x0]	646792	1			T1	2		T2	4		T3	2
all_pins[8]	values[0x1]	86	1			T17	3		T39	1		T182	1
all_pins[8]	transitions[0x0=>0x1]	61	1			T17	1		T39	1		T43	1
all_pins[8]	transitions[0x1=>0x0]	439766	1			T2	1		T4	7		T10	6
all_pins[9]	values[0x0]	207087	1			T1	2		T2	3		T3	2
all_pins[9]	values[0x1]	439791	1			T2	1		T4	7		T10	6
all_pins[9]	transitions[0x0=>0x1]	439772	1			T2	1		T4	7		T10	6
all_pins[9]	transitions[0x1=>0x0]	62	1			T39	2		T27	2		T124	1
all_pins[10]	values[0x0]	646797	1			T1	2		T2	4		T3	2
all_pins[10]	values[0x1]	81	1			T17	1		T39	3		T27	2
all_pins[10]	transitions[0x0=>0x1]	61	1			T17	1		T39	2		T27	2
all_pins[10]	transitions[0x1=>0x0]	640599	1			T1	2		T2	4		T3	2
all_pins[11]	values[0x0]	6259	1			T4	3		T5	1		T9	2
all_pins[11]	values[0x1]	640619	1			T1	2		T2	4		T3	2
all_pins[11]	transitions[0x0=>0x1]	640593	1			T1	2		T2	4		T3	2
all_pins[11]	transitions[0x1=>0x0]	112	1			T56	1		T57	1		T17	1
all_pins[12]	values[0x0]	646740	1			T1	2		T2	4		T3	2
all_pins[12]	values[0x1]	138	1			T56	1		T57	1		T17	1
all_pins[12]	transitions[0x0=>0x1]	122	1			T56	1		T57	1		T17	1
all_pins[12]	transitions[0x1=>0x0]	69	1			T17	1		T43	1		T242	1
all_pins[13]	values[0x0]	646793	1			T1	2		T2	4		T3	2
all_pins[13]	values[0x1]	85	1			T17	1		T43	1		T242	2
all_pins[13]	transitions[0x0=>0x1]	58	1			T17	1		T43	1		T242	1
all_pins[13]	transitions[0x1=>0x0]	100	1			T17	1		T39	3		T242	2
all_pins[14]	values[0x0]	646751	1			T1	2		T2	4		T3	2
all_pins[14]	values[0x1]	127	1			T17	1		T39	3		T242	3
all_pins[14]	transitions[0x0=>0x1]	81	1			T17	1		T39	3		T242	2
all_pins[14]	transitions[0x1=>0x0]	544800	1			T1	1		T2	3		T3	1