Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	388	1			T17	7		T39	7		T182	4
all_values[1]	388	1			T17	7		T39	7		T182	4
all_values[2]	388	1			T17	7		T39	7		T182	4
all_values[3]	388	1			T17	7		T39	7		T182	4
all_values[4]	388	1			T17	7		T39	7		T182	4
all_values[5]	388	1			T17	7		T39	7		T182	4
all_values[6]	388	1			T17	7		T39	7		T182	4
all_values[7]	388	1			T17	7		T39	7		T182	4
all_values[8]	388	1			T17	7		T39	7		T182	4
all_values[9]	388	1			T17	7		T39	7		T182	4
all_values[10]	388	1			T17	7		T39	7		T182	4
all_values[11]	388	1			T17	7		T39	7		T182	4
all_values[12]	388	1			T17	7		T39	7		T182	4
all_values[13]	388	1			T17	7		T39	7		T182	4
all_values[14]	388	1			T17	7		T39	7		T182	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3004

1

T17

52

T39

59

T182

33

auto[1]

2816

1

T17

53

T39

46

T182

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

950

1

T17

12

T39

11

T182

14

auto[1]

4870

1

T17

93

T39

94

T182

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3387

1

T17

58

T39

60

T182

39

auto[1]

2433

1

T17

47

T39

45

T182

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	27	1			T182	2		T43	1		T126	1
all_values[0]	auto[0]	auto[0]	auto[1]	82	1			T17	1		T39	3		T43	3
all_values[0]	auto[0]	auto[1]	auto[0]	28	1			T182	2		T267	1		T268	1
all_values[0]	auto[0]	auto[1]	auto[1]	91	1			T17	2		T39	1		T43	2
all_values[0]	auto[1]	auto[0]	auto[1]	75	1			T17	2		T39	3		T43	1
all_values[0]	auto[1]	auto[1]	auto[1]	85	1			T17	2		T242	1		T27	2
all_values[1]	auto[0]	auto[0]	auto[0]	32	1			T17	1		T43	3		T242	2
all_values[1]	auto[0]	auto[0]	auto[1]	83	1			T182	1		T242	2		T27	4
all_values[1]	auto[0]	auto[1]	auto[0]	26	1			T182	1		T43	4		T242	1
all_values[1]	auto[0]	auto[1]	auto[1]	91	1			T17	3		T39	3		T27	5
all_values[1]	auto[1]	auto[0]	auto[1]	76	1			T17	1		T39	1		T182	1
all_values[1]	auto[1]	auto[1]	auto[1]	80	1			T17	2		T39	3		T182	1
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T17	1		T242	1		T269	3
all_values[2]	auto[0]	auto[0]	auto[1]	85	1			T17	1		T39	2		T182	2
all_values[2]	auto[0]	auto[1]	auto[0]	26	1			T27	1		T269	1		T270	2
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T17	1		T39	2		T43	2
all_values[2]	auto[1]	auto[0]	auto[1]	99	1			T17	1		T39	2		T182	1
all_values[2]	auto[1]	auto[1]	auto[1]	72	1			T17	3		T39	1		T182	1
all_values[3]	auto[0]	auto[0]	auto[0]	39	1			T17	1		T39	2		T242	1
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T17	4		T39	3		T43	1
all_values[3]	auto[0]	auto[1]	auto[0]	40	1			T43	3		T242	4		T269	2
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T182	3		T43	1		T27	5
all_values[3]	auto[1]	auto[0]	auto[1]	80	1			T17	2		T39	2		T182	1
all_values[3]	auto[1]	auto[1]	auto[1]	68	1			T27	2		T124	1		T267	4
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T39	1		T182	1		T124	2
all_values[4]	auto[0]	auto[0]	auto[1]	85	1			T39	2		T182	2		T43	1
all_values[4]	auto[0]	auto[1]	auto[0]	21	1			T124	3		T269	1		T268	2
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T17	3		T39	2		T43	1
all_values[4]	auto[1]	auto[0]	auto[1]	79	1			T17	1		T39	2		T43	4
all_values[4]	auto[1]	auto[1]	auto[1]	74	1			T17	3		T182	1		T43	1
all_values[5]	auto[0]	auto[0]	auto[0]	37	1			T39	2		T124	1		T267	1
all_values[5]	auto[0]	auto[0]	auto[1]	74	1			T39	2		T182	2		T43	1
all_values[5]	auto[0]	auto[1]	auto[0]	32	1			T267	1		T269	1		T268	1
all_values[5]	auto[0]	auto[1]	auto[1]	68	1			T17	1		T39	1		T182	1
all_values[5]	auto[1]	auto[0]	auto[1]	90	1			T17	4		T39	1		T43	1
all_values[5]	auto[1]	auto[1]	auto[1]	87	1			T17	2		T39	1		T182	1
all_values[6]	auto[0]	auto[0]	auto[0]	43	1			T39	1		T242	1		T267	1
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T39	1		T43	1		T27	4
all_values[6]	auto[0]	auto[1]	auto[0]	23	1			T43	3		T267	1		T271	2
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T17	4		T39	1		T182	3
all_values[6]	auto[1]	auto[0]	auto[1]	84	1			T17	2		T39	1		T43	1
all_values[6]	auto[1]	auto[1]	auto[1]	84	1			T17	1		T39	3		T182	1
all_values[7]	auto[0]	auto[0]	auto[0]	44	1			T17	5		T182	2		T27	2
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T39	1		T43	2		T242	1
all_values[7]	auto[0]	auto[1]	auto[0]	39	1			T17	2		T182	2		T43	1
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T39	3		T242	4		T27	2
all_values[7]	auto[1]	auto[0]	auto[1]	77	1			T39	3		T43	2		T242	1
all_values[7]	auto[1]	auto[1]	auto[1]	73	1			T43	2		T242	1		T27	4
all_values[8]	auto[0]	auto[0]	auto[0]	35	1			T182	1		T124	1		T272	2
all_values[8]	auto[0]	auto[0]	auto[1]	86	1			T17	1		T39	3		T182	2
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T43	1		T267	1		T273	1
all_values[8]	auto[0]	auto[1]	auto[1]	84	1			T17	2		T39	1		T242	4
all_values[8]	auto[1]	auto[0]	auto[1]	84	1			T17	2		T39	2		T43	2
all_values[8]	auto[1]	auto[1]	auto[1]	77	1			T17	2		T39	1		T182	1
all_values[9]	auto[0]	auto[0]	auto[0]	49	1			T242	5		T124	1		T274	3
all_values[9]	auto[0]	auto[0]	auto[1]	63	1			T43	1		T27	2		T124	1
all_values[9]	auto[0]	auto[1]	auto[0]	32	1			T39	1		T43	1		T242	2
all_values[9]	auto[0]	auto[1]	auto[1]	79	1			T17	5		T39	2		T182	1
all_values[9]	auto[1]	auto[0]	auto[1]	85	1			T17	1		T43	2		T27	4
all_values[9]	auto[1]	auto[1]	auto[1]	80	1			T17	1		T39	4		T182	3
all_values[10]	auto[0]	auto[0]	auto[0]	33	1			T39	2		T182	1		T43	2
all_values[10]	auto[0]	auto[0]	auto[1]	87	1			T17	2		T182	1		T43	2
all_values[10]	auto[0]	auto[1]	auto[0]	18	1			T39	1		T182	1		T125	1
all_values[10]	auto[0]	auto[1]	auto[1]	85	1			T17	4		T39	1		T43	1
all_values[10]	auto[1]	auto[0]	auto[1]	90	1			T17	1		T182	1		T43	1
all_values[10]	auto[1]	auto[1]	auto[1]	75	1			T39	3		T43	1		T27	4
all_values[11]	auto[0]	auto[0]	auto[0]	39	1			T124	5		T125	1		T274	1
all_values[11]	auto[0]	auto[0]	auto[1]	76	1			T39	2		T182	2		T43	2
all_values[11]	auto[0]	auto[1]	auto[0]	27	1			T242	1		T124	1		T117	1
all_values[11]	auto[0]	auto[1]	auto[1]	91	1			T17	2		T39	2		T43	2
all_values[11]	auto[1]	auto[0]	auto[1]	83	1			T17	5		T182	2		T43	2
all_values[11]	auto[1]	auto[1]	auto[1]	72	1			T39	3		T43	1		T242	2
all_values[12]	auto[0]	auto[0]	auto[0]	25	1			T17	1		T242	1		T27	2
all_values[12]	auto[0]	auto[0]	auto[1]	92	1			T39	4		T182	1		T43	1
all_values[12]	auto[0]	auto[1]	auto[0]	31	1			T182	1		T117	1		T270	3
all_values[12]	auto[0]	auto[1]	auto[1]	79	1			T17	4		T39	1		T43	4
all_values[12]	auto[1]	auto[0]	auto[1]	81	1			T39	2		T182	1		T242	2
all_values[12]	auto[1]	auto[1]	auto[1]	80	1			T17	2		T182	1		T43	2
all_values[13]	auto[0]	auto[0]	auto[0]	33	1			T17	1		T39	1		T267	3
all_values[13]	auto[0]	auto[0]	auto[1]	86	1			T17	2		T39	1		T182	2
all_values[13]	auto[0]	auto[1]	auto[0]	15	1			T43	1		T267	1		T269	1
all_values[13]	auto[0]	auto[1]	auto[1]	78	1			T17	2		T39	1		T43	1
all_values[13]	auto[1]	auto[0]	auto[1]	99	1			T17	2		T39	3		T182	1
all_values[13]	auto[1]	auto[1]	auto[1]	77	1			T39	1		T182	1		T43	3
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T242	1		T27	1		T124	4
all_values[14]	auto[0]	auto[0]	auto[1]	70	1			T17	2		T39	1		T182	2
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T43	1		T267	2		T270	1
all_values[14]	auto[0]	auto[1]	auto[1]	82	1			T39	3		T43	3		T242	3
all_values[14]	auto[1]	auto[0]	auto[1]	86	1			T17	5		T39	3		T182	1
all_values[14]	auto[1]	auto[1]	auto[1]	81	1			T182	1		T43	2		T242	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal