Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	654138	1			T1	4		T2	2		T3	2
all_values[1]	654138	1			T1	4		T2	2		T3	2
all_values[2]	654138	1			T1	4		T2	2		T3	2
all_values[3]	654138	1			T1	4		T2	2		T3	2
all_values[4]	654138	1			T1	4		T2	2		T3	2
all_values[5]	654138	1			T1	4		T2	2		T3	2
all_values[6]	654138	1			T1	4		T2	2		T3	2
all_values[7]	654138	1			T1	4		T2	2		T3	2
all_values[8]	654138	1			T1	4		T2	2		T3	2
all_values[9]	654138	1			T1	4		T2	2		T3	2
all_values[10]	654138	1			T1	4		T2	2		T3	2
all_values[11]	654138	1			T1	4		T2	2		T3	2
all_values[12]	654138	1			T1	4		T2	2		T3	2
all_values[13]	654138	1			T1	4		T2	2		T3	2
all_values[14]	654138	1			T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8109853

1

T1

51

T2

26

T3

26

auto[1]

1702217

1

T1

9

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9489919

1

T1

60

T2

30

T3

30

auto[1]

322151

1

T24

121

T196

55037

T197

5651

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	112126	1			T5	2		T6	1		T14	13
all_values[0]	auto[0]	auto[1]	3001	1			T24	6		T196	512		T197	8
all_values[0]	auto[1]	auto[0]	517421	1			T1	4		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	21590	1			T24	3		T196	3418		T197	370
all_values[1]	auto[0]	auto[0]	629241	1			T1	4		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	24363	1			T24	3		T196	3930		T197	373
all_values[1]	auto[1]	auto[0]	330	1			T38	2		T290	2		T291	2
all_values[1]	auto[1]	auto[1]	204	1			T24	5		T196	1		T197	4
all_values[2]	auto[0]	auto[0]	629391	1			T1	4		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	24405	1			T24	5		T196	3929		T197	374
all_values[2]	auto[1]	auto[0]	189	1			T9	1		T171	1		T292	2
all_values[2]	auto[1]	auto[1]	153	1			T24	4		T196	1		T197	1
all_values[3]	auto[0]	auto[0]	629560	1			T1	4		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	24388	1			T24	7		T196	3931		T197	373
all_values[3]	auto[1]	auto[1]	190	1			T24	2		T196	1		T197	4
all_values[4]	auto[0]	auto[0]	642935	1			T1	4		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	11025	1			T24	3		T196	3931		T197	374
all_values[4]	auto[1]	auto[0]	22	1			T271	1		T90	1		T285	2
all_values[4]	auto[1]	auto[1]	156	1			T24	1		T196	1		T197	3
all_values[5]	auto[0]	auto[0]	629570	1			T1	4		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	24381	1			T24	5		T196	3928		T197	372
all_values[5]	auto[1]	auto[1]	187	1			T24	4		T196	3		T197	6
all_values[6]	auto[0]	auto[0]	633502	1			T1	4		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	20471	1			T24	5		T197	374		T129	7
all_values[6]	auto[1]	auto[1]	165	1			T24	3		T197	1		T140	4
all_values[7]	auto[0]	auto[0]	604285	1			T1	4		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	23345	1			T24	2		T196	3621		T197	311
all_values[7]	auto[1]	auto[0]	25269	1			T6	1		T14	10		T15	119
all_values[7]	auto[1]	auto[1]	1239	1			T24	7		T196	311		T197	64
all_values[8]	auto[0]	auto[0]	631182	1			T1	4		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	22771	1			T24	6		T196	3928		T197	372
all_values[8]	auto[1]	auto[1]	185	1			T24	3		T196	2		T197	6
all_values[9]	auto[0]	auto[0]	164644	1			T1	3		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	6747	1			T24	2		T196	915		T197	358
all_values[9]	auto[1]	auto[0]	464918	1			T1	1		T6	1		T14	3
all_values[9]	auto[1]	auto[1]	17829	1			T24	4		T196	3016		T197	18
all_values[10]	auto[0]	auto[0]	631955	1			T1	4		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	22035	1			T24	7		T196	3930		T197	373
all_values[10]	auto[1]	auto[1]	148	1			T24	2		T196	2		T197	4
all_values[11]	auto[0]	auto[0]	2352	1			T5	2		T6	1		T14	2
all_values[11]	auto[0]	auto[1]	358	1			T24	4		T196	7		T197	6
all_values[11]	auto[1]	auto[0]	627209	1			T1	4		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	24219	1			T24	5		T196	3925		T197	372
all_values[12]	auto[0]	auto[0]	629515	1			T1	4		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	24395	1			T24	3		T196	3930		T197	374
all_values[12]	auto[1]	auto[0]	64	1			T9	1		T69	1		T70	1
all_values[12]	auto[1]	auto[1]	164	1			T24	2		T196	2		T197	4
all_values[13]	auto[0]	auto[0]	641312	1			T1	4		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	12638	1			T24	3		T196	3929		T197	371
all_values[13]	auto[1]	auto[1]	188	1			T24	6		T196	2		T197	4
all_values[14]	auto[0]	auto[0]	642927	1			T1	4		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	11033	1			T24	6		T196	3929		T197	374
all_values[14]	auto[1]	auto[1]	178	1			T24	3		T196	2		T197	3