Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	654138	1			T1	4		T2	2		T3	2
all_pins[1]	654138	1			T1	4		T2	2		T3	2
all_pins[2]	654138	1			T1	4		T2	2		T3	2
all_pins[3]	654138	1			T1	4		T2	2		T3	2
all_pins[4]	654138	1			T1	4		T2	2		T3	2
all_pins[5]	654138	1			T1	4		T2	2		T3	2
all_pins[6]	654138	1			T1	4		T2	2		T3	2
all_pins[7]	654138	1			T1	4		T2	2		T3	2
all_pins[8]	654138	1			T1	4		T2	2		T3	2
all_pins[9]	654138	1			T1	4		T2	2		T3	2
all_pins[10]	654138	1			T1	4		T2	2		T3	2
all_pins[11]	654138	1			T1	4		T2	2		T3	2
all_pins[12]	654138	1			T1	4		T2	2		T3	2
all_pins[13]	654138	1			T1	4		T2	2		T3	2
all_pins[14]	654138	1			T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8116485	1			T1	51		T2	26		T3	26
values[0x1]	1695585	1			T1	9		T2	4		T3	4
transitions[0x0=>0x1]	1694764	1			T1	9		T2	4		T3	4
transitions[0x1=>0x0]	1693462	1			T1	8		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	118842	1			T5	2		T6	1		T9	1
all_pins[0]	values[0x1]	535296	1			T1	4		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	534835	1			T1	4		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	67	1			T24	2		T196	1		T197	1
all_pins[1]	values[0x0]	653610	1			T1	4		T2	2		T3	2
all_pins[1]	values[0x1]	528	1			T38	2		T24	3		T290	3
all_pins[1]	transitions[0x0=>0x1]	504	1			T38	2		T24	2		T290	3
all_pins[1]	transitions[0x1=>0x0]	100	1			T297	1		T298	1		T187	1
all_pins[2]	values[0x0]	654014	1			T1	4		T2	2		T3	2
all_pins[2]	values[0x1]	124	1			T297	1		T298	1		T187	1
all_pins[2]	transitions[0x0=>0x1]	105	1			T297	1		T298	1		T187	1
all_pins[2]	transitions[0x1=>0x0]	74	1			T24	1		T196	1		T197	2
all_pins[3]	values[0x0]	654045	1			T1	4		T2	2		T3	2
all_pins[3]	values[0x1]	93	1			T24	2		T196	1		T197	2
all_pins[3]	transitions[0x0=>0x1]	76	1			T24	2		T196	1		T197	2
all_pins[3]	transitions[0x1=>0x0]	84	1			T24	1		T271	1		T90	2
all_pins[4]	values[0x0]	654037	1			T1	4		T2	2		T3	2
all_pins[4]	values[0x1]	101	1			T24	1		T271	1		T90	2
all_pins[4]	transitions[0x0=>0x1]	86	1			T24	1		T271	1		T90	2
all_pins[4]	transitions[0x1=>0x0]	74	1			T196	2		T197	2		T129	1
all_pins[5]	values[0x0]	654049	1			T1	4		T2	2		T3	2
all_pins[5]	values[0x1]	89	1			T196	2		T197	3		T129	1
all_pins[5]	transitions[0x0=>0x1]	61	1			T196	2		T197	3		T129	1
all_pins[5]	transitions[0x1=>0x0]	51	1			T24	2		T140	3		T117	3
all_pins[6]	values[0x0]	654059	1			T1	4		T2	2		T3	2
all_pins[6]	values[0x1]	79	1			T24	2		T140	3		T117	3
all_pins[6]	transitions[0x0=>0x1]	56	1			T24	2		T140	2		T117	1
all_pins[6]	transitions[0x1=>0x0]	28881	1			T6	1		T15	131		T38	215
all_pins[7]	values[0x0]	625234	1			T1	4		T2	2		T3	2
all_pins[7]	values[0x1]	28904	1			T6	1		T15	131		T38	215
all_pins[7]	transitions[0x0=>0x1]	28874	1			T6	1		T15	131		T38	215
all_pins[7]	transitions[0x1=>0x0]	76	1			T24	2		T197	2		T140	1
all_pins[8]	values[0x0]	654032	1			T1	4		T2	2		T3	2
all_pins[8]	values[0x1]	106	1			T24	3		T197	2		T140	1
all_pins[8]	transitions[0x0=>0x1]	74	1			T24	3		T197	2		T140	1
all_pins[8]	transitions[0x1=>0x0]	482646	1			T1	1		T6	1		T14	4
all_pins[9]	values[0x0]	171460	1			T1	3		T2	2		T3	2
all_pins[9]	values[0x1]	482678	1			T1	1		T6	1		T14	4
all_pins[9]	transitions[0x0=>0x1]	482663	1			T1	1		T6	1		T14	4
all_pins[9]	transitions[0x1=>0x0]	60	1			T24	2		T196	2		T197	1
all_pins[10]	values[0x0]	654063	1			T1	4		T2	2		T3	2
all_pins[10]	values[0x1]	75	1			T24	2		T196	2		T197	1
all_pins[10]	transitions[0x0=>0x1]	55	1			T24	1		T196	1		T197	1
all_pins[10]	transitions[0x1=>0x0]	647143	1			T1	4		T2	2		T3	2
all_pins[11]	values[0x0]	6975	1			T5	2		T6	1		T9	1
all_pins[11]	values[0x1]	647163	1			T1	4		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	647127	1			T1	4		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	119	1			T9	1		T69	1		T70	1
all_pins[12]	values[0x0]	653983	1			T1	4		T2	2		T3	2
all_pins[12]	values[0x1]	155	1			T9	1		T69	1		T70	1
all_pins[12]	transitions[0x0=>0x1]	123	1			T9	1		T69	1		T70	1
all_pins[12]	transitions[0x1=>0x0]	71	1			T24	3		T196	2		T197	1
all_pins[13]	values[0x0]	654035	1			T1	4		T2	2		T3	2
all_pins[13]	values[0x1]	103	1			T24	5		T196	2		T197	2
all_pins[13]	transitions[0x0=>0x1]	70	1			T24	3		T196	2		T197	2
all_pins[13]	transitions[0x1=>0x0]	58	1			T197	1		T129	1		T140	1
all_pins[14]	values[0x0]	654047	1			T1	4		T2	2		T3	2
all_pins[14]	values[0x1]	91	1			T24	2		T197	1		T129	1
all_pins[14]	transitions[0x0=>0x1]	55	1			T24	2		T197	1		T140	2
all_pins[14]	transitions[0x1=>0x0]	533958	1			T1	3		T2	1		T3	1