Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	382	1			T24	7		T196	4		T197	7
all_values[1]	382	1			T24	7		T196	4		T197	7
all_values[2]	382	1			T24	7		T196	4		T197	7
all_values[3]	382	1			T24	7		T196	4		T197	7
all_values[4]	382	1			T24	7		T196	4		T197	7
all_values[5]	382	1			T24	7		T196	4		T197	7
all_values[6]	382	1			T24	7		T196	4		T197	7
all_values[7]	382	1			T24	7		T196	4		T197	7
all_values[8]	382	1			T24	7		T196	4		T197	7
all_values[9]	382	1			T24	7		T196	4		T197	7
all_values[10]	382	1			T24	7		T196	4		T197	7
all_values[11]	382	1			T24	7		T196	4		T197	7
all_values[12]	382	1			T24	7		T196	4		T197	7
all_values[13]	382	1			T24	7		T196	4		T197	7
all_values[14]	382	1			T24	7		T196	4		T197	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2972

1

T24

41

T196

34

T197

63

auto[1]

2758

1

T24

64

T196

26

T197

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

941

1

T24

14

T196

15

T197

19

auto[1]

4789

1

T24

91

T196

45

T197

86

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3328

1

T24

56

T196

37

T197

63

auto[1]

2402

1

T24

49

T196

23

T197

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	20	1			T132	2		T299	1		T300	1
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T24	3		T197	3		T129	1
all_values[0]	auto[0]	auto[1]	auto[0]	23	1			T196	2		T129	1		T117	1
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T24	1		T196	1		T197	1
all_values[0]	auto[1]	auto[0]	auto[1]	92	1			T24	1		T197	2		T140	2
all_values[0]	auto[1]	auto[1]	auto[1]	82	1			T24	2		T196	1		T197	1
all_values[1]	auto[0]	auto[0]	auto[0]	33	1			T24	1		T196	1		T197	1
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T24	1		T197	1		T140	2
all_values[1]	auto[0]	auto[1]	auto[0]	32	1			T117	2		T301	1		T34	1
all_values[1]	auto[0]	auto[1]	auto[1]	59	1			T196	2		T197	1		T129	1
all_values[1]	auto[1]	auto[0]	auto[1]	80	1			T24	2		T196	1		T197	2
all_values[1]	auto[1]	auto[1]	auto[1]	98	1			T24	3		T197	2		T129	1
all_values[2]	auto[0]	auto[0]	auto[0]	34	1			T196	2		T197	1		T140	1
all_values[2]	auto[0]	auto[0]	auto[1]	59	1			T24	1		T196	1		T129	1
all_values[2]	auto[0]	auto[1]	auto[0]	39	1			T197	2		T129	2		T117	2
all_values[2]	auto[0]	auto[1]	auto[1]	97	1			T24	2		T197	3		T140	1
all_values[2]	auto[1]	auto[0]	auto[1]	83	1			T24	1		T196	1		T140	2
all_values[2]	auto[1]	auto[1]	auto[1]	70	1			T24	3		T197	1		T129	1
all_values[3]	auto[0]	auto[0]	auto[0]	26	1			T197	1		T130	1		T302	1
all_values[3]	auto[0]	auto[0]	auto[1]	94	1			T196	2		T197	1		T140	2
all_values[3]	auto[0]	auto[1]	auto[0]	29	1			T129	2		T117	1		T303	1
all_values[3]	auto[0]	auto[1]	auto[1]	59	1			T24	3		T197	3		T129	1
all_values[3]	auto[1]	auto[0]	auto[1]	95	1			T24	1		T129	1		T140	6
all_values[3]	auto[1]	auto[1]	auto[1]	79	1			T24	3		T196	2		T197	2
all_values[4]	auto[0]	auto[0]	auto[0]	35	1			T197	1		T117	1		T301	3
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T196	3		T197	1		T140	3
all_values[4]	auto[0]	auto[1]	auto[0]	44	1			T24	5		T129	2		T117	4
all_values[4]	auto[0]	auto[1]	auto[1]	64	1			T24	1		T197	2		T129	1
all_values[4]	auto[1]	auto[0]	auto[1]	88	1			T196	1		T197	3		T129	1
all_values[4]	auto[1]	auto[1]	auto[1]	68	1			T24	1		T140	3		T117	1
all_values[5]	auto[0]	auto[0]	auto[0]	26	1			T196	1		T140	1		T303	1
all_values[5]	auto[0]	auto[0]	auto[1]	76	1			T24	3		T140	3		T117	3
all_values[5]	auto[0]	auto[1]	auto[0]	38	1			T301	2		T304	2		T299	3
all_values[5]	auto[0]	auto[1]	auto[1]	84	1			T196	1		T197	1		T129	2
all_values[5]	auto[1]	auto[0]	auto[1]	93	1			T24	4		T196	1		T197	5
all_values[5]	auto[1]	auto[1]	auto[1]	65	1			T196	1		T197	1		T140	3
all_values[6]	auto[0]	auto[0]	auto[0]	43	1			T24	1		T196	2		T197	3
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T24	3		T197	2		T140	2
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T196	2		T140	1		T303	2
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T197	1		T129	1		T140	2
all_values[6]	auto[1]	auto[0]	auto[1]	76	1			T24	1		T197	1		T129	1
all_values[6]	auto[1]	auto[1]	auto[1]	70	1			T24	2		T140	4		T117	4
all_values[7]	auto[0]	auto[0]	auto[0]	30	1			T197	2		T140	2		T304	1
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T24	2		T197	3		T140	2
all_values[7]	auto[0]	auto[1]	auto[0]	23	1			T197	1		T117	1		T301	2
all_values[7]	auto[0]	auto[1]	auto[1]	95	1			T24	2		T196	1		T129	2
all_values[7]	auto[1]	auto[0]	auto[1]	85	1			T24	2		T196	2		T140	3
all_values[7]	auto[1]	auto[1]	auto[1]	78	1			T24	1		T196	1		T197	1
all_values[8]	auto[0]	auto[0]	auto[0]	41	1			T304	3		T130	2		T302	1
all_values[8]	auto[0]	auto[0]	auto[1]	73	1			T24	1		T196	1		T197	3
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T196	2		T129	4		T117	1
all_values[8]	auto[0]	auto[1]	auto[1]	89	1			T24	4		T197	1		T140	4
all_values[8]	auto[1]	auto[0]	auto[1]	79	1			T196	1		T197	1		T140	2
all_values[8]	auto[1]	auto[1]	auto[1]	78	1			T24	2		T197	2		T140	2
all_values[9]	auto[0]	auto[0]	auto[0]	31	1			T24	1		T197	1		T129	2
all_values[9]	auto[0]	auto[0]	auto[1]	86	1			T24	1		T196	2		T197	2
all_values[9]	auto[0]	auto[1]	auto[0]	24	1			T24	2		T196	1		T197	1
all_values[9]	auto[0]	auto[1]	auto[1]	77	1			T197	1		T140	2		T117	2
all_values[9]	auto[1]	auto[0]	auto[1]	83	1			T24	1		T140	6		T117	1
all_values[9]	auto[1]	auto[1]	auto[1]	81	1			T24	2		T196	1		T197	2
all_values[10]	auto[0]	auto[0]	auto[0]	51	1			T197	1		T140	3		T117	1
all_values[10]	auto[0]	auto[0]	auto[1]	76	1			T24	2		T196	2		T197	1
all_values[10]	auto[0]	auto[1]	auto[0]	33	1			T140	1		T117	1		T303	4
all_values[10]	auto[0]	auto[1]	auto[1]	74	1			T24	3		T197	1		T129	1
all_values[10]	auto[1]	auto[0]	auto[1]	74	1			T197	2		T129	1		T140	4
all_values[10]	auto[1]	auto[1]	auto[1]	74	1			T24	2		T196	2		T197	2
all_values[11]	auto[0]	auto[0]	auto[0]	30	1			T129	1		T140	1		T304	1
all_values[11]	auto[0]	auto[0]	auto[1]	88	1			T197	2		T140	3		T34	3
all_values[11]	auto[0]	auto[1]	auto[0]	26	1			T117	1		T301	1		T130	1
all_values[11]	auto[0]	auto[1]	auto[1]	88	1			T24	2		T196	2		T129	2
all_values[11]	auto[1]	auto[0]	auto[1]	80	1			T24	1		T196	2		T197	5
all_values[11]	auto[1]	auto[1]	auto[1]	70	1			T24	4		T140	1		T117	3
all_values[12]	auto[0]	auto[0]	auto[0]	43	1			T24	2		T140	1		T301	3
all_values[12]	auto[0]	auto[0]	auto[1]	80	1			T196	2		T197	1		T140	2
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T24	2		T117	1		T301	1
all_values[12]	auto[0]	auto[1]	auto[1]	69	1			T24	1		T197	2		T129	2
all_values[12]	auto[1]	auto[0]	auto[1]	85	1			T24	1		T197	2		T140	2
all_values[12]	auto[1]	auto[1]	auto[1]	79	1			T24	1		T196	2		T197	2
all_values[13]	auto[0]	auto[0]	auto[0]	29	1			T196	1		T197	2		T302	2
all_values[13]	auto[0]	auto[0]	auto[1]	77	1			T197	1		T140	3		T301	2
all_values[13]	auto[0]	auto[1]	auto[0]	26	1			T197	1		T301	1		T302	2
all_values[13]	auto[0]	auto[1]	auto[1]	83	1			T24	2		T196	1		T197	1
all_values[13]	auto[1]	auto[0]	auto[1]	74	1			T24	1		T196	1		T197	2
all_values[13]	auto[1]	auto[1]	auto[1]	93	1			T24	4		T196	1		T129	2
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T196	1		T197	1		T34	1
all_values[14]	auto[0]	auto[0]	auto[1]	91	1			T24	1		T196	1		T197	3
all_values[14]	auto[0]	auto[1]	auto[0]	16	1			T34	1		T304	1		T302	1
all_values[14]	auto[0]	auto[1]	auto[1]	83	1			T24	3		T197	2		T140	3
all_values[14]	auto[1]	auto[0]	auto[1]	87	1			T24	2		T196	2		T129	2
all_values[14]	auto[1]	auto[1]	auto[1]	63	1			T24	1		T197	1		T129	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal