Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	777158	1			T1	3		T2	4		T4	2
all_values[1]	777158	1			T1	3		T2	4		T4	2
all_values[2]	777158	1			T1	3		T2	4		T4	2
all_values[3]	777158	1			T1	3		T2	4		T4	2
all_values[4]	777158	1			T1	3		T2	4		T4	2
all_values[5]	777158	1			T1	3		T2	4		T4	2
all_values[6]	777158	1			T1	3		T2	4		T4	2
all_values[7]	777158	1			T1	3		T2	4		T4	2
all_values[8]	777158	1			T1	3		T2	4		T4	2
all_values[9]	777158	1			T1	3		T2	4		T4	2
all_values[10]	777158	1			T1	3		T2	4		T4	2
all_values[11]	777158	1			T1	3		T2	4		T4	2
all_values[12]	777158	1			T1	3		T2	4		T4	2
all_values[13]	777158	1			T1	3		T2	4		T4	2
all_values[14]	777158	1			T1	3		T2	4		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9572085

1

T1

39

T2

51

T4

26

auto[1]

2085285

1

T1

6

T2

9

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11150667

1

T1

45

T2

60

T4

30

auto[1]

506703

1

T18

307

T33

5619

T179

8397

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103664	1			T1	1		T5	351		T6	110
all_values[0]	auto[0]	auto[1]	6059	1			T33	359		T179	470		T240	5
all_values[0]	auto[1]	auto[0]	639360	1			T1	2		T2	4		T4	2
all_values[0]	auto[1]	auto[1]	28075	1			T33	107		T179	89		T240	4
all_values[1]	auto[0]	auto[0]	742710	1			T1	3		T2	4		T4	2
all_values[1]	auto[0]	auto[1]	33887	1			T18	23		T33	464		T179	551
all_values[1]	auto[1]	auto[0]	301	1			T274	32		T22	1		T275	7
all_values[1]	auto[1]	auto[1]	260	1			T18	3		T33	1		T179	9
all_values[2]	auto[0]	auto[0]	742831	1			T1	3		T2	4		T4	2
all_values[2]	auto[0]	auto[1]	33959	1			T33	462		T179	551		T240	3
all_values[2]	auto[1]	auto[0]	195	1			T10	2		T155	2		T166	1
all_values[2]	auto[1]	auto[1]	173	1			T33	4		T179	9		T240	5
all_values[3]	auto[0]	auto[0]	742997	1			T1	3		T2	4		T4	2
all_values[3]	auto[0]	auto[1]	33975	1			T18	25		T33	462		T179	554
all_values[3]	auto[1]	auto[1]	186	1			T18	1		T33	5		T179	6
all_values[4]	auto[0]	auto[0]	743002	1			T1	3		T2	4		T4	2
all_values[4]	auto[0]	auto[1]	33972	1			T18	25		T33	462		T179	546
all_values[4]	auto[1]	auto[0]	13	1			T252	3		T254	1		T259	1
all_values[4]	auto[1]	auto[1]	171	1			T18	1		T33	5		T179	7
all_values[5]	auto[0]	auto[0]	743000	1			T1	3		T2	4		T4	2
all_values[5]	auto[0]	auto[1]	33949	1			T18	24		T33	459		T179	549
all_values[5]	auto[1]	auto[1]	209	1			T33	7		T179	12		T240	7
all_values[6]	auto[0]	auto[0]	743668	1			T1	3		T2	4		T4	2
all_values[6]	auto[0]	auto[1]	33305	1			T18	25		T33	462		T179	557
all_values[6]	auto[1]	auto[1]	185	1			T18	1		T33	5		T179	4
all_values[7]	auto[0]	auto[0]	712502	1			T1	2		T2	4		T4	2
all_values[7]	auto[0]	auto[1]	32125	1			T18	23		T33	410		T179	422
all_values[7]	auto[1]	auto[0]	30512	1			T1	1		T5	134		T7	30
all_values[7]	auto[1]	auto[1]	2019	1			T18	3		T33	56		T179	139
all_values[8]	auto[0]	auto[0]	743484	1			T1	3		T2	4		T4	2
all_values[8]	auto[0]	auto[1]	33497	1			T18	25		T33	5		T179	557
all_values[8]	auto[1]	auto[1]	177	1			T18	1		T33	1		T179	3
all_values[9]	auto[0]	auto[0]	162730	1			T1	2		T2	3		T4	2
all_values[9]	auto[0]	auto[1]	6119	1			T18	23		T33	5		T179	547
all_values[9]	auto[1]	auto[0]	580733	1			T1	1		T2	1		T5	7
all_values[9]	auto[1]	auto[1]	27576	1			T18	2		T33	4		T179	14
all_values[10]	auto[0]	auto[0]	746435	1			T1	3		T2	4		T4	2
all_values[10]	auto[0]	auto[1]	30543	1			T18	23		T33	461		T179	550
all_values[10]	auto[1]	auto[1]	180	1			T18	3		T33	5		T179	10
all_values[11]	auto[0]	auto[0]	2532	1			T1	1		T5	2		T6	2
all_values[11]	auto[0]	auto[1]	299	1			T18	21		T33	16		T179	9
all_values[11]	auto[1]	auto[0]	740472	1			T1	2		T2	4		T4	2
all_values[11]	auto[1]	auto[1]	33855	1			T18	5		T33	450		T179	552
all_values[12]	auto[0]	auto[0]	743421	1			T1	3		T2	4		T4	2
all_values[12]	auto[0]	auto[1]	33520	1			T18	24		T33	6		T179	553
all_values[12]	auto[1]	auto[0]	60	1			T57	1		T69	1		T70	1
all_values[12]	auto[1]	auto[1]	157	1			T18	2		T33	3		T179	6
all_values[13]	auto[0]	auto[0]	743042	1			T1	3		T2	4		T4	2
all_values[13]	auto[0]	auto[1]	33905	1			T33	460		T179	558		T240	5
all_values[13]	auto[1]	auto[1]	211	1			T33	7		T179	3		T240	4
all_values[14]	auto[0]	auto[0]	743003	1			T1	3		T2	4		T4	2
all_values[14]	auto[0]	auto[1]	33950	1			T18	22		T33	461		T179	552
all_values[14]	auto[1]	auto[1]	205	1			T18	2		T33	5		T179	8