Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	777158	1			T1	3		T2	4		T4	2
all_pins[1]	777158	1			T1	3		T2	4		T4	2
all_pins[2]	777158	1			T1	3		T2	4		T4	2
all_pins[3]	777158	1			T1	3		T2	4		T4	2
all_pins[4]	777158	1			T1	3		T2	4		T4	2
all_pins[5]	777158	1			T1	3		T2	4		T4	2
all_pins[6]	777158	1			T1	3		T2	4		T4	2
all_pins[7]	777158	1			T1	3		T2	4		T4	2
all_pins[8]	777158	1			T1	3		T2	4		T4	2
all_pins[9]	777158	1			T1	3		T2	4		T4	2
all_pins[10]	777158	1			T1	3		T2	4		T4	2
all_pins[11]	777158	1			T1	3		T2	4		T4	2
all_pins[12]	777158	1			T1	3		T2	4		T4	2
all_pins[13]	777158	1			T1	3		T2	4		T4	2
all_pins[14]	777158	1			T1	3		T2	4		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9578233	1			T1	39		T2	51		T4	26
values[0x1]	2079137	1			T1	6		T2	9		T4	4
transitions[0x0=>0x1]	2078329	1			T1	6		T2	9		T4	4
transitions[0x1=>0x0]	2077013	1			T1	5		T2	8		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	113346	1			T1	1		T5	351		T6	111
all_pins[0]	values[0x1]	663812	1			T1	2		T2	4		T4	2
all_pins[0]	transitions[0x0=>0x1]	663333	1			T1	2		T2	4		T4	2
all_pins[0]	transitions[0x1=>0x0]	67	1			T22	1		T179	1		T121	3
all_pins[1]	values[0x0]	776612	1			T1	3		T2	4		T4	2
all_pins[1]	values[0x1]	546	1			T274	43		T22	1		T275	9
all_pins[1]	transitions[0x0=>0x1]	523	1			T274	43		T22	1		T275	9
all_pins[1]	transitions[0x1=>0x0]	113	1			T166	1		T169	1		T283	1
all_pins[2]	values[0x0]	777022	1			T1	3		T2	4		T4	2
all_pins[2]	values[0x1]	136	1			T166	1		T169	1		T283	1
all_pins[2]	transitions[0x0=>0x1]	120	1			T166	1		T169	1		T283	1
all_pins[2]	transitions[0x1=>0x0]	85	1			T18	1		T33	1		T179	2
all_pins[3]	values[0x0]	777057	1			T1	3		T2	4		T4	2
all_pins[3]	values[0x1]	101	1			T18	1		T33	2		T179	3
all_pins[3]	transitions[0x0=>0x1]	77	1			T33	1		T179	1		T240	2
all_pins[3]	transitions[0x1=>0x0]	78	1			T33	3		T252	4		T179	2
all_pins[4]	values[0x0]	777056	1			T1	3		T2	4		T4	2
all_pins[4]	values[0x1]	102	1			T18	1		T33	4		T252	4
all_pins[4]	transitions[0x0=>0x1]	78	1			T18	1		T33	3		T252	4
all_pins[4]	transitions[0x1=>0x0]	78	1			T33	3		T179	3		T240	3
all_pins[5]	values[0x0]	777056	1			T1	3		T2	4		T4	2
all_pins[5]	values[0x1]	102	1			T33	4		T179	3		T240	4
all_pins[5]	transitions[0x0=>0x1]	83	1			T33	4		T179	3		T240	4
all_pins[5]	transitions[0x1=>0x0]	76	1			T33	1		T179	3		T121	6
all_pins[6]	values[0x0]	777063	1			T1	3		T2	4		T4	2
all_pins[6]	values[0x1]	95	1			T33	1		T179	3		T121	6
all_pins[6]	transitions[0x0=>0x1]	71	1			T33	1		T179	2		T121	6
all_pins[6]	transitions[0x1=>0x0]	35290	1			T1	1		T5	150		T7	30
all_pins[7]	values[0x0]	741844	1			T1	2		T2	4		T4	2
all_pins[7]	values[0x1]	35314	1			T1	1		T5	150		T7	30
all_pins[7]	transitions[0x0=>0x1]	35296	1			T1	1		T5	150		T7	30
all_pins[7]	transitions[0x1=>0x0]	74	1			T179	2		T121	3		T284	3
all_pins[8]	values[0x0]	777066	1			T1	3		T2	4		T4	2
all_pins[8]	values[0x1]	92	1			T179	2		T240	1		T121	3
all_pins[8]	transitions[0x0=>0x1]	69	1			T179	2		T240	1		T121	2
all_pins[8]	transitions[0x1=>0x0]	608210	1			T1	1		T2	1		T5	7
all_pins[9]	values[0x0]	168925	1			T1	2		T2	3		T4	2
all_pins[9]	values[0x1]	608233	1			T1	1		T2	1		T5	7
all_pins[9]	transitions[0x0=>0x1]	608219	1			T1	1		T2	1		T5	7
all_pins[9]	transitions[0x1=>0x0]	59	1			T18	1		T179	5		T240	1
all_pins[10]	values[0x0]	777085	1			T1	3		T2	4		T4	2
all_pins[10]	values[0x1]	73	1			T18	1		T179	5		T240	1
all_pins[10]	transitions[0x0=>0x1]	49	1			T18	1		T179	4		T285	1
all_pins[10]	transitions[0x1=>0x0]	770167	1			T1	2		T2	4		T4	2
all_pins[11]	values[0x0]	6967	1			T1	1		T5	2		T6	2
all_pins[11]	values[0x1]	770191	1			T1	2		T2	4		T4	2
all_pins[11]	transitions[0x0=>0x1]	770157	1			T1	2		T2	4		T4	2
all_pins[11]	transitions[0x1=>0x0]	107	1			T57	1		T69	1		T18	1
all_pins[12]	values[0x0]	777017	1			T1	3		T2	4		T4	2
all_pins[12]	values[0x1]	141	1			T57	1		T69	1		T18	1
all_pins[12]	transitions[0x0=>0x1]	122	1			T57	1		T69	1		T18	1
all_pins[12]	transitions[0x1=>0x0]	77	1			T33	3		T179	1		T240	2
all_pins[13]	values[0x0]	777062	1			T1	3		T2	4		T4	2
all_pins[13]	values[0x1]	96	1			T33	3		T179	1		T240	3
all_pins[13]	transitions[0x0=>0x1]	71	1			T33	3		T179	1		T240	1
all_pins[13]	transitions[0x1=>0x0]	78	1			T18	2		T33	2		T179	4
all_pins[14]	values[0x0]	777055	1			T1	3		T2	4		T4	2
all_pins[14]	values[0x1]	103	1			T18	2		T33	2		T179	4
all_pins[14]	transitions[0x0=>0x1]	61	1			T18	2		T33	1		T179	3
all_pins[14]	transitions[0x1=>0x0]	662454	1			T1	1		T2	3		T4	1