Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	413	1			T18	4		T33	11		T179	18
all_values[1]	413	1			T18	4		T33	11		T179	18
all_values[2]	413	1			T18	4		T33	11		T179	18
all_values[3]	413	1			T18	4		T33	11		T179	18
all_values[4]	413	1			T18	4		T33	11		T179	18
all_values[5]	413	1			T18	4		T33	11		T179	18
all_values[6]	413	1			T18	4		T33	11		T179	18
all_values[7]	413	1			T18	4		T33	11		T179	18
all_values[8]	413	1			T18	4		T33	11		T179	18
all_values[9]	413	1			T18	4		T33	11		T179	18
all_values[10]	413	1			T18	4		T33	11		T179	18
all_values[11]	413	1			T18	4		T33	11		T179	18
all_values[12]	413	1			T18	4		T33	11		T179	18
all_values[13]	413	1			T18	4		T33	11		T179	18
all_values[14]	413	1			T18	4		T33	11		T179	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3216

1

T18

41

T33

84

T179

156

auto[1]

2979

1

T18

19

T33

81

T179

114

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

982

1

T18

17

T33

24

T179

17

auto[1]

5213

1

T18

43

T33

141

T179

253

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3646

1

T18

37

T33

100

T179

158

auto[1]

2549

1

T18

23

T33

65

T179

112

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	39	1			T18	4		T179	2		T285	1
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T33	2		T179	7		T240	2
all_values[0]	auto[0]	auto[1]	auto[0]	21	1			T33	1		T286	1		T122	1
all_values[0]	auto[0]	auto[1]	auto[1]	98	1			T33	3		T179	5		T240	1
all_values[0]	auto[1]	auto[0]	auto[1]	91	1			T33	2		T179	1		T240	2
all_values[0]	auto[1]	auto[1]	auto[1]	75	1			T33	3		T179	3		T240	2
all_values[1]	auto[0]	auto[0]	auto[0]	29	1			T33	1		T286	1		T287	1
all_values[1]	auto[0]	auto[0]	auto[1]	95	1			T18	1		T33	3		T179	5
all_values[1]	auto[0]	auto[1]	auto[0]	30	1			T33	1		T179	1		T286	3
all_values[1]	auto[0]	auto[1]	auto[1]	89	1			T33	5		T179	3		T240	1
all_values[1]	auto[1]	auto[0]	auto[1]	85	1			T18	3		T179	4		T240	2
all_values[1]	auto[1]	auto[1]	auto[1]	85	1			T33	1		T179	5		T240	1
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T18	1		T123	1		T287	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T33	3		T179	3		T121	4
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T18	3		T33	1		T179	1
all_values[2]	auto[0]	auto[1]	auto[1]	101	1			T33	3		T179	5		T240	1
all_values[2]	auto[1]	auto[0]	auto[1]	87	1			T33	1		T179	4		T240	4
all_values[2]	auto[1]	auto[1]	auto[1]	86	1			T33	3		T179	5		T240	1
all_values[3]	auto[0]	auto[0]	auto[0]	34	1			T121	1		T285	1		T122	1
all_values[3]	auto[0]	auto[0]	auto[1]	97	1			T18	2		T33	3		T179	6
all_values[3]	auto[0]	auto[1]	auto[0]	23	1			T179	1		T121	1		T286	1
all_values[3]	auto[0]	auto[1]	auto[1]	97	1			T33	4		T179	2		T240	4
all_values[3]	auto[1]	auto[0]	auto[1]	79	1			T18	1		T33	1		T179	5
all_values[3]	auto[1]	auto[1]	auto[1]	83	1			T18	1		T33	3		T179	4
all_values[4]	auto[0]	auto[0]	auto[0]	40	1			T179	6		T285	1		T284	1
all_values[4]	auto[0]	auto[0]	auto[1]	79	1			T18	2		T33	2		T179	2
all_values[4]	auto[0]	auto[1]	auto[0]	27	1			T179	1		T287	1		T288	1
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T18	1		T33	4		T179	2
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T18	1		T33	2		T179	4
all_values[4]	auto[1]	auto[1]	auto[1]	90	1			T33	3		T179	3		T240	2
all_values[5]	auto[0]	auto[0]	auto[0]	34	1			T18	1		T285	6		T284	1
all_values[5]	auto[0]	auto[0]	auto[1]	96	1			T18	1		T33	3		T179	10
all_values[5]	auto[0]	auto[1]	auto[0]	23	1			T18	1		T33	1		T285	1
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T33	3		T179	4		T240	1
all_values[5]	auto[1]	auto[0]	auto[1]	95	1			T18	1		T33	3		T179	3
all_values[5]	auto[1]	auto[1]	auto[1]	78	1			T33	1		T179	1		T240	2
all_values[6]	auto[0]	auto[0]	auto[0]	36	1			T121	1		T285	1		T284	1
all_values[6]	auto[0]	auto[0]	auto[1]	90	1			T18	2		T33	4		T179	3
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T121	1		T285	1		T123	2
all_values[6]	auto[0]	auto[1]	auto[1]	93	1			T179	8		T121	6		T286	2
all_values[6]	auto[1]	auto[0]	auto[1]	90	1			T18	2		T33	4		T179	2
all_values[6]	auto[1]	auto[1]	auto[1]	78	1			T33	3		T179	5		T240	1
all_values[7]	auto[0]	auto[0]	auto[0]	36	1			T285	1		T287	2		T124	3
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T18	1		T33	4		T179	6
all_values[7]	auto[0]	auto[1]	auto[0]	34	1			T33	1		T286	1		T289	5
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T18	1		T33	4		T179	4
all_values[7]	auto[1]	auto[0]	auto[1]	76	1			T18	1		T179	5		T240	3
all_values[7]	auto[1]	auto[1]	auto[1]	86	1			T18	1		T33	2		T179	3
all_values[8]	auto[0]	auto[0]	auto[0]	48	1			T33	4		T179	1		T122	3
all_values[8]	auto[0]	auto[0]	auto[1]	76	1			T33	1		T179	7		T240	2
all_values[8]	auto[0]	auto[1]	auto[0]	37	1			T33	3		T240	1		T286	1
all_values[8]	auto[0]	auto[1]	auto[1]	96	1			T18	2		T179	3		T240	2
all_values[8]	auto[1]	auto[0]	auto[1]	84	1			T18	2		T33	3		T179	4
all_values[8]	auto[1]	auto[1]	auto[1]	72	1			T179	3		T121	3		T285	2
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T18	1		T240	1		T285	1
all_values[9]	auto[0]	auto[0]	auto[1]	86	1			T18	1		T33	2		T179	7
all_values[9]	auto[0]	auto[1]	auto[0]	28	1			T33	4		T240	1		T123	2
all_values[9]	auto[0]	auto[1]	auto[1]	84	1			T33	2		T179	4		T240	2
all_values[9]	auto[1]	auto[0]	auto[1]	102	1			T18	1		T33	2		T179	6
all_values[9]	auto[1]	auto[1]	auto[1]	77	1			T18	1		T33	1		T179	1
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T179	1		T121	1		T284	4
all_values[10]	auto[0]	auto[0]	auto[1]	81	1			T33	5		T179	3		T240	1
all_values[10]	auto[0]	auto[1]	auto[0]	21	1			T33	1		T121	1		T124	5
all_values[10]	auto[0]	auto[1]	auto[1]	93	1			T18	1		T179	4		T240	2
all_values[10]	auto[1]	auto[0]	auto[1]	109	1			T18	2		T33	5		T179	5
all_values[10]	auto[1]	auto[1]	auto[1]	71	1			T18	1		T179	5		T240	2
all_values[11]	auto[0]	auto[0]	auto[0]	33	1			T121	1		T285	2		T284	2
all_values[11]	auto[0]	auto[0]	auto[1]	82	1			T33	3		T179	6		T240	1
all_values[11]	auto[0]	auto[1]	auto[0]	29	1			T33	1		T240	1		T121	1
all_values[11]	auto[0]	auto[1]	auto[1]	95	1			T18	2		T33	1		T179	3
all_values[11]	auto[1]	auto[0]	auto[1]	93	1			T18	2		T33	4		T179	4
all_values[11]	auto[1]	auto[1]	auto[1]	81	1			T33	2		T179	5		T240	2
all_values[12]	auto[0]	auto[0]	auto[0]	44	1			T33	3		T240	2		T285	2
all_values[12]	auto[0]	auto[0]	auto[1]	87	1			T18	1		T33	1		T179	6
all_values[12]	auto[0]	auto[1]	auto[0]	38	1			T33	1		T179	2		T121	1
all_values[12]	auto[0]	auto[1]	auto[1]	87	1			T18	1		T33	3		T179	4
all_values[12]	auto[1]	auto[0]	auto[1]	84	1			T18	2		T33	1		T179	6
all_values[12]	auto[1]	auto[1]	auto[1]	73	1			T33	2		T240	3		T121	4
all_values[13]	auto[0]	auto[0]	auto[0]	40	1			T18	4		T284	1		T122	1
all_values[13]	auto[0]	auto[0]	auto[1]	82	1			T33	1		T179	8		T240	1
all_values[13]	auto[0]	auto[1]	auto[0]	37	1			T286	2		T122	3		T123	3
all_values[13]	auto[0]	auto[1]	auto[1]	79	1			T33	2		T179	3		T240	1
all_values[13]	auto[1]	auto[0]	auto[1]	95	1			T33	4		T179	3		T240	1
all_values[13]	auto[1]	auto[1]	auto[1]	80	1			T33	4		T179	4		T240	4
all_values[14]	auto[0]	auto[0]	auto[0]	37	1			T18	1		T179	1		T285	1
all_values[14]	auto[0]	auto[0]	auto[1]	88	1			T33	3		T179	5		T121	4
all_values[14]	auto[0]	auto[1]	auto[0]	21	1			T18	1		T33	1		T284	1
all_values[14]	auto[0]	auto[1]	auto[1]	84	1			T18	1		T33	2		T179	3
all_values[14]	auto[1]	auto[0]	auto[1]	109	1			T33	4		T179	5		T240	2
all_values[14]	auto[1]	auto[1]	auto[1]	74	1			T18	1		T33	1		T179	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal