Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.40 97.37 89.80 97.22 72.62 94.47 98.44 89.89


Total test records in report: 1866
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html
T1775 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3068215453 Jul 28 05:00:16 PM PDT 24 Jul 28 05:00:18 PM PDT 24 51465083 ps
T1776 /workspace/coverage/cover_reg_top/2.i2c_intr_test.2380202689 Jul 28 05:00:05 PM PDT 24 Jul 28 05:00:09 PM PDT 24 66146832 ps
T102 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3451584532 Jul 28 05:00:11 PM PDT 24 Jul 28 05:00:13 PM PDT 24 87357352 ps
T1777 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1845972375 Jul 28 05:00:12 PM PDT 24 Jul 28 05:00:13 PM PDT 24 137588496 ps
T103 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.942589901 Jul 28 05:00:08 PM PDT 24 Jul 28 05:00:09 PM PDT 24 27032839 ps
T222 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2902139076 Jul 28 04:59:54 PM PDT 24 Jul 28 04:59:55 PM PDT 24 28634668 ps
T1778 /workspace/coverage/cover_reg_top/9.i2c_intr_test.4253656175 Jul 28 05:00:09 PM PDT 24 Jul 28 05:00:09 PM PDT 24 65102914 ps
T1779 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2035074507 Jul 28 05:00:24 PM PDT 24 Jul 28 05:00:25 PM PDT 24 31870222 ps
T120 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.143139422 Jul 28 05:00:08 PM PDT 24 Jul 28 05:00:09 PM PDT 24 41139740 ps
T1780 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3437320277 Jul 28 04:59:52 PM PDT 24 Jul 28 04:59:53 PM PDT 24 20120634 ps
T1781 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.624383459 Jul 28 04:59:58 PM PDT 24 Jul 28 04:59:58 PM PDT 24 16001254 ps
T199 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3422771549 Jul 28 04:59:58 PM PDT 24 Jul 28 05:00:00 PM PDT 24 230642316 ps
T1782 /workspace/coverage/cover_reg_top/7.i2c_intr_test.257902689 Jul 28 05:00:05 PM PDT 24 Jul 28 05:00:08 PM PDT 24 44868842 ps
T1783 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3738574187 Jul 28 05:00:09 PM PDT 24 Jul 28 05:00:11 PM PDT 24 97149674 ps
T1784 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1913768872 Jul 28 05:00:05 PM PDT 24 Jul 28 05:00:09 PM PDT 24 20303851 ps
T1785 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3081442009 Jul 28 05:00:01 PM PDT 24 Jul 28 05:00:07 PM PDT 24 17945192 ps
T1786 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2462599076 Jul 28 05:00:31 PM PDT 24 Jul 28 05:00:33 PM PDT 24 259187334 ps
T1787 /workspace/coverage/cover_reg_top/45.i2c_intr_test.1449651023 Jul 28 05:00:20 PM PDT 24 Jul 28 05:00:21 PM PDT 24 21018926 ps
T1788 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3395968627 Jul 28 05:00:06 PM PDT 24 Jul 28 05:00:09 PM PDT 24 22303666 ps
T1789 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2961849020 Jul 28 05:00:30 PM PDT 24 Jul 28 05:00:31 PM PDT 24 20160376 ps
T206 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2802962720 Jul 28 05:00:24 PM PDT 24 Jul 28 05:00:27 PM PDT 24 191417598 ps
T1790 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3579139631 Jul 28 05:00:24 PM PDT 24 Jul 28 05:00:25 PM PDT 24 18246463 ps
T207 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1185897994 Jul 28 05:00:10 PM PDT 24 Jul 28 05:00:12 PM PDT 24 164042693 ps
T1791 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3858245483 Jul 28 04:59:56 PM PDT 24 Jul 28 04:59:58 PM PDT 24 68924645 ps
T1792 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3760725879 Jul 28 05:00:15 PM PDT 24 Jul 28 05:00:22 PM PDT 24 32229030 ps
T1793 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1625225718 Jul 28 05:00:06 PM PDT 24 Jul 28 05:00:12 PM PDT 24 24393141 ps
T208 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3031367423 Jul 28 05:00:34 PM PDT 24 Jul 28 05:00:36 PM PDT 24 85190116 ps
T1794 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3660311969 Jul 28 05:00:24 PM PDT 24 Jul 28 05:00:25 PM PDT 24 173800360 ps
T1795 /workspace/coverage/cover_reg_top/37.i2c_intr_test.824623041 Jul 28 05:00:28 PM PDT 24 Jul 28 05:00:29 PM PDT 24 41282779 ps
T1796 /workspace/coverage/cover_reg_top/49.i2c_intr_test.1910453367 Jul 28 05:00:21 PM PDT 24 Jul 28 05:00:22 PM PDT 24 25498046 ps
T1797 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2223619654 Jul 28 05:00:25 PM PDT 24 Jul 28 05:00:26 PM PDT 24 16486253 ps
T210 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3240583550 Jul 28 05:00:13 PM PDT 24 Jul 28 05:00:15 PM PDT 24 82908058 ps
T1798 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.157506988 Jul 28 04:59:59 PM PDT 24 Jul 28 05:00:01 PM PDT 24 123791788 ps
T1799 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3428902819 Jul 28 05:00:30 PM PDT 24 Jul 28 05:00:31 PM PDT 24 255103899 ps
T202 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.500266180 Jul 28 05:00:14 PM PDT 24 Jul 28 05:00:16 PM PDT 24 111523623 ps
T1800 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2802969812 Jul 28 05:00:11 PM PDT 24 Jul 28 05:00:17 PM PDT 24 57125276 ps
T1801 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3057272818 Jul 28 05:00:03 PM PDT 24 Jul 28 05:00:09 PM PDT 24 183580768 ps
T1802 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2202291029 Jul 28 05:00:09 PM PDT 24 Jul 28 05:00:10 PM PDT 24 113781041 ps
T1803 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3460958580 Jul 28 05:00:10 PM PDT 24 Jul 28 05:00:11 PM PDT 24 69483205 ps
T1804 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1664120870 Jul 28 05:00:02 PM PDT 24 Jul 28 05:00:08 PM PDT 24 122420285 ps
T1805 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2504464511 Jul 28 05:00:07 PM PDT 24 Jul 28 05:00:09 PM PDT 24 85219975 ps
T1806 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1753730372 Jul 28 05:00:07 PM PDT 24 Jul 28 05:00:09 PM PDT 24 46424149 ps
T1807 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3714747808 Jul 28 05:00:05 PM PDT 24 Jul 28 05:00:08 PM PDT 24 16935067 ps
T1808 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4143408618 Jul 28 05:00:14 PM PDT 24 Jul 28 05:00:15 PM PDT 24 24237284 ps
T1809 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3566600418 Jul 28 05:00:32 PM PDT 24 Jul 28 05:00:33 PM PDT 24 16208483 ps
T1810 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2407850635 Jul 28 05:00:42 PM PDT 24 Jul 28 05:00:43 PM PDT 24 19431636 ps
T1811 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1787853545 Jul 28 05:00:13 PM PDT 24 Jul 28 05:00:14 PM PDT 24 102612471 ps
T1812 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2302131424 Jul 28 05:00:22 PM PDT 24 Jul 28 05:00:24 PM PDT 24 121040861 ps
T1813 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2606101419 Jul 28 05:00:07 PM PDT 24 Jul 28 05:00:10 PM PDT 24 302849563 ps
T1814 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2377077245 Jul 28 05:00:13 PM PDT 24 Jul 28 05:00:13 PM PDT 24 69005619 ps
T1815 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3258272072 Jul 28 05:00:30 PM PDT 24 Jul 28 05:00:31 PM PDT 24 45870484 ps
T1816 /workspace/coverage/cover_reg_top/43.i2c_intr_test.917201475 Jul 28 05:00:14 PM PDT 24 Jul 28 05:00:15 PM PDT 24 31711459 ps
T1817 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3356129361 Jul 28 04:59:56 PM PDT 24 Jul 28 04:59:57 PM PDT 24 76860700 ps
T1818 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1618771722 Jul 28 05:00:13 PM PDT 24 Jul 28 05:00:14 PM PDT 24 87707134 ps
T223 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1953302703 Jul 28 05:00:07 PM PDT 24 Jul 28 05:00:10 PM PDT 24 106285661 ps
T1819 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3949294343 Jul 28 05:00:05 PM PDT 24 Jul 28 05:00:09 PM PDT 24 41364588 ps
T1820 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2282087862 Jul 28 05:00:04 PM PDT 24 Jul 28 05:00:09 PM PDT 24 212066772 ps
T1821 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2591968265 Jul 28 05:00:14 PM PDT 24 Jul 28 05:00:15 PM PDT 24 43394119 ps
T224 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.194083468 Jul 28 05:00:02 PM PDT 24 Jul 28 05:00:07 PM PDT 24 53042716 ps
T1822 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1972938181 Jul 28 05:00:11 PM PDT 24 Jul 28 05:00:13 PM PDT 24 48117605 ps
T1823 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.75425230 Jul 28 05:00:01 PM PDT 24 Jul 28 05:00:04 PM PDT 24 86734002 ps
T1824 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.65104420 Jul 28 04:59:56 PM PDT 24 Jul 28 05:00:02 PM PDT 24 23583202 ps
T1825 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2648834245 Jul 28 05:00:02 PM PDT 24 Jul 28 05:00:09 PM PDT 24 32253144 ps
T1826 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1535951050 Jul 28 05:00:16 PM PDT 24 Jul 28 05:00:17 PM PDT 24 31754273 ps
T1827 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.833263007 Jul 28 04:59:59 PM PDT 24 Jul 28 05:00:00 PM PDT 24 30432533 ps
T1828 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3735623918 Jul 28 05:00:17 PM PDT 24 Jul 28 05:00:18 PM PDT 24 36952583 ps
T1829 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2964341200 Jul 28 05:00:07 PM PDT 24 Jul 28 05:00:09 PM PDT 24 100765682 ps
T1830 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2636418809 Jul 28 05:00:36 PM PDT 24 Jul 28 05:00:37 PM PDT 24 25848591 ps
T225 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.144401260 Jul 28 05:00:09 PM PDT 24 Jul 28 05:00:10 PM PDT 24 126647157 ps
T1831 /workspace/coverage/cover_reg_top/12.i2c_intr_test.1349052740 Jul 28 05:00:11 PM PDT 24 Jul 28 05:00:12 PM PDT 24 19203421 ps
T204 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3065847944 Jul 28 04:59:59 PM PDT 24 Jul 28 05:00:01 PM PDT 24 163353792 ps
T205 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4203609560 Jul 28 05:00:16 PM PDT 24 Jul 28 05:00:18 PM PDT 24 893810448 ps
T1832 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3628092976 Jul 28 05:00:08 PM PDT 24 Jul 28 05:00:10 PM PDT 24 106253465 ps
T1833 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3858669790 Jul 28 04:59:59 PM PDT 24 Jul 28 05:00:01 PM PDT 24 185166045 ps
T1834 /workspace/coverage/cover_reg_top/25.i2c_intr_test.2962776700 Jul 28 05:00:11 PM PDT 24 Jul 28 05:00:12 PM PDT 24 20263071 ps
T1835 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2284189873 Jul 28 05:00:09 PM PDT 24 Jul 28 05:00:16 PM PDT 24 149186147 ps
T1836 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4115660565 Jul 28 05:00:03 PM PDT 24 Jul 28 05:00:09 PM PDT 24 241996646 ps
T1837 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.640012754 Jul 28 04:59:53 PM PDT 24 Jul 28 04:59:54 PM PDT 24 44738562 ps
T1838 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1523159493 Jul 28 05:00:01 PM PDT 24 Jul 28 05:00:02 PM PDT 24 121580167 ps
T1839 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1232007603 Jul 28 05:00:05 PM PDT 24 Jul 28 05:00:09 PM PDT 24 105585140 ps
T1840 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2569007686 Jul 28 05:00:29 PM PDT 24 Jul 28 05:00:30 PM PDT 24 86472206 ps
T1841 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1527242036 Jul 28 05:00:01 PM PDT 24 Jul 28 05:00:06 PM PDT 24 1288946943 ps
T227 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1979576100 Jul 28 05:00:01 PM PDT 24 Jul 28 05:00:09 PM PDT 24 1399589015 ps
T1842 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3951402493 Jul 28 05:00:01 PM PDT 24 Jul 28 05:00:03 PM PDT 24 519059742 ps
T1843 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1599589768 Jul 28 05:00:24 PM PDT 24 Jul 28 05:00:25 PM PDT 24 25136472 ps
T1844 /workspace/coverage/cover_reg_top/14.i2c_intr_test.841523727 Jul 28 05:00:26 PM PDT 24 Jul 28 05:00:27 PM PDT 24 21785843 ps
T1845 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3700744609 Jul 28 05:00:24 PM PDT 24 Jul 28 05:00:26 PM PDT 24 46314268 ps
T230 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1965872522 Jul 28 05:00:03 PM PDT 24 Jul 28 05:00:08 PM PDT 24 22228725 ps
T1846 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.52136246 Jul 28 05:00:09 PM PDT 24 Jul 28 05:00:11 PM PDT 24 135613023 ps
T1847 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1772839818 Jul 28 04:59:57 PM PDT 24 Jul 28 05:00:00 PM PDT 24 66994693 ps
T1848 /workspace/coverage/cover_reg_top/31.i2c_intr_test.732350653 Jul 28 05:00:22 PM PDT 24 Jul 28 05:00:23 PM PDT 24 52010349 ps
T1849 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2166499114 Jul 28 05:00:09 PM PDT 24 Jul 28 05:00:11 PM PDT 24 206072353 ps
T1850 /workspace/coverage/cover_reg_top/3.i2c_intr_test.673873796 Jul 28 05:00:06 PM PDT 24 Jul 28 05:00:08 PM PDT 24 21314104 ps
T231 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3489363776 Jul 28 05:00:06 PM PDT 24 Jul 28 05:00:09 PM PDT 24 435270945 ps
T203 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1688695017 Jul 28 05:00:06 PM PDT 24 Jul 28 05:00:10 PM PDT 24 87312827 ps
T1851 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1841779482 Jul 28 05:00:04 PM PDT 24 Jul 28 05:00:08 PM PDT 24 65691701 ps
T1852 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2869882353 Jul 28 05:00:10 PM PDT 24 Jul 28 05:00:11 PM PDT 24 669118352 ps
T1853 /workspace/coverage/cover_reg_top/38.i2c_intr_test.4080734936 Jul 28 05:00:15 PM PDT 24 Jul 28 05:00:16 PM PDT 24 23800959 ps
T1854 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3517061127 Jul 28 05:00:19 PM PDT 24 Jul 28 05:05:40 PM PDT 24 177750865270 ps
T1855 /workspace/coverage/cover_reg_top/39.i2c_intr_test.2600345909 Jul 28 05:00:33 PM PDT 24 Jul 28 05:00:34 PM PDT 24 28880797 ps
T276 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4249991504 Jul 28 04:59:56 PM PDT 24 Jul 28 04:59:59 PM PDT 24 365222391 ps
T1856 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1635817759 Jul 28 05:00:00 PM PDT 24 Jul 28 05:00:01 PM PDT 24 105527179 ps
T1857 /workspace/coverage/cover_reg_top/10.i2c_intr_test.712526592 Jul 28 05:00:14 PM PDT 24 Jul 28 05:00:15 PM PDT 24 40426974 ps
T228 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2168710152 Jul 28 05:00:01 PM PDT 24 Jul 28 05:00:02 PM PDT 24 15917661 ps
T232 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2720083985 Jul 28 05:00:14 PM PDT 24 Jul 28 05:00:15 PM PDT 24 74996643 ps
T1858 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3543711983 Jul 28 05:00:12 PM PDT 24 Jul 28 05:00:13 PM PDT 24 15580211 ps
T1859 /workspace/coverage/cover_reg_top/36.i2c_intr_test.885771419 Jul 28 05:00:21 PM PDT 24 Jul 28 05:00:22 PM PDT 24 15057994 ps
T1860 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3731176248 Jul 28 05:00:03 PM PDT 24 Jul 28 05:00:09 PM PDT 24 58573779 ps
T1861 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1679583612 Jul 28 05:00:11 PM PDT 24 Jul 28 05:00:13 PM PDT 24 103609959 ps
T1862 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2167889023 Jul 28 05:00:05 PM PDT 24 Jul 28 05:00:08 PM PDT 24 51630181 ps
T209 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3153130933 Jul 28 05:00:14 PM PDT 24 Jul 28 05:00:16 PM PDT 24 154701656 ps
T1863 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3032349644 Jul 28 04:59:54 PM PDT 24 Jul 28 04:59:55 PM PDT 24 172799405 ps
T1864 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.722508630 Jul 28 05:00:03 PM PDT 24 Jul 28 05:00:09 PM PDT 24 115341877 ps
T229 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2130132075 Jul 28 05:00:10 PM PDT 24 Jul 28 05:00:10 PM PDT 24 45365008 ps
T1865 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3399470770 Jul 28 05:00:17 PM PDT 24 Jul 28 05:00:18 PM PDT 24 70729968 ps
T1866 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2503879211 Jul 28 05:00:27 PM PDT 24 Jul 28 05:00:28 PM PDT 24 18294091 ps

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.360623611
Short name T1
Test name
Test status
Simulation time 4899218625 ps
CPU time 79.83 seconds
Started Jul 28 05:04:51 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 727840 kb
Host smart-f1779805-f073-4a67-8559-312e43b82097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360623611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.360623611
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_target_perf.439592369
Short name T46
Test name
Test status
Simulation time 514438014 ps
CPU time 4.53 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:04:40 PM PDT 24
Peak memory 222488 kb
Host smart-a4c6b68a-f531-452f-8040-fda05f2555ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439592369 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_perf.439592369
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1196899771
Short name T52
Test name
Test status
Simulation time 4069837435 ps
CPU time 11.09 seconds
Started Jul 28 05:02:52 PM PDT 24
Finished Jul 28 05:03:03 PM PDT 24
Peak memory 214568 kb
Host smart-2d4059b7-752c-49ec-a8da-9dc12fd8a7d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196899771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1196899771
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2734965934
Short name T18
Test name
Test status
Simulation time 17860389299 ps
CPU time 321.1 seconds
Started Jul 28 05:02:59 PM PDT 24
Finished Jul 28 05:08:20 PM PDT 24
Peak memory 1553636 kb
Host smart-4ae48aef-493f-4542-bdcd-f5bcb74ae66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734965934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2734965934
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1981902639
Short name T6
Test name
Test status
Simulation time 3222992893 ps
CPU time 11.86 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:03:06 PM PDT 24
Peak memory 223452 kb
Host smart-95e1b8c7-4b17-4167-b5d2-b77d64ec7a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981902639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1981902639
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3536088419
Short name T97
Test name
Test status
Simulation time 135072417 ps
CPU time 2.19 seconds
Started Jul 28 05:00:22 PM PDT 24
Finished Jul 28 05:00:24 PM PDT 24
Peak memory 204368 kb
Host smart-e60db10d-3ef1-4606-a6be-d3d7ba911b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536088419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3536088419
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3953932063
Short name T121
Test name
Test status
Simulation time 39288181224 ps
CPU time 367.05 seconds
Started Jul 28 05:04:29 PM PDT 24
Finished Jul 28 05:10:36 PM PDT 24
Peak memory 864368 kb
Host smart-57b14005-663f-4005-ad7a-a31e165ac07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953932063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3953932063
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.2751851547
Short name T54
Test name
Test status
Simulation time 4633639448 ps
CPU time 2.99 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:05:30 PM PDT 24
Peak memory 214232 kb
Host smart-2e1beefb-e16e-423d-8d86-1e484be5baba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751851547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_acqfull.2751851547
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_host_override.933893234
Short name T75
Test name
Test status
Simulation time 88043355 ps
CPU time 0.67 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 205468 kb
Host smart-d2fe9399-79d4-477b-a3f1-bcf843f73d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933893234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.933893234
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.3174288608
Short name T59
Test name
Test status
Simulation time 51324677190 ps
CPU time 2286.54 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:42:17 PM PDT 24
Peak memory 8348348 kb
Host smart-89ceffdf-5c0c-4343-8821-e141ac21240d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174288608 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.3174288608
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1735482610
Short name T252
Test name
Test status
Simulation time 668186845 ps
CPU time 9.6 seconds
Started Jul 28 05:04:40 PM PDT 24
Finished Jul 28 05:04:50 PM PDT 24
Peak memory 205752 kb
Host smart-5852748e-7c5a-4a5f-836c-87119def0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735482610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1735482610
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.99374995
Short name T99
Test name
Test status
Simulation time 268878415 ps
CPU time 2.69 seconds
Started Jul 28 04:59:59 PM PDT 24
Finished Jul 28 05:00:02 PM PDT 24
Peak memory 204488 kb
Host smart-69962541-3daa-498f-a705-f8ae02216b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99374995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.99374995
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/default/25.i2c_target_nack_txstretch.1158860965
Short name T50
Test name
Test status
Simulation time 1981966995 ps
CPU time 1.52 seconds
Started Jul 28 05:04:54 PM PDT 24
Finished Jul 28 05:04:56 PM PDT 24
Peak memory 222832 kb
Host smart-0d72cb2d-9e86-44b7-b8b2-ec8b02f7797b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158860965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_nack_txstretch.1158860965
Directory /workspace/25.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.3907886496
Short name T61
Test name
Test status
Simulation time 1039254397 ps
CPU time 2.72 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:52 PM PDT 24
Peak memory 205888 kb
Host smart-43eeafc1-cc45-4c2b-9516-565c660cf5c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907886496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.3907886496
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2573356628
Short name T347
Test name
Test status
Simulation time 36128541 ps
CPU time 0.64 seconds
Started Jul 28 05:04:01 PM PDT 24
Finished Jul 28 05:04:02 PM PDT 24
Peak memory 205024 kb
Host smart-6f364f34-71f6-4a65-b465-dea57f7f5af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573356628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2573356628
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.840613454
Short name T37
Test name
Test status
Simulation time 395116840 ps
CPU time 1.01 seconds
Started Jul 28 05:05:45 PM PDT 24
Finished Jul 28 05:05:46 PM PDT 24
Peak memory 205524 kb
Host smart-72217e34-6c50-401f-84fd-40b77e2506c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840613454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.840613454
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1856085061
Short name T33
Test name
Test status
Simulation time 41179055680 ps
CPU time 426.1 seconds
Started Jul 28 05:03:21 PM PDT 24
Finished Jul 28 05:10:32 PM PDT 24
Peak memory 892216 kb
Host smart-c8443247-099c-4819-9ade-a86db80faa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856085061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1856085061
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.942589901
Short name T103
Test name
Test status
Simulation time 27032839 ps
CPU time 0.78 seconds
Started Jul 28 05:00:08 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204328 kb
Host smart-83abb707-d74c-480f-82cb-8da6391ec1a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942589901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.942589901
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.786621970
Short name T32
Test name
Test status
Simulation time 115377489 ps
CPU time 1.5 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:02:55 PM PDT 24
Peak memory 214036 kb
Host smart-1edf6757-defb-4bdf-a241-3591e43b0bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786621970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.786621970
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1385688700
Short name T64
Test name
Test status
Simulation time 2587254695 ps
CPU time 3.71 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:12 PM PDT 24
Peak memory 209720 kb
Host smart-a31ff2eb-40d3-4a82-a07a-1446058af536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385688700 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1385688700
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.2398016584
Short name T66
Test name
Test status
Simulation time 4824161727 ps
CPU time 2.71 seconds
Started Jul 28 05:04:27 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 214204 kb
Host smart-7d7f34d2-f713-4c06-901a-ce7007a77d03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398016584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_acqfull.2398016584
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.3141040281
Short name T185
Test name
Test status
Simulation time 159000912 ps
CPU time 0.87 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 223972 kb
Host smart-1c52deed-7b6f-4da9-87a6-cdef2f4cc5fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141040281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3141040281
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.240443613
Short name T143
Test name
Test status
Simulation time 837595845 ps
CPU time 9.18 seconds
Started Jul 28 05:03:43 PM PDT 24
Finished Jul 28 05:03:53 PM PDT 24
Peak memory 298184 kb
Host smart-83c033e5-1a6b-404b-aa74-ad65f0edcb97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240443613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.240443613
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3966943118
Short name T171
Test name
Test status
Simulation time 302711511 ps
CPU time 3.84 seconds
Started Jul 28 05:03:36 PM PDT 24
Finished Jul 28 05:03:40 PM PDT 24
Peak memory 232904 kb
Host smart-62d856da-ff9e-40d6-9dc3-b7937f35821e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966943118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3966943118
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.2689631645
Short name T283
Test name
Test status
Simulation time 1246541310 ps
CPU time 2.18 seconds
Started Jul 28 05:04:33 PM PDT 24
Finished Jul 28 05:04:36 PM PDT 24
Peak memory 205908 kb
Host smart-b0d0cfa1-723a-4264-b025-1fc206d12bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689631645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.2689631645
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2334387778
Short name T106
Test name
Test status
Simulation time 5732929464 ps
CPU time 160.61 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:07:52 PM PDT 24
Peak memory 1592328 kb
Host smart-e5ef9ce6-e0cb-41f1-88ec-3464d8bab9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334387778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2334387778
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1619857282
Short name T247
Test name
Test status
Simulation time 169448822 ps
CPU time 1.26 seconds
Started Jul 28 05:04:44 PM PDT 24
Finished Jul 28 05:04:46 PM PDT 24
Peak memory 205492 kb
Host smart-0c88b7ce-92c6-4539-a22e-f66a7c317da8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619857282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1619857282
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1219875639
Short name T1772
Test name
Test status
Simulation time 48043909 ps
CPU time 0.7 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:17 PM PDT 24
Peak memory 204376 kb
Host smart-0ea5cb0a-dabb-4f09-a49b-45fd507c0903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219875639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1219875639
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.4000148882
Short name T23
Test name
Test status
Simulation time 7714190646 ps
CPU time 30.02 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 205856 kb
Host smart-87536b24-69e0-4dce-82e6-634707f70841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000148882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.4000148882
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3532901661
Short name T12
Test name
Test status
Simulation time 85384112 ps
CPU time 1.26 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:18 PM PDT 24
Peak memory 205740 kb
Host smart-e68da027-2745-4c32-b2b1-7a6c37071a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532901661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3532901661
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_perf.596948979
Short name T14
Test name
Test status
Simulation time 5992122841 ps
CPU time 243.49 seconds
Started Jul 28 05:04:35 PM PDT 24
Finished Jul 28 05:08:39 PM PDT 24
Peak memory 219296 kb
Host smart-be371c92-cce7-4b88-918e-5ec86dab6ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596948979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.596948979
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4219089218
Short name T237
Test name
Test status
Simulation time 37444490 ps
CPU time 0.84 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:02 PM PDT 24
Peak memory 204472 kb
Host smart-56b145ba-249e-4b35-868b-8ef7296aad6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219089218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.4219089218
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2038062992
Short name T81
Test name
Test status
Simulation time 1078309391 ps
CPU time 34.05 seconds
Started Jul 28 05:02:57 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 214144 kb
Host smart-2e0fb6fc-3e20-49f1-940d-39e21550f8d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038062992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2038062992
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.4087251081
Short name T175
Test name
Test status
Simulation time 8125418324 ps
CPU time 5.8 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:03:54 PM PDT 24
Peak memory 206052 kb
Host smart-6f69e8ff-bf4b-44ba-9359-6be4b6fa1fe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087251081 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.4087251081
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4203609560
Short name T205
Test name
Test status
Simulation time 893810448 ps
CPU time 2.06 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:18 PM PDT 24
Peak memory 204424 kb
Host smart-a04cb990-2b5c-44ac-a400-0c9aed5dad7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203609560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.4203609560
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.4003689055
Short name T1474
Test name
Test status
Simulation time 2654269229 ps
CPU time 8.63 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:02:41 PM PDT 24
Peak memory 214208 kb
Host smart-8c63f8c4-fbb0-4a1b-a5c8-d733434a5e1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003689055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.4003689055
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_override.4043109998
Short name T269
Test name
Test status
Simulation time 28671883 ps
CPU time 0.77 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:02:54 PM PDT 24
Peak memory 205416 kb
Host smart-00c022e0-3648-4e66-8926-a2435fa38944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043109998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.4043109998
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.870445218
Short name T42
Test name
Test status
Simulation time 54302544646 ps
CPU time 552.76 seconds
Started Jul 28 05:06:24 PM PDT 24
Finished Jul 28 05:15:37 PM PDT 24
Peak memory 1891880 kb
Host smart-35110fb6-76af-426e-aa27-37e49660d954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870445218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.870445218
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2377041196
Short name T53
Test name
Test status
Simulation time 3693370001 ps
CPU time 9.66 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:46 PM PDT 24
Peak memory 214456 kb
Host smart-4d10d755-8fe3-4566-853c-6418adfa014d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377041196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2377041196
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2380202689
Short name T1776
Test name
Test status
Simulation time 66146832 ps
CPU time 0.72 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204264 kb
Host smart-2653181e-e16b-482a-b237-562a095c13bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380202689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2380202689
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.693536579
Short name T22
Test name
Test status
Simulation time 2357358723 ps
CPU time 7.44 seconds
Started Jul 28 05:02:42 PM PDT 24
Finished Jul 28 05:02:49 PM PDT 24
Peak memory 205876 kb
Host smart-5005439f-8a7a-4fb9-935e-703bb1b7c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693536579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.693536579
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.848966614
Short name T521
Test name
Test status
Simulation time 619658143 ps
CPU time 2.73 seconds
Started Jul 28 05:02:45 PM PDT 24
Finished Jul 28 05:02:48 PM PDT 24
Peak memory 205972 kb
Host smart-e8c9afe0-06d1-4e2f-aef5-6cb5c53580b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848966614 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.848966614
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_host_override.3605319179
Short name T297
Test name
Test status
Simulation time 25082952 ps
CPU time 0.65 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 205396 kb
Host smart-ee3afbb8-6e8e-4fa1-bfbe-5cff87638ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605319179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3605319179
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3019300588
Short name T575
Test name
Test status
Simulation time 6518021515 ps
CPU time 27.85 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:03:56 PM PDT 24
Peak memory 230512 kb
Host smart-5fdac46b-12a8-40ca-b44a-c50060f50c00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019300588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3019300588
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.2332105784
Short name T299
Test name
Test status
Simulation time 1086957647 ps
CPU time 12.52 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:54 PM PDT 24
Peak memory 221564 kb
Host smart-10859f89-28aa-4903-9503-9fa9c0d85429
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332105784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.2332105784
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3832341959
Short name T277
Test name
Test status
Simulation time 1362745447 ps
CPU time 7.13 seconds
Started Jul 28 05:03:58 PM PDT 24
Finished Jul 28 05:04:05 PM PDT 24
Peak memory 219296 kb
Host smart-0b120065-aa9b-49f4-845e-3c1bf1b03433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832341959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3832341959
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.3622947233
Short name T1459
Test name
Test status
Simulation time 14171167040 ps
CPU time 92.73 seconds
Started Jul 28 05:04:05 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 1349428 kb
Host smart-eed5ed97-7621-4e83-a782-760e6908b968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622947233 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.3622947233
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2469100640
Short name T300
Test name
Test status
Simulation time 274313306 ps
CPU time 2 seconds
Started Jul 28 05:04:03 PM PDT 24
Finished Jul 28 05:04:05 PM PDT 24
Peak memory 205960 kb
Host smart-e2bb3ce7-daec-4eff-ac0b-0bf6d7c48dd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469100640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2469100640
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.4161075860
Short name T259
Test name
Test status
Simulation time 1777823552 ps
CPU time 6.12 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:23 PM PDT 24
Peak memory 205860 kb
Host smart-eb89f7ae-9e71-4a49-9a73-6ed336bcaba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161075860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.4161075860
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2763263025
Short name T256
Test name
Test status
Simulation time 7108009032 ps
CPU time 8.06 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:21 PM PDT 24
Peak memory 205884 kb
Host smart-5bc154ee-cf5e-4838-90f0-bba58e69f0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763263025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2763263025
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.1786761963
Short name T254
Test name
Test status
Simulation time 902928050 ps
CPU time 6.36 seconds
Started Jul 28 05:05:03 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 205820 kb
Host smart-13944bdd-008d-4fc5-a4cb-faf0c25e56a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786761963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1786761963
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3576981211
Short name T265
Test name
Test status
Simulation time 376104030 ps
CPU time 15.17 seconds
Started Jul 28 05:05:52 PM PDT 24
Finished Jul 28 05:06:07 PM PDT 24
Peak memory 205772 kb
Host smart-ef35ba1b-0b3a-4f64-9987-0c9d243a597d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576981211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3576981211
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.2618569603
Short name T251
Test name
Test status
Simulation time 863349248 ps
CPU time 15.78 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:03:39 PM PDT 24
Peak memory 205696 kb
Host smart-dcf4f14e-5280-4467-92b6-9d9a89b4dd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618569603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.2618569603
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3153130933
Short name T209
Test name
Test status
Simulation time 154701656 ps
CPU time 1.44 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:16 PM PDT 24
Peak memory 204436 kb
Host smart-799551b4-a327-4c02-8e36-fdf9e34a9396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153130933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3153130933
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.4071656193
Short name T197
Test name
Test status
Simulation time 66224725 ps
CPU time 1.64 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204404 kb
Host smart-731c4696-3fbb-405c-80fc-7d7c2248b3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071656193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.4071656193
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.500266180
Short name T202
Test name
Test status
Simulation time 111523623 ps
CPU time 1.94 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:16 PM PDT 24
Peak memory 204492 kb
Host smart-92e30b92-f9af-436f-8fe2-ed699e81b4e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500266180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.500266180
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1621975066
Short name T31
Test name
Test status
Simulation time 125473954 ps
CPU time 1.79 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:03:25 PM PDT 24
Peak memory 217140 kb
Host smart-86291699-68ac-4a70-95f4-84267218129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621975066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1621975066
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3240583550
Short name T210
Test name
Test status
Simulation time 82908058 ps
CPU time 1.31 seconds
Started Jul 28 05:00:13 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204500 kb
Host smart-70545fde-61ef-4a1a-9e10-d9ebc03dbad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240583550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3240583550
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.1522732565
Short name T638
Test name
Test status
Simulation time 198145596 ps
CPU time 1.46 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:02:57 PM PDT 24
Peak memory 213880 kb
Host smart-ce2e2ec5-75f1-4a4d-a46e-ed329ad5566b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522732565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.1522732565
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3467282637
Short name T1085
Test name
Test status
Simulation time 59736361 ps
CPU time 1.83 seconds
Started Jul 28 05:03:33 PM PDT 24
Finished Jul 28 05:03:35 PM PDT 24
Peak memory 213936 kb
Host smart-e3f83b77-0777-41bc-b4bb-67594c3e2b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467282637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3467282637
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1736923788
Short name T24
Test name
Test status
Simulation time 210464015 ps
CPU time 3 seconds
Started Jul 28 05:06:49 PM PDT 24
Finished Jul 28 05:06:52 PM PDT 24
Peak memory 215016 kb
Host smart-e337a6ad-d056-424f-a373-380b07ab73c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736923788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1736923788
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.973211477
Short name T73
Test name
Test status
Simulation time 173813604 ps
CPU time 1.59 seconds
Started Jul 28 05:03:41 PM PDT 24
Finished Jul 28 05:03:42 PM PDT 24
Peak memory 213964 kb
Host smart-a9d1e075-a81f-482a-aa37-2178fa68df39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973211477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.973211477
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2902139076
Short name T222
Test name
Test status
Simulation time 28634668 ps
CPU time 1.17 seconds
Started Jul 28 04:59:54 PM PDT 24
Finished Jul 28 04:59:55 PM PDT 24
Peak memory 204528 kb
Host smart-4aee2e44-d48b-4bfa-bed6-5151b432f0c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902139076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2902139076
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1772839818
Short name T1847
Test name
Test status
Simulation time 66994693 ps
CPU time 2.56 seconds
Started Jul 28 04:59:57 PM PDT 24
Finished Jul 28 05:00:00 PM PDT 24
Peak memory 204564 kb
Host smart-ee718c3e-10e8-48cb-9f9e-d86da4dcfdb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772839818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1772839818
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.833263007
Short name T1827
Test name
Test status
Simulation time 30432533 ps
CPU time 0.75 seconds
Started Jul 28 04:59:59 PM PDT 24
Finished Jul 28 05:00:00 PM PDT 24
Peak memory 204400 kb
Host smart-39a0f1e5-a969-495a-bb91-956474705f94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833263007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.833263007
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1664120870
Short name T1804
Test name
Test status
Simulation time 122420285 ps
CPU time 0.96 seconds
Started Jul 28 05:00:02 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204360 kb
Host smart-20df55eb-c272-4f09-9111-8738562da8e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664120870 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1664120870
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.640012754
Short name T1837
Test name
Test status
Simulation time 44738562 ps
CPU time 0.77 seconds
Started Jul 28 04:59:53 PM PDT 24
Finished Jul 28 04:59:54 PM PDT 24
Peak memory 204320 kb
Host smart-c0f0d0a7-485c-4f05-b940-cf0dd3b5581e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640012754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.640012754
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3081442009
Short name T1785
Test name
Test status
Simulation time 17945192 ps
CPU time 0.69 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:07 PM PDT 24
Peak memory 204392 kb
Host smart-44b0fe2e-4f5d-476d-97b7-96463e73e430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081442009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3081442009
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3032349644
Short name T1863
Test name
Test status
Simulation time 172799405 ps
CPU time 1.11 seconds
Started Jul 28 04:59:54 PM PDT 24
Finished Jul 28 04:59:55 PM PDT 24
Peak memory 204556 kb
Host smart-b62850f3-012a-48c1-ba1c-bab7e9642d4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032349644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3032349644
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4249991504
Short name T276
Test name
Test status
Simulation time 365222391 ps
CPU time 2.17 seconds
Started Jul 28 04:59:56 PM PDT 24
Finished Jul 28 04:59:59 PM PDT 24
Peak memory 204516 kb
Host smart-934b388c-0e47-469a-81c0-b63287b803c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249991504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.4249991504
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1953302703
Short name T223
Test name
Test status
Simulation time 106285661 ps
CPU time 1.99 seconds
Started Jul 28 05:00:07 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204488 kb
Host smart-9414d398-5d4a-4c4e-bc7a-5cb88b229f87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953302703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1953302703
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3247894403
Short name T226
Test name
Test status
Simulation time 187759688 ps
CPU time 4.37 seconds
Started Jul 28 05:00:06 PM PDT 24
Finished Jul 28 05:00:13 PM PDT 24
Peak memory 204528 kb
Host smart-a877e85e-9d2f-438c-9f39-063b8a4f38a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247894403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3247894403
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3395968627
Short name T1788
Test name
Test status
Simulation time 22303666 ps
CPU time 0.71 seconds
Started Jul 28 05:00:06 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204312 kb
Host smart-d04abe4b-6c33-4430-86e3-57a7d0b0dbd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395968627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3395968627
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3731176248
Short name T1860
Test name
Test status
Simulation time 58573779 ps
CPU time 1.51 seconds
Started Jul 28 05:00:03 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 212844 kb
Host smart-6499a099-3913-4736-854a-b0f89bf7c214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731176248 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3731176248
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.624383459
Short name T1781
Test name
Test status
Simulation time 16001254 ps
CPU time 0.65 seconds
Started Jul 28 04:59:58 PM PDT 24
Finished Jul 28 04:59:58 PM PDT 24
Peak memory 204400 kb
Host smart-a828948f-6ee8-48a5-a6c1-f714572c4262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624383459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.624383459
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3437320277
Short name T1780
Test name
Test status
Simulation time 20120634 ps
CPU time 0.66 seconds
Started Jul 28 04:59:52 PM PDT 24
Finished Jul 28 04:59:53 PM PDT 24
Peak memory 204320 kb
Host smart-dc7f8032-5de3-45a7-b3d8-a6504522e754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437320277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3437320277
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2648834245
Short name T1825
Test name
Test status
Simulation time 32253144 ps
CPU time 1.52 seconds
Started Jul 28 05:00:02 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204476 kb
Host smart-7a8db397-ecc1-4458-85b7-ce3bc5df9fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648834245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2648834245
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2606101419
Short name T1813
Test name
Test status
Simulation time 302849563 ps
CPU time 2.04 seconds
Started Jul 28 05:00:07 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204392 kb
Host smart-48d92a54-e5e7-463e-b44e-c8b14f726cda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606101419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2606101419
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2167889023
Short name T1862
Test name
Test status
Simulation time 51630181 ps
CPU time 0.76 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204360 kb
Host smart-ffface04-43a1-45ee-9879-5299bf162148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167889023 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2167889023
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3517061127
Short name T1854
Test name
Test status
Simulation time 177750865270 ps
CPU time 320.8 seconds
Started Jul 28 05:00:19 PM PDT 24
Finished Jul 28 05:05:40 PM PDT 24
Peak memory 204476 kb
Host smart-13570e26-020d-47bf-8466-e7a7142f38c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517061127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3517061127
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.712526592
Short name T1857
Test name
Test status
Simulation time 40426974 ps
CPU time 0.65 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204392 kb
Host smart-a1b325ab-cb7c-449d-bcc5-f3b667d88ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712526592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.712526592
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2802969812
Short name T1800
Test name
Test status
Simulation time 57125276 ps
CPU time 0.9 seconds
Started Jul 28 05:00:11 PM PDT 24
Finished Jul 28 05:00:17 PM PDT 24
Peak memory 204376 kb
Host smart-34ecb491-92c4-48fa-bb93-27b9eaec9f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802969812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2802969812
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2284189873
Short name T1835
Test name
Test status
Simulation time 149186147 ps
CPU time 1.96 seconds
Started Jul 28 05:00:09 PM PDT 24
Finished Jul 28 05:00:16 PM PDT 24
Peak memory 204600 kb
Host smart-c2ba1fde-61ba-424c-b5c4-463a7e0e8a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284189873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2284189873
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2317251817
Short name T200
Test name
Test status
Simulation time 23588215 ps
CPU time 1.06 seconds
Started Jul 28 05:00:12 PM PDT 24
Finished Jul 28 05:00:13 PM PDT 24
Peak memory 204560 kb
Host smart-f2d7b29c-2254-446a-a2c1-1699703d5921
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317251817 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2317251817
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.144401260
Short name T225
Test name
Test status
Simulation time 126647157 ps
CPU time 0.77 seconds
Started Jul 28 05:00:09 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204432 kb
Host smart-c79c317e-8e16-46cd-9256-54252f6f3220
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144401260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.144401260
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1510180162
Short name T1763
Test name
Test status
Simulation time 43410238 ps
CPU time 0.65 seconds
Started Jul 28 05:00:10 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204316 kb
Host smart-110a79d5-2cee-427c-ae7c-59358dcc4583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510180162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1510180162
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1618771722
Short name T1818
Test name
Test status
Simulation time 87707134 ps
CPU time 1.13 seconds
Started Jul 28 05:00:13 PM PDT 24
Finished Jul 28 05:00:14 PM PDT 24
Peak memory 204440 kb
Host smart-f725f1c7-2001-4ac0-98f1-efe61c1643f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618771722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1618771722
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2869882353
Short name T1852
Test name
Test status
Simulation time 669118352 ps
CPU time 1.36 seconds
Started Jul 28 05:00:10 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204508 kb
Host smart-ced15afd-f494-4dc5-9d04-1174c0ddc72e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869882353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2869882353
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2624963278
Short name T94
Test name
Test status
Simulation time 26270607 ps
CPU time 0.8 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:17 PM PDT 24
Peak memory 204364 kb
Host smart-1fbab918-e18c-4f37-afd6-90da8ed99010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624963278 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2624963278
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1841779482
Short name T1851
Test name
Test status
Simulation time 65691701 ps
CPU time 0.69 seconds
Started Jul 28 05:00:04 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204512 kb
Host smart-519ea91a-48b8-4fe3-83a4-50601d614151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841779482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1841779482
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1349052740
Short name T1831
Test name
Test status
Simulation time 19203421 ps
CPU time 0.64 seconds
Started Jul 28 05:00:11 PM PDT 24
Finished Jul 28 05:00:12 PM PDT 24
Peak memory 204276 kb
Host smart-ca888b7d-7c95-4e16-b407-73db1b03d104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349052740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1349052740
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3068215453
Short name T1775
Test name
Test status
Simulation time 51465083 ps
CPU time 0.87 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:18 PM PDT 24
Peak memory 204360 kb
Host smart-6847513e-049a-40f0-bc76-548097872e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068215453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3068215453
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2166499114
Short name T1849
Test name
Test status
Simulation time 206072353 ps
CPU time 2.21 seconds
Started Jul 28 05:00:09 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204592 kb
Host smart-aad33b25-6c0f-4bbc-aad0-351496a88884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166499114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2166499114
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1934178459
Short name T1773
Test name
Test status
Simulation time 562486211 ps
CPU time 1.51 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204368 kb
Host smart-b031abc9-18b5-42b6-ae19-983c48d0cbab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934178459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1934178459
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2504464511
Short name T1805
Test name
Test status
Simulation time 85219975 ps
CPU time 0.86 seconds
Started Jul 28 05:00:07 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204380 kb
Host smart-c1445b30-aa56-45a5-9449-4de93fcf056b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504464511 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2504464511
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3714747808
Short name T1807
Test name
Test status
Simulation time 16935067 ps
CPU time 0.69 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204316 kb
Host smart-06516249-f2d8-4294-81ff-e66bc0fe736a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714747808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3714747808
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3949294343
Short name T1819
Test name
Test status
Simulation time 41364588 ps
CPU time 0.95 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204428 kb
Host smart-f144de7b-93d0-4523-b653-2693c58e6ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949294343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3949294343
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3451584532
Short name T102
Test name
Test status
Simulation time 87357352 ps
CPU time 1.81 seconds
Started Jul 28 05:00:11 PM PDT 24
Finished Jul 28 05:00:13 PM PDT 24
Peak memory 204440 kb
Host smart-8778493d-3a12-4185-a5d5-120b375ab40b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451584532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3451584532
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1679583612
Short name T1861
Test name
Test status
Simulation time 103609959 ps
CPU time 1.4 seconds
Started Jul 28 05:00:11 PM PDT 24
Finished Jul 28 05:00:13 PM PDT 24
Peak memory 214044 kb
Host smart-2c5be52e-b0fe-48a7-9247-132c37e01e71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679583612 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1679583612
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1046939625
Short name T235
Test name
Test status
Simulation time 32299608 ps
CPU time 0.7 seconds
Started Jul 28 05:00:04 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204364 kb
Host smart-ec1222d3-963a-457d-b991-595a219ff4c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046939625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1046939625
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.841523727
Short name T1844
Test name
Test status
Simulation time 21785843 ps
CPU time 0.62 seconds
Started Jul 28 05:00:26 PM PDT 24
Finished Jul 28 05:00:27 PM PDT 24
Peak memory 204612 kb
Host smart-ca408256-f3fa-4617-ad71-b8c348fb8c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841523727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.841523727
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2410788600
Short name T236
Test name
Test status
Simulation time 28036571 ps
CPU time 1.1 seconds
Started Jul 28 05:00:18 PM PDT 24
Finished Jul 28 05:00:19 PM PDT 24
Peak memory 204432 kb
Host smart-71839a0d-54bb-4f77-acdd-be8910c672ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410788600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2410788600
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.231687372
Short name T198
Test name
Test status
Simulation time 271624650 ps
CPU time 1.5 seconds
Started Jul 28 05:00:21 PM PDT 24
Finished Jul 28 05:00:23 PM PDT 24
Peak memory 204544 kb
Host smart-9c6cb7d4-6db3-460f-bef0-35fcd6b0e48f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231687372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.231687372
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1185897994
Short name T207
Test name
Test status
Simulation time 164042693 ps
CPU time 2.01 seconds
Started Jul 28 05:00:10 PM PDT 24
Finished Jul 28 05:00:12 PM PDT 24
Peak memory 204544 kb
Host smart-72f4f137-ca9b-45e6-a11e-4880d04800f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185897994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1185897994
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3700744609
Short name T1845
Test name
Test status
Simulation time 46314268 ps
CPU time 1.73 seconds
Started Jul 28 05:00:24 PM PDT 24
Finished Jul 28 05:00:26 PM PDT 24
Peak memory 212804 kb
Host smart-ec37ed49-cba9-43f1-8814-954f9f6fcf5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700744609 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3700744609
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3460958580
Short name T1803
Test name
Test status
Simulation time 69483205 ps
CPU time 0.79 seconds
Started Jul 28 05:00:10 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204472 kb
Host smart-83f35aed-9185-43d3-a9ff-bf88685822c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460958580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3460958580
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2378251957
Short name T101
Test name
Test status
Simulation time 35497084 ps
CPU time 0.85 seconds
Started Jul 28 05:00:26 PM PDT 24
Finished Jul 28 05:00:27 PM PDT 24
Peak memory 204492 kb
Host smart-3cbcf76f-4d81-4f78-9f34-9f8650f0254b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378251957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2378251957
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.464450200
Short name T182
Test name
Test status
Simulation time 27707339 ps
CPU time 1.2 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:16 PM PDT 24
Peak memory 204408 kb
Host smart-02e061a1-3748-436f-864e-fc25a2f3c945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464450200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.464450200
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1531074394
Short name T215
Test name
Test status
Simulation time 40232187 ps
CPU time 0.78 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204484 kb
Host smart-731acd93-4c6f-42bd-9791-186b48ce71eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531074394 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1531074394
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2130132075
Short name T229
Test name
Test status
Simulation time 45365008 ps
CPU time 0.73 seconds
Started Jul 28 05:00:10 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204376 kb
Host smart-982c3ae0-36f7-4668-9933-48af9565a7ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130132075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2130132075
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3566600418
Short name T1809
Test name
Test status
Simulation time 16208483 ps
CPU time 0.66 seconds
Started Jul 28 05:00:32 PM PDT 24
Finished Jul 28 05:00:33 PM PDT 24
Peak memory 204288 kb
Host smart-5980254e-db8b-483b-ac49-bcc12df15fa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566600418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3566600418
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1132267894
Short name T239
Test name
Test status
Simulation time 104675159 ps
CPU time 1.12 seconds
Started Jul 28 05:00:15 PM PDT 24
Finished Jul 28 05:00:16 PM PDT 24
Peak memory 204508 kb
Host smart-767c8ac0-77c7-4acf-9b07-7ed29f7d96c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132267894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1132267894
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1535951050
Short name T1826
Test name
Test status
Simulation time 31754273 ps
CPU time 1.56 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:17 PM PDT 24
Peak memory 204592 kb
Host smart-9c3c6a04-6a5f-471e-8063-722ec2ff9d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535951050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1535951050
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.160128219
Short name T211
Test name
Test status
Simulation time 159522573 ps
CPU time 1.4 seconds
Started Jul 28 05:00:43 PM PDT 24
Finished Jul 28 05:00:44 PM PDT 24
Peak memory 204536 kb
Host smart-39e8d05f-041d-4885-9c0f-7c76f0284a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160128219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.160128219
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3112959804
Short name T96
Test name
Test status
Simulation time 29158193 ps
CPU time 0.83 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:17 PM PDT 24
Peak memory 204432 kb
Host smart-de0450ba-9480-43e1-a3e8-fad1cf556bab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112959804 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3112959804
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2903052340
Short name T1774
Test name
Test status
Simulation time 22781120 ps
CPU time 0.71 seconds
Started Jul 28 05:00:20 PM PDT 24
Finished Jul 28 05:00:21 PM PDT 24
Peak memory 204428 kb
Host smart-57939e22-1690-4a4b-8cac-243bdd370d9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903052340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2903052340
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1913768872
Short name T1784
Test name
Test status
Simulation time 20303851 ps
CPU time 0.76 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204256 kb
Host smart-3dcf0832-b46e-4f05-9e7f-c8bc77425f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913768872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1913768872
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3428902819
Short name T1799
Test name
Test status
Simulation time 255103899 ps
CPU time 1.15 seconds
Started Jul 28 05:00:30 PM PDT 24
Finished Jul 28 05:00:31 PM PDT 24
Peak memory 204352 kb
Host smart-8ea9c548-6a08-4a25-9291-a113f110ce82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428902819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3428902819
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3660311969
Short name T1794
Test name
Test status
Simulation time 173800360 ps
CPU time 1.13 seconds
Started Jul 28 05:00:24 PM PDT 24
Finished Jul 28 05:00:25 PM PDT 24
Peak memory 204292 kb
Host smart-72c6f9b9-2f9c-4cf0-a455-31a43a1038af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660311969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3660311969
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2569007686
Short name T1840
Test name
Test status
Simulation time 86472206 ps
CPU time 0.88 seconds
Started Jul 28 05:00:29 PM PDT 24
Finished Jul 28 05:00:30 PM PDT 24
Peak memory 204484 kb
Host smart-fbcc3e35-d491-43f7-9c23-e1d211e9910e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569007686 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2569007686
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2202178898
Short name T212
Test name
Test status
Simulation time 21199065 ps
CPU time 0.77 seconds
Started Jul 28 05:00:20 PM PDT 24
Finished Jul 28 05:00:21 PM PDT 24
Peak memory 204600 kb
Host smart-f7ae523a-950e-4483-9e81-fa32621fbc05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202178898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2202178898
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2961849020
Short name T1789
Test name
Test status
Simulation time 20160376 ps
CPU time 0.68 seconds
Started Jul 28 05:00:30 PM PDT 24
Finished Jul 28 05:00:31 PM PDT 24
Peak memory 204596 kb
Host smart-04b67386-b381-4138-b1e4-c3bebf192cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961849020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2961849020
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3628092976
Short name T1832
Test name
Test status
Simulation time 106253465 ps
CPU time 1.02 seconds
Started Jul 28 05:00:08 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204540 kb
Host smart-7272dc50-d820-498b-8391-0a015b65c68e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628092976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3628092976
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2802962720
Short name T206
Test name
Test status
Simulation time 191417598 ps
CPU time 3.25 seconds
Started Jul 28 05:00:24 PM PDT 24
Finished Jul 28 05:00:27 PM PDT 24
Peak memory 204304 kb
Host smart-42eae6da-8afb-46df-9f24-7046941d0b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802962720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2802962720
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3031367423
Short name T208
Test name
Test status
Simulation time 85190116 ps
CPU time 1.52 seconds
Started Jul 28 05:00:34 PM PDT 24
Finished Jul 28 05:00:36 PM PDT 24
Peak memory 204456 kb
Host smart-aa609044-850c-4da9-816b-0cc9d363c2ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031367423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3031367423
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3760725879
Short name T1792
Test name
Test status
Simulation time 32229030 ps
CPU time 1.46 seconds
Started Jul 28 05:00:15 PM PDT 24
Finished Jul 28 05:00:22 PM PDT 24
Peak memory 204748 kb
Host smart-48f62b82-25c6-4bf1-a91c-0f3dc0aba2ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760725879 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3760725879
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.46218984
Short name T221
Test name
Test status
Simulation time 20993181 ps
CPU time 0.72 seconds
Started Jul 28 05:00:11 PM PDT 24
Finished Jul 28 05:00:12 PM PDT 24
Peak memory 204300 kb
Host smart-e9de7b7b-2727-4ea8-b64c-fb0c6bc61891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46218984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.46218984
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.930877432
Short name T1762
Test name
Test status
Simulation time 15200894 ps
CPU time 0.68 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:17 PM PDT 24
Peak memory 204448 kb
Host smart-b53f62a4-cf38-4f9c-886d-33381af45e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930877432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.930877432
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2462599076
Short name T1786
Test name
Test status
Simulation time 259187334 ps
CPU time 1.18 seconds
Started Jul 28 05:00:31 PM PDT 24
Finished Jul 28 05:00:33 PM PDT 24
Peak memory 204536 kb
Host smart-926cf8c2-0d34-4946-9c9c-8e5e0caec1d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462599076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2462599076
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2302131424
Short name T1812
Test name
Test status
Simulation time 121040861 ps
CPU time 1.49 seconds
Started Jul 28 05:00:22 PM PDT 24
Finished Jul 28 05:00:24 PM PDT 24
Peak memory 204424 kb
Host smart-f782a47e-338c-441d-9f0d-5ca21412f5c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302131424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2302131424
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3215444017
Short name T201
Test name
Test status
Simulation time 131008595 ps
CPU time 2.24 seconds
Started Jul 28 05:00:19 PM PDT 24
Finished Jul 28 05:00:21 PM PDT 24
Peak memory 204384 kb
Host smart-aa8797f0-61a8-4fce-82e8-d2f0b069b729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215444017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3215444017
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1048604651
Short name T1767
Test name
Test status
Simulation time 46510882 ps
CPU time 1.2 seconds
Started Jul 28 05:00:10 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204392 kb
Host smart-d5da84cc-307f-4c45-9eaa-ada5c63dc7d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048604651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1048604651
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1979576100
Short name T227
Test name
Test status
Simulation time 1399589015 ps
CPU time 2.85 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204440 kb
Host smart-6da3baaa-8825-448c-9fe2-1a697382151d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979576100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1979576100
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4143408618
Short name T1808
Test name
Test status
Simulation time 24237284 ps
CPU time 0.77 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204400 kb
Host smart-fb1ade34-b368-4fba-93a8-86b22876dba7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143408618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.4143408618
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1626048920
Short name T100
Test name
Test status
Simulation time 106631193 ps
CPU time 0.88 seconds
Started Jul 28 04:59:54 PM PDT 24
Finished Jul 28 04:59:55 PM PDT 24
Peak memory 204472 kb
Host smart-8970fc61-0f20-43df-b61d-1944f7e27e40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626048920 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1626048920
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2168710152
Short name T228
Test name
Test status
Simulation time 15917661 ps
CPU time 0.73 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:02 PM PDT 24
Peak memory 204432 kb
Host smart-c18839c5-9603-4423-a5a8-2ca301c4bd11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168710152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2168710152
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3057272818
Short name T1801
Test name
Test status
Simulation time 183580768 ps
CPU time 1.13 seconds
Started Jul 28 05:00:03 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204564 kb
Host smart-df886092-a609-4d47-9895-a04b0a7ab512
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057272818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3057272818
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3858669790
Short name T1833
Test name
Test status
Simulation time 185166045 ps
CPU time 2.03 seconds
Started Jul 28 04:59:59 PM PDT 24
Finished Jul 28 05:00:01 PM PDT 24
Peak memory 204580 kb
Host smart-f37a8172-d959-4aa9-a7a3-ae56abcb126b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858669790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3858669790
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2809142970
Short name T125
Test name
Test status
Simulation time 26091231 ps
CPU time 0.71 seconds
Started Jul 28 05:00:24 PM PDT 24
Finished Jul 28 05:00:25 PM PDT 24
Peak memory 204104 kb
Host smart-9a075b19-ad1b-46ca-b9ff-aae955b895c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809142970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2809142970
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.193951340
Short name T1769
Test name
Test status
Simulation time 22232067 ps
CPU time 0.72 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:16 PM PDT 24
Peak memory 204404 kb
Host smart-436e27fe-59f3-40c7-9028-1171337eed69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193951340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.193951340
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1753730372
Short name T1806
Test name
Test status
Simulation time 46424149 ps
CPU time 0.73 seconds
Started Jul 28 05:00:07 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204392 kb
Host smart-5a430c10-a223-497b-a2e4-4297efef9bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753730372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1753730372
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1787853545
Short name T1811
Test name
Test status
Simulation time 102612471 ps
CPU time 0.63 seconds
Started Jul 28 05:00:13 PM PDT 24
Finished Jul 28 05:00:14 PM PDT 24
Peak memory 204280 kb
Host smart-778a427a-8612-4691-a641-0539964f0a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787853545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1787853545
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2503879211
Short name T1866
Test name
Test status
Simulation time 18294091 ps
CPU time 0.71 seconds
Started Jul 28 05:00:27 PM PDT 24
Finished Jul 28 05:00:28 PM PDT 24
Peak memory 204320 kb
Host smart-9d49f6d6-ec02-4848-a1f8-825a93937aff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503879211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2503879211
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.2962776700
Short name T1834
Test name
Test status
Simulation time 20263071 ps
CPU time 0.66 seconds
Started Jul 28 05:00:11 PM PDT 24
Finished Jul 28 05:00:12 PM PDT 24
Peak memory 204276 kb
Host smart-d33d3b53-c6a4-4c06-ad85-c3fdf2b87caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962776700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2962776700
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.817395209
Short name T1768
Test name
Test status
Simulation time 51552819 ps
CPU time 0.67 seconds
Started Jul 28 05:00:44 PM PDT 24
Finished Jul 28 05:00:45 PM PDT 24
Peak memory 204372 kb
Host smart-a94a9c8e-a119-490b-8aef-92272614b726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817395209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.817395209
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.164085440
Short name T1764
Test name
Test status
Simulation time 15201868 ps
CPU time 0.68 seconds
Started Jul 28 05:00:10 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204388 kb
Host smart-940dd9e1-ab41-482a-b5d3-8944084f7b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164085440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.164085440
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2591968265
Short name T1821
Test name
Test status
Simulation time 43394119 ps
CPU time 0.69 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204596 kb
Host smart-4575f079-c168-4215-b2f6-d04d05ffb617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591968265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2591968265
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2377077245
Short name T1814
Test name
Test status
Simulation time 69005619 ps
CPU time 0.7 seconds
Started Jul 28 05:00:13 PM PDT 24
Finished Jul 28 05:00:13 PM PDT 24
Peak memory 204336 kb
Host smart-de263c9d-aa38-45ce-8581-3c2a10d725ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377077245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2377077245
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3489363776
Short name T231
Test name
Test status
Simulation time 435270945 ps
CPU time 1.96 seconds
Started Jul 28 05:00:06 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204424 kb
Host smart-e0defa54-bcb7-45f2-a45c-4fa462bdd394
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489363776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3489363776
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1527242036
Short name T1841
Test name
Test status
Simulation time 1288946943 ps
CPU time 4.87 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:06 PM PDT 24
Peak memory 204516 kb
Host smart-70264595-fe9e-48b2-a822-e97fb28fce47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527242036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1527242036
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1625225718
Short name T1793
Test name
Test status
Simulation time 24393141 ps
CPU time 0.7 seconds
Started Jul 28 05:00:06 PM PDT 24
Finished Jul 28 05:00:12 PM PDT 24
Peak memory 204276 kb
Host smart-1433024b-c3ef-4e35-8c54-fc5599545d92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625225718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1625225718
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1608919376
Short name T216
Test name
Test status
Simulation time 25578420 ps
CPU time 1.03 seconds
Started Jul 28 05:00:03 PM PDT 24
Finished Jul 28 05:00:18 PM PDT 24
Peak memory 204612 kb
Host smart-01f340f6-af07-4ce3-9ba4-321094e1a177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608919376 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1608919376
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.194083468
Short name T224
Test name
Test status
Simulation time 53042716 ps
CPU time 0.75 seconds
Started Jul 28 05:00:02 PM PDT 24
Finished Jul 28 05:00:07 PM PDT 24
Peak memory 204304 kb
Host smart-3e87d524-8f9c-4dbf-8af2-edc8ec2cc796
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194083468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.194083468
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.673873796
Short name T1850
Test name
Test status
Simulation time 21314104 ps
CPU time 0.67 seconds
Started Jul 28 05:00:06 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204424 kb
Host smart-81342973-9cb8-4986-8183-2c3c81567601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673873796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.673873796
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.143139422
Short name T120
Test name
Test status
Simulation time 41139740 ps
CPU time 0.91 seconds
Started Jul 28 05:00:08 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204400 kb
Host smart-9ba6a458-ddff-49ce-bc83-858c05be8aa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143139422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out
standing.143139422
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.157506988
Short name T1798
Test name
Test status
Simulation time 123791788 ps
CPU time 2.24 seconds
Started Jul 28 04:59:59 PM PDT 24
Finished Jul 28 05:00:01 PM PDT 24
Peak memory 204572 kb
Host smart-158c3bdc-6f74-4e0a-a2b6-c46194ca35ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157506988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.157506988
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3858245483
Short name T1791
Test name
Test status
Simulation time 68924645 ps
CPU time 1.42 seconds
Started Jul 28 04:59:56 PM PDT 24
Finished Jul 28 04:59:58 PM PDT 24
Peak memory 204444 kb
Host smart-9029d89f-4be1-4cb5-bd69-7242b9bf8d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858245483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3858245483
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2673656198
Short name T1760
Test name
Test status
Simulation time 41292291 ps
CPU time 0.68 seconds
Started Jul 28 05:00:31 PM PDT 24
Finished Jul 28 05:00:32 PM PDT 24
Peak memory 204320 kb
Host smart-4c20e111-af23-43ca-b268-01e4e3197bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673656198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2673656198
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.732350653
Short name T1848
Test name
Test status
Simulation time 52010349 ps
CPU time 0.73 seconds
Started Jul 28 05:00:22 PM PDT 24
Finished Jul 28 05:00:23 PM PDT 24
Peak memory 204252 kb
Host smart-3308f8a4-7a04-4463-832a-9a93af746905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732350653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.732350653
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2035074507
Short name T1779
Test name
Test status
Simulation time 31870222 ps
CPU time 0.68 seconds
Started Jul 28 05:00:24 PM PDT 24
Finished Jul 28 05:00:25 PM PDT 24
Peak memory 204108 kb
Host smart-c387273c-a20f-499c-82d1-5ba89e5064bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035074507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2035074507
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1599589768
Short name T1843
Test name
Test status
Simulation time 25136472 ps
CPU time 0.65 seconds
Started Jul 28 05:00:24 PM PDT 24
Finished Jul 28 05:00:25 PM PDT 24
Peak memory 204320 kb
Host smart-6843b7e7-b089-4f82-af06-d5b14339f7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599589768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1599589768
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3258272072
Short name T1815
Test name
Test status
Simulation time 45870484 ps
CPU time 0.62 seconds
Started Jul 28 05:00:30 PM PDT 24
Finished Jul 28 05:00:31 PM PDT 24
Peak memory 204312 kb
Host smart-6026d2fc-ad92-4623-baa6-db4aa7cf24dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258272072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3258272072
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1845972375
Short name T1777
Test name
Test status
Simulation time 137588496 ps
CPU time 0.65 seconds
Started Jul 28 05:00:12 PM PDT 24
Finished Jul 28 05:00:13 PM PDT 24
Peak memory 204428 kb
Host smart-1a258c9c-bce1-43f2-a139-740894749f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845972375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1845972375
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.885771419
Short name T1859
Test name
Test status
Simulation time 15057994 ps
CPU time 0.65 seconds
Started Jul 28 05:00:21 PM PDT 24
Finished Jul 28 05:00:22 PM PDT 24
Peak memory 204316 kb
Host smart-ed5700b6-3cb6-41f1-bdf8-0eadadebf025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885771419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.885771419
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.824623041
Short name T1795
Test name
Test status
Simulation time 41282779 ps
CPU time 0.64 seconds
Started Jul 28 05:00:28 PM PDT 24
Finished Jul 28 05:00:29 PM PDT 24
Peak memory 204404 kb
Host smart-88f38a1a-5977-4704-a495-d8fc159c9829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824623041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.824623041
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.4080734936
Short name T1853
Test name
Test status
Simulation time 23800959 ps
CPU time 0.68 seconds
Started Jul 28 05:00:15 PM PDT 24
Finished Jul 28 05:00:16 PM PDT 24
Peak memory 204612 kb
Host smart-b7681fb3-567f-4741-9fbc-00d10ef82414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080734936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.4080734936
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2600345909
Short name T1855
Test name
Test status
Simulation time 28880797 ps
CPU time 0.68 seconds
Started Jul 28 05:00:33 PM PDT 24
Finished Jul 28 05:00:34 PM PDT 24
Peak memory 204448 kb
Host smart-8cbe6bd8-aa74-4006-a60d-bf29233ab31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600345909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2600345909
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3731769513
Short name T218
Test name
Test status
Simulation time 73125288 ps
CPU time 1.73 seconds
Started Jul 28 04:59:56 PM PDT 24
Finished Jul 28 04:59:58 PM PDT 24
Peak memory 204548 kb
Host smart-9899dd49-37f2-4e0e-a2ec-e833ea398fc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731769513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3731769513
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.766682026
Short name T219
Test name
Test status
Simulation time 442109095 ps
CPU time 4.46 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:06 PM PDT 24
Peak memory 204536 kb
Host smart-6dce01f2-4baa-4811-b53f-cedb2bd83d09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766682026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.766682026
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.65104420
Short name T1824
Test name
Test status
Simulation time 23583202 ps
CPU time 0.74 seconds
Started Jul 28 04:59:56 PM PDT 24
Finished Jul 28 05:00:02 PM PDT 24
Peak memory 204420 kb
Host smart-e2747767-7624-425b-ba0c-ef5b9d02b41c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65104420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.65104420
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.722508630
Short name T1864
Test name
Test status
Simulation time 115341877 ps
CPU time 1.45 seconds
Started Jul 28 05:00:03 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204556 kb
Host smart-5be9d1da-383c-427f-8d6e-e6a9e8be66fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722508630 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.722508630
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2600176698
Short name T220
Test name
Test status
Simulation time 120952455 ps
CPU time 0.82 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204392 kb
Host smart-cd1dc934-58ac-412b-86bb-7fbb2c16385f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600176698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2600176698
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.785134382
Short name T289
Test name
Test status
Simulation time 26578563 ps
CPU time 0.66 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204320 kb
Host smart-959a58c4-9f17-4fe2-b368-f9f5bc3b8bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785134382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.785134382
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2964341200
Short name T1829
Test name
Test status
Simulation time 100765682 ps
CPU time 0.87 seconds
Started Jul 28 05:00:07 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204396 kb
Host smart-2fa61ad7-0ecf-4107-b6f1-63bafe2a194e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964341200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2964341200
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3422771549
Short name T199
Test name
Test status
Simulation time 230642316 ps
CPU time 1.63 seconds
Started Jul 28 04:59:58 PM PDT 24
Finished Jul 28 05:00:00 PM PDT 24
Peak memory 212660 kb
Host smart-51989bc4-6d3e-45c4-bf03-bac11c9f32fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422771549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3422771549
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3399470770
Short name T1865
Test name
Test status
Simulation time 70729968 ps
CPU time 1.34 seconds
Started Jul 28 05:00:17 PM PDT 24
Finished Jul 28 05:00:18 PM PDT 24
Peak memory 204492 kb
Host smart-a5d05990-18ab-4c07-a54a-db569e5565f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399470770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3399470770
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2636418809
Short name T1830
Test name
Test status
Simulation time 25848591 ps
CPU time 0.65 seconds
Started Jul 28 05:00:36 PM PDT 24
Finished Jul 28 05:00:37 PM PDT 24
Peak memory 204352 kb
Host smart-e2d952e2-1c20-4059-a516-7a9380b21037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636418809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2636418809
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2223619654
Short name T1797
Test name
Test status
Simulation time 16486253 ps
CPU time 0.73 seconds
Started Jul 28 05:00:25 PM PDT 24
Finished Jul 28 05:00:26 PM PDT 24
Peak memory 204352 kb
Host smart-85207574-72ae-47fd-99aa-01b884a380b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223619654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2223619654
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3579139631
Short name T1790
Test name
Test status
Simulation time 18246463 ps
CPU time 0.77 seconds
Started Jul 28 05:00:24 PM PDT 24
Finished Jul 28 05:00:25 PM PDT 24
Peak memory 204320 kb
Host smart-c2df4aa3-e9c4-4ec0-b6c0-7c448bd83c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579139631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3579139631
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.917201475
Short name T1816
Test name
Test status
Simulation time 31711459 ps
CPU time 0.63 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204320 kb
Host smart-57dcb0d4-433b-47fa-9ecd-db190423407a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917201475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.917201475
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1846953399
Short name T1771
Test name
Test status
Simulation time 24848024 ps
CPU time 0.66 seconds
Started Jul 28 05:00:22 PM PDT 24
Finished Jul 28 05:00:23 PM PDT 24
Peak memory 204400 kb
Host smart-d1c5bd76-15a6-41ab-bd8b-c32c2ece8b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846953399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1846953399
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.1449651023
Short name T1787
Test name
Test status
Simulation time 21018926 ps
CPU time 0.62 seconds
Started Jul 28 05:00:20 PM PDT 24
Finished Jul 28 05:00:21 PM PDT 24
Peak memory 204376 kb
Host smart-a6a1023b-8691-4fa2-a2dc-94cd5ab5e64e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449651023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1449651023
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2407850635
Short name T1810
Test name
Test status
Simulation time 19431636 ps
CPU time 0.74 seconds
Started Jul 28 05:00:42 PM PDT 24
Finished Jul 28 05:00:43 PM PDT 24
Peak memory 204260 kb
Host smart-0816c327-6325-4a0e-8dc8-40665286aa68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407850635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2407850635
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2008548799
Short name T1766
Test name
Test status
Simulation time 49117745 ps
CPU time 0.66 seconds
Started Jul 28 05:00:29 PM PDT 24
Finished Jul 28 05:00:30 PM PDT 24
Peak memory 204256 kb
Host smart-8faaae53-6a21-480e-9aa6-3f1d1de6ac62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008548799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2008548799
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3543711983
Short name T1858
Test name
Test status
Simulation time 15580211 ps
CPU time 0.7 seconds
Started Jul 28 05:00:12 PM PDT 24
Finished Jul 28 05:00:13 PM PDT 24
Peak memory 204268 kb
Host smart-e47acfd3-9381-4995-9a99-71ed40d932c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543711983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3543711983
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1910453367
Short name T1796
Test name
Test status
Simulation time 25498046 ps
CPU time 0.67 seconds
Started Jul 28 05:00:21 PM PDT 24
Finished Jul 28 05:00:22 PM PDT 24
Peak memory 204400 kb
Host smart-a9fcba53-fc61-4340-9457-f780e62684fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910453367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1910453367
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.671366813
Short name T95
Test name
Test status
Simulation time 37580171 ps
CPU time 0.94 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204440 kb
Host smart-a7618dbf-b65e-42c1-8ad3-c9e35ea8bec1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671366813 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.671366813
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3536639073
Short name T233
Test name
Test status
Simulation time 27715312 ps
CPU time 0.71 seconds
Started Jul 28 05:00:11 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204388 kb
Host smart-cfd148da-3dad-4078-8993-cf7cb8fb568f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536639073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3536639073
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.4017744182
Short name T1770
Test name
Test status
Simulation time 18308787 ps
CPU time 0.63 seconds
Started Jul 28 05:00:15 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204320 kb
Host smart-a4fd165a-d278-407f-89eb-67993b2b2e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017744182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.4017744182
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3738574187
Short name T1783
Test name
Test status
Simulation time 97149674 ps
CPU time 1.17 seconds
Started Jul 28 05:00:09 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204744 kb
Host smart-b4b590fa-adca-47e8-85df-fbe955a6deeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738574187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3738574187
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.75425230
Short name T1823
Test name
Test status
Simulation time 86734002 ps
CPU time 2.33 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:04 PM PDT 24
Peak memory 204432 kb
Host smart-09b38dc1-6f0d-4484-9c87-1522ba1ba77a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75425230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.75425230
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1064905057
Short name T196
Test name
Test status
Simulation time 46645523 ps
CPU time 1.37 seconds
Started Jul 28 05:00:07 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204528 kb
Host smart-82e4f6c3-45ef-4757-84c7-9b3ce7a95314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064905057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1064905057
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3356129361
Short name T1817
Test name
Test status
Simulation time 76860700 ps
CPU time 0.97 seconds
Started Jul 28 04:59:56 PM PDT 24
Finished Jul 28 04:59:57 PM PDT 24
Peak memory 204524 kb
Host smart-3903d640-c96e-40f0-bb41-d8f743ce4250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356129361 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3356129361
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2720083985
Short name T232
Test name
Test status
Simulation time 74996643 ps
CPU time 0.78 seconds
Started Jul 28 05:00:14 PM PDT 24
Finished Jul 28 05:00:15 PM PDT 24
Peak memory 204344 kb
Host smart-64bc536b-29cf-41a5-b84b-fa8ff8b14400
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720083985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2720083985
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.927372531
Short name T1759
Test name
Test status
Simulation time 17326129 ps
CPU time 0.7 seconds
Started Jul 28 05:00:03 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204280 kb
Host smart-564e9c7e-7832-4a24-8bc3-eb9e9a7a2280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927372531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.927372531
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1523159493
Short name T1838
Test name
Test status
Simulation time 121580167 ps
CPU time 0.83 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:02 PM PDT 24
Peak memory 204312 kb
Host smart-f6710477-6883-44cb-afe2-1f38dd8b3b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523159493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1523159493
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1232007603
Short name T1839
Test name
Test status
Simulation time 105585140 ps
CPU time 1.06 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204480 kb
Host smart-01bfe3a4-e72b-42b9-a66d-48c1aa00fcdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232007603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1232007603
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3951402493
Short name T1842
Test name
Test status
Simulation time 519059742 ps
CPU time 2.23 seconds
Started Jul 28 05:00:01 PM PDT 24
Finished Jul 28 05:00:03 PM PDT 24
Peak memory 204556 kb
Host smart-9a1c5514-f78a-421f-ae65-a17a5fd162c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951402493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3951402493
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2282087862
Short name T1820
Test name
Test status
Simulation time 212066772 ps
CPU time 1.32 seconds
Started Jul 28 05:00:04 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204752 kb
Host smart-8edc09d0-996c-4278-b49f-d9fa42da3d2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282087862 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2282087862
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.409275984
Short name T1765
Test name
Test status
Simulation time 18324722 ps
CPU time 0.72 seconds
Started Jul 28 05:00:06 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204388 kb
Host smart-71672bc9-8af1-4546-9e7a-2ff457a662f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409275984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.409275984
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.257902689
Short name T1782
Test name
Test status
Simulation time 44868842 ps
CPU time 0.66 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204328 kb
Host smart-3ded33c0-4aee-4be7-89af-832301a96967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257902689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.257902689
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1635817759
Short name T1856
Test name
Test status
Simulation time 105527179 ps
CPU time 1.18 seconds
Started Jul 28 05:00:00 PM PDT 24
Finished Jul 28 05:00:01 PM PDT 24
Peak memory 204440 kb
Host smart-50be1ad4-52c8-4130-af18-35000e39c64f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635817759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1635817759
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4115660565
Short name T1836
Test name
Test status
Simulation time 241996646 ps
CPU time 1.47 seconds
Started Jul 28 05:00:03 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204620 kb
Host smart-1abcc89b-2704-4c27-90da-bdcf9109d7ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115660565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4115660565
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2579880186
Short name T98
Test name
Test status
Simulation time 269997667 ps
CPU time 2.24 seconds
Started Jul 28 05:00:16 PM PDT 24
Finished Jul 28 05:00:19 PM PDT 24
Peak memory 204180 kb
Host smart-c74aa7a9-cee4-4004-8835-4a7820e3cdbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579880186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2579880186
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2202291029
Short name T1802
Test name
Test status
Simulation time 113781041 ps
CPU time 1.18 seconds
Started Jul 28 05:00:09 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204540 kb
Host smart-969ca521-430f-4afc-b8be-7dd7461d820b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202291029 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2202291029
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1965872522
Short name T230
Test name
Test status
Simulation time 22228725 ps
CPU time 0.73 seconds
Started Jul 28 05:00:03 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204468 kb
Host smart-ce993cbe-fa02-404c-a469-fae4e96cc4cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965872522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1965872522
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1331434685
Short name T1761
Test name
Test status
Simulation time 24321469 ps
CPU time 0.65 seconds
Started Jul 28 05:00:06 PM PDT 24
Finished Jul 28 05:00:08 PM PDT 24
Peak memory 204364 kb
Host smart-ada8931a-2a44-45f7-a802-f33632e58de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331434685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1331434685
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3764693171
Short name T238
Test name
Test status
Simulation time 585565522 ps
CPU time 1.2 seconds
Started Jul 28 05:00:24 PM PDT 24
Finished Jul 28 05:00:25 PM PDT 24
Peak memory 204476 kb
Host smart-5b75b571-36ff-4ac7-ae2d-e00b2ae6b04e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764693171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3764693171
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1972938181
Short name T1822
Test name
Test status
Simulation time 48117605 ps
CPU time 2.5 seconds
Started Jul 28 05:00:11 PM PDT 24
Finished Jul 28 05:00:13 PM PDT 24
Peak memory 212756 kb
Host smart-b5df15d9-fc67-42a6-a46b-7ffcb56d2d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972938181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1972938181
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1688695017
Short name T203
Test name
Test status
Simulation time 87312827 ps
CPU time 2.04 seconds
Started Jul 28 05:00:06 PM PDT 24
Finished Jul 28 05:00:10 PM PDT 24
Peak memory 204532 kb
Host smart-e09c1636-3fa5-4477-aba6-332f228861e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688695017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1688695017
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3735623918
Short name T1828
Test name
Test status
Simulation time 36952583 ps
CPU time 1 seconds
Started Jul 28 05:00:17 PM PDT 24
Finished Jul 28 05:00:18 PM PDT 24
Peak memory 204356 kb
Host smart-a1c71aa3-615d-4bd0-8445-4e801e7d4a64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735623918 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3735623918
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1445584474
Short name T213
Test name
Test status
Simulation time 20657001 ps
CPU time 0.71 seconds
Started Jul 28 05:00:05 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204292 kb
Host smart-c6a90420-17c3-4e54-b90a-bc8415c54736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445584474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1445584474
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.4253656175
Short name T1778
Test name
Test status
Simulation time 65102914 ps
CPU time 0.69 seconds
Started Jul 28 05:00:09 PM PDT 24
Finished Jul 28 05:00:09 PM PDT 24
Peak memory 204412 kb
Host smart-d52dddce-055a-47b3-884d-ffd7ad35602d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253656175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4253656175
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2892225931
Short name T234
Test name
Test status
Simulation time 84826830 ps
CPU time 1.05 seconds
Started Jul 28 05:00:17 PM PDT 24
Finished Jul 28 05:00:19 PM PDT 24
Peak memory 204748 kb
Host smart-9a8f4147-8eb9-41d5-86c1-48b14c6633ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892225931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2892225931
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.52136246
Short name T1846
Test name
Test status
Simulation time 135613023 ps
CPU time 1.77 seconds
Started Jul 28 05:00:09 PM PDT 24
Finished Jul 28 05:00:11 PM PDT 24
Peak memory 204472 kb
Host smart-daccb7e9-7b0a-462a-949d-aac0e91877eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52136246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.52136246
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3065847944
Short name T204
Test name
Test status
Simulation time 163353792 ps
CPU time 1.46 seconds
Started Jul 28 04:59:59 PM PDT 24
Finished Jul 28 05:00:01 PM PDT 24
Peak memory 204588 kb
Host smart-b7a26724-10f6-4614-8e4b-669f308b56e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065847944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3065847944
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2521669554
Short name T1205
Test name
Test status
Simulation time 46867765 ps
CPU time 0.62 seconds
Started Jul 28 05:02:50 PM PDT 24
Finished Jul 28 05:02:51 PM PDT 24
Peak memory 204888 kb
Host smart-6a692cd2-0875-4079-806e-78b2386a144b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521669554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2521669554
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.797271527
Short name T1065
Test name
Test status
Simulation time 284175969 ps
CPU time 1.75 seconds
Started Jul 28 05:02:41 PM PDT 24
Finished Jul 28 05:02:43 PM PDT 24
Peak memory 213956 kb
Host smart-428ba2f6-084f-45e4-a0d1-679ca34dcd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797271527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.797271527
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3649393428
Short name T1244
Test name
Test status
Simulation time 120047987 ps
CPU time 2.18 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 220556 kb
Host smart-39e0132f-7dcb-4da2-a1aa-a97717835845
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649393428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3649393428
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3482655559
Short name T1741
Test name
Test status
Simulation time 15220379096 ps
CPU time 253.11 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:07:01 PM PDT 24
Peak memory 555740 kb
Host smart-85c344dc-d037-418f-8174-a9aca23a473e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482655559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3482655559
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1943376014
Short name T1528
Test name
Test status
Simulation time 2400653366 ps
CPU time 164.2 seconds
Started Jul 28 05:02:46 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 683276 kb
Host smart-3bf950ca-c558-48ef-8372-18d5427cd71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943376014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1943376014
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2789423079
Short name T1578
Test name
Test status
Simulation time 616910158 ps
CPU time 1.1 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:02:54 PM PDT 24
Peak memory 205856 kb
Host smart-b1176e50-3b36-4622-ac42-4f91009cdbd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789423079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2789423079
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.555075405
Short name T723
Test name
Test status
Simulation time 465904000 ps
CPU time 13.13 seconds
Started Jul 28 05:02:45 PM PDT 24
Finished Jul 28 05:02:58 PM PDT 24
Peak memory 251156 kb
Host smart-7b9b3740-2f9d-4877-8735-82420f3f5fdc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555075405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.555075405
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.697747934
Short name T1361
Test name
Test status
Simulation time 17740822178 ps
CPU time 132.67 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:05:06 PM PDT 24
Peak memory 1283196 kb
Host smart-12d49bb2-84d6-413d-b277-06ed4a467dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697747934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.697747934
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_override.3091971604
Short name T1148
Test name
Test status
Simulation time 79246852 ps
CPU time 0.65 seconds
Started Jul 28 05:02:45 PM PDT 24
Finished Jul 28 05:02:46 PM PDT 24
Peak memory 205488 kb
Host smart-90a6b6d5-7786-4027-8a65-22b5be186e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091971604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3091971604
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.111633067
Short name T446
Test name
Test status
Simulation time 3055728421 ps
CPU time 18.72 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:03:13 PM PDT 24
Peak memory 206364 kb
Host smart-1e454e96-4730-4882-8dd3-0ecfdb890890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111633067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.111633067
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.3159713467
Short name T157
Test name
Test status
Simulation time 140800729 ps
CPU time 2.19 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 206388 kb
Host smart-3a85aa37-85a6-4fa3-b4c0-b44ab56b363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159713467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.3159713467
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3253609927
Short name T1581
Test name
Test status
Simulation time 996131220 ps
CPU time 46.39 seconds
Started Jul 28 05:02:43 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 301656 kb
Host smart-ad4e3a77-4739-47f8-8d2f-6332eaaa9b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253609927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3253609927
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2859911062
Short name T460
Test name
Test status
Simulation time 1614594251 ps
CPU time 34.99 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:03:04 PM PDT 24
Peak memory 214012 kb
Host smart-62f9675f-76cd-40a8-a502-4596175be276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859911062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2859911062
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1530613119
Short name T684
Test name
Test status
Simulation time 2133568959 ps
CPU time 3.24 seconds
Started Jul 28 05:02:46 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 222268 kb
Host smart-a40dfac1-bda7-4d68-847f-cb3125e1f2cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530613119 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1530613119
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.4024086749
Short name T1145
Test name
Test status
Simulation time 172987969 ps
CPU time 1.09 seconds
Started Jul 28 05:02:41 PM PDT 24
Finished Jul 28 05:02:42 PM PDT 24
Peak memory 205736 kb
Host smart-c5b21624-866d-434f-90a6-6aa1aa41ac34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024086749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.4024086749
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.339148265
Short name T1358
Test name
Test status
Simulation time 133480257 ps
CPU time 1.01 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:02:52 PM PDT 24
Peak memory 205740 kb
Host smart-608826eb-6e24-4273-9edb-cdbdb544ec25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339148265 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.339148265
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.4230661371
Short name T340
Test name
Test status
Simulation time 395692852 ps
CPU time 2.13 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 205900 kb
Host smart-1adee3b4-6404-4459-a763-9d5f621a14bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230661371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.4230661371
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.4116419757
Short name T1143
Test name
Test status
Simulation time 214379370 ps
CPU time 1.08 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 205776 kb
Host smart-f5efca5e-9e7a-438a-a603-1369398ff807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116419757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.4116419757
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3020548784
Short name T680
Test name
Test status
Simulation time 900580529 ps
CPU time 3.75 seconds
Started Jul 28 05:02:47 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 214124 kb
Host smart-af8d6117-4247-4ecc-884f-b6b24425463a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020548784 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3020548784
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.949516731
Short name T1657
Test name
Test status
Simulation time 20346886309 ps
CPU time 32 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:03:04 PM PDT 24
Peak memory 606256 kb
Host smart-28752b9c-c49b-4245-87fb-efc66b18cdb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949516731 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.949516731
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.3844265053
Short name T1475
Test name
Test status
Simulation time 1117937410 ps
CPU time 3.05 seconds
Started Jul 28 05:02:47 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 214088 kb
Host smart-5bf5e5bc-572e-4d3d-99d1-d01a204bd1b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844265053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_nack_acqfull.3844265053
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_txstretch.2521231782
Short name T918
Test name
Test status
Simulation time 159657346 ps
CPU time 1.45 seconds
Started Jul 28 05:02:39 PM PDT 24
Finished Jul 28 05:02:41 PM PDT 24
Peak memory 222652 kb
Host smart-75378c8e-9368-4b9f-a2ea-9165d53c32ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521231782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_nack_txstretch.2521231782
Directory /workspace/0.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/0.i2c_target_perf.1186498231
Short name T1746
Test name
Test status
Simulation time 708272095 ps
CPU time 3.98 seconds
Started Jul 28 05:02:34 PM PDT 24
Finished Jul 28 05:02:38 PM PDT 24
Peak memory 214296 kb
Host smart-540976c0-9da3-4ca1-b589-2b2af2e35c83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186498231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.1186498231
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.827250731
Short name T155
Test name
Test status
Simulation time 926920774 ps
CPU time 2.2 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 205700 kb
Host smart-ed9b7e62-9714-4934-b98f-131da5718a01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827250731 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_smbus_maxlen.827250731
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.689397735
Short name T1184
Test name
Test status
Simulation time 109652415604 ps
CPU time 606.6 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:13:03 PM PDT 24
Peak memory 3159792 kb
Host smart-76dac17b-006e-4474-ac0d-f81bd871db06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689397735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_stress_all.689397735
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.4078519816
Short name T1022
Test name
Test status
Simulation time 6110164457 ps
CPU time 15.81 seconds
Started Jul 28 05:02:43 PM PDT 24
Finished Jul 28 05:02:59 PM PDT 24
Peak memory 222996 kb
Host smart-31dfe721-1bdf-4cfd-b595-e344929bc026
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078519816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.4078519816
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1194551483
Short name T840
Test name
Test status
Simulation time 45983624657 ps
CPU time 1008.74 seconds
Started Jul 28 05:02:47 PM PDT 24
Finished Jul 28 05:19:36 PM PDT 24
Peak memory 6442240 kb
Host smart-37a07251-3b95-45fc-a7f9-6c8fc4501476
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194551483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1194551483
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.2651087345
Short name T349
Test name
Test status
Simulation time 1618341837 ps
CPU time 2.02 seconds
Started Jul 28 05:02:57 PM PDT 24
Finished Jul 28 05:02:59 PM PDT 24
Peak memory 214372 kb
Host smart-a31164bd-d55a-466f-ace3-7dea90b722af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651087345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.2651087345
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2330030755
Short name T628
Test name
Test status
Simulation time 11314677025 ps
CPU time 7.2 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:39 PM PDT 24
Peak memory 231836 kb
Host smart-45a30d15-4569-45b9-b4cb-574b35b6e799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330030755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2330030755
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.3435688923
Short name T665
Test name
Test status
Simulation time 178119351 ps
CPU time 2.91 seconds
Started Jul 28 05:02:42 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 205952 kb
Host smart-81429e59-e231-4fbf-8762-08e38a2f7d61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435688923 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.3435688923
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1958277232
Short name T1015
Test name
Test status
Simulation time 37219315 ps
CPU time 0.62 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 204964 kb
Host smart-6ca1ad5e-4c83-415d-a079-f9a788a12ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958277232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1958277232
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2810881880
Short name T1634
Test name
Test status
Simulation time 70497530 ps
CPU time 1.23 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:06 PM PDT 24
Peak memory 214064 kb
Host smart-77bef8fc-a102-4646-9d40-8541e0538f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810881880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2810881880
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2160959301
Short name T530
Test name
Test status
Simulation time 656869550 ps
CPU time 6.16 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:03:02 PM PDT 24
Peak memory 272988 kb
Host smart-53ad5f4f-02fa-4acc-acf5-3d8e17bcfe14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160959301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2160959301
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3941846155
Short name T1504
Test name
Test status
Simulation time 9745152906 ps
CPU time 65.35 seconds
Started Jul 28 05:03:07 PM PDT 24
Finished Jul 28 05:04:13 PM PDT 24
Peak memory 524488 kb
Host smart-40df268d-09c0-4eae-8d59-f8695c3c8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941846155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3941846155
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3719524761
Short name T798
Test name
Test status
Simulation time 2146930268 ps
CPU time 165.74 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:05:22 PM PDT 24
Peak memory 727788 kb
Host smart-884992bd-4b88-4b68-9290-31e709544b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719524761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3719524761
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3727009255
Short name T805
Test name
Test status
Simulation time 376400104 ps
CPU time 1.1 seconds
Started Jul 28 05:02:46 PM PDT 24
Finished Jul 28 05:02:48 PM PDT 24
Peak memory 205540 kb
Host smart-bfe948f4-6e79-48dc-b0cb-fb9ff004f670
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727009255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3727009255
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1007433390
Short name T1587
Test name
Test status
Simulation time 407600727 ps
CPU time 8.73 seconds
Started Jul 28 05:03:02 PM PDT 24
Finished Jul 28 05:03:10 PM PDT 24
Peak memory 232340 kb
Host smart-d6b4e787-3bd0-4754-8d3f-d8cf640d5040
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007433390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1007433390
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.373434836
Short name T1670
Test name
Test status
Simulation time 12842186622 ps
CPU time 140.41 seconds
Started Jul 28 05:02:34 PM PDT 24
Finished Jul 28 05:04:54 PM PDT 24
Peak memory 1329248 kb
Host smart-98ed2503-dcb8-4fbb-b6fd-1e5237a66aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373434836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.373434836
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.3882502809
Short name T1590
Test name
Test status
Simulation time 808278987 ps
CPU time 20.61 seconds
Started Jul 28 05:03:03 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 205756 kb
Host smart-a2d97539-972e-45aa-bdcc-a6f43e9bbfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882502809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.3882502809
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.851277210
Short name T1497
Test name
Test status
Simulation time 20245976 ps
CPU time 0.64 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:49 PM PDT 24
Peak memory 205420 kb
Host smart-bf8d678f-861c-472c-964e-3bd3011bfc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851277210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.851277210
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.2099367472
Short name T1492
Test name
Test status
Simulation time 65713110 ps
CPU time 1.5 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:51 PM PDT 24
Peak memory 205672 kb
Host smart-a406aa77-6399-4c7c-ad51-c820ea756bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099367472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.2099367472
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2860415841
Short name T500
Test name
Test status
Simulation time 3921103006 ps
CPU time 17.25 seconds
Started Jul 28 05:03:02 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 300484 kb
Host smart-ca13c94c-21ca-4f65-89b7-39c7eff1b1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860415841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2860415841
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.355099714
Short name T999
Test name
Test status
Simulation time 449032233 ps
CPU time 8.68 seconds
Started Jul 28 05:03:01 PM PDT 24
Finished Jul 28 05:03:10 PM PDT 24
Peak memory 213908 kb
Host smart-0626b759-09d3-424f-b473-90cb640b35d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355099714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.355099714
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.4207348370
Short name T184
Test name
Test status
Simulation time 38706564 ps
CPU time 0.83 seconds
Started Jul 28 05:02:43 PM PDT 24
Finished Jul 28 05:02:44 PM PDT 24
Peak memory 223972 kb
Host smart-708e1625-a705-48ea-b3cc-8cffae98cf26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207348370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.4207348370
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1597235281
Short name T1628
Test name
Test status
Simulation time 747055384 ps
CPU time 4.41 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 214088 kb
Host smart-677e8b29-4161-4056-85ba-05e47be52360
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597235281 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1597235281
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.444806209
Short name T1457
Test name
Test status
Simulation time 1102276784 ps
CPU time 1.51 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:51 PM PDT 24
Peak memory 205728 kb
Host smart-4d3f8fc7-0adf-4301-afa9-b1a035fd1fd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444806209 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_acq.444806209
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3561913537
Short name T696
Test name
Test status
Simulation time 172273248 ps
CPU time 1.11 seconds
Started Jul 28 05:02:47 PM PDT 24
Finished Jul 28 05:02:48 PM PDT 24
Peak memory 205772 kb
Host smart-0e5dcbaa-56c9-4ae0-8541-66e883f2c4e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561913537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3561913537
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.3804405338
Short name T1192
Test name
Test status
Simulation time 628829386 ps
CPU time 3.38 seconds
Started Jul 28 05:02:46 PM PDT 24
Finished Jul 28 05:02:49 PM PDT 24
Peak memory 205936 kb
Host smart-4265902f-6977-4d50-b026-ead5c6388396
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804405338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.3804405338
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.3926974303
Short name T1396
Test name
Test status
Simulation time 112850521 ps
CPU time 1.33 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:02:58 PM PDT 24
Peak memory 205756 kb
Host smart-f2cf3bd2-84e0-4245-a1ab-b2dfaf908a4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926974303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.3926974303
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3112593173
Short name T1338
Test name
Test status
Simulation time 1275344759 ps
CPU time 6.98 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 222320 kb
Host smart-ebd1adaf-61cb-4dcb-8f5a-0a2f791041ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112593173 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3112593173
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.1301186208
Short name T797
Test name
Test status
Simulation time 20337817402 ps
CPU time 55.63 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 1047288 kb
Host smart-d3004f00-2241-4e2c-be37-48091644c7eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301186208 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.1301186208
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.1002701411
Short name T1719
Test name
Test status
Simulation time 6695799441 ps
CPU time 2.88 seconds
Started Jul 28 05:02:39 PM PDT 24
Finished Jul 28 05:02:42 PM PDT 24
Peak memory 214296 kb
Host smart-93e1c9d2-6b7a-4a7f-9670-717cb475b98d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002701411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_nack_acqfull.1002701411
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.2538481346
Short name T1499
Test name
Test status
Simulation time 2059438456 ps
CPU time 2.47 seconds
Started Jul 28 05:02:50 PM PDT 24
Finished Jul 28 05:02:53 PM PDT 24
Peak memory 205912 kb
Host smart-1dd33bf0-8dd3-43d3-bdb4-a2d3f99ac3b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538481346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.2538481346
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.1033962860
Short name T806
Test name
Test status
Simulation time 873585389 ps
CPU time 5.89 seconds
Started Jul 28 05:03:05 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 222316 kb
Host smart-426821d4-200f-4fe5-8272-3644bf0a5c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033962860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.1033962860
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.1664357389
Short name T884
Test name
Test status
Simulation time 422340428 ps
CPU time 2.08 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 205724 kb
Host smart-51f3e6e4-7204-4d9c-9da5-feb8e57e9e0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664357389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_smbus_maxlen.1664357389
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1983681014
Short name T1561
Test name
Test status
Simulation time 795223058 ps
CPU time 11.75 seconds
Started Jul 28 05:02:59 PM PDT 24
Finished Jul 28 05:03:11 PM PDT 24
Peak memory 214176 kb
Host smart-62a014ed-dc29-40e6-a0de-137840d96875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983681014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1983681014
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.3782435898
Short name T1339
Test name
Test status
Simulation time 34351459051 ps
CPU time 34.36 seconds
Started Jul 28 05:02:43 PM PDT 24
Finished Jul 28 05:03:17 PM PDT 24
Peak memory 295236 kb
Host smart-6ebda245-d0ab-4be5-a4af-d8cf52697449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782435898 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.3782435898
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1885684598
Short name T430
Test name
Test status
Simulation time 768045365 ps
CPU time 6.51 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:03:00 PM PDT 24
Peak memory 205892 kb
Host smart-595c9cf8-6bd1-4be5-a341-04d9794c4b3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885684598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1885684598
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3819742744
Short name T514
Test name
Test status
Simulation time 15392052409 ps
CPU time 8.42 seconds
Started Jul 28 05:03:03 PM PDT 24
Finished Jul 28 05:03:11 PM PDT 24
Peak memory 206140 kb
Host smart-f8f43371-6c27-4d61-83f1-4afcd9d8ea23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819742744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3819742744
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.2478627602
Short name T393
Test name
Test status
Simulation time 3114531130 ps
CPU time 24.07 seconds
Started Jul 28 05:02:41 PM PDT 24
Finished Jul 28 05:03:05 PM PDT 24
Peak memory 497512 kb
Host smart-0fcd3a6d-53ea-4b68-a9cd-66c73818cbc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478627602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.2478627602
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.3924098008
Short name T414
Test name
Test status
Simulation time 1124278684 ps
CPU time 6.61 seconds
Started Jul 28 05:03:02 PM PDT 24
Finished Jul 28 05:03:08 PM PDT 24
Peak memory 222324 kb
Host smart-26b9387b-8cd4-4360-9038-fa082fe3ec05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924098008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.3924098008
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.3276037659
Short name T734
Test name
Test status
Simulation time 224979837 ps
CPU time 3.18 seconds
Started Jul 28 05:02:52 PM PDT 24
Finished Jul 28 05:02:55 PM PDT 24
Peak memory 205876 kb
Host smart-ffb8cb1a-3f70-417a-b0e0-2f0e8e1af6ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276037659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.3276037659
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.4053300325
Short name T1333
Test name
Test status
Simulation time 20468460 ps
CPU time 0.6 seconds
Started Jul 28 05:03:31 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 204928 kb
Host smart-b08ab3ab-42d6-498b-907e-4d3665054cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053300325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.4053300325
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2044403866
Short name T1160
Test name
Test status
Simulation time 1809415904 ps
CPU time 93.25 seconds
Started Jul 28 05:03:26 PM PDT 24
Finished Jul 28 05:04:59 PM PDT 24
Peak memory 286232 kb
Host smart-8541b8c3-ef68-4a80-8e59-9a1737d3407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044403866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2044403866
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3156977005
Short name T1749
Test name
Test status
Simulation time 2589145032 ps
CPU time 177.53 seconds
Started Jul 28 05:03:44 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 780596 kb
Host smart-d0580d8c-c80c-43ab-831a-13c2cbe2259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156977005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3156977005
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1058986590
Short name T1032
Test name
Test status
Simulation time 139374147 ps
CPU time 1.2 seconds
Started Jul 28 05:03:33 PM PDT 24
Finished Jul 28 05:03:34 PM PDT 24
Peak memory 205500 kb
Host smart-d74850d8-ff24-4721-b2ef-1737cb29a861
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058986590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1058986590
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3039669385
Short name T1662
Test name
Test status
Simulation time 18859885030 ps
CPU time 164.4 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:06:13 PM PDT 24
Peak memory 1525940 kb
Host smart-176b3c29-7bf4-4073-b27c-9c2fa0289461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039669385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3039669385
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1923365785
Short name T1304
Test name
Test status
Simulation time 1279857802 ps
CPU time 10.99 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:03:39 PM PDT 24
Peak memory 205756 kb
Host smart-2d33069c-ceb0-4aa6-9ae8-2456838cd438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923365785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1923365785
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_perf.2120220285
Short name T1612
Test name
Test status
Simulation time 2835934863 ps
CPU time 76.18 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:04:39 PM PDT 24
Peak memory 504120 kb
Host smart-0468c72a-9c92-43ad-9a5b-1c5cfe1b826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120220285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2120220285
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.2429242094
Short name T1287
Test name
Test status
Simulation time 5849626268 ps
CPU time 31.41 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:54 PM PDT 24
Peak memory 205744 kb
Host smart-78518c96-e759-43ea-ab89-e757f0f9904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429242094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.2429242094
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.4036787296
Short name T1577
Test name
Test status
Simulation time 2409538000 ps
CPU time 56.76 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:04:22 PM PDT 24
Peak memory 324836 kb
Host smart-2cfcab84-6118-4ffd-9fb1-36701a4420be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036787296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.4036787296
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.2773202588
Short name T107
Test name
Test status
Simulation time 10510666671 ps
CPU time 559.41 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:12:44 PM PDT 24
Peak memory 2257404 kb
Host smart-e1c49b08-7d3c-497c-bbb0-4079cb684823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773202588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2773202588
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2295541189
Short name T30
Test name
Test status
Simulation time 2089996884 ps
CPU time 10.02 seconds
Started Jul 28 05:03:32 PM PDT 24
Finished Jul 28 05:03:42 PM PDT 24
Peak memory 218048 kb
Host smart-112c53dd-868b-4fc0-86fd-397161a9cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295541189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2295541189
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2586272836
Short name T1033
Test name
Test status
Simulation time 18621850183 ps
CPU time 5.15 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:03:31 PM PDT 24
Peak memory 214240 kb
Host smart-5ac5faab-2eb5-4002-b234-2fe7dc0f3419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586272836 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2586272836
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1463382785
Short name T1062
Test name
Test status
Simulation time 230188309 ps
CPU time 0.97 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 205736 kb
Host smart-83c9c00a-b11c-4fd9-901a-e6a9e4eebefe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463382785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1463382785
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1588460049
Short name T1464
Test name
Test status
Simulation time 696367974 ps
CPU time 1.53 seconds
Started Jul 28 05:03:35 PM PDT 24
Finished Jul 28 05:03:36 PM PDT 24
Peak memory 214044 kb
Host smart-842acaf8-904f-457a-97be-a0d9d7287cd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588460049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1588460049
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.2469715444
Short name T1111
Test name
Test status
Simulation time 853032192 ps
CPU time 1.84 seconds
Started Jul 28 05:03:30 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 205684 kb
Host smart-51a2d9c1-2a70-4f52-a46d-3bf9d5ce2cc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469715444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.2469715444
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2859711621
Short name T1550
Test name
Test status
Simulation time 450337657 ps
CPU time 1.03 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:03:25 PM PDT 24
Peak memory 205696 kb
Host smart-815a2a6e-f112-4484-8ec0-d6bceb764aeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859711621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2859711621
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3674062144
Short name T178
Test name
Test status
Simulation time 224395349 ps
CPU time 1.64 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 214088 kb
Host smart-38f2abfc-1df9-4bd1-9044-51e69603e385
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674062144 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3674062144
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.3626194794
Short name T1716
Test name
Test status
Simulation time 1330683981 ps
CPU time 4.76 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 216848 kb
Host smart-d08b2e1a-edfa-4584-b6e5-c3fe781b07ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626194794 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.3626194794
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.3168190838
Short name T382
Test name
Test status
Simulation time 13380834139 ps
CPU time 32.51 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:03:57 PM PDT 24
Peak memory 687532 kb
Host smart-11946c6c-69a9-4936-8b0a-34632ea60732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168190838 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.3168190838
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.3417331340
Short name T1216
Test name
Test status
Simulation time 480837875 ps
CPU time 2.64 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:03:26 PM PDT 24
Peak memory 214068 kb
Host smart-c7744016-711a-4c6f-9d98-a25ab05dc695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417331340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_acqfull.3417331340
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.1482028203
Short name T936
Test name
Test status
Simulation time 5445421408 ps
CPU time 2.49 seconds
Started Jul 28 05:03:40 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 206056 kb
Host smart-aceb89c7-e9d0-48fd-9dd6-10eb80846493
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482028203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.1482028203
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_txstretch.3736133228
Short name T1030
Test name
Test status
Simulation time 546887412 ps
CPU time 1.43 seconds
Started Jul 28 05:03:27 PM PDT 24
Finished Jul 28 05:03:29 PM PDT 24
Peak memory 222376 kb
Host smart-d435ee96-5ebb-4b5e-91c7-d9560446c936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736133228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_nack_txstretch.3736133228
Directory /workspace/10.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/10.i2c_target_perf.1688836126
Short name T478
Test name
Test status
Simulation time 2554421681 ps
CPU time 4.12 seconds
Started Jul 28 05:03:31 PM PDT 24
Finished Jul 28 05:03:35 PM PDT 24
Peak memory 218812 kb
Host smart-eeeb2439-b336-4240-9e3e-aacbfbedf759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688836126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.1688836126
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.2199063902
Short name T739
Test name
Test status
Simulation time 517305448 ps
CPU time 2.34 seconds
Started Jul 28 05:03:40 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 205712 kb
Host smart-750ab2ca-9a9d-404f-bbe4-04e233e725d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199063902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.2199063902
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.3214822323
Short name T596
Test name
Test status
Simulation time 1053591438 ps
CPU time 13.07 seconds
Started Jul 28 05:03:32 PM PDT 24
Finished Jul 28 05:03:45 PM PDT 24
Peak memory 214092 kb
Host smart-7e6e20f4-ab76-456c-9386-5ef6774d9329
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214822323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.3214822323
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.82243223
Short name T1321
Test name
Test status
Simulation time 16505701054 ps
CPU time 67.57 seconds
Started Jul 28 05:03:34 PM PDT 24
Finished Jul 28 05:04:42 PM PDT 24
Peak memory 299384 kb
Host smart-54f45b8a-9798-4aaf-b452-904798f1c2fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82243223 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.i2c_target_stress_all.82243223
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1018939051
Short name T427
Test name
Test status
Simulation time 39603682764 ps
CPU time 590.9 seconds
Started Jul 28 05:03:31 PM PDT 24
Finished Jul 28 05:13:22 PM PDT 24
Peak memory 4766632 kb
Host smart-149a7aa8-4019-4275-aa07-e317c5a10ad5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018939051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1018939051
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.177258944
Short name T1576
Test name
Test status
Simulation time 1086809234 ps
CPU time 6.95 seconds
Started Jul 28 05:03:26 PM PDT 24
Finished Jul 28 05:03:33 PM PDT 24
Peak memory 218556 kb
Host smart-3682cddc-51f8-49de-b924-bdb31bd0b907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177258944 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_timeout.177258944
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.692445675
Short name T1707
Test name
Test status
Simulation time 162108944 ps
CPU time 2.72 seconds
Started Jul 28 05:03:34 PM PDT 24
Finished Jul 28 05:03:37 PM PDT 24
Peak memory 205136 kb
Host smart-b46a2c5c-4dbd-4700-b0ff-07da3cff4f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692445675 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.692445675
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1738568950
Short name T887
Test name
Test status
Simulation time 18846885 ps
CPU time 0.65 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 204892 kb
Host smart-7a3d18fb-a764-488f-9d2d-6d5c16730e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738568950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1738568950
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2620730035
Short name T375
Test name
Test status
Simulation time 477083954 ps
CPU time 2.08 seconds
Started Jul 28 05:03:37 PM PDT 24
Finished Jul 28 05:03:39 PM PDT 24
Peak memory 214004 kb
Host smart-29314c04-8f7f-499d-9b4a-009468e326da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620730035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2620730035
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2068285996
Short name T1436
Test name
Test status
Simulation time 2317648380 ps
CPU time 27.26 seconds
Started Jul 28 05:03:32 PM PDT 24
Finished Jul 28 05:04:00 PM PDT 24
Peak memory 317100 kb
Host smart-65334ae0-6897-49f3-adbf-0741c62f5369
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068285996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2068285996
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1115998808
Short name T1384
Test name
Test status
Simulation time 7553541022 ps
CPU time 40.54 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:04:10 PM PDT 24
Peak memory 245980 kb
Host smart-4f146c40-4043-4f48-ac0c-53d40258aba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115998808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1115998808
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1700759923
Short name T620
Test name
Test status
Simulation time 33107232593 ps
CPU time 99.42 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:05:03 PM PDT 24
Peak memory 870544 kb
Host smart-59c04d4c-6d85-464b-a056-aa85427076ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700759923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1700759923
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1233284887
Short name T249
Test name
Test status
Simulation time 117155444 ps
CPU time 0.99 seconds
Started Jul 28 05:03:26 PM PDT 24
Finished Jul 28 05:03:27 PM PDT 24
Peak memory 205440 kb
Host smart-eb56dd87-6f95-4bee-ad7b-34c6f1b50af7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233284887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1233284887
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3979717366
Short name T699
Test name
Test status
Simulation time 357031338 ps
CPU time 7.33 seconds
Started Jul 28 05:03:35 PM PDT 24
Finished Jul 28 05:03:42 PM PDT 24
Peak memory 205824 kb
Host smart-88775939-aa6e-40eb-9f48-1434f7dc3cd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979717366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3979717366
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1829418643
Short name T1308
Test name
Test status
Simulation time 4042219565 ps
CPU time 175.82 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:06:20 PM PDT 24
Peak memory 861828 kb
Host smart-6c272bc5-e3db-4124-8e8b-3be3d91581bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829418643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1829418643
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2440506559
Short name T1400
Test name
Test status
Simulation time 1855005007 ps
CPU time 9.49 seconds
Started Jul 28 05:03:44 PM PDT 24
Finished Jul 28 05:03:53 PM PDT 24
Peak memory 205764 kb
Host smart-9d4ff27f-d6a8-4448-8b98-0995872d4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440506559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2440506559
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_override.1812646711
Short name T1137
Test name
Test status
Simulation time 16707114 ps
CPU time 0.64 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:03:29 PM PDT 24
Peak memory 205488 kb
Host smart-bf724dac-dd7e-44f9-ba98-cf28ffb0550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812646711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1812646711
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3203030862
Short name T8
Test name
Test status
Simulation time 2728038761 ps
CPU time 177.84 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:06:40 PM PDT 24
Peak memory 798960 kb
Host smart-30a7e148-1a5a-4477-ac29-dddaae97c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203030862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3203030862
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.2127459574
Short name T1647
Test name
Test status
Simulation time 510829243 ps
CPU time 4.13 seconds
Started Jul 28 05:03:44 PM PDT 24
Finished Jul 28 05:03:49 PM PDT 24
Peak memory 205748 kb
Host smart-4a0358b2-434d-4988-b904-d3e51830db92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127459574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.2127459574
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1103417490
Short name T1149
Test name
Test status
Simulation time 8562115018 ps
CPU time 42.64 seconds
Started Jul 28 05:03:30 PM PDT 24
Finished Jul 28 05:04:13 PM PDT 24
Peak memory 367252 kb
Host smart-7a92098f-ed27-4377-94b4-1e677df2f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103417490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1103417490
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.2662327217
Short name T250
Test name
Test status
Simulation time 44198079683 ps
CPU time 1176.07 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:23:22 PM PDT 24
Peak memory 2110192 kb
Host smart-807b9c0c-0303-469d-8a1f-303c3687e2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662327217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.2662327217
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.4107782444
Short name T1098
Test name
Test status
Simulation time 2054905273 ps
CPU time 25.97 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:48 PM PDT 24
Peak memory 213980 kb
Host smart-3b635cee-534c-4cf9-bc5e-2a315546b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107782444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.4107782444
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3299837820
Short name T714
Test name
Test status
Simulation time 923094586 ps
CPU time 5.57 seconds
Started Jul 28 05:03:26 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 220492 kb
Host smart-7402421d-f2e1-4325-8a22-9c603a3ec659
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299837820 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3299837820
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3278981289
Short name T1500
Test name
Test status
Simulation time 668764172 ps
CPU time 1.64 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:31 PM PDT 24
Peak memory 205864 kb
Host smart-38f19dde-1781-4e6f-a851-695927301c9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278981289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3278981289
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1405820427
Short name T344
Test name
Test status
Simulation time 308578042 ps
CPU time 1.26 seconds
Started Jul 28 05:03:35 PM PDT 24
Finished Jul 28 05:03:37 PM PDT 24
Peak memory 206684 kb
Host smart-1fd39138-6865-4fc4-844a-3ac51b18d788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405820427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1405820427
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.768394654
Short name T865
Test name
Test status
Simulation time 479207625 ps
CPU time 2.05 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 205776 kb
Host smart-1915080d-ad8a-4644-8738-ab314c800e55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768394654 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.768394654
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.1883253140
Short name T1278
Test name
Test status
Simulation time 360900021 ps
CPU time 1.05 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 205748 kb
Host smart-5b78da65-ad36-41f9-bc30-46b1b04cf82d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883253140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.1883253140
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1116551903
Short name T953
Test name
Test status
Simulation time 13050375678 ps
CPU time 8.19 seconds
Started Jul 28 05:03:30 PM PDT 24
Finished Jul 28 05:03:38 PM PDT 24
Peak memory 222336 kb
Host smart-c01d3a5b-bbca-492a-b51b-25f06a7d50be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116551903 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1116551903
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1576694928
Short name T434
Test name
Test status
Simulation time 13002825628 ps
CPU time 9.9 seconds
Started Jul 28 05:03:34 PM PDT 24
Finished Jul 28 05:03:44 PM PDT 24
Peak memory 409288 kb
Host smart-3e302ca1-ed13-495d-bc1e-81caf1cc93e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576694928 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1576694928
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.2982834154
Short name T1449
Test name
Test status
Simulation time 1098080048 ps
CPU time 3.23 seconds
Started Jul 28 05:03:31 PM PDT 24
Finished Jul 28 05:03:34 PM PDT 24
Peak memory 214116 kb
Host smart-a4fb7c7e-94fe-4b3c-b1f0-c4eb8b16d646
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982834154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_nack_acqfull.2982834154
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.3378892465
Short name T975
Test name
Test status
Simulation time 984011382 ps
CPU time 2.47 seconds
Started Jul 28 05:03:30 PM PDT 24
Finished Jul 28 05:03:33 PM PDT 24
Peak memory 205988 kb
Host smart-cb55d000-f844-4bb4-ae32-82ab0fe3f46f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378892465 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.3378892465
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_txstretch.3276965781
Short name T1600
Test name
Test status
Simulation time 134188356 ps
CPU time 1.3 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 222368 kb
Host smart-a04877b7-6586-4514-acd1-20986228d285
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276965781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_nack_txstretch.3276965781
Directory /workspace/11.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/11.i2c_target_perf.2085871400
Short name T741
Test name
Test status
Simulation time 578225458 ps
CPU time 4.69 seconds
Started Jul 28 05:03:39 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 218320 kb
Host smart-a37accc1-f54a-4c47-af74-0a82edf1ddb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085871400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.2085871400
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.1735647203
Short name T1478
Test name
Test status
Simulation time 741260647 ps
CPU time 2 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:03:25 PM PDT 24
Peak memory 205628 kb
Host smart-7b09a99f-a1fb-43d0-a2ff-949f5cfd9028
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735647203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_smbus_maxlen.1735647203
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2105620893
Short name T920
Test name
Test status
Simulation time 1878854159 ps
CPU time 14.2 seconds
Started Jul 28 05:03:26 PM PDT 24
Finished Jul 28 05:03:40 PM PDT 24
Peak memory 214116 kb
Host smart-28d538a5-164e-4ca8-9fad-3fee4e79fd77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105620893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2105620893
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.434076821
Short name T1631
Test name
Test status
Simulation time 35078761625 ps
CPU time 35.17 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:04:01 PM PDT 24
Peak memory 273776 kb
Host smart-82daf33e-02ce-40d3-b080-243eff4c62a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434076821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_stress_all.434076821
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1685113918
Short name T418
Test name
Test status
Simulation time 1674226597 ps
CPU time 14.25 seconds
Started Jul 28 05:03:36 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 222120 kb
Host smart-2f5bf904-73d1-4671-a622-2a59d91b2ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685113918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1685113918
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.741049575
Short name T554
Test name
Test status
Simulation time 30987960786 ps
CPU time 230.55 seconds
Started Jul 28 05:03:31 PM PDT 24
Finished Jul 28 05:07:22 PM PDT 24
Peak memory 2807856 kb
Host smart-96be5baa-27ba-4503-8ac4-fee34b306130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741049575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.741049575
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2368887740
Short name T319
Test name
Test status
Simulation time 4683269682 ps
CPU time 46.89 seconds
Started Jul 28 05:03:27 PM PDT 24
Finished Jul 28 05:04:14 PM PDT 24
Peak memory 733076 kb
Host smart-3f3d77bf-179d-4c04-ab65-fada14e4a00e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368887740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2368887740
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.536578521
Short name T1073
Test name
Test status
Simulation time 1524786019 ps
CPU time 7.11 seconds
Started Jul 28 05:03:53 PM PDT 24
Finished Jul 28 05:04:00 PM PDT 24
Peak memory 214112 kb
Host smart-a1bbde2a-291e-405b-bf5e-5a07f8f3042b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536578521 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.536578521
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.3500721114
Short name T1257
Test name
Test status
Simulation time 213297494 ps
CPU time 3.68 seconds
Started Jul 28 05:03:37 PM PDT 24
Finished Jul 28 05:03:40 PM PDT 24
Peak memory 206168 kb
Host smart-14656446-a731-4758-98e6-eb907d98216e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500721114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.3500721114
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.1094619625
Short name T1233
Test name
Test status
Simulation time 106187681 ps
CPU time 0.65 seconds
Started Jul 28 05:03:40 PM PDT 24
Finished Jul 28 05:03:40 PM PDT 24
Peak memory 205080 kb
Host smart-0e63cda8-36ec-4e0d-a21e-3874aa8d1c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094619625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1094619625
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.877460296
Short name T1668
Test name
Test status
Simulation time 2864665773 ps
CPU time 12.35 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:03:36 PM PDT 24
Peak memory 214136 kb
Host smart-3c2c1f5d-b96c-425f-8a13-b3f1aa4e0a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877460296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.877460296
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3666915634
Short name T1608
Test name
Test status
Simulation time 344065208 ps
CPU time 5.48 seconds
Started Jul 28 05:03:35 PM PDT 24
Finished Jul 28 05:03:41 PM PDT 24
Peak memory 253148 kb
Host smart-0a371ed4-c09a-4b9d-82fa-4b7eef1b5f3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666915634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3666915634
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3126621143
Short name T1681
Test name
Test status
Simulation time 6682320707 ps
CPU time 101.96 seconds
Started Jul 28 05:03:41 PM PDT 24
Finished Jul 28 05:05:23 PM PDT 24
Peak memory 621176 kb
Host smart-ad5d325c-4345-48ff-9890-6ca08bfe83d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126621143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3126621143
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2506107141
Short name T1064
Test name
Test status
Simulation time 11767283312 ps
CPU time 167.61 seconds
Started Jul 28 05:03:39 PM PDT 24
Finished Jul 28 05:06:26 PM PDT 24
Peak memory 763328 kb
Host smart-87c3eee9-5356-4197-b4ef-f8939cacd3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506107141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2506107141
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1463371654
Short name T244
Test name
Test status
Simulation time 483473222 ps
CPU time 1.35 seconds
Started Jul 28 05:04:00 PM PDT 24
Finished Jul 28 05:04:01 PM PDT 24
Peak memory 205676 kb
Host smart-70cd240c-d854-4761-bf08-5832fdc70c26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463371654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.1463371654
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2619494519
Short name T982
Test name
Test status
Simulation time 431940405 ps
CPU time 2.92 seconds
Started Jul 28 05:03:27 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 220776 kb
Host smart-3db5ef49-288a-4d0f-b8d4-5ae877436986
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619494519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2619494519
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2450199020
Short name T79
Test name
Test status
Simulation time 4967196246 ps
CPU time 146.43 seconds
Started Jul 28 05:03:30 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 1345376 kb
Host smart-5fd36f4d-5508-4ca2-852c-4fb59868046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450199020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2450199020
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1744775408
Short name T21
Test name
Test status
Simulation time 1974985174 ps
CPU time 5.36 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:03:56 PM PDT 24
Peak memory 205772 kb
Host smart-27b4d076-56a2-4a1f-870d-1355b5a10f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744775408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1744775408
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.3553410265
Short name T768
Test name
Test status
Simulation time 94803790 ps
CPU time 0.69 seconds
Started Jul 28 05:03:31 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 205408 kb
Host smart-7f00043d-4818-4a57-8e02-b590cb0a6331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553410265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3553410265
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.1576814315
Short name T20
Test name
Test status
Simulation time 7655933258 ps
CPU time 67.08 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:04:37 PM PDT 24
Peak memory 214132 kb
Host smart-7d268671-c02a-40d9-9938-7c79f684372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576814315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1576814315
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.1313938986
Short name T373
Test name
Test status
Simulation time 99415135 ps
CPU time 1.73 seconds
Started Jul 28 05:03:39 PM PDT 24
Finished Jul 28 05:03:41 PM PDT 24
Peak memory 226432 kb
Host smart-fa88b29b-44dc-4170-aad7-3998fbfda3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313938986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.1313938986
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.404117083
Short name T743
Test name
Test status
Simulation time 1376250900 ps
CPU time 23.68 seconds
Started Jul 28 05:03:39 PM PDT 24
Finished Jul 28 05:04:03 PM PDT 24
Peak memory 351248 kb
Host smart-f4961fbb-2ed9-411c-8e2d-19db63661993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404117083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.404117083
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1862180307
Short name T1534
Test name
Test status
Simulation time 1470660284 ps
CPU time 32.15 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 213908 kb
Host smart-162dc1a5-f270-4ecd-9efd-565eca81fa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862180307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1862180307
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2534508955
Short name T1654
Test name
Test status
Simulation time 1099739850 ps
CPU time 5.34 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:03:50 PM PDT 24
Peak memory 214164 kb
Host smart-528fd286-3754-4ae9-8135-ed2dd4c12045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534508955 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2534508955
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2339252674
Short name T635
Test name
Test status
Simulation time 1085092764 ps
CPU time 1.36 seconds
Started Jul 28 05:03:39 PM PDT 24
Finished Jul 28 05:03:41 PM PDT 24
Peak memory 210756 kb
Host smart-cb336519-da2a-469b-92da-0677b676dca7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339252674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2339252674
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.258027369
Short name T1586
Test name
Test status
Simulation time 116465098 ps
CPU time 0.97 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 205660 kb
Host smart-990bbd79-50bb-4f58-8f19-af849be17044
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258027369 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.258027369
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.1452941509
Short name T1209
Test name
Test status
Simulation time 1553119009 ps
CPU time 2.13 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 205904 kb
Host smart-47108c44-2443-4a42-86e8-32f5f196fdae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452941509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.1452941509
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.1197803413
Short name T165
Test name
Test status
Simulation time 147289470 ps
CPU time 1.58 seconds
Started Jul 28 05:03:33 PM PDT 24
Finished Jul 28 05:03:34 PM PDT 24
Peak memory 205768 kb
Host smart-40026134-d73d-4a7d-ae56-7e6ae6c0f96a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197803413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.1197803413
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3214915548
Short name T1404
Test name
Test status
Simulation time 834547931 ps
CPU time 3.64 seconds
Started Jul 28 05:03:43 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 214044 kb
Host smart-4d9e6828-bb39-4fad-9bcc-f2766e59d7a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214915548 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3214915548
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3305139068
Short name T978
Test name
Test status
Simulation time 13083761140 ps
CPU time 36.94 seconds
Started Jul 28 05:03:33 PM PDT 24
Finished Jul 28 05:04:10 PM PDT 24
Peak memory 798148 kb
Host smart-3ea10292-b308-420d-9916-e64577b38845
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305139068 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3305139068
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.4272607791
Short name T772
Test name
Test status
Simulation time 423204827 ps
CPU time 2.5 seconds
Started Jul 28 05:03:41 PM PDT 24
Finished Jul 28 05:03:44 PM PDT 24
Peak memory 214108 kb
Host smart-c8d2f2a0-e648-4de0-b3bf-7817b40aef5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272607791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_acqfull.4272607791
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.1506586669
Short name T1551
Test name
Test status
Simulation time 467061266 ps
CPU time 2.42 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:48 PM PDT 24
Peak memory 206112 kb
Host smart-ef244c18-a002-4ea5-86a3-ee83607da923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506586669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.1506586669
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.1595707663
Short name T1164
Test name
Test status
Simulation time 1234786309 ps
CPU time 4.75 seconds
Started Jul 28 05:03:32 PM PDT 24
Finished Jul 28 05:03:37 PM PDT 24
Peak memory 211136 kb
Host smart-dd0c2a58-571f-499f-8e35-2cbe6f90ecf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595707663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.1595707663
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.2078737518
Short name T492
Test name
Test status
Simulation time 536971916 ps
CPU time 2.38 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 205684 kb
Host smart-d95a355a-f5b0-4ec6-b384-b6264bd3e6af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078737518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.2078737518
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3641151272
Short name T623
Test name
Test status
Simulation time 4906157037 ps
CPU time 17.32 seconds
Started Jul 28 05:03:58 PM PDT 24
Finished Jul 28 05:04:15 PM PDT 24
Peak memory 214276 kb
Host smart-876c5274-179d-4491-8df5-664b3a25cebd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641151272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3641151272
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.52488268
Short name T686
Test name
Test status
Simulation time 24660814433 ps
CPU time 617.9 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:13:47 PM PDT 24
Peak memory 3370592 kb
Host smart-944ef1fc-bf4f-4ea7-baf0-7a6bb16c7b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52488268 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.i2c_target_stress_all.52488268
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.102778158
Short name T1730
Test name
Test status
Simulation time 1381216431 ps
CPU time 5.32 seconds
Started Jul 28 05:03:43 PM PDT 24
Finished Jul 28 05:03:48 PM PDT 24
Peak memory 206008 kb
Host smart-cd4ea99e-5549-4dae-b395-a16160a8a3a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102778158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_rd.102778158
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2988842579
Short name T770
Test name
Test status
Simulation time 60718312276 ps
CPU time 47.72 seconds
Started Jul 28 05:03:44 PM PDT 24
Finished Jul 28 05:04:32 PM PDT 24
Peak memory 730968 kb
Host smart-c42bb203-eb93-44f4-bf12-8281d9b539de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988842579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2988842579
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.4104276522
Short name T1142
Test name
Test status
Simulation time 604962148 ps
CPU time 2.21 seconds
Started Jul 28 05:03:34 PM PDT 24
Finished Jul 28 05:03:37 PM PDT 24
Peak memory 222032 kb
Host smart-653c1740-2293-4f17-a83e-a9891f0f0623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104276522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.4104276522
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1765845342
Short name T991
Test name
Test status
Simulation time 1281052560 ps
CPU time 6.28 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:03:31 PM PDT 24
Peak memory 220008 kb
Host smart-7644151b-9f20-4007-95f2-ab1e13a4c9d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765845342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1765845342
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.3774090677
Short name T1072
Test name
Test status
Simulation time 658614423 ps
CPU time 9.09 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:55 PM PDT 24
Peak memory 206352 kb
Host smart-1b7a319b-e888-4863-ae71-c91b08a2a391
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774090677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.3774090677
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3527287791
Short name T1556
Test name
Test status
Simulation time 23845297 ps
CPU time 0.61 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 204904 kb
Host smart-e07eb10d-483e-414e-a76e-e1c39575d3f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527287791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3527287791
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.126714190
Short name T934
Test name
Test status
Simulation time 465016126 ps
CPU time 1.79 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:03:54 PM PDT 24
Peak memory 213924 kb
Host smart-6221326f-1809-4679-a714-b1544e4488f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126714190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.126714190
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.370500403
Short name T651
Test name
Test status
Simulation time 1551900023 ps
CPU time 6.33 seconds
Started Jul 28 05:03:39 PM PDT 24
Finished Jul 28 05:03:46 PM PDT 24
Peak memory 263284 kb
Host smart-3d3e1fdb-baf8-49b4-a5e7-1eb3dcc5d174
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370500403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empt
y.370500403
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.4193631012
Short name T338
Test name
Test status
Simulation time 2979326528 ps
CPU time 113.61 seconds
Started Jul 28 05:03:34 PM PDT 24
Finished Jul 28 05:05:28 PM PDT 24
Peak memory 784320 kb
Host smart-ac336795-5df8-45b5-9a33-b8d83fd4ea55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193631012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.4193631012
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1522484077
Short name T404
Test name
Test status
Simulation time 4642169402 ps
CPU time 84.04 seconds
Started Jul 28 05:03:47 PM PDT 24
Finished Jul 28 05:05:11 PM PDT 24
Peak memory 773160 kb
Host smart-c53d1139-c79b-4f7c-b7b6-de7771b809f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522484077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1522484077
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2403129926
Short name T1028
Test name
Test status
Simulation time 231007307 ps
CPU time 1.21 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 205420 kb
Host smart-e1ac7a2f-867b-435f-be7e-787c8b904b2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403129926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2403129926
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.2249999320
Short name T1350
Test name
Test status
Simulation time 214964870 ps
CPU time 10.34 seconds
Started Jul 28 05:03:43 PM PDT 24
Finished Jul 28 05:03:53 PM PDT 24
Peak memory 205804 kb
Host smart-fab245d7-0b81-4203-b98a-7eda2acdec38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249999320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.2249999320
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1173605683
Short name T1059
Test name
Test status
Simulation time 43359312502 ps
CPU time 329.43 seconds
Started Jul 28 05:03:38 PM PDT 24
Finished Jul 28 05:09:08 PM PDT 24
Peak memory 1259868 kb
Host smart-220f4f3b-28f8-4943-899a-35f605d08716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173605683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1173605683
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.3775046763
Short name T260
Test name
Test status
Simulation time 193745204 ps
CPU time 8.03 seconds
Started Jul 28 05:03:54 PM PDT 24
Finished Jul 28 05:04:02 PM PDT 24
Peak memory 205696 kb
Host smart-d683ef29-c5f1-42ee-82fd-3bfafc05725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775046763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3775046763
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.3262354132
Short name T533
Test name
Test status
Simulation time 268463995 ps
CPU time 2.3 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:49 PM PDT 24
Peak memory 221452 kb
Host smart-ace8d93e-d514-4118-9c98-322c5312c959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262354132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3262354132
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3427058183
Short name T1316
Test name
Test status
Simulation time 29451130 ps
CPU time 0.64 seconds
Started Jul 28 05:03:44 PM PDT 24
Finished Jul 28 05:03:45 PM PDT 24
Peak memory 205464 kb
Host smart-3c91c5f1-9a23-48e7-9012-05356a617f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427058183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3427058183
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3136774618
Short name T445
Test name
Test status
Simulation time 2632694650 ps
CPU time 38 seconds
Started Jul 28 05:03:37 PM PDT 24
Finished Jul 28 05:04:15 PM PDT 24
Peak memory 206580 kb
Host smart-5d4b646d-d3c3-4ef2-b89b-bf051884318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136774618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3136774618
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.873744557
Short name T483
Test name
Test status
Simulation time 53108583 ps
CPU time 1.3 seconds
Started Jul 28 05:03:59 PM PDT 24
Finished Jul 28 05:04:01 PM PDT 24
Peak memory 226940 kb
Host smart-f2db619b-ab73-45b3-915f-030bb1fb4a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873744557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.873744557
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.222514275
Short name T1314
Test name
Test status
Simulation time 1164040844 ps
CPU time 19.62 seconds
Started Jul 28 05:03:35 PM PDT 24
Finished Jul 28 05:03:55 PM PDT 24
Peak memory 270560 kb
Host smart-3e06dfdc-b228-40c6-8dd4-a219e0610b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222514275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.222514275
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.468427889
Short name T1717
Test name
Test status
Simulation time 467632910 ps
CPU time 7.18 seconds
Started Jul 28 05:03:36 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 215344 kb
Host smart-ce877b4a-496c-4001-a3bc-10200ee429a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468427889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.468427889
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.4047685448
Short name T1342
Test name
Test status
Simulation time 7622973365 ps
CPU time 6.48 seconds
Started Jul 28 05:03:44 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 219940 kb
Host smart-b0bcc18d-cdcf-4afc-ba91-29338d47d637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047685448 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.4047685448
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.6878685
Short name T745
Test name
Test status
Simulation time 540414833 ps
CPU time 1.07 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 205680 kb
Host smart-027945b7-c01e-4964-bd78-d058efd639fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6878685 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_fifo_reset_acq.6878685
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3161706030
Short name T390
Test name
Test status
Simulation time 451474608 ps
CPU time 1.28 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 205848 kb
Host smart-7fc20838-054b-4059-b007-0d27431c5d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161706030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3161706030
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.3485049085
Short name T870
Test name
Test status
Simulation time 3867987766 ps
CPU time 2.42 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:49 PM PDT 24
Peak memory 206048 kb
Host smart-80646a45-f25f-4015-a7bc-b9b847b72d72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485049085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.3485049085
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.3332276312
Short name T465
Test name
Test status
Simulation time 469409685 ps
CPU time 1.62 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:48 PM PDT 24
Peak memory 205696 kb
Host smart-6ead9dbb-a993-44f9-9417-755a8d6aaa6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332276312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.3332276312
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.821281294
Short name T951
Test name
Test status
Simulation time 1432828148 ps
CPU time 4.3 seconds
Started Jul 28 05:03:47 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 222228 kb
Host smart-e6e0d78c-3ffc-4484-ac23-8e5dd62edc1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821281294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.821281294
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.1242618700
Short name T394
Test name
Test status
Simulation time 575092588 ps
CPU time 2.76 seconds
Started Jul 28 05:04:06 PM PDT 24
Finished Jul 28 05:04:09 PM PDT 24
Peak memory 214056 kb
Host smart-5c896529-1180-4548-a93f-42bb32d4d67c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242618700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.1242618700
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.2346280339
Short name T435
Test name
Test status
Simulation time 1588260694 ps
CPU time 2.17 seconds
Started Jul 28 05:03:49 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 205716 kb
Host smart-c050b037-7caf-4545-9043-d3da6bd4dffa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346280339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.2346280339
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.1482136692
Short name T1067
Test name
Test status
Simulation time 2785977303 ps
CPU time 4.97 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 218568 kb
Host smart-bc2bd0de-dafb-4c38-952b-53c8a5bfaa51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482136692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.1482136692
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.2224135239
Short name T314
Test name
Test status
Simulation time 10459794922 ps
CPU time 2.27 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:03:50 PM PDT 24
Peak memory 205820 kb
Host smart-981b8cad-f4a2-4ec5-a431-53c46f2132cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224135239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_smbus_maxlen.2224135239
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1825576802
Short name T1676
Test name
Test status
Simulation time 5206029879 ps
CPU time 43.59 seconds
Started Jul 28 05:03:43 PM PDT 24
Finished Jul 28 05:04:26 PM PDT 24
Peak memory 214248 kb
Host smart-40fd5681-50af-41c8-b1d8-40cb4b51c88f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825576802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1825576802
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.1870275151
Short name T1372
Test name
Test status
Simulation time 44890122142 ps
CPU time 150.59 seconds
Started Jul 28 05:03:51 PM PDT 24
Finished Jul 28 05:06:22 PM PDT 24
Peak memory 1198996 kb
Host smart-cfbd1580-61f5-4423-83d6-84088e859df4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870275151 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.1870275151
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1930450863
Short name T363
Test name
Test status
Simulation time 1842016955 ps
CPU time 41.22 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:04:09 PM PDT 24
Peak memory 214080 kb
Host smart-c2bca99e-7559-4abd-b7c0-5a80ebd83aa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930450863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1930450863
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.3144695405
Short name T764
Test name
Test status
Simulation time 10976633630 ps
CPU time 12.81 seconds
Started Jul 28 05:03:40 PM PDT 24
Finished Jul 28 05:03:52 PM PDT 24
Peak memory 206096 kb
Host smart-a233607a-52f6-4654-8ac7-6c6feeb7aa0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144695405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.3144695405
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1065283693
Short name T507
Test name
Test status
Simulation time 3499506736 ps
CPU time 11.45 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:03:40 PM PDT 24
Peak memory 364896 kb
Host smart-4afc9e5d-b9e4-4e66-b0c8-f126c7bef835
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065283693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1065283693
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3357502261
Short name T967
Test name
Test status
Simulation time 4963857573 ps
CPU time 5.81 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:03:58 PM PDT 24
Peak memory 222376 kb
Host smart-a3ad4f5e-bf79-4e29-acf0-c3e5a4a58ac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357502261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3357502261
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2346910582
Short name T377
Test name
Test status
Simulation time 26132879 ps
CPU time 0.64 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:03:46 PM PDT 24
Peak memory 204988 kb
Host smart-48d206dc-0a7c-4280-90c9-3e5327033501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346910582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2346910582
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1944387350
Short name T1429
Test name
Test status
Simulation time 433372451 ps
CPU time 3.28 seconds
Started Jul 28 05:03:51 PM PDT 24
Finished Jul 28 05:03:54 PM PDT 24
Peak memory 214092 kb
Host smart-cd4b559a-a8fc-452f-9b5a-d1143c56a641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944387350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1944387350
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.316613114
Short name T892
Test name
Test status
Simulation time 1389825239 ps
CPU time 6.3 seconds
Started Jul 28 05:03:43 PM PDT 24
Finished Jul 28 05:03:49 PM PDT 24
Peak memory 280716 kb
Host smart-7fcbc224-518e-4c1d-8947-eff1163cfd3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316613114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.316613114
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1083412348
Short name T453
Test name
Test status
Simulation time 2227428016 ps
CPU time 100.3 seconds
Started Jul 28 05:03:41 PM PDT 24
Finished Jul 28 05:05:22 PM PDT 24
Peak memory 247192 kb
Host smart-be996be1-a346-460f-b5e4-3768b00511be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083412348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1083412348
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.208549578
Short name T809
Test name
Test status
Simulation time 4140235775 ps
CPU time 152.62 seconds
Started Jul 28 05:04:01 PM PDT 24
Finished Jul 28 05:06:34 PM PDT 24
Peak memory 720416 kb
Host smart-5236feeb-7454-454c-9dba-ff3e5cb731d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208549578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.208549578
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.979986012
Short name T1311
Test name
Test status
Simulation time 259463669 ps
CPU time 0.81 seconds
Started Jul 28 05:03:56 PM PDT 24
Finished Jul 28 05:03:57 PM PDT 24
Peak memory 205392 kb
Host smart-fa8c055e-4500-4af4-be1f-769f8cccc108
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979986012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fm
t.979986012
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.200454841
Short name T1146
Test name
Test status
Simulation time 425994720 ps
CPU time 7.75 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:03:52 PM PDT 24
Peak memory 229208 kb
Host smart-ae6f17da-c18f-4560-8c54-11d624a2dd9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200454841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
200454841
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1941579402
Short name T1527
Test name
Test status
Simulation time 3082361454 ps
CPU time 197.52 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 956464 kb
Host smart-4322b1bc-4105-4220-a583-8c3deb3e31a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941579402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1941579402
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2625635332
Short name T555
Test name
Test status
Simulation time 1545405878 ps
CPU time 5.8 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:48 PM PDT 24
Peak memory 205680 kb
Host smart-e4751895-38a6-45a5-8c60-6f7cbd014984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625635332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2625635332
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_override.3431615981
Short name T526
Test name
Test status
Simulation time 18496565 ps
CPU time 0.74 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 205404 kb
Host smart-75ba1516-e8c9-490c-8a33-4985aadbeafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431615981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3431615981
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3565648145
Short name T903
Test name
Test status
Simulation time 680608347 ps
CPU time 7.04 seconds
Started Jul 28 05:03:41 PM PDT 24
Finished Jul 28 05:03:48 PM PDT 24
Peak memory 261620 kb
Host smart-8bcc2910-6402-4f68-9604-542db50c81ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565648145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3565648145
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.219931855
Short name T1594
Test name
Test status
Simulation time 426503873 ps
CPU time 4.99 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 205704 kb
Host smart-22095194-aa1e-43ac-9353-13a674809262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219931855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.219931855
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2162953113
Short name T368
Test name
Test status
Simulation time 2315615808 ps
CPU time 43.47 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:04:33 PM PDT 24
Peak memory 364804 kb
Host smart-b2e9ebb5-8546-40c2-8aba-dcdbb0decb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162953113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2162953113
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2840959356
Short name T1177
Test name
Test status
Simulation time 64915856734 ps
CPU time 1053.43 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:21:20 PM PDT 24
Peak memory 1546088 kb
Host smart-e224ae38-87f1-42c1-8a3f-3f3f79fd5333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840959356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2840959356
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3079002165
Short name T1263
Test name
Test status
Simulation time 2557553383 ps
CPU time 12.99 seconds
Started Jul 28 05:03:51 PM PDT 24
Finished Jul 28 05:04:04 PM PDT 24
Peak memory 220308 kb
Host smart-88d1990d-5bcc-4306-901a-a9d8ac944533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079002165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3079002165
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3804722078
Short name T1383
Test name
Test status
Simulation time 2798795832 ps
CPU time 4.65 seconds
Started Jul 28 05:03:53 PM PDT 24
Finished Jul 28 05:03:57 PM PDT 24
Peak memory 217144 kb
Host smart-4caaff5f-622c-4b99-940f-1e7c640dc540
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804722078 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3804722078
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.4159760034
Short name T952
Test name
Test status
Simulation time 350396088 ps
CPU time 0.94 seconds
Started Jul 28 05:03:54 PM PDT 24
Finished Jul 28 05:04:00 PM PDT 24
Peak memory 205940 kb
Host smart-da674026-9535-435e-a771-97e7b88b339d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159760034 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.4159760034
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3966808109
Short name T326
Test name
Test status
Simulation time 236865805 ps
CPU time 1.36 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 205880 kb
Host smart-9d0c0110-89a1-41e2-9d70-4953e509e8ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966808109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3966808109
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.1488727875
Short name T366
Test name
Test status
Simulation time 387799740 ps
CPU time 2.2 seconds
Started Jul 28 05:03:47 PM PDT 24
Finished Jul 28 05:03:50 PM PDT 24
Peak memory 205888 kb
Host smart-ffda4991-f8b1-4e98-81e1-6048bd242887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488727875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.1488727875
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.2387001799
Short name T1057
Test name
Test status
Simulation time 170810787 ps
CPU time 1.54 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:03:52 PM PDT 24
Peak memory 205696 kb
Host smart-e6c4a9c2-2fd2-41dc-a83e-906cb7bfcbb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387001799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.2387001799
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.218429531
Short name T1273
Test name
Test status
Simulation time 273888121 ps
CPU time 2.34 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:44 PM PDT 24
Peak memory 222336 kb
Host smart-3d108ce6-73d9-4133-828c-d018660c1b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218429531 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.218429531
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3865693130
Short name T353
Test name
Test status
Simulation time 1272428279 ps
CPU time 7.16 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:03:58 PM PDT 24
Peak memory 219320 kb
Host smart-5a13aafa-03fd-490c-acf3-ff39aae7658b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865693130 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3865693130
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.513644754
Short name T782
Test name
Test status
Simulation time 19713636445 ps
CPU time 291.41 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:08:37 PM PDT 24
Peak memory 3518772 kb
Host smart-e5b2c0cc-9852-4ede-977e-5186cc754d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513644754 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.513644754
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.232231682
Short name T153
Test name
Test status
Simulation time 552560693 ps
CPU time 2.73 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:03:53 PM PDT 24
Peak memory 214056 kb
Host smart-049d970a-016d-4cbf-aceb-3c0db8c4f7fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232231682 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_nack_acqfull.232231682
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.2071708389
Short name T1441
Test name
Test status
Simulation time 604338510 ps
CPU time 2.87 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 205920 kb
Host smart-df4e0bc8-8d99-4881-bc66-cbc42648c65e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071708389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.2071708389
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_txstretch.900002913
Short name T771
Test name
Test status
Simulation time 1806266704 ps
CPU time 1.59 seconds
Started Jul 28 05:04:00 PM PDT 24
Finished Jul 28 05:04:02 PM PDT 24
Peak memory 222580 kb
Host smart-bee2f236-1058-4f0c-9ef5-607b71a1dc51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900002913 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_nack_txstretch.900002913
Directory /workspace/14.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/14.i2c_target_perf.3685590998
Short name T82
Test name
Test status
Simulation time 1686313799 ps
CPU time 5.77 seconds
Started Jul 28 05:03:43 PM PDT 24
Finished Jul 28 05:03:49 PM PDT 24
Peak memory 222344 kb
Host smart-cce62dfe-d517-4a2e-8479-61f76659af0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685590998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.3685590998
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.1735922184
Short name T1565
Test name
Test status
Simulation time 5507634611 ps
CPU time 2.16 seconds
Started Jul 28 05:04:00 PM PDT 24
Finished Jul 28 05:04:02 PM PDT 24
Peak memory 205776 kb
Host smart-eae459c9-ba7d-472a-8074-b6105061ceac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735922184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.1735922184
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2867468551
Short name T582
Test name
Test status
Simulation time 728208032 ps
CPU time 22.2 seconds
Started Jul 28 05:03:55 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 214120 kb
Host smart-41ea7772-de55-445d-9002-b46f03780d3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867468551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2867468551
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.365964936
Short name T510
Test name
Test status
Simulation time 63805033235 ps
CPU time 3560.08 seconds
Started Jul 28 05:04:06 PM PDT 24
Finished Jul 28 06:03:27 PM PDT 24
Peak memory 9941348 kb
Host smart-e2700292-b049-4ff8-96ad-de99512486e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365964936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.i2c_target_stress_all.365964936
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.216043300
Short name T1322
Test name
Test status
Simulation time 1062698283 ps
CPU time 19.29 seconds
Started Jul 28 05:04:05 PM PDT 24
Finished Jul 28 05:04:24 PM PDT 24
Peak memory 222196 kb
Host smart-12d915d4-ce14-403e-ab2a-717336abb0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216043300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.216043300
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1951737042
Short name T984
Test name
Test status
Simulation time 55602318774 ps
CPU time 1645.44 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:31:11 PM PDT 24
Peak memory 8422964 kb
Host smart-3523e471-c5ad-46d7-830c-4e05f1fbd11e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951737042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1951737042
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3867272769
Short name T965
Test name
Test status
Simulation time 2891518796 ps
CPU time 11.25 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:03:59 PM PDT 24
Peak memory 240412 kb
Host smart-2bfe1259-3202-47e5-8de1-a4fd0bec649d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867272769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3867272769
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2469650502
Short name T928
Test name
Test status
Simulation time 1085268160 ps
CPU time 6.09 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:48 PM PDT 24
Peak memory 214076 kb
Host smart-9559d655-4eff-4c44-a76f-c01a848d85c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469650502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2469650502
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.1531410761
Short name T1230
Test name
Test status
Simulation time 145946450 ps
CPU time 3 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:03:55 PM PDT 24
Peak memory 206232 kb
Host smart-5d3fb91b-73d5-4124-a827-14178cd7bfbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531410761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.1531410761
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3933715028
Short name T541
Test name
Test status
Simulation time 181333328 ps
CPU time 1.67 seconds
Started Jul 28 05:03:51 PM PDT 24
Finished Jul 28 05:03:53 PM PDT 24
Peak memory 222180 kb
Host smart-2c2cd781-0dc5-4ab1-b142-3b6b55ec85ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933715028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3933715028
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2890152819
Short name T350
Test name
Test status
Simulation time 329394914 ps
CPU time 17.18 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:04:09 PM PDT 24
Peak memory 274620 kb
Host smart-e60192e7-106e-4f86-88ca-10b0d519d720
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890152819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2890152819
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.2895554155
Short name T43
Test name
Test status
Simulation time 3924317890 ps
CPU time 69.39 seconds
Started Jul 28 05:03:56 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 663848 kb
Host smart-ea81b021-e3b7-475d-8cf3-791dedde1ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895554155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2895554155
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3404623722
Short name T1538
Test name
Test status
Simulation time 10208628886 ps
CPU time 177.16 seconds
Started Jul 28 05:04:05 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 746040 kb
Host smart-efdad85d-5499-4378-b33c-f443256dc680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404623722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3404623722
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.187928181
Short name T1710
Test name
Test status
Simulation time 93694621 ps
CPU time 0.91 seconds
Started Jul 28 05:03:54 PM PDT 24
Finished Jul 28 05:03:56 PM PDT 24
Peak memory 205488 kb
Host smart-9bc5ad2d-c573-475a-83ad-5a3b48c82971
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187928181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.187928181
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2867457031
Short name T374
Test name
Test status
Simulation time 182803227 ps
CPU time 3.84 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:03:54 PM PDT 24
Peak memory 205960 kb
Host smart-71470702-5420-4921-805f-cac3b246be36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867457031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2867457031
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.4158883026
Short name T371
Test name
Test status
Simulation time 9151919855 ps
CPU time 322.76 seconds
Started Jul 28 05:03:47 PM PDT 24
Finished Jul 28 05:09:10 PM PDT 24
Peak memory 1324296 kb
Host smart-934bdf8b-75ad-4643-85b9-1285ae08710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158883026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.4158883026
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2921861257
Short name T263
Test name
Test status
Simulation time 924073027 ps
CPU time 38.46 seconds
Started Jul 28 05:03:57 PM PDT 24
Finished Jul 28 05:04:35 PM PDT 24
Peak memory 205744 kb
Host smart-b6928440-308c-44b7-90b9-717a1370f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921861257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2921861257
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2055474197
Short name T1696
Test name
Test status
Simulation time 354680170 ps
CPU time 2.26 seconds
Started Jul 28 05:03:47 PM PDT 24
Finished Jul 28 05:03:50 PM PDT 24
Peak memory 213972 kb
Host smart-c71d36bd-0bf3-4c83-9d8d-c88f8f89528a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055474197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2055474197
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1632135646
Short name T972
Test name
Test status
Simulation time 58594498 ps
CPU time 0.66 seconds
Started Jul 28 05:03:53 PM PDT 24
Finished Jul 28 05:03:54 PM PDT 24
Peak memory 205496 kb
Host smart-a7008454-e6bb-4c5c-bff2-a9447a6c6793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632135646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1632135646
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.352727920
Short name T381
Test name
Test status
Simulation time 12140040066 ps
CPU time 234.06 seconds
Started Jul 28 05:03:55 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 765960 kb
Host smart-06f0791b-28aa-47d1-b694-c7a6a5f475ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352727920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.352727920
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.2388234710
Short name T416
Test name
Test status
Simulation time 5840641799 ps
CPU time 182.5 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:06:45 PM PDT 24
Peak memory 1252308 kb
Host smart-bfa8b01a-ed17-435b-84aa-963babad136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388234710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.2388234710
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1064903421
Short name T291
Test name
Test status
Simulation time 2087750798 ps
CPU time 92.79 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:05:21 PM PDT 24
Peak memory 296420 kb
Host smart-a91e6aa3-0cfb-4005-9f18-83c27573475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064903421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1064903421
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3257713464
Short name T438
Test name
Test status
Simulation time 3956016419 ps
CPU time 11.03 seconds
Started Jul 28 05:03:56 PM PDT 24
Finished Jul 28 05:04:07 PM PDT 24
Peak memory 215120 kb
Host smart-672578d6-a0f1-4c1e-a972-67f9fdd77a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257713464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3257713464
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.837336303
Short name T1494
Test name
Test status
Simulation time 691005739 ps
CPU time 4.14 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:03:50 PM PDT 24
Peak memory 217344 kb
Host smart-86bdb6f6-1901-4f97-a279-a66bb6368a1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837336303 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.837336303
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3599335837
Short name T1341
Test name
Test status
Simulation time 1532142030 ps
CPU time 1.03 seconds
Started Jul 28 05:03:55 PM PDT 24
Finished Jul 28 05:03:56 PM PDT 24
Peak memory 205796 kb
Host smart-6b24a9b2-37df-4744-a337-ab0e7097af4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599335837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3599335837
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2358396506
Short name T318
Test name
Test status
Simulation time 256296988 ps
CPU time 1.4 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:03:53 PM PDT 24
Peak memory 205792 kb
Host smart-5280e0a7-f212-4a80-9286-d3aed643037f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358396506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2358396506
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1456466799
Short name T1049
Test name
Test status
Simulation time 2884051145 ps
CPU time 2.36 seconds
Started Jul 28 05:03:49 PM PDT 24
Finished Jul 28 05:03:52 PM PDT 24
Peak memory 205968 kb
Host smart-d0a0bbe9-09a4-409f-93a8-42c7c786b426
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456466799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1456466799
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.1298160206
Short name T1736
Test name
Test status
Simulation time 122781487 ps
CPU time 1.42 seconds
Started Jul 28 05:03:54 PM PDT 24
Finished Jul 28 05:03:55 PM PDT 24
Peak memory 205716 kb
Host smart-a8df37e1-a6d7-47ad-a629-ce429e9e6b37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298160206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.1298160206
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.3866298247
Short name T564
Test name
Test status
Simulation time 1137770030 ps
CPU time 2.81 seconds
Started Jul 28 05:03:58 PM PDT 24
Finished Jul 28 05:04:01 PM PDT 24
Peak memory 214116 kb
Host smart-86c47213-8213-468b-a526-bb1ef79b1c82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866298247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.3866298247
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3674644009
Short name T330
Test name
Test status
Simulation time 767857491 ps
CPU time 5 seconds
Started Jul 28 05:03:45 PM PDT 24
Finished Jul 28 05:03:50 PM PDT 24
Peak memory 219108 kb
Host smart-a52ebb5e-b786-412e-8ebc-3d30dbd94501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674644009 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3674644009
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3400776108
Short name T360
Test name
Test status
Simulation time 13322542978 ps
CPU time 35.93 seconds
Started Jul 28 05:03:54 PM PDT 24
Finished Jul 28 05:04:30 PM PDT 24
Peak memory 875412 kb
Host smart-40a98d45-3746-4fb4-a584-98e31739882c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400776108 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3400776108
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.837483108
Short name T819
Test name
Test status
Simulation time 542048316 ps
CPU time 2.88 seconds
Started Jul 28 05:03:55 PM PDT 24
Finished Jul 28 05:03:58 PM PDT 24
Peak memory 214092 kb
Host smart-00edf419-e51d-409a-9f7e-cbac16214cc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837483108 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_nack_acqfull.837483108
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.927867272
Short name T1743
Test name
Test status
Simulation time 2158438962 ps
CPU time 2.93 seconds
Started Jul 28 05:04:06 PM PDT 24
Finished Jul 28 05:04:15 PM PDT 24
Peak memory 206048 kb
Host smart-5dac9737-1ab7-4b83-92f8-e837dd7fab74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927867272 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.927867272
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.2692043561
Short name T829
Test name
Test status
Simulation time 1303725832 ps
CPU time 4.38 seconds
Started Jul 28 05:03:57 PM PDT 24
Finished Jul 28 05:04:02 PM PDT 24
Peak memory 214148 kb
Host smart-c233cb1f-97b3-48fb-b4ef-df5d74d94e33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692043561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.2692043561
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.1214657000
Short name T1543
Test name
Test status
Simulation time 1553683555 ps
CPU time 2.26 seconds
Started Jul 28 05:03:55 PM PDT 24
Finished Jul 28 05:03:58 PM PDT 24
Peak memory 205720 kb
Host smart-645414dd-2e15-4c54-97a6-ce5fa286a823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214657000 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.1214657000
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3418082788
Short name T619
Test name
Test status
Simulation time 788429825 ps
CPU time 11.69 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:04:00 PM PDT 24
Peak memory 214204 kb
Host smart-25c47fee-9860-4609-b4e4-b5ace5316488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418082788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3418082788
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.1816302497
Short name T242
Test name
Test status
Simulation time 31382134106 ps
CPU time 511.17 seconds
Started Jul 28 05:03:47 PM PDT 24
Finished Jul 28 05:12:19 PM PDT 24
Peak memory 4103840 kb
Host smart-bb04ac4d-198a-4006-bb07-464dd1c877e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816302497 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.1816302497
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.194823570
Short name T1748
Test name
Test status
Simulation time 2108495548 ps
CPU time 44.22 seconds
Started Jul 28 05:03:47 PM PDT 24
Finished Jul 28 05:04:31 PM PDT 24
Peak memory 214168 kb
Host smart-55fa2d97-115c-4ade-a78a-ed0c798732c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194823570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.194823570
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2018029922
Short name T1660
Test name
Test status
Simulation time 12076963105 ps
CPU time 7.36 seconds
Started Jul 28 05:04:09 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 206032 kb
Host smart-9e500564-2813-4798-9ae7-064995948079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018029922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2018029922
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2779637615
Short name T1026
Test name
Test status
Simulation time 2308919910 ps
CPU time 36.61 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:04:26 PM PDT 24
Peak memory 715032 kb
Host smart-f2f79c37-a836-4467-af26-8add1e62fe4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779637615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2779637615
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.1320944816
Short name T1488
Test name
Test status
Simulation time 253309062 ps
CPU time 3.1 seconds
Started Jul 28 05:03:59 PM PDT 24
Finished Jul 28 05:04:02 PM PDT 24
Peak memory 205896 kb
Host smart-b4f1dd24-26f6-4ae4-b94e-b5fead4bf71d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320944816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.1320944816
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.495855299
Short name T1406
Test name
Test status
Simulation time 27911292 ps
CPU time 0.63 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:03:52 PM PDT 24
Peak memory 204880 kb
Host smart-7a93a873-5abf-4431-94ec-2c4bd0f6eae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495855299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.495855299
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.254409645
Short name T476
Test name
Test status
Simulation time 84455328 ps
CPU time 1.56 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 213932 kb
Host smart-5aa4ded2-fe22-492e-a139-7f34626595af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254409645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.254409645
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.145852582
Short name T856
Test name
Test status
Simulation time 484061575 ps
CPU time 5.24 seconds
Started Jul 28 05:04:00 PM PDT 24
Finished Jul 28 05:04:05 PM PDT 24
Peak memory 253636 kb
Host smart-d8023bf1-b598-4b0b-8d9d-2b47e85ec1dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145852582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.145852582
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3144733151
Short name T356
Test name
Test status
Simulation time 2773281098 ps
CPU time 83.34 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:05:39 PM PDT 24
Peak memory 573168 kb
Host smart-0ef6debc-d85e-4955-85d7-62f8a7ed4433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144733151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3144733151
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.4289872510
Short name T788
Test name
Test status
Simulation time 10760979411 ps
CPU time 73.87 seconds
Started Jul 28 05:03:53 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 614408 kb
Host smart-36c1e649-bea8-4499-8f6f-666cbb996ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289872510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.4289872510
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3553647473
Short name T245
Test name
Test status
Simulation time 359319098 ps
CPU time 1.23 seconds
Started Jul 28 05:03:54 PM PDT 24
Finished Jul 28 05:03:55 PM PDT 24
Peak memory 205384 kb
Host smart-841e3b18-6957-41f6-b28c-8822f31f2a8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553647473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3553647473
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.1815181691
Short name T878
Test name
Test status
Simulation time 716198341 ps
CPU time 3.73 seconds
Started Jul 28 05:04:02 PM PDT 24
Finished Jul 28 05:04:11 PM PDT 24
Peak memory 205700 kb
Host smart-54791228-7ade-4247-a2d9-04f94159f236
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815181691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.1815181691
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.110412295
Short name T760
Test name
Test status
Simulation time 3610717911 ps
CPU time 233.66 seconds
Started Jul 28 05:03:48 PM PDT 24
Finished Jul 28 05:07:42 PM PDT 24
Peak memory 1000500 kb
Host smart-781d4c6a-40f3-4951-af16-8a115533689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110412295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.110412295
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.786172413
Short name T1134
Test name
Test status
Simulation time 311947074 ps
CPU time 13.25 seconds
Started Jul 28 05:04:19 PM PDT 24
Finished Jul 28 05:04:32 PM PDT 24
Peak memory 205712 kb
Host smart-158824dd-732a-4290-ab01-bc29e8102c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786172413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.786172413
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1930820873
Short name T1515
Test name
Test status
Simulation time 80425385 ps
CPU time 1.53 seconds
Started Jul 28 05:04:01 PM PDT 24
Finished Jul 28 05:04:03 PM PDT 24
Peak memory 217936 kb
Host smart-acadcc53-6ca6-4c7b-86e4-611957282149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930820873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1930820873
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.3374167762
Short name T883
Test name
Test status
Simulation time 155443185 ps
CPU time 0.64 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:03:52 PM PDT 24
Peak memory 205480 kb
Host smart-f25358f7-ba3a-47ac-9c20-399ea4fe8f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374167762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3374167762
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.193190855
Short name T1276
Test name
Test status
Simulation time 3736912102 ps
CPU time 24.25 seconds
Started Jul 28 05:04:03 PM PDT 24
Finished Jul 28 05:04:27 PM PDT 24
Peak memory 322444 kb
Host smart-7183f894-04e6-4727-bd5f-a1d02d889385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193190855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.193190855
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.3741763142
Short name T1070
Test name
Test status
Simulation time 94691550 ps
CPU time 1.22 seconds
Started Jul 28 05:04:06 PM PDT 24
Finished Jul 28 05:04:07 PM PDT 24
Peak memory 206076 kb
Host smart-dae75b1e-859d-4b83-b53a-c98e477846e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741763142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3741763142
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2117493763
Short name T1283
Test name
Test status
Simulation time 1257441039 ps
CPU time 18.96 seconds
Started Jul 28 05:03:51 PM PDT 24
Finished Jul 28 05:04:10 PM PDT 24
Peak memory 299784 kb
Host smart-cda27d82-89c6-4fb9-9f2f-9e14fc78a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117493763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2117493763
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.2335666728
Short name T292
Test name
Test status
Simulation time 5991736792 ps
CPU time 26.9 seconds
Started Jul 28 05:03:57 PM PDT 24
Finished Jul 28 05:04:24 PM PDT 24
Peak memory 214056 kb
Host smart-d3502796-45d0-45cf-82d2-8a4756b358bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335666728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2335666728
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3072550913
Short name T440
Test name
Test status
Simulation time 2529160758 ps
CPU time 6.05 seconds
Started Jul 28 05:04:04 PM PDT 24
Finished Jul 28 05:04:10 PM PDT 24
Peak memory 214996 kb
Host smart-3851a67b-7311-4914-95a0-b91744caf087
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072550913 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3072550913
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.332173780
Short name T932
Test name
Test status
Simulation time 129893996 ps
CPU time 0.93 seconds
Started Jul 28 05:03:46 PM PDT 24
Finished Jul 28 05:03:47 PM PDT 24
Peak memory 205724 kb
Host smart-1724fff3-4369-45cd-ba17-9efbbbd71687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332173780 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.332173780
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.837331468
Short name T1453
Test name
Test status
Simulation time 471780439 ps
CPU time 1.2 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 205880 kb
Host smart-94a397ec-84e9-4c81-a25c-664d2aa8c865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837331468 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.837331468
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.2753604322
Short name T512
Test name
Test status
Simulation time 283994472 ps
CPU time 1.18 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:14 PM PDT 24
Peak memory 205716 kb
Host smart-29593730-be73-44c2-8ac4-e25e9474de19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753604322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.2753604322
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.4119502416
Short name T657
Test name
Test status
Simulation time 834932992 ps
CPU time 1.41 seconds
Started Jul 28 05:04:11 PM PDT 24
Finished Jul 28 05:04:13 PM PDT 24
Peak memory 205740 kb
Host smart-a40e995e-0425-4f8f-9d7c-029214967b0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119502416 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.4119502416
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3322766931
Short name T449
Test name
Test status
Simulation time 1922621723 ps
CPU time 5.31 seconds
Started Jul 28 05:04:07 PM PDT 24
Finished Jul 28 05:04:12 PM PDT 24
Peak memory 214128 kb
Host smart-ee4ff9ba-25bb-4098-a15b-c4b478a629dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322766931 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3322766931
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.1714193696
Short name T895
Test name
Test status
Simulation time 14746533991 ps
CPU time 107.26 seconds
Started Jul 28 05:03:50 PM PDT 24
Finished Jul 28 05:05:37 PM PDT 24
Peak memory 1844468 kb
Host smart-7ca00ea7-ac76-4878-be5f-812665959c32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714193696 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1714193696
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.3904341562
Short name T754
Test name
Test status
Simulation time 511014177 ps
CPU time 2.79 seconds
Started Jul 28 05:04:09 PM PDT 24
Finished Jul 28 05:04:12 PM PDT 24
Peak memory 214184 kb
Host smart-608a1897-e9e8-4427-a0a0-e064144ea23f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904341562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_nack_acqfull.3904341562
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.2880580724
Short name T70
Test name
Test status
Simulation time 2258142165 ps
CPU time 2.54 seconds
Started Jul 28 05:04:12 PM PDT 24
Finished Jul 28 05:04:15 PM PDT 24
Peak memory 206084 kb
Host smart-c1f53504-1722-4118-ab4f-c594bdd47d8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880580724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.2880580724
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_txstretch.1774837375
Short name T1416
Test name
Test status
Simulation time 749486010 ps
CPU time 1.44 seconds
Started Jul 28 05:04:05 PM PDT 24
Finished Jul 28 05:04:06 PM PDT 24
Peak memory 222536 kb
Host smart-7b32f8c4-15c4-4d55-a8db-225bea6c643d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774837375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_nack_txstretch.1774837375
Directory /workspace/16.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/16.i2c_target_perf.1526793235
Short name T1658
Test name
Test status
Simulation time 3788220009 ps
CPU time 5.92 seconds
Started Jul 28 05:03:49 PM PDT 24
Finished Jul 28 05:03:55 PM PDT 24
Peak memory 222352 kb
Host smart-10162e25-2f6c-4c3d-b6d5-f9fca53a3a3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526793235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.1526793235
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.2490538226
Short name T1731
Test name
Test status
Simulation time 986175191 ps
CPU time 2.49 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:04:12 PM PDT 24
Peak memory 205732 kb
Host smart-52e57956-6bc4-49a7-9f67-9c1146a10f65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490538226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.2490538226
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.992073948
Short name T864
Test name
Test status
Simulation time 2405933159 ps
CPU time 39.13 seconds
Started Jul 28 05:04:04 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 214232 kb
Host smart-ebaf5d43-b99f-4e31-904f-3706fd7ab19b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992073948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.992073948
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1776550726
Short name T1194
Test name
Test status
Simulation time 26422263818 ps
CPU time 29.94 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:04:38 PM PDT 24
Peak memory 249248 kb
Host smart-fe9e635f-15f2-4903-b7cd-4aee81839ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776550726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1776550726
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3883024245
Short name T355
Test name
Test status
Simulation time 15163593577 ps
CPU time 29.51 seconds
Started Jul 28 05:03:57 PM PDT 24
Finished Jul 28 05:04:27 PM PDT 24
Peak memory 206068 kb
Host smart-6809d096-e60c-4e33-8dac-3e53c9e39663
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883024245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3883024245
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.2021621321
Short name T1486
Test name
Test status
Simulation time 1150128539 ps
CPU time 3.62 seconds
Started Jul 28 05:03:57 PM PDT 24
Finished Jul 28 05:04:01 PM PDT 24
Peak memory 214956 kb
Host smart-1364438c-205a-4ff4-94f5-483092b16347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021621321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.2021621321
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2182957845
Short name T1392
Test name
Test status
Simulation time 6407626888 ps
CPU time 6.9 seconds
Started Jul 28 05:04:23 PM PDT 24
Finished Jul 28 05:04:30 PM PDT 24
Peak memory 214200 kb
Host smart-2f12827d-6a48-45d2-8d11-5c9c7f08266d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182957845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2182957845
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.1442555430
Short name T1698
Test name
Test status
Simulation time 140841580 ps
CPU time 2.82 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:04:13 PM PDT 24
Peak memory 205952 kb
Host smart-74bc7540-a4d2-4871-ba36-3edce0d75db9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442555430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.1442555430
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2274716209
Short name T1108
Test name
Test status
Simulation time 29106593 ps
CPU time 0.6 seconds
Started Jul 28 05:03:54 PM PDT 24
Finished Jul 28 05:03:55 PM PDT 24
Peak memory 204864 kb
Host smart-91b0e724-e916-4af7-a520-852e3e766910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274716209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2274716209
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.1257630803
Short name T1476
Test name
Test status
Simulation time 132058996 ps
CPU time 2 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:04:10 PM PDT 24
Peak memory 213992 kb
Host smart-fbd3c307-4d9a-432e-af82-60937caf0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257630803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1257630803
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.3457341855
Short name T519
Test name
Test status
Simulation time 1470641162 ps
CPU time 17.81 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:32 PM PDT 24
Peak memory 277660 kb
Host smart-cefc41ff-3515-4152-bd31-e9ccaa1d3421
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457341855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.3457341855
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1572013387
Short name T1362
Test name
Test status
Simulation time 5785651308 ps
CPU time 200.67 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:07:13 PM PDT 24
Peak memory 712364 kb
Host smart-10c95df7-479c-49ce-886e-6f74916c49a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572013387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1572013387
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3876503690
Short name T1656
Test name
Test status
Simulation time 8827901125 ps
CPU time 69.78 seconds
Started Jul 28 05:04:21 PM PDT 24
Finished Jul 28 05:05:30 PM PDT 24
Peak memory 714884 kb
Host smart-0ea35763-9426-4cff-9e6f-a731a13e6270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876503690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3876503690
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2500287057
Short name T243
Test name
Test status
Simulation time 703026747 ps
CPU time 1.07 seconds
Started Jul 28 05:03:54 PM PDT 24
Finished Jul 28 05:03:56 PM PDT 24
Peak memory 205456 kb
Host smart-8a0c5988-e0f7-44f0-8f0e-420158b04e51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500287057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2500287057
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1229250818
Short name T78
Test name
Test status
Simulation time 158697848 ps
CPU time 3.6 seconds
Started Jul 28 05:04:05 PM PDT 24
Finished Jul 28 05:04:09 PM PDT 24
Peak memory 205692 kb
Host smart-446e498e-f88a-4624-afb2-50346ffd8070
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229250818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1229250818
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2730141310
Short name T105
Test name
Test status
Simulation time 5737167297 ps
CPU time 157.62 seconds
Started Jul 28 05:03:52 PM PDT 24
Finished Jul 28 05:06:30 PM PDT 24
Peak memory 1609984 kb
Host smart-a8139c86-c4c8-42ff-bb86-e34c0c40aae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730141310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2730141310
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.3508337669
Short name T1591
Test name
Test status
Simulation time 591944666 ps
CPU time 6.98 seconds
Started Jul 28 05:04:06 PM PDT 24
Finished Jul 28 05:04:13 PM PDT 24
Peak memory 205816 kb
Host smart-30e9217c-a7e9-4d3e-b49f-41713013a211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508337669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3508337669
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.638942990
Short name T767
Test name
Test status
Simulation time 110490124 ps
CPU time 0.64 seconds
Started Jul 28 05:04:07 PM PDT 24
Finished Jul 28 05:04:08 PM PDT 24
Peak memory 205392 kb
Host smart-53bad2f5-a022-4d3e-903a-83ba17c51aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638942990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.638942990
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1180473850
Short name T405
Test name
Test status
Simulation time 18312142798 ps
CPU time 244.53 seconds
Started Jul 28 05:04:12 PM PDT 24
Finished Jul 28 05:08:17 PM PDT 24
Peak memory 1506580 kb
Host smart-8076d729-7418-47f5-8f22-1f38b7f81212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180473850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1180473850
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.2565230972
Short name T1666
Test name
Test status
Simulation time 5822641573 ps
CPU time 218.38 seconds
Started Jul 28 05:03:57 PM PDT 24
Finished Jul 28 05:07:36 PM PDT 24
Peak memory 205904 kb
Host smart-2bea49d8-b53e-49c5-8e69-7ce13dd39f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565230972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.2565230972
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1753206880
Short name T1009
Test name
Test status
Simulation time 1233365999 ps
CPU time 20.54 seconds
Started Jul 28 05:03:51 PM PDT 24
Finished Jul 28 05:04:12 PM PDT 24
Peak memory 270740 kb
Host smart-93914d7b-d7e8-426c-8e2c-a37cedcf0c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753206880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1753206880
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.126946272
Short name T287
Test name
Test status
Simulation time 64808010160 ps
CPU time 1473.67 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:28:42 PM PDT 24
Peak memory 3364888 kb
Host smart-74c35bd5-fbee-4e7f-9f5a-e91b3095e084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126946272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.126946272
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1949870720
Short name T758
Test name
Test status
Simulation time 15028147933 ps
CPU time 12.39 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:27 PM PDT 24
Peak memory 222236 kb
Host smart-c212ecbc-e814-4618-b2ba-2adfa7ce2d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949870720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1949870720
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2884774958
Short name T1346
Test name
Test status
Simulation time 2505059870 ps
CPU time 6.2 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:21 PM PDT 24
Peak memory 218940 kb
Host smart-cba293be-e031-485c-ae37-a0d04ab5dee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884774958 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2884774958
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3721475744
Short name T1739
Test name
Test status
Simulation time 539119663 ps
CPU time 1.21 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:15 PM PDT 24
Peak memory 205952 kb
Host smart-a4788b01-f2eb-4155-bf26-de4556ac28a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721475744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3721475744
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.4070510718
Short name T919
Test name
Test status
Simulation time 489549823 ps
CPU time 2.67 seconds
Started Jul 28 05:04:01 PM PDT 24
Finished Jul 28 05:04:04 PM PDT 24
Peak memory 205980 kb
Host smart-bd9b81f5-71a9-4bc0-afdd-0d1e0b457459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070510718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.4070510718
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.298514403
Short name T1004
Test name
Test status
Simulation time 2802687379 ps
CPU time 1.58 seconds
Started Jul 28 05:04:05 PM PDT 24
Finished Jul 28 05:04:07 PM PDT 24
Peak memory 205828 kb
Host smart-467094cf-2f4b-467f-af60-08f00dc3e3c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298514403 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.298514403
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.417471237
Short name T1423
Test name
Test status
Simulation time 1452459878 ps
CPU time 3.44 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 222208 kb
Host smart-6e0728db-94f7-4e2b-9276-12102fd07fb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417471237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.417471237
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.3228825487
Short name T312
Test name
Test status
Simulation time 20564931408 ps
CPU time 64.15 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:05:13 PM PDT 24
Peak memory 956728 kb
Host smart-b790bb0a-8904-4537-97d3-c436c2286a21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228825487 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.3228825487
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.1166905972
Short name T1617
Test name
Test status
Simulation time 2702103960 ps
CPU time 2.69 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:19 PM PDT 24
Peak memory 214168 kb
Host smart-76b7dbe2-48ef-4f01-ac90-e08de71fd110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166905972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.1166905972
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.2764301365
Short name T726
Test name
Test status
Simulation time 3800185157 ps
CPU time 2.76 seconds
Started Jul 28 05:04:12 PM PDT 24
Finished Jul 28 05:04:15 PM PDT 24
Peak memory 206064 kb
Host smart-80325ac5-5592-4055-abf7-41005c8dbb16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764301365 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.2764301365
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.2835168403
Short name T361
Test name
Test status
Simulation time 5660398332 ps
CPU time 6.34 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 223312 kb
Host smart-525aaa67-f1db-4998-9e15-93478d35b71d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835168403 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.2835168403
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.4174458577
Short name T336
Test name
Test status
Simulation time 439911168 ps
CPU time 2.16 seconds
Started Jul 28 05:04:12 PM PDT 24
Finished Jul 28 05:04:14 PM PDT 24
Peak memory 205740 kb
Host smart-8093a63a-da8b-4705-b65b-570c44f14f4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174458577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_smbus_maxlen.4174458577
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2260995531
Short name T1231
Test name
Test status
Simulation time 2725984315 ps
CPU time 18.07 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:04:27 PM PDT 24
Peak memory 222500 kb
Host smart-1a577d74-a419-4d46-9496-5204f842b840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260995531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2260995531
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.252238092
Short name T1604
Test name
Test status
Simulation time 4377511138 ps
CPU time 18.81 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:35 PM PDT 24
Peak memory 222280 kb
Host smart-e6ef0788-97e9-404e-ab37-c7eb2e4c2bcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252238092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.252238092
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3156169878
Short name T1227
Test name
Test status
Simulation time 48054767124 ps
CPU time 1317.03 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:26:11 PM PDT 24
Peak memory 7017592 kb
Host smart-d2907378-b079-4377-85e5-3b11bce15e9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156169878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3156169878
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3179540303
Short name T825
Test name
Test status
Simulation time 3133151587 ps
CPU time 32.32 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 358024 kb
Host smart-2a44eb01-598f-4482-9bf7-fea8115f2a4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179540303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3179540303
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.2711641119
Short name T1703
Test name
Test status
Simulation time 4743611814 ps
CPU time 7.14 seconds
Started Jul 28 05:04:09 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 214196 kb
Host smart-e6eba4c8-ea89-497a-a0bb-8df60e53742f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711641119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.2711641119
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.3273312004
Short name T1198
Test name
Test status
Simulation time 165617191 ps
CPU time 2.93 seconds
Started Jul 28 05:03:55 PM PDT 24
Finished Jul 28 05:03:58 PM PDT 24
Peak memory 205972 kb
Host smart-e97b57dd-87c1-4994-b971-3302513d3bb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273312004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.3273312004
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.65302401
Short name T379
Test name
Test status
Simulation time 23768020 ps
CPU time 0.67 seconds
Started Jul 28 05:04:24 PM PDT 24
Finished Jul 28 05:04:25 PM PDT 24
Peak memory 204896 kb
Host smart-b5fb266c-c66c-43f8-aecc-5fff931b9fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65302401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.65302401
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3753143286
Short name T546
Test name
Test status
Simulation time 54516039 ps
CPU time 1.19 seconds
Started Jul 28 05:03:53 PM PDT 24
Finished Jul 28 05:03:54 PM PDT 24
Peak memory 214052 kb
Host smart-8414dba5-981e-440e-ab60-23a10bf9c848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753143286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3753143286
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.940278193
Short name T1519
Test name
Test status
Simulation time 460434300 ps
CPU time 9.17 seconds
Started Jul 28 05:04:20 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 303728 kb
Host smart-fa5fd333-f1a3-4700-9fe9-e6ed4fac05f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940278193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.940278193
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.4279268604
Short name T1605
Test name
Test status
Simulation time 3291758569 ps
CPU time 115.21 seconds
Started Jul 28 05:04:11 PM PDT 24
Finished Jul 28 05:06:06 PM PDT 24
Peak memory 749568 kb
Host smart-552e948a-06d1-415c-afcd-d1acaac6fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279268604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.4279268604
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.240323518
Short name T976
Test name
Test status
Simulation time 7367229094 ps
CPU time 58.04 seconds
Started Jul 28 05:03:59 PM PDT 24
Finished Jul 28 05:04:58 PM PDT 24
Peak memory 619868 kb
Host smart-1433b023-7476-46b6-bc3b-66eab21f243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240323518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.240323518
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2278225761
Short name T1001
Test name
Test status
Simulation time 202930206 ps
CPU time 0.91 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:04:11 PM PDT 24
Peak memory 205464 kb
Host smart-b88e5410-57c6-4a75-b12c-64fc106587f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278225761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2278225761
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.924464850
Short name T1462
Test name
Test status
Simulation time 154104403 ps
CPU time 3.35 seconds
Started Jul 28 05:04:01 PM PDT 24
Finished Jul 28 05:04:05 PM PDT 24
Peak memory 205708 kb
Host smart-f1504e36-3a8d-4924-93c2-47776143970d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924464850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
924464850
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3615155953
Short name T1359
Test name
Test status
Simulation time 3532232306 ps
CPU time 96.36 seconds
Started Jul 28 05:04:21 PM PDT 24
Finished Jul 28 05:05:58 PM PDT 24
Peak memory 1043484 kb
Host smart-36c0f7b8-b791-4b42-8076-a086437b53a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615155953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3615155953
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.3985131028
Short name T74
Test name
Test status
Simulation time 260508281 ps
CPU time 1.12 seconds
Started Jul 28 05:04:06 PM PDT 24
Finished Jul 28 05:04:07 PM PDT 24
Peak memory 205792 kb
Host smart-a5d2e89b-a61b-4e3b-8445-bff9d02f6f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985131028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3985131028
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2503383096
Short name T663
Test name
Test status
Simulation time 26384389 ps
CPU time 0.67 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:16 PM PDT 24
Peak memory 205440 kb
Host smart-4451f0e5-d707-4509-b747-2e1919a6af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503383096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2503383096
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1190213481
Short name T1356
Test name
Test status
Simulation time 432642303 ps
CPU time 2.4 seconds
Started Jul 28 05:04:01 PM PDT 24
Finished Jul 28 05:04:04 PM PDT 24
Peak memory 230280 kb
Host smart-5eb3f1ac-552b-4ee8-b6ff-7cd44428a4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190213481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1190213481
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.3866812790
Short name T217
Test name
Test status
Simulation time 772507026 ps
CPU time 17.85 seconds
Started Jul 28 05:03:53 PM PDT 24
Finished Jul 28 05:04:11 PM PDT 24
Peak memory 213824 kb
Host smart-ecbeae83-6971-468a-9218-449673948947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866812790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.3866812790
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.188687426
Short name T1481
Test name
Test status
Simulation time 5562707600 ps
CPU time 63.05 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:05:17 PM PDT 24
Peak memory 328544 kb
Host smart-e8f2c78d-7f23-4cd4-8d61-06adaff04ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188687426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.188687426
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1618031373
Short name T1197
Test name
Test status
Simulation time 632751878 ps
CPU time 26.78 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:04:35 PM PDT 24
Peak memory 213920 kb
Host smart-ada11e9b-e769-4514-a330-a8a3e7c6d71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618031373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1618031373
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2364291477
Short name T410
Test name
Test status
Simulation time 2114465584 ps
CPU time 5.06 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:04:16 PM PDT 24
Peak memory 214036 kb
Host smart-f997c97c-7922-4c51-a6c1-f10c1ce46ac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364291477 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2364291477
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1723493517
Short name T689
Test name
Test status
Simulation time 262253840 ps
CPU time 0.8 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:04:09 PM PDT 24
Peak memory 205724 kb
Host smart-67882574-0c64-4e52-bc3a-68dc84513a33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723493517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1723493517
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3751708165
Short name T9
Test name
Test status
Simulation time 155532460 ps
CPU time 1.1 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:04:11 PM PDT 24
Peak memory 205688 kb
Host smart-692c6755-af21-40f9-9a14-4c1bb8bc7867
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751708165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3751708165
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.68686417
Short name T1408
Test name
Test status
Simulation time 1569830285 ps
CPU time 2.36 seconds
Started Jul 28 05:04:09 PM PDT 24
Finished Jul 28 05:04:11 PM PDT 24
Peak memory 205916 kb
Host smart-3f160fb8-0c57-413b-b4aa-3749e82c13de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68686417 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.68686417
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.3792657010
Short name T396
Test name
Test status
Simulation time 135500037 ps
CPU time 1.23 seconds
Started Jul 28 05:04:23 PM PDT 24
Finished Jul 28 05:04:25 PM PDT 24
Peak memory 205716 kb
Host smart-2f127a21-b4ac-46de-8227-6ddf50135aaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792657010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.3792657010
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2777846416
Short name T1584
Test name
Test status
Simulation time 4344806235 ps
CPU time 5.85 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:23 PM PDT 24
Peak memory 222440 kb
Host smart-9ed73d6b-03b2-4810-96c4-c40a8d81aad1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777846416 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2777846416
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2735215755
Short name T1641
Test name
Test status
Simulation time 7946359282 ps
CPU time 80.94 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 1736020 kb
Host smart-d5d99943-d6ed-40e8-b121-e58396911b2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735215755 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2735215755
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.2817435259
Short name T912
Test name
Test status
Simulation time 1039702777 ps
CPU time 2.59 seconds
Started Jul 28 05:04:27 PM PDT 24
Finished Jul 28 05:04:30 PM PDT 24
Peak memory 214080 kb
Host smart-ca1fba92-51ef-4719-a2e5-7745e4c9bd74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817435259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.2817435259
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.3323123556
Short name T1451
Test name
Test status
Simulation time 525190882 ps
CPU time 2.21 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:04:10 PM PDT 24
Peak memory 205892 kb
Host smart-faddd510-5b86-436b-ae5e-98bea5f4bd8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323123556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.3323123556
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_txstretch.1541420691
Short name T1529
Test name
Test status
Simulation time 135878069 ps
CPU time 1.34 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:18 PM PDT 24
Peak memory 223024 kb
Host smart-1780bdd1-6cf9-440f-aa4c-fe7766102eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541420691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_nack_txstretch.1541420691
Directory /workspace/18.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/18.i2c_target_perf.2408490006
Short name T1290
Test name
Test status
Simulation time 1338643131 ps
CPU time 6.5 seconds
Started Jul 28 05:04:22 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 214144 kb
Host smart-e5c5c1a2-65d2-4aae-84cf-09dbc817fa45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408490006 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.2408490006
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.1628514311
Short name T1347
Test name
Test status
Simulation time 1024095073 ps
CPU time 2.23 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 205696 kb
Host smart-1241b2da-7b8c-42cc-af1a-bc795cf0629b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628514311 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_smbus_maxlen.1628514311
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3670107069
Short name T1720
Test name
Test status
Simulation time 3096446550 ps
CPU time 27.12 seconds
Started Jul 28 05:04:06 PM PDT 24
Finished Jul 28 05:04:34 PM PDT 24
Peak memory 214228 kb
Host smart-725310eb-f2db-4541-b25b-465eb1835199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670107069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3670107069
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.1962580412
Short name T1188
Test name
Test status
Simulation time 48892975152 ps
CPU time 104.82 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:05:58 PM PDT 24
Peak memory 743940 kb
Host smart-9ec98e3b-7d68-4316-ba7e-ff54dbe0e2e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962580412 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.1962580412
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3138755280
Short name T850
Test name
Test status
Simulation time 1720349410 ps
CPU time 78.74 seconds
Started Jul 28 05:03:51 PM PDT 24
Finished Jul 28 05:05:10 PM PDT 24
Peak memory 218228 kb
Host smart-330724c0-beee-4dc8-928e-3691515fcf94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138755280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3138755280
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1316492459
Short name T874
Test name
Test status
Simulation time 33048185933 ps
CPU time 40.07 seconds
Started Jul 28 05:04:02 PM PDT 24
Finished Jul 28 05:04:42 PM PDT 24
Peak memory 835516 kb
Host smart-4bba7e4a-bafa-4c3f-88b4-337a4bc2023c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316492459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1316492459
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2023730977
Short name T400
Test name
Test status
Simulation time 3703150273 ps
CPU time 35.32 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:48 PM PDT 24
Peak memory 375832 kb
Host smart-055306e8-25af-4731-a58c-2d2bed944db3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023730977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2023730977
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3656990530
Short name T1056
Test name
Test status
Simulation time 3784987422 ps
CPU time 6.46 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:24 PM PDT 24
Peak memory 222360 kb
Host smart-adb5d0f6-63d7-4af0-a41e-8205e5eb72b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656990530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3656990530
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.461474719
Short name T560
Test name
Test status
Simulation time 59032364 ps
CPU time 1.42 seconds
Started Jul 28 05:04:12 PM PDT 24
Finished Jul 28 05:04:14 PM PDT 24
Peak memory 205928 kb
Host smart-f7cea2df-37c4-46fd-912c-c975aca37bee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461474719 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.461474719
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1088221545
Short name T180
Test name
Test status
Simulation time 21147038 ps
CPU time 0.61 seconds
Started Jul 28 05:04:38 PM PDT 24
Finished Jul 28 05:04:39 PM PDT 24
Peak memory 204772 kb
Host smart-fc9efc37-0d8c-43e6-a5c1-717f94347c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088221545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1088221545
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3971668957
Short name T1241
Test name
Test status
Simulation time 197740708 ps
CPU time 1.51 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:16 PM PDT 24
Peak memory 213996 kb
Host smart-7ae57f13-ba32-4c07-b6db-73cc9cc7d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971668957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3971668957
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1821112410
Short name T1008
Test name
Test status
Simulation time 232235445 ps
CPU time 3.94 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:19 PM PDT 24
Peak memory 235004 kb
Host smart-c90edbe5-37f9-429f-a7f7-846a5d8c1388
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821112410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1821112410
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.296532671
Short name T147
Test name
Test status
Simulation time 4584024036 ps
CPU time 71.53 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:05:22 PM PDT 24
Peak memory 622684 kb
Host smart-d36b1f5a-a2f0-4289-8ae6-b54d6e98029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296532671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.296532671
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.362611065
Short name T1351
Test name
Test status
Simulation time 20721702810 ps
CPU time 53.41 seconds
Started Jul 28 05:04:18 PM PDT 24
Finished Jul 28 05:05:11 PM PDT 24
Peak memory 589832 kb
Host smart-d490d139-51db-42b4-b203-be638ddfe401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362611065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.362611065
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2282860803
Short name T1483
Test name
Test status
Simulation time 459036040 ps
CPU time 1.13 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:21 PM PDT 24
Peak memory 205648 kb
Host smart-870492a3-fb45-4eb7-abde-9d2648eb3477
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282860803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2282860803
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2660989492
Short name T1039
Test name
Test status
Simulation time 238649502 ps
CPU time 6.92 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 205764 kb
Host smart-b4645e86-ccdb-4bc6-b36d-9990f1b6ab4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660989492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2660989492
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1316610990
Short name T423
Test name
Test status
Simulation time 4628237035 ps
CPU time 315.77 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:09:24 PM PDT 24
Peak memory 1303760 kb
Host smart-a873ab82-bce6-4ce7-8b10-13eb9dd6b9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316610990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1316610990
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_override.144274448
Short name T136
Test name
Test status
Simulation time 50581655 ps
CPU time 0.68 seconds
Started Jul 28 05:04:09 PM PDT 24
Finished Jul 28 05:04:10 PM PDT 24
Peak memory 205508 kb
Host smart-da0a3337-6ea7-405d-bbb7-2f1903c0f16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144274448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.144274448
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2160197029
Short name T983
Test name
Test status
Simulation time 15609193548 ps
CPU time 27.35 seconds
Started Jul 28 05:04:09 PM PDT 24
Finished Jul 28 05:04:37 PM PDT 24
Peak memory 498648 kb
Host smart-5ea2f0c1-8df6-48be-b187-038fd506aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160197029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2160197029
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.295387625
Short name T144
Test name
Test status
Simulation time 273163176 ps
CPU time 1.32 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:16 PM PDT 24
Peak memory 205648 kb
Host smart-5deaaa9f-68eb-4b66-907f-7c7cf59835bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295387625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.295387625
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2452596374
Short name T1599
Test name
Test status
Simulation time 1384599336 ps
CPU time 57.43 seconds
Started Jul 28 05:04:05 PM PDT 24
Finished Jul 28 05:05:03 PM PDT 24
Peak memory 341072 kb
Host smart-9f8dd24c-8df9-499f-8843-e91eb2d30e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452596374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2452596374
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3925116828
Short name T844
Test name
Test status
Simulation time 4526478204 ps
CPU time 24.61 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:40 PM PDT 24
Peak memory 214052 kb
Host smart-6653cb4d-945b-4a11-997b-350fefd09e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925116828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3925116828
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3541565025
Short name T1139
Test name
Test status
Simulation time 2375111017 ps
CPU time 6.18 seconds
Started Jul 28 05:04:21 PM PDT 24
Finished Jul 28 05:04:27 PM PDT 24
Peak memory 215092 kb
Host smart-1ebd36ff-7e82-48b0-968e-839085f9e99f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541565025 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3541565025
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3891985891
Short name T145
Test name
Test status
Simulation time 209325531 ps
CPU time 0.84 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:18 PM PDT 24
Peak memory 205664 kb
Host smart-a44eded2-aa98-433e-adb3-9a726319063d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891985891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3891985891
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1884887921
Short name T921
Test name
Test status
Simulation time 282255470 ps
CPU time 1.19 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:16 PM PDT 24
Peak memory 205708 kb
Host smart-8fd127d0-2ec5-43fd-8b4d-d82f1ae2a8c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884887921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1884887921
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.3338396800
Short name T1284
Test name
Test status
Simulation time 1915338424 ps
CPU time 2.38 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 205976 kb
Host smart-8bc69b90-4bc2-4e08-b9c0-2ff5da7a7091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338396800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.3338396800
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.3452220656
Short name T439
Test name
Test status
Simulation time 631869131 ps
CPU time 1.08 seconds
Started Jul 28 05:04:07 PM PDT 24
Finished Jul 28 05:04:13 PM PDT 24
Peak memory 205720 kb
Host smart-64c10143-c48b-416f-9401-5ebfe934e565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452220656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.3452220656
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.3248311181
Short name T777
Test name
Test status
Simulation time 988189265 ps
CPU time 2.15 seconds
Started Jul 28 05:04:18 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 214112 kb
Host smart-e7ee3891-f9a1-442c-96f2-22d5f0e0b36c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248311181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.3248311181
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.3822827429
Short name T569
Test name
Test status
Simulation time 1538978389 ps
CPU time 7.98 seconds
Started Jul 28 05:04:19 PM PDT 24
Finished Jul 28 05:04:27 PM PDT 24
Peak memory 230372 kb
Host smart-403ff175-6872-4ca8-b596-9e634058f812
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822827429 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.3822827429
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.544073513
Short name T1632
Test name
Test status
Simulation time 10422796302 ps
CPU time 8.42 seconds
Started Jul 28 05:04:11 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 263584 kb
Host smart-313d1225-b621-4a42-9d84-5af3c868367c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544073513 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.544073513
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.1965351167
Short name T150
Test name
Test status
Simulation time 623571408 ps
CPU time 3.06 seconds
Started Jul 28 05:04:29 PM PDT 24
Finished Jul 28 05:04:33 PM PDT 24
Peak memory 214148 kb
Host smart-89925a4a-fd82-496c-970a-386238a863b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965351167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_nack_acqfull.1965351167
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.1870204072
Short name T1401
Test name
Test status
Simulation time 2400466862 ps
CPU time 2.64 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:19 PM PDT 24
Peak memory 206056 kb
Host smart-7417f57e-a111-4ea6-9ea1-98847abe6979
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870204072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.1870204072
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_txstretch.1332242532
Short name T1150
Test name
Test status
Simulation time 481504713 ps
CPU time 1.33 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 223104 kb
Host smart-0010dc07-caec-42dd-b3aa-d1e8e6f28e64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332242532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_nack_txstretch.1332242532
Directory /workspace/19.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/19.i2c_target_perf.980984450
Short name T1335
Test name
Test status
Simulation time 2767659176 ps
CPU time 5.19 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:21 PM PDT 24
Peak memory 219968 kb
Host smart-a007b2bf-d1bd-44b6-96b4-53219e730786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980984450 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_perf.980984450
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.1084178290
Short name T1047
Test name
Test status
Simulation time 3405609536 ps
CPU time 2.47 seconds
Started Jul 28 05:04:29 PM PDT 24
Finished Jul 28 05:04:32 PM PDT 24
Peak memory 205824 kb
Host smart-ef06a273-fae4-4107-8d90-926260d1067f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084178290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_smbus_maxlen.1084178290
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.2370308025
Short name T846
Test name
Test status
Simulation time 14923358216 ps
CPU time 20.53 seconds
Started Jul 28 05:04:32 PM PDT 24
Finished Jul 28 05:04:52 PM PDT 24
Peak memory 214220 kb
Host smart-e6caf36a-1d25-4d93-b9d7-f3555d8150bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370308025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.2370308025
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.2732811425
Short name T617
Test name
Test status
Simulation time 44412569489 ps
CPU time 1183.53 seconds
Started Jul 28 05:04:25 PM PDT 24
Finished Jul 28 05:24:09 PM PDT 24
Peak memory 5124012 kb
Host smart-a5151b0b-f7a9-4a02-84ed-0d6ac3f245c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732811425 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.2732811425
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.4002998834
Short name T488
Test name
Test status
Simulation time 3803829713 ps
CPU time 39.31 seconds
Started Jul 28 05:04:20 PM PDT 24
Finished Jul 28 05:04:59 PM PDT 24
Peak memory 214612 kb
Host smart-7dc82a9f-28b6-44ce-bb65-dac7c3259165
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002998834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.4002998834
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2847075943
Short name T428
Test name
Test status
Simulation time 17199320373 ps
CPU time 32.16 seconds
Started Jul 28 05:04:06 PM PDT 24
Finished Jul 28 05:04:38 PM PDT 24
Peak memory 206036 kb
Host smart-78299955-c859-47ee-a9ac-6174b49d74c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847075943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2847075943
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3270220936
Short name T1560
Test name
Test status
Simulation time 1967473803 ps
CPU time 7.41 seconds
Started Jul 28 05:04:18 PM PDT 24
Finished Jul 28 05:04:26 PM PDT 24
Peak memory 214168 kb
Host smart-f7e60f93-57ad-4ecb-bbb1-c10a4e023439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270220936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3270220936
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.3355727387
Short name T130
Test name
Test status
Simulation time 1223677074 ps
CPU time 14.47 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 221524 kb
Host smart-1fa26fbc-f25b-45a4-a82d-6b0b1099b371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355727387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.3355727387
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2638958143
Short name T1095
Test name
Test status
Simulation time 16090503 ps
CPU time 0.61 seconds
Started Jul 28 05:02:52 PM PDT 24
Finished Jul 28 05:02:53 PM PDT 24
Peak memory 204992 kb
Host smart-39be6cae-599c-4d32-9e13-9e8a93ac7aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638958143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2638958143
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.4136209944
Short name T35
Test name
Test status
Simulation time 1320382947 ps
CPU time 5.44 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:53 PM PDT 24
Peak memory 214100 kb
Host smart-8a1d53e7-7fee-44f2-a81f-68afd74dbe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136209944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.4136209944
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2889005443
Short name T1052
Test name
Test status
Simulation time 282239465 ps
CPU time 5.93 seconds
Started Jul 28 05:02:50 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 263060 kb
Host smart-a09d0ad0-1afe-495c-8f7e-95209d69a05a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889005443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2889005443
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3429968644
Short name T391
Test name
Test status
Simulation time 2941057498 ps
CPU time 94.33 seconds
Started Jul 28 05:03:00 PM PDT 24
Finished Jul 28 05:04:35 PM PDT 24
Peak memory 668064 kb
Host smart-73e98031-5481-4615-bef4-43370a3b1173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429968644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3429968644
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1731850613
Short name T961
Test name
Test status
Simulation time 3225063534 ps
CPU time 85.7 seconds
Started Jul 28 05:02:57 PM PDT 24
Finished Jul 28 05:04:23 PM PDT 24
Peak memory 520272 kb
Host smart-ef9ffef4-ef5f-4b04-987c-709460c24bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731850613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1731850613
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2424801790
Short name T694
Test name
Test status
Simulation time 416827006 ps
CPU time 0.91 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 205444 kb
Host smart-e0840c7b-f4fb-4e3e-954d-3137fa7092a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424801790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2424801790
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3865330635
Short name T650
Test name
Test status
Simulation time 446886684 ps
CPU time 5 seconds
Started Jul 28 05:03:02 PM PDT 24
Finished Jul 28 05:03:08 PM PDT 24
Peak memory 205776 kb
Host smart-6d45e31f-814a-40cd-962c-d2bd2eb41770
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865330635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3865330635
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1776538970
Short name T115
Test name
Test status
Simulation time 3895609202 ps
CPU time 103.2 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:04:33 PM PDT 24
Peak memory 1100848 kb
Host smart-b2ecbdd9-ee1a-42a3-9fff-1d62f9766e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776538970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1776538970
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.2395598124
Short name T1503
Test name
Test status
Simulation time 954067711 ps
CPU time 19.44 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:23 PM PDT 24
Peak memory 205740 kb
Host smart-5457d35a-cdda-46b7-a804-78e9b409ce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395598124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2395598124
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3698574044
Short name T13
Test name
Test status
Simulation time 325323660 ps
CPU time 1.63 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:02:55 PM PDT 24
Peak memory 213988 kb
Host smart-0c4cf6a8-2252-4c4f-9f16-127bbc60802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698574044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3698574044
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2329634335
Short name T15
Test name
Test status
Simulation time 26158243679 ps
CPU time 1494.35 seconds
Started Jul 28 05:03:13 PM PDT 24
Finished Jul 28 05:28:08 PM PDT 24
Peak memory 3707180 kb
Host smart-dc264e10-01c3-413b-b9ae-ebd998fb2bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329634335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2329634335
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.1036498630
Short name T733
Test name
Test status
Simulation time 1861435737 ps
CPU time 16.43 seconds
Started Jul 28 05:02:46 PM PDT 24
Finished Jul 28 05:03:03 PM PDT 24
Peak memory 205624 kb
Host smart-f23d6f4a-bd1b-4ccd-96df-68cdc51db01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036498630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.1036498630
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.1679218947
Short name T469
Test name
Test status
Simulation time 4821977224 ps
CPU time 56.59 seconds
Started Jul 28 05:02:59 PM PDT 24
Finished Jul 28 05:03:56 PM PDT 24
Peak memory 325996 kb
Host smart-d8e93770-9bad-49c1-971e-bc32f8224842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679218947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1679218947
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.2600851463
Short name T123
Test name
Test status
Simulation time 2552288015 ps
CPU time 71.61 seconds
Started Jul 28 05:03:05 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 552484 kb
Host smart-d596f032-627b-4ace-9580-d5b3b90c3d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600851463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.2600851463
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3812994814
Short name T1021
Test name
Test status
Simulation time 703347929 ps
CPU time 11.05 seconds
Started Jul 28 05:02:57 PM PDT 24
Finished Jul 28 05:03:08 PM PDT 24
Peak memory 221504 kb
Host smart-8b0b0a52-214f-4fa9-8715-478e901475ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812994814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3812994814
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2011008605
Short name T183
Test name
Test status
Simulation time 75728410 ps
CPU time 0.94 seconds
Started Jul 28 05:03:11 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 224112 kb
Host smart-21c897e0-a51a-428b-936c-717af9a3e473
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011008605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2011008605
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.3736154248
Short name T503
Test name
Test status
Simulation time 1327344400 ps
CPU time 6.98 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:02:59 PM PDT 24
Peak memory 211708 kb
Host smart-49839e55-a35e-472e-a973-afed6fd7daf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736154248 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3736154248
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2769320074
Short name T1437
Test name
Test status
Simulation time 239795932 ps
CPU time 1.58 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 205960 kb
Host smart-b3e3bdeb-2c40-413c-8a22-0a845f73bc9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769320074 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2769320074
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2233528867
Short name T621
Test name
Test status
Simulation time 144461694 ps
CPU time 1.01 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:02:55 PM PDT 24
Peak memory 205756 kb
Host smart-0f1f1cd3-b8c3-41b8-bee0-14d0910a54c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233528867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2233528867
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.2828260468
Short name T1232
Test name
Test status
Simulation time 443834652 ps
CPU time 2.35 seconds
Started Jul 28 05:02:58 PM PDT 24
Finished Jul 28 05:03:06 PM PDT 24
Peak memory 205816 kb
Host smart-ad9ca8d5-9af1-4501-9d08-a253437306bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828260468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.2828260468
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.593686585
Short name T539
Test name
Test status
Simulation time 100969495 ps
CPU time 1.03 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:03:09 PM PDT 24
Peak memory 205720 kb
Host smart-ebab8a2e-b4b0-4a2b-bb41-2828087020d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593686585 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.593686585
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.2483733473
Short name T1234
Test name
Test status
Simulation time 433541970 ps
CPU time 3.13 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:02:57 PM PDT 24
Peak memory 214060 kb
Host smart-e2723d18-04ad-460d-8afe-657e3f1b9bbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483733473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.2483733473
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2355380843
Short name T1229
Test name
Test status
Simulation time 637620844 ps
CPU time 3.73 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:53 PM PDT 24
Peak memory 214112 kb
Host smart-4051a0c6-51ec-4988-afe6-505d61238458
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355380843 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2355380843
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2554747842
Short name T1168
Test name
Test status
Simulation time 12721870387 ps
CPU time 14.68 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:03:09 PM PDT 24
Peak memory 358084 kb
Host smart-f96be0ec-adc1-49ea-bc2d-4c4736e081e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554747842 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2554747842
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.1108540489
Short name T1000
Test name
Test status
Simulation time 628514595 ps
CPU time 3.24 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:08 PM PDT 24
Peak memory 214032 kb
Host smart-91dcfd9e-6dad-4a1e-99f2-86b380184b4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108540489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.1108540489
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/2.i2c_target_nack_txstretch.2849530988
Short name T789
Test name
Test status
Simulation time 302101637 ps
CPU time 1.31 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:03:10 PM PDT 24
Peak memory 222380 kb
Host smart-4a60c94f-80e1-465d-9d59-250d7c11050e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849530988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_nack_txstretch.2849530988
Directory /workspace/2.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/2.i2c_target_perf.4273017596
Short name T1715
Test name
Test status
Simulation time 4045567248 ps
CPU time 4.94 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:03:13 PM PDT 24
Peak memory 220380 kb
Host smart-59d204ac-452a-4319-96ee-e8fb6886a533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273017596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.4273017596
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.3030607016
Short name T722
Test name
Test status
Simulation time 552555281 ps
CPU time 2.52 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 205692 kb
Host smart-7e0c1349-484b-4ece-8463-c2a6c3b8306f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030607016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_smbus_maxlen.3030607016
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.11150431
Short name T1727
Test name
Test status
Simulation time 965689055 ps
CPU time 13.76 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:03:09 PM PDT 24
Peak memory 214048 kb
Host smart-b9396681-a921-441e-b4d5-76e998d4cd59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11150431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targe
t_smoke.11150431
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.2948646502
Short name T822
Test name
Test status
Simulation time 20798763881 ps
CPU time 31.19 seconds
Started Jul 28 05:03:09 PM PDT 24
Finished Jul 28 05:03:40 PM PDT 24
Peak memory 271540 kb
Host smart-07ab0dfd-7af1-42fa-8860-c6bf2ffbfe40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948646502 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.2948646502
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3634471287
Short name T85
Test name
Test status
Simulation time 4898142703 ps
CPU time 21.38 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:03:15 PM PDT 24
Peak memory 222248 kb
Host smart-cd3cf2d3-e8f5-4be1-a84f-a53edf2f5208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634471287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3634471287
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.501209128
Short name T655
Test name
Test status
Simulation time 34216090022 ps
CPU time 48.96 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:03:43 PM PDT 24
Peak memory 927760 kb
Host smart-393a5d4e-aab7-4d41-a081-6ee880c445d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501209128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.501209128
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.2764332858
Short name T1018
Test name
Test status
Simulation time 2403069058 ps
CPU time 7.65 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 300436 kb
Host smart-90117c58-cd40-4cb4-871f-7adafdb8373d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764332858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.2764332858
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.89095808
Short name T995
Test name
Test status
Simulation time 2461917396 ps
CPU time 6.37 seconds
Started Jul 28 05:02:50 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 222392 kb
Host smart-6ec62dae-aa53-4fd9-9159-75f850985807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89095808 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_timeout.89095808
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.3665416451
Short name T816
Test name
Test status
Simulation time 250280099 ps
CPU time 4.07 seconds
Started Jul 28 05:02:45 PM PDT 24
Finished Jul 28 05:02:49 PM PDT 24
Peak memory 205836 kb
Host smart-575e704f-2b08-46fa-9882-67d55226d163
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665416451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.3665416451
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1054585125
Short name T322
Test name
Test status
Simulation time 15875942 ps
CPU time 0.62 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 205012 kb
Host smart-cdcd1409-907c-4268-876a-cbaa62ece30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054585125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1054585125
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3467835411
Short name T692
Test name
Test status
Simulation time 127857332 ps
CPU time 2.09 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:18 PM PDT 24
Peak memory 214044 kb
Host smart-73797dae-a0d9-40de-883c-f0e544a9d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467835411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3467835411
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2398490890
Short name T1549
Test name
Test status
Simulation time 1132572600 ps
CPU time 12.88 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:04:23 PM PDT 24
Peak memory 256048 kb
Host smart-d6b43cca-65b1-43a3-a745-34e79103dd54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398490890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2398490890
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2757930295
Short name T824
Test name
Test status
Simulation time 2691656602 ps
CPU time 78.07 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:05:28 PM PDT 24
Peak memory 584444 kb
Host smart-a95cce39-4fe2-4c40-8585-1853be21825b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757930295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2757930295
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.71688268
Short name T518
Test name
Test status
Simulation time 1399773494 ps
CPU time 43.94 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:58 PM PDT 24
Peak memory 551616 kb
Host smart-be44ac18-f48f-4ab2-99fd-7c5b1d7210d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71688268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.71688268
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3966457008
Short name T652
Test name
Test status
Simulation time 294789552 ps
CPU time 0.97 seconds
Started Jul 28 05:04:25 PM PDT 24
Finished Jul 28 05:04:27 PM PDT 24
Peak memory 205420 kb
Host smart-e61171d6-5b57-4c44-8284-7094b7028a50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966457008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3966457008
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3942866970
Short name T407
Test name
Test status
Simulation time 322735154 ps
CPU time 3.69 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:21 PM PDT 24
Peak memory 205664 kb
Host smart-cc1e9abe-4115-4400-a997-fc6b7aad08d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942866970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3942866970
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2023810456
Short name T1180
Test name
Test status
Simulation time 5426167189 ps
CPU time 151.22 seconds
Started Jul 28 05:04:35 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 1558616 kb
Host smart-c3673457-c9cb-4c6f-bbe9-b63f499e7b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023810456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2023810456
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.2831402210
Short name T1615
Test name
Test status
Simulation time 1110399345 ps
CPU time 11.22 seconds
Started Jul 28 05:04:18 PM PDT 24
Finished Jul 28 05:04:30 PM PDT 24
Peak memory 205684 kb
Host smart-6cb92054-61fa-4220-8831-dea2f700cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831402210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2831402210
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3227147296
Short name T11
Test name
Test status
Simulation time 178241085 ps
CPU time 1.49 seconds
Started Jul 28 05:04:23 PM PDT 24
Finished Jul 28 05:04:25 PM PDT 24
Peak memory 222052 kb
Host smart-c75826b2-c9c5-4d87-b752-98514868d598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227147296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3227147296
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.3915888466
Short name T529
Test name
Test status
Simulation time 79896954 ps
CPU time 0.66 seconds
Started Jul 28 05:04:18 PM PDT 24
Finished Jul 28 05:04:19 PM PDT 24
Peak memory 205388 kb
Host smart-97c7b963-9c5d-4be9-95e4-770226d4828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915888466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3915888466
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2865443414
Short name T1166
Test name
Test status
Simulation time 5559228860 ps
CPU time 17.28 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:33 PM PDT 24
Peak memory 230340 kb
Host smart-85710e5f-6d09-47ec-a1e5-a4400987606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865443414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2865443414
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.2130416121
Short name T718
Test name
Test status
Simulation time 23585926443 ps
CPU time 63.4 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:05:17 PM PDT 24
Peak memory 213940 kb
Host smart-100d255c-2e65-4a6a-baf5-d65c2c0f24d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130416121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2130416121
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1503906236
Short name T1377
Test name
Test status
Simulation time 2762298983 ps
CPU time 65.86 seconds
Started Jul 28 05:04:18 PM PDT 24
Finished Jul 28 05:05:24 PM PDT 24
Peak memory 299856 kb
Host smart-05de6449-d407-4ea1-b2c6-24ea3675a685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503906236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1503906236
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.2817146420
Short name T285
Test name
Test status
Simulation time 237561673169 ps
CPU time 1899.91 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:35:55 PM PDT 24
Peak memory 3660060 kb
Host smart-0769c7a1-04f2-431f-aec9-25bdc23c404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817146420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.2817146420
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2049901479
Short name T750
Test name
Test status
Simulation time 7054176363 ps
CPU time 19.48 seconds
Started Jul 28 05:04:23 PM PDT 24
Finished Jul 28 05:04:42 PM PDT 24
Peak memory 214268 kb
Host smart-df0c42f9-a24a-4e4a-8841-8fbe153b6a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049901479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2049901479
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3254690905
Short name T634
Test name
Test status
Simulation time 4096738133 ps
CPU time 4.81 seconds
Started Jul 28 05:04:27 PM PDT 24
Finished Jul 28 05:04:32 PM PDT 24
Peak memory 218744 kb
Host smart-96a6880b-ee6c-46b1-b338-41e376648e36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254690905 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3254690905
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.296077220
Short name T1672
Test name
Test status
Simulation time 230610423 ps
CPU time 0.93 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:15 PM PDT 24
Peak memory 205696 kb
Host smart-f406cb4d-7513-469a-b010-70a14ce7770e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296077220 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.296077220
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.673381791
Short name T643
Test name
Test status
Simulation time 203434993 ps
CPU time 1.28 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:19 PM PDT 24
Peak memory 205980 kb
Host smart-7a1e7945-f46f-4af9-986e-eb6b5640d8b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673381791 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.673381791
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.243738039
Short name T781
Test name
Test status
Simulation time 1922830496 ps
CPU time 2.62 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 205848 kb
Host smart-9ad385c8-0381-4bb4-8672-c8a39ffc88e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243738039 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.243738039
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.3570113998
Short name T133
Test name
Test status
Simulation time 290216476 ps
CPU time 0.98 seconds
Started Jul 28 05:04:12 PM PDT 24
Finished Jul 28 05:04:13 PM PDT 24
Peak memory 205668 kb
Host smart-e07495b1-c19a-4e54-8dc2-d3a413e770e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570113998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.3570113998
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.37516903
Short name T728
Test name
Test status
Simulation time 1045007008 ps
CPU time 6.22 seconds
Started Jul 28 05:04:41 PM PDT 24
Finished Jul 28 05:04:47 PM PDT 24
Peak memory 222200 kb
Host smart-0b740ad5-d664-4c96-8bb8-7695dcf570f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37516903 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.37516903
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2201584167
Short name T1007
Test name
Test status
Simulation time 22895594309 ps
CPU time 126.83 seconds
Started Jul 28 05:04:34 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 1490848 kb
Host smart-3c20b7f3-00ac-4b60-929c-7574afc0a122
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201584167 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2201584167
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.2426987333
Short name T152
Test name
Test status
Simulation time 2550633544 ps
CPU time 2.86 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:18 PM PDT 24
Peak memory 214224 kb
Host smart-67aa2b20-c8aa-4379-8549-0fa75e040dc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426987333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_nack_acqfull.2426987333
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.1305827447
Short name T194
Test name
Test status
Simulation time 432591614 ps
CPU time 2.43 seconds
Started Jul 28 05:04:23 PM PDT 24
Finished Jul 28 05:04:25 PM PDT 24
Peak memory 205900 kb
Host smart-fbcf85ea-e073-459b-adb3-0ee0acc97dc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305827447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.1305827447
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.3046151228
Short name T114
Test name
Test status
Simulation time 821206261 ps
CPU time 1.96 seconds
Started Jul 28 05:04:28 PM PDT 24
Finished Jul 28 05:04:30 PM PDT 24
Peak memory 205644 kb
Host smart-bd0669d3-989d-4a90-8a00-2b20bc4ec7f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046151228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_smbus_maxlen.3046151228
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2629401725
Short name T1285
Test name
Test status
Simulation time 1277615905 ps
CPU time 15.09 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:31 PM PDT 24
Peak memory 222292 kb
Host smart-1970d88d-21f9-44fd-8991-a552fecbef91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629401725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2629401725
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.4178686190
Short name T997
Test name
Test status
Simulation time 56924166683 ps
CPU time 251.21 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:08:27 PM PDT 24
Peak memory 2463096 kb
Host smart-02a010f7-53d8-453e-abfa-5ae143d7f5ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178686190 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.4178686190
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.4059848090
Short name T1165
Test name
Test status
Simulation time 4616950612 ps
CPU time 35.44 seconds
Started Jul 28 05:04:08 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 234580 kb
Host smart-c71aa818-5eef-49b9-96b5-50d1de2a9e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059848090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.4059848090
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2736502972
Short name T900
Test name
Test status
Simulation time 68796611583 ps
CPU time 3273.36 seconds
Started Jul 28 05:04:10 PM PDT 24
Finished Jul 28 05:58:44 PM PDT 24
Peak memory 12189736 kb
Host smart-d23e936f-7c55-4dd5-bb2d-a9898cf6a779
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736502972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2736502972
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.165071920
Short name T156
Test name
Test status
Simulation time 3425706462 ps
CPU time 9.36 seconds
Started Jul 28 05:04:30 PM PDT 24
Finished Jul 28 05:04:40 PM PDT 24
Peak memory 334440 kb
Host smart-64557fa0-94da-45cc-8517-0e280342ed20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165071920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.165071920
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.847118887
Short name T742
Test name
Test status
Simulation time 1104715653 ps
CPU time 6.2 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:04:42 PM PDT 24
Peak memory 219968 kb
Host smart-548462a0-8bad-4fde-8c5e-4d9d0dc6747c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847118887 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.847118887
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.1303499541
Short name T795
Test name
Test status
Simulation time 339625933 ps
CPU time 4.84 seconds
Started Jul 28 05:04:09 PM PDT 24
Finished Jul 28 05:04:14 PM PDT 24
Peak memory 205916 kb
Host smart-5a43f081-c351-4c9c-9189-5e757d219d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303499541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1303499541
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.4193679779
Short name T181
Test name
Test status
Simulation time 38680851 ps
CPU time 0.61 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 204864 kb
Host smart-da61b29c-45d2-4ae8-8b40-acef57f3c097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193679779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.4193679779
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.665806102
Short name T1485
Test name
Test status
Simulation time 306221670 ps
CPU time 1.19 seconds
Started Jul 28 05:04:24 PM PDT 24
Finished Jul 28 05:04:25 PM PDT 24
Peak memory 213980 kb
Host smart-1d0be850-d4db-4f3b-8f57-a839065b3043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665806102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.665806102
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3072872342
Short name T988
Test name
Test status
Simulation time 271363222 ps
CPU time 4.72 seconds
Started Jul 28 05:04:24 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 240848 kb
Host smart-bfe64bac-6bd0-45ef-ab90-7b69221101f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072872342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3072872342
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1101808466
Short name T522
Test name
Test status
Simulation time 6371336186 ps
CPU time 171.77 seconds
Started Jul 28 05:04:28 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 363944 kb
Host smart-bd590da7-509e-4452-9fee-a47e8619ae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101808466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1101808466
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.303894812
Short name T698
Test name
Test status
Simulation time 3066919686 ps
CPU time 47.56 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 573724 kb
Host smart-34112dba-54c8-4d08-8ca8-cb7ae71529ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303894812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.303894812
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.3800596668
Short name T930
Test name
Test status
Simulation time 483733664 ps
CPU time 1.23 seconds
Started Jul 28 05:04:28 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 205692 kb
Host smart-4c5184a0-434c-4fc6-b5df-f0463b38e983
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800596668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.3800596668
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.910608994
Short name T576
Test name
Test status
Simulation time 389819343 ps
CPU time 10.36 seconds
Started Jul 28 05:04:28 PM PDT 24
Finished Jul 28 05:04:39 PM PDT 24
Peak memory 242664 kb
Host smart-d6e84409-a6b3-444e-917d-6afa35f29c22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910608994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
910608994
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2660946990
Short name T1625
Test name
Test status
Simulation time 5278936051 ps
CPU time 168.65 seconds
Started Jul 28 05:04:33 PM PDT 24
Finished Jul 28 05:07:22 PM PDT 24
Peak memory 1524308 kb
Host smart-fa22239f-1a31-41ce-8c44-4709bc1391d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660946990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2660946990
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1779620141
Short name T261
Test name
Test status
Simulation time 503793930 ps
CPU time 7.65 seconds
Started Jul 28 05:04:33 PM PDT 24
Finished Jul 28 05:04:41 PM PDT 24
Peak memory 205716 kb
Host smart-00e97648-aaf6-414e-b992-f59c3f087b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779620141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1779620141
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.1924916079
Short name T766
Test name
Test status
Simulation time 452450665 ps
CPU time 3.87 seconds
Started Jul 28 05:04:25 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 219084 kb
Host smart-baedefc1-5999-4e7b-8b0b-d43b2ea7adfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924916079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.1924916079
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.70804013
Short name T372
Test name
Test status
Simulation time 51145917 ps
CPU time 0.67 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:04:43 PM PDT 24
Peak memory 205448 kb
Host smart-c82c44c1-ef39-40bd-b354-80c21199fcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70804013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.70804013
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2165104646
Short name T1469
Test name
Test status
Simulation time 24998260033 ps
CPU time 1515.15 seconds
Started Jul 28 05:04:24 PM PDT 24
Finished Jul 28 05:29:40 PM PDT 24
Peak memory 4093552 kb
Host smart-cb2aff27-c582-491b-8cac-29e6839d3de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165104646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2165104646
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.4165993666
Short name T636
Test name
Test status
Simulation time 505448122 ps
CPU time 1.05 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:16 PM PDT 24
Peak memory 205740 kb
Host smart-399870b9-9e7f-48b6-9fc5-fc77ceb74f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165993666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.4165993666
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3483338883
Short name T499
Test name
Test status
Simulation time 8968627494 ps
CPU time 21.46 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:38 PM PDT 24
Peak memory 287056 kb
Host smart-c898a106-5129-42e3-8c5d-5def5200fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483338883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3483338883
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2497442200
Short name T1433
Test name
Test status
Simulation time 1042273031 ps
CPU time 19.48 seconds
Started Jul 28 05:04:35 PM PDT 24
Finished Jul 28 05:04:55 PM PDT 24
Peak memory 219492 kb
Host smart-2f4106d5-51b2-45cb-a815-3623c3813380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497442200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2497442200
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2324232630
Short name T1571
Test name
Test status
Simulation time 2420987894 ps
CPU time 6.22 seconds
Started Jul 28 05:04:14 PM PDT 24
Finished Jul 28 05:04:21 PM PDT 24
Peak memory 210772 kb
Host smart-79df47b5-465c-4aef-9db2-5b1b0f310a70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324232630 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2324232630
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2882562954
Short name T858
Test name
Test status
Simulation time 495017998 ps
CPU time 1.13 seconds
Started Jul 28 05:04:17 PM PDT 24
Finished Jul 28 05:04:19 PM PDT 24
Peak memory 205424 kb
Host smart-135c40a1-441a-4ddd-8d99-6da6bac061af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882562954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2882562954
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1519659295
Short name T939
Test name
Test status
Simulation time 137402790 ps
CPU time 1.02 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:18 PM PDT 24
Peak memory 205668 kb
Host smart-8097e0c1-cd91-4e4b-93d1-c0d7ffc5724a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519659295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1519659295
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.1004484555
Short name T588
Test name
Test status
Simulation time 302187486 ps
CPU time 2 seconds
Started Jul 28 05:04:18 PM PDT 24
Finished Jul 28 05:04:20 PM PDT 24
Peak memory 205652 kb
Host smart-4348a1f8-0fea-44a7-8af1-545bb75992b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004484555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.1004484555
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.2158563349
Short name T607
Test name
Test status
Simulation time 569282605 ps
CPU time 1.49 seconds
Started Jul 28 05:04:28 PM PDT 24
Finished Jul 28 05:04:30 PM PDT 24
Peak memory 205964 kb
Host smart-d60ebce2-a5e4-45c7-86b9-4d36fdab97a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158563349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.2158563349
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2809603110
Short name T176
Test name
Test status
Simulation time 309459168 ps
CPU time 2.4 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:17 PM PDT 24
Peak memory 215196 kb
Host smart-de1936bb-2439-4e56-8947-733138b38811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809603110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2809603110
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3542871785
Short name T454
Test name
Test status
Simulation time 1075069015 ps
CPU time 6.35 seconds
Started Jul 28 05:04:29 PM PDT 24
Finished Jul 28 05:04:35 PM PDT 24
Peak memory 222284 kb
Host smart-25bf78ea-2f44-4b06-aab1-db6e156f90ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542871785 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3542871785
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.603922734
Short name T1034
Test name
Test status
Simulation time 7663201552 ps
CPU time 80.43 seconds
Started Jul 28 05:04:24 PM PDT 24
Finished Jul 28 05:05:44 PM PDT 24
Peak memory 1781456 kb
Host smart-7f7107b2-09f4-4c00-b9ae-77d04faa6429
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603922734 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.603922734
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.3273404260
Short name T679
Test name
Test status
Simulation time 567438328 ps
CPU time 2.89 seconds
Started Jul 28 05:04:18 PM PDT 24
Finished Jul 28 05:04:21 PM PDT 24
Peak memory 205900 kb
Host smart-8ec523a6-1272-4895-9b17-6158b79dd8b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273404260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.3273404260
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_txstretch.618362773
Short name T644
Test name
Test status
Simulation time 139632806 ps
CPU time 1.59 seconds
Started Jul 28 05:04:26 PM PDT 24
Finished Jul 28 05:04:28 PM PDT 24
Peak memory 222400 kb
Host smart-a7b07090-a7f9-4b3a-9e45-af598f577108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618362773 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_nack_txstretch.618362773
Directory /workspace/21.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/21.i2c_target_perf.1127554489
Short name T1294
Test name
Test status
Simulation time 1632435320 ps
CPU time 5.92 seconds
Started Jul 28 05:04:23 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 214192 kb
Host smart-bd77ec47-b165-463b-9734-47b955ab86d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127554489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.1127554489
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.1670028614
Short name T1583
Test name
Test status
Simulation time 840463668 ps
CPU time 2.21 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:04:51 PM PDT 24
Peak memory 205704 kb
Host smart-91f53533-8da0-49b2-a52d-309c1355e687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670028614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_smbus_maxlen.1670028614
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1653345891
Short name T527
Test name
Test status
Simulation time 2576572257 ps
CPU time 40.51 seconds
Started Jul 28 05:04:31 PM PDT 24
Finished Jul 28 05:05:11 PM PDT 24
Peak memory 214276 kb
Host smart-12e77c47-9dd3-4b51-bc9b-9a1ffadce1c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653345891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1653345891
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.3421448770
Short name T279
Test name
Test status
Simulation time 25530750229 ps
CPU time 69.8 seconds
Started Jul 28 05:04:30 PM PDT 24
Finished Jul 28 05:05:40 PM PDT 24
Peak memory 494940 kb
Host smart-f888cf92-1e9e-4084-a163-49d9ab99ece2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421448770 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_stress_all.3421448770
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1105143917
Short name T1355
Test name
Test status
Simulation time 3821567361 ps
CPU time 18.63 seconds
Started Jul 28 05:04:13 PM PDT 24
Finished Jul 28 05:04:32 PM PDT 24
Peak memory 223320 kb
Host smart-128bd102-931d-40b2-8856-fa53aa566020
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105143917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1105143917
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.2863033495
Short name T1419
Test name
Test status
Simulation time 49799371715 ps
CPU time 166.04 seconds
Started Jul 28 05:04:25 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 2007128 kb
Host smart-d097ba64-283e-4a56-b914-205b01bc3f97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863033495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.2863033495
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.3531913155
Short name T960
Test name
Test status
Simulation time 4335721721 ps
CPU time 108.12 seconds
Started Jul 28 05:04:23 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 898536 kb
Host smart-9c15d7ee-d6d4-48d8-a3a3-656cf422f134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531913155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.3531913155
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3884275819
Short name T1068
Test name
Test status
Simulation time 2636754316 ps
CPU time 7.26 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:04:50 PM PDT 24
Peak memory 222032 kb
Host smart-95ee8ca6-3cd8-4186-a99c-74bbb1798d49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884275819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3884275819
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.965604123
Short name T457
Test name
Test status
Simulation time 291367805 ps
CPU time 4.63 seconds
Started Jul 28 05:04:34 PM PDT 24
Finished Jul 28 05:04:39 PM PDT 24
Peak memory 205892 kb
Host smart-8678dd24-2722-4bc9-883b-7424ad89f2a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965604123 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.965604123
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1135233303
Short name T959
Test name
Test status
Simulation time 120199247 ps
CPU time 0.61 seconds
Started Jul 28 05:04:30 PM PDT 24
Finished Jul 28 05:04:30 PM PDT 24
Peak memory 204980 kb
Host smart-31727923-710d-4132-8335-3ab84656c247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135233303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1135233303
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3169254042
Short name T993
Test name
Test status
Simulation time 118568476 ps
CPU time 2.85 seconds
Started Jul 28 05:04:16 PM PDT 24
Finished Jul 28 05:04:19 PM PDT 24
Peak memory 213944 kb
Host smart-4cee132e-05fd-498c-b9fc-65709f5ca0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169254042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3169254042
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.318374630
Short name T384
Test name
Test status
Simulation time 1641301567 ps
CPU time 11.42 seconds
Started Jul 28 05:04:15 PM PDT 24
Finished Jul 28 05:04:27 PM PDT 24
Peak memory 321288 kb
Host smart-c88d2d1e-147f-48ca-af5b-78a038792bec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318374630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.318374630
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1305531945
Short name T701
Test name
Test status
Simulation time 7335478503 ps
CPU time 55.67 seconds
Started Jul 28 05:04:22 PM PDT 24
Finished Jul 28 05:05:18 PM PDT 24
Peak memory 503212 kb
Host smart-1f1d4f3e-a5c9-4728-8b00-996bf1a8f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305531945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1305531945
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2875751985
Short name T92
Test name
Test status
Simulation time 9696631786 ps
CPU time 48.82 seconds
Started Jul 28 05:04:34 PM PDT 24
Finished Jul 28 05:05:23 PM PDT 24
Peak memory 555784 kb
Host smart-8ce9463e-ad50-46bd-98c4-21444bbcb809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875751985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2875751985
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2073204215
Short name T958
Test name
Test status
Simulation time 108727179 ps
CPU time 1.18 seconds
Started Jul 28 05:04:24 PM PDT 24
Finished Jul 28 05:04:25 PM PDT 24
Peak memory 205720 kb
Host smart-18ece55c-e4ec-4653-99c9-9b0a1b0f08da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073204215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2073204215
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.4280547227
Short name T146
Test name
Test status
Simulation time 236425959 ps
CPU time 6.37 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:04:43 PM PDT 24
Peak memory 251332 kb
Host smart-a0105fd2-5cfd-4fe8-ba74-e42e888831c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280547227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.4280547227
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1275842800
Short name T109
Test name
Test status
Simulation time 53128909036 ps
CPU time 136.29 seconds
Started Jul 28 05:04:31 PM PDT 24
Finished Jul 28 05:06:48 PM PDT 24
Peak memory 1525712 kb
Host smart-0a266681-8587-4433-99a6-4cfffa1dd271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275842800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1275842800
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.454802317
Short name T872
Test name
Test status
Simulation time 2168608317 ps
CPU time 4.97 seconds
Started Jul 28 05:04:25 PM PDT 24
Finished Jul 28 05:04:30 PM PDT 24
Peak memory 205820 kb
Host smart-f6b0aeb8-87ad-4149-aeac-503c6adea1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454802317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.454802317
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.228605266
Short name T138
Test name
Test status
Simulation time 26143919 ps
CPU time 0.64 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:40 PM PDT 24
Peak memory 205488 kb
Host smart-5336a4fd-6528-4930-a799-6c19d24ae291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228605266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.228605266
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2193616093
Short name T946
Test name
Test status
Simulation time 49169121548 ps
CPU time 1203.55 seconds
Started Jul 28 05:04:25 PM PDT 24
Finished Jul 28 05:24:29 PM PDT 24
Peak memory 2053412 kb
Host smart-93b09068-92c2-4982-8464-fa1e144805ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193616093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2193616093
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.3823528236
Short name T1328
Test name
Test status
Simulation time 102360722 ps
CPU time 1 seconds
Started Jul 28 05:04:27 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 223128 kb
Host smart-19eb7e6a-e300-4c17-a126-2cd946fe052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823528236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3823528236
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3275245907
Short name T676
Test name
Test status
Simulation time 1029643926 ps
CPU time 46.77 seconds
Started Jul 28 05:04:29 PM PDT 24
Finished Jul 28 05:05:16 PM PDT 24
Peak memory 286528 kb
Host smart-9e6a269d-0d60-4f8a-bfe3-8204a04dd096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275245907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3275245907
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.86410493
Short name T1664
Test name
Test status
Simulation time 2389072540 ps
CPU time 25.22 seconds
Started Jul 28 05:04:35 PM PDT 24
Finished Jul 28 05:05:01 PM PDT 24
Peak memory 213924 kb
Host smart-f6580aa8-bdfa-4b7c-b459-b1b5a452b765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86410493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.86410493
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3950934694
Short name T1458
Test name
Test status
Simulation time 11532834514 ps
CPU time 7.08 seconds
Started Jul 28 05:04:48 PM PDT 24
Finished Jul 28 05:04:55 PM PDT 24
Peak memory 214636 kb
Host smart-8d5bd2de-fbab-4d43-8252-ef72cd0adf46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950934694 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3950934694
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1528449947
Short name T1513
Test name
Test status
Simulation time 907066174 ps
CPU time 1.28 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 206004 kb
Host smart-d8c32695-1e77-4bf8-a319-4ef1910db561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528449947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1528449947
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1915132078
Short name T1210
Test name
Test status
Simulation time 284084731 ps
CPU time 1.07 seconds
Started Jul 28 05:04:38 PM PDT 24
Finished Jul 28 05:04:39 PM PDT 24
Peak memory 205608 kb
Host smart-296783d1-bb5c-4201-8b38-1c359df55e02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915132078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1915132078
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.3750694732
Short name T432
Test name
Test status
Simulation time 80138423 ps
CPU time 0.92 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 205672 kb
Host smart-9b1ef801-e929-4093-b022-f15815f6e0f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750694732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.3750694732
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2768523022
Short name T783
Test name
Test status
Simulation time 328060298 ps
CPU time 2.59 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:42 PM PDT 24
Peak memory 214112 kb
Host smart-6b9a3d84-cde9-49a5-a01c-5c316034d370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768523022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2768523022
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.334610260
Short name T1616
Test name
Test status
Simulation time 3267025753 ps
CPU time 8.91 seconds
Started Jul 28 05:04:34 PM PDT 24
Finished Jul 28 05:04:43 PM PDT 24
Peak memory 222336 kb
Host smart-d424f586-90eb-46e8-a0b4-3e44e4c89b89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334610260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.334610260
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2856708452
Short name T508
Test name
Test status
Simulation time 15275531443 ps
CPU time 28.62 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:05:08 PM PDT 24
Peak memory 593988 kb
Host smart-defa1255-e117-4105-974d-ff82531d790b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856708452 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2856708452
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.2594047249
Short name T1336
Test name
Test status
Simulation time 2473172787 ps
CPU time 3.26 seconds
Started Jul 28 05:04:29 PM PDT 24
Finished Jul 28 05:04:33 PM PDT 24
Peak memory 214456 kb
Host smart-2f3c058e-8ee4-457d-980b-8f541720c046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594047249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.2594047249
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.3672726298
Short name T1275
Test name
Test status
Simulation time 828455389 ps
CPU time 2.8 seconds
Started Jul 28 05:04:44 PM PDT 24
Finished Jul 28 05:04:47 PM PDT 24
Peak memory 205952 kb
Host smart-be66ff4c-ddd3-466f-9f95-cf869bf89bbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672726298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.3672726298
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.957148469
Short name T48
Test name
Test status
Simulation time 490219000 ps
CPU time 4.11 seconds
Started Jul 28 05:04:40 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 214956 kb
Host smart-ca89865d-02b5-4ff3-a0ec-feaacb29bf4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957148469 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_perf.957148469
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.975083210
Short name T553
Test name
Test status
Simulation time 580306098 ps
CPU time 2.48 seconds
Started Jul 28 05:04:38 PM PDT 24
Finished Jul 28 05:04:41 PM PDT 24
Peak memory 205592 kb
Host smart-d9a4c472-58f7-4ad3-a348-6c15b8fa4b51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975083210 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_smbus_maxlen.975083210
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.382062021
Short name T683
Test name
Test status
Simulation time 861890565 ps
CPU time 24.95 seconds
Started Jul 28 05:04:29 PM PDT 24
Finished Jul 28 05:04:54 PM PDT 24
Peak memory 214252 kb
Host smart-2fa1ff7d-1058-4cd4-9758-e6ddaf3635d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382062021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.382062021
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.2110414973
Short name T668
Test name
Test status
Simulation time 16815367672 ps
CPU time 40.41 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:05:23 PM PDT 24
Peak memory 350416 kb
Host smart-c3148f91-d207-4db0-b1a4-e9b2fefa3c0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110414973 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.2110414973
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1904346945
Short name T901
Test name
Test status
Simulation time 2068391638 ps
CPU time 9.59 seconds
Started Jul 28 05:04:29 PM PDT 24
Finished Jul 28 05:04:38 PM PDT 24
Peak memory 216972 kb
Host smart-84b4a368-2981-448d-86ea-65e26cab4c3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904346945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1904346945
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2453444768
Short name T190
Test name
Test status
Simulation time 65803572252 ps
CPU time 3360.18 seconds
Started Jul 28 05:04:31 PM PDT 24
Finished Jul 28 06:00:32 PM PDT 24
Peak memory 11688220 kb
Host smart-b856bbd3-1202-4dc4-a4c1-572c5148649e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453444768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2453444768
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2242027489
Short name T447
Test name
Test status
Simulation time 308555646 ps
CPU time 1.5 seconds
Started Jul 28 05:04:27 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 205972 kb
Host smart-cc8cac32-69a7-43bd-a8f5-a01f862da95f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242027489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2242027489
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1662710303
Short name T1218
Test name
Test status
Simulation time 3245426373 ps
CPU time 7.22 seconds
Started Jul 28 05:04:27 PM PDT 24
Finished Jul 28 05:04:35 PM PDT 24
Peak memory 214272 kb
Host smart-362aa1a7-441d-4716-b49e-d5002f26042f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662710303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1662710303
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.3284630713
Short name T1200
Test name
Test status
Simulation time 226233794 ps
CPU time 4.22 seconds
Started Jul 28 05:04:32 PM PDT 24
Finished Jul 28 05:04:41 PM PDT 24
Peak memory 205960 kb
Host smart-38b12dde-d27f-4342-8851-53f12af9cf3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284630713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.3284630713
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3901052657
Short name T1737
Test name
Test status
Simulation time 44061588 ps
CPU time 0.61 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:43 PM PDT 24
Peak memory 204916 kb
Host smart-1e0071cf-ad34-425d-b2e1-26c45b1c397d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901052657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3901052657
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2097832362
Short name T28
Test name
Test status
Simulation time 58739953 ps
CPU time 1.33 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:41 PM PDT 24
Peak memory 213988 kb
Host smart-d6b59039-851a-4702-b8f0-e14066878ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097832362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2097832362
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.4198729613
Short name T1121
Test name
Test status
Simulation time 3038453173 ps
CPU time 12.22 seconds
Started Jul 28 05:04:27 PM PDT 24
Finished Jul 28 05:04:40 PM PDT 24
Peak memory 357768 kb
Host smart-7b92039a-fc76-4f01-b510-077f90ed31ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198729613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.4198729613
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1339355861
Short name T1246
Test name
Test status
Simulation time 2177878983 ps
CPU time 131.92 seconds
Started Jul 28 05:04:34 PM PDT 24
Finished Jul 28 05:06:46 PM PDT 24
Peak memory 505496 kb
Host smart-d4ea9617-d021-4029-a9bb-3cfbd391ef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339355861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1339355861
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.860479640
Short name T1564
Test name
Test status
Simulation time 9345760706 ps
CPU time 67.35 seconds
Started Jul 28 05:04:30 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 768176 kb
Host smart-7a6e5471-4a08-4015-95d8-e540c8057e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860479640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.860479640
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3478115753
Short name T248
Test name
Test status
Simulation time 162879544 ps
CPU time 1.28 seconds
Started Jul 28 05:04:40 PM PDT 24
Finished Jul 28 05:04:42 PM PDT 24
Peak memory 205500 kb
Host smart-5988513d-dcd1-4b21-9825-74df637c47be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478115753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3478115753
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1746144637
Short name T370
Test name
Test status
Simulation time 195184837 ps
CPU time 4.33 seconds
Started Jul 28 05:04:40 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 205700 kb
Host smart-33312a00-66fa-4534-96eb-1b93ed5ea956
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746144637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1746144637
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1629799758
Short name T1468
Test name
Test status
Simulation time 47178251843 ps
CPU time 116.28 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:06:32 PM PDT 24
Peak memory 1149920 kb
Host smart-076e081c-1b03-4b16-939a-bc0010a5ab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629799758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1629799758
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.2892218579
Short name T1402
Test name
Test status
Simulation time 261719632 ps
CPU time 9.71 seconds
Started Jul 28 05:04:34 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 205704 kb
Host smart-11e24aa6-4e36-4d35-b496-7f410456f708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892218579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2892218579
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.1039259035
Short name T1673
Test name
Test status
Simulation time 44199405 ps
CPU time 0.66 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:04:47 PM PDT 24
Peak memory 205440 kb
Host smart-0f5f150f-a7eb-4c13-b4de-3489e8dfdabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039259035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1039259035
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.4256982050
Short name T852
Test name
Test status
Simulation time 1863444709 ps
CPU time 6.14 seconds
Started Jul 28 05:04:30 PM PDT 24
Finished Jul 28 05:04:36 PM PDT 24
Peak memory 264644 kb
Host smart-20e3f012-cfbe-4ecb-8b89-3927e0671a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256982050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.4256982050
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.1223494045
Short name T1202
Test name
Test status
Simulation time 74670080 ps
CPU time 1.36 seconds
Started Jul 28 05:04:40 PM PDT 24
Finished Jul 28 05:04:41 PM PDT 24
Peak memory 206412 kb
Host smart-3e766552-077c-48cc-bae8-61d3c0f36f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223494045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1223494045
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1747406397
Short name T922
Test name
Test status
Simulation time 1267372348 ps
CPU time 59.35 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 285820 kb
Host smart-d89a31d4-c74d-4255-a9ac-17741a98e3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747406397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1747406397
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1433563313
Short name T1671
Test name
Test status
Simulation time 3051130081 ps
CPU time 32.97 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 214072 kb
Host smart-543e2193-418a-4729-8a99-29aa913711eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433563313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1433563313
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2438844929
Short name T1060
Test name
Test status
Simulation time 1256111788 ps
CPU time 5.31 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 222264 kb
Host smart-e3ecce02-fccd-4322-bfbe-2ad8213ecc51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438844929 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2438844929
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.621538990
Short name T1187
Test name
Test status
Simulation time 136853828 ps
CPU time 0.93 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:04:43 PM PDT 24
Peak memory 205760 kb
Host smart-ac125508-ea5d-4339-9650-cf307fb6311e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621538990 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.621538990
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.4141253917
Short name T1575
Test name
Test status
Simulation time 161680756 ps
CPU time 0.84 seconds
Started Jul 28 05:04:34 PM PDT 24
Finished Jul 28 05:04:35 PM PDT 24
Peak memory 205644 kb
Host smart-6fa803f3-f3d8-4488-be0c-de3674fbce25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141253917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.4141253917
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.1040090860
Short name T1151
Test name
Test status
Simulation time 377403163 ps
CPU time 2.22 seconds
Started Jul 28 05:04:35 PM PDT 24
Finished Jul 28 05:04:38 PM PDT 24
Peak memory 205960 kb
Host smart-71058641-f54e-4d28-b137-9cd9b0ed05ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040090860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.1040090860
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.3029015072
Short name T1505
Test name
Test status
Simulation time 792693874 ps
CPU time 1.09 seconds
Started Jul 28 05:04:26 PM PDT 24
Finished Jul 28 05:04:28 PM PDT 24
Peak memory 205668 kb
Host smart-364386f7-d7ac-4c31-bfda-6f8be95d7529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029015072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.3029015072
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3915670130
Short name T737
Test name
Test status
Simulation time 2404250373 ps
CPU time 2.62 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:42 PM PDT 24
Peak memory 214252 kb
Host smart-23d6db45-0800-4bc9-95a3-eabc08ef8523
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915670130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3915670130
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.1254220565
Short name T785
Test name
Test status
Simulation time 2235289977 ps
CPU time 5.07 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:48 PM PDT 24
Peak memory 222464 kb
Host smart-db3c3e99-223e-40cc-b45b-400e539bb251
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254220565 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.1254220565
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.43392633
Short name T320
Test name
Test status
Simulation time 9463454508 ps
CPU time 137.25 seconds
Started Jul 28 05:04:38 PM PDT 24
Finished Jul 28 05:06:56 PM PDT 24
Peak memory 2441400 kb
Host smart-a52d67ae-fa0c-442c-b44c-85cb019bf6db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43392633 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.43392633
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.3973001354
Short name T1299
Test name
Test status
Simulation time 2353141951 ps
CPU time 2.71 seconds
Started Jul 28 05:04:32 PM PDT 24
Finished Jul 28 05:04:35 PM PDT 24
Peak memory 214284 kb
Host smart-542aab29-595d-49f3-807d-92a5fd4dd6cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973001354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_nack_acqfull.3973001354
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.708970604
Short name T1327
Test name
Test status
Simulation time 454326580 ps
CPU time 2.69 seconds
Started Jul 28 05:04:41 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 205880 kb
Host smart-0f46e676-8730-43cb-8921-dead3b18c24c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708970604 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.708970604
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.3594466887
Short name T458
Test name
Test status
Simulation time 2305670907 ps
CPU time 4.46 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 214236 kb
Host smart-83ecc985-c25f-4af2-b969-dfd485c2b81a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594466887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.3594466887
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.1043928928
Short name T905
Test name
Test status
Simulation time 462498547 ps
CPU time 2.27 seconds
Started Jul 28 05:04:30 PM PDT 24
Finished Jul 28 05:04:33 PM PDT 24
Peak memory 205648 kb
Host smart-1404b3ef-88a0-446a-a435-990deacc209e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043928928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_smbus_maxlen.1043928928
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1925341201
Short name T471
Test name
Test status
Simulation time 6885894562 ps
CPU time 11.17 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:50 PM PDT 24
Peak memory 214200 kb
Host smart-f00fe6df-6fdb-43cd-b490-3e4a8358cfdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925341201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1925341201
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.2397004169
Short name T1266
Test name
Test status
Simulation time 89056022749 ps
CPU time 90.99 seconds
Started Jul 28 05:04:52 PM PDT 24
Finished Jul 28 05:06:23 PM PDT 24
Peak memory 557828 kb
Host smart-340b8a4e-af1d-4449-bcf7-fbf998f8cd7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397004169 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.2397004169
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2339525271
Short name T1204
Test name
Test status
Simulation time 2424151164 ps
CPU time 20.22 seconds
Started Jul 28 05:04:40 PM PDT 24
Finished Jul 28 05:05:00 PM PDT 24
Peak memory 223592 kb
Host smart-fd7c0b3d-506f-496e-9920-afffb37805de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339525271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2339525271
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2604705091
Short name T1613
Test name
Test status
Simulation time 64096930553 ps
CPU time 362.09 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:10:45 PM PDT 24
Peak memory 3052992 kb
Host smart-fda6b3be-cb5f-4e18-96e6-5f7aa968f797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604705091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2604705091
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.4014592512
Short name T831
Test name
Test status
Simulation time 1358601218 ps
CPU time 3.11 seconds
Started Jul 28 05:04:28 PM PDT 24
Finished Jul 28 05:04:31 PM PDT 24
Peak memory 215172 kb
Host smart-00a02f68-a396-447f-a1ec-eee583b27325
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014592512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.4014592512
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2940660942
Short name T76
Test name
Test status
Simulation time 1255813731 ps
CPU time 6.79 seconds
Started Jul 28 05:04:52 PM PDT 24
Finished Jul 28 05:04:59 PM PDT 24
Peak memory 222212 kb
Host smart-9e7736ad-2da5-4c16-a0f7-51749f8bf21a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940660942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2940660942
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.3715984440
Short name T902
Test name
Test status
Simulation time 303795103 ps
CPU time 4.22 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:04:46 PM PDT 24
Peak memory 205980 kb
Host smart-8cee33a2-9c85-41e9-ba5d-95de39d107c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715984440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.3715984440
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3231205385
Short name T1258
Test name
Test status
Simulation time 34588062 ps
CPU time 0.6 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:46 PM PDT 24
Peak memory 204948 kb
Host smart-147c4656-8c9d-40ed-8334-8eefddd0f354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231205385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3231205385
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3029382090
Short name T1011
Test name
Test status
Simulation time 382771304 ps
CPU time 1.5 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 214088 kb
Host smart-0d212e62-f001-4743-9bec-99acca8dcece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029382090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3029382090
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.801112421
Short name T479
Test name
Test status
Simulation time 364108830 ps
CPU time 6.48 seconds
Started Jul 28 05:04:40 PM PDT 24
Finished Jul 28 05:04:46 PM PDT 24
Peak memory 282536 kb
Host smart-a0c03f14-7e30-4da3-a039-4f79facb9b9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801112421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.801112421
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2093553104
Short name T1679
Test name
Test status
Simulation time 12880303253 ps
CPU time 87.65 seconds
Started Jul 28 05:04:35 PM PDT 24
Finished Jul 28 05:06:03 PM PDT 24
Peak memory 646912 kb
Host smart-5186e1c1-de8d-4382-9416-7d152b4f386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093553104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2093553104
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1995165178
Short name T1317
Test name
Test status
Simulation time 9471162950 ps
CPU time 70.48 seconds
Started Jul 28 05:04:34 PM PDT 24
Finished Jul 28 05:05:45 PM PDT 24
Peak memory 773496 kb
Host smart-e01e9666-4e29-4763-9dd8-f942ec535bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995165178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1995165178
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3361382463
Short name T779
Test name
Test status
Simulation time 73188516 ps
CPU time 0.83 seconds
Started Jul 28 05:04:55 PM PDT 24
Finished Jul 28 05:04:56 PM PDT 24
Peak memory 205468 kb
Host smart-69b62b6f-5712-4dd9-865c-99cc076116c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361382463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3361382463
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2029111848
Short name T880
Test name
Test status
Simulation time 742543749 ps
CPU time 5.69 seconds
Started Jul 28 05:04:28 PM PDT 24
Finished Jul 28 05:04:34 PM PDT 24
Peak memory 241472 kb
Host smart-cb8f99d7-e0a7-4029-b511-523b5bef4715
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029111848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2029111848
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1110026089
Short name T1460
Test name
Test status
Simulation time 2856405956 ps
CPU time 56.11 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:05:45 PM PDT 24
Peak memory 832636 kb
Host smart-3569b559-4faa-46f9-93cd-2b276233800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110026089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1110026089
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3681554059
Short name T255
Test name
Test status
Simulation time 321441786 ps
CPU time 4.22 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:49 PM PDT 24
Peak memory 205772 kb
Host smart-f6495ae0-f07d-42af-b552-245a9c2d61a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681554059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3681554059
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.1853717715
Short name T593
Test name
Test status
Simulation time 66631438 ps
CPU time 0.65 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:04:43 PM PDT 24
Peak memory 205488 kb
Host smart-70c74613-1401-4ed7-ba8e-5634e728fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853717715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1853717715
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.4001355605
Short name T1203
Test name
Test status
Simulation time 1735484502 ps
CPU time 1.5 seconds
Started Jul 28 05:05:03 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 205684 kb
Host smart-d0cccc5a-7a44-42ca-9baf-4e37060f7243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001355605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.4001355605
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1347458447
Short name T869
Test name
Test status
Simulation time 3073511266 ps
CPU time 20.98 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 318444 kb
Host smart-7e73d137-e986-42ac-80b1-c8a639fcc20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347458447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1347458447
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.243234508
Short name T1201
Test name
Test status
Simulation time 6452965718 ps
CPU time 27.09 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:05:14 PM PDT 24
Peak memory 214104 kb
Host smart-b27b5074-3820-42f6-924c-57444fdce362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243234508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.243234508
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.230382738
Short name T1094
Test name
Test status
Simulation time 718824520 ps
CPU time 4.09 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:49 PM PDT 24
Peak memory 209216 kb
Host smart-7a60a8ab-0040-4190-809f-a6d0c3ba0486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230382738 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.230382738
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.833745812
Short name T1757
Test name
Test status
Simulation time 291307159 ps
CPU time 1.26 seconds
Started Jul 28 05:04:44 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 205744 kb
Host smart-5c4cfe3b-a9e9-47f7-9898-79d3e5f1c372
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833745812 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.833745812
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.4049368178
Short name T309
Test name
Test status
Simulation time 169845062 ps
CPU time 1.01 seconds
Started Jul 28 05:04:38 PM PDT 24
Finished Jul 28 05:04:39 PM PDT 24
Peak memory 205732 kb
Host smart-022ff9a3-45b8-4d63-b26f-e521d0814caf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049368178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.4049368178
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.3190627165
Short name T808
Test name
Test status
Simulation time 811074052 ps
CPU time 2.32 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 205916 kb
Host smart-bad7823d-b7b8-48bb-9c7a-67be84f41c0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190627165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.3190627165
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.1667366590
Short name T1403
Test name
Test status
Simulation time 128068714 ps
CPU time 1.13 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:41 PM PDT 24
Peak memory 205696 kb
Host smart-4fdb6dee-5a2c-480e-bbcf-11a1e7d8c1f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667366590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.1667366590
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.4061773727
Short name T695
Test name
Test status
Simulation time 305146604 ps
CPU time 2.31 seconds
Started Jul 28 05:04:32 PM PDT 24
Finished Jul 28 05:04:34 PM PDT 24
Peak memory 222300 kb
Host smart-4e835d90-3ddd-4840-8727-e3113b3426a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061773727 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.4061773727
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.14389851
Short name T1179
Test name
Test status
Simulation time 1405114857 ps
CPU time 7.09 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:47 PM PDT 24
Peak memory 222260 kb
Host smart-eb938589-b8e3-408a-862e-018aaa1d7989
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389851 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.14389851
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.938450542
Short name T461
Test name
Test status
Simulation time 22609811647 ps
CPU time 20 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 598572 kb
Host smart-c3c54d1a-6ada-4dae-b6f2-9aa48895e74e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938450542 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.938450542
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.3502557337
Short name T944
Test name
Test status
Simulation time 985482109 ps
CPU time 3.03 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:04:49 PM PDT 24
Peak memory 214216 kb
Host smart-46e35cb3-dd39-43d8-bc31-6a14a5928c7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502557337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_nack_acqfull.3502557337
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.418915835
Short name T1428
Test name
Test status
Simulation time 741468561 ps
CPU time 2.41 seconds
Started Jul 28 05:04:37 PM PDT 24
Finished Jul 28 05:04:40 PM PDT 24
Peak memory 205972 kb
Host smart-fe02b018-d7d9-4c5b-8061-846631f3c3bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418915835 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.418915835
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_txstretch.3495757078
Short name T1422
Test name
Test status
Simulation time 172745597 ps
CPU time 1.42 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:04:38 PM PDT 24
Peak memory 222384 kb
Host smart-0ceda181-43be-4bc6-9999-0e2476f22ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495757078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_nack_txstretch.3495757078
Directory /workspace/24.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/24.i2c_target_perf.3679909030
Short name T501
Test name
Test status
Simulation time 1403885849 ps
CPU time 4.65 seconds
Started Jul 28 05:04:40 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 222392 kb
Host smart-60cc95ad-bfae-4fc9-887f-5def958fe345
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679909030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.3679909030
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.1338846393
Short name T1223
Test name
Test status
Simulation time 1503640806 ps
CPU time 2.23 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:04:38 PM PDT 24
Peak memory 205600 kb
Host smart-533e822c-7c1c-41ab-b594-0a5fc7036a16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338846393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_smbus_maxlen.1338846393
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3927766081
Short name T649
Test name
Test status
Simulation time 4091921481 ps
CPU time 37.93 seconds
Started Jul 28 05:04:33 PM PDT 24
Finished Jul 28 05:05:11 PM PDT 24
Peak memory 214400 kb
Host smart-af112a01-0bb6-49f6-94f3-b594d6c5ecf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927766081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3927766081
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.135038878
Short name T862
Test name
Test status
Simulation time 78305196457 ps
CPU time 91.23 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 919780 kb
Host smart-1e2ac2a1-785a-45b0-9018-a0a17104747d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135038878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.i2c_target_stress_all.135038878
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3375808307
Short name T406
Test name
Test status
Simulation time 1117687319 ps
CPU time 8.74 seconds
Started Jul 28 05:04:38 PM PDT 24
Finished Jul 28 05:04:46 PM PDT 24
Peak memory 222000 kb
Host smart-e6ee6c79-49ee-4253-88b1-e9dc69b040d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375808307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3375808307
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3801321048
Short name T56
Test name
Test status
Simulation time 72745944610 ps
CPU time 41.34 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:05:18 PM PDT 24
Peak memory 619044 kb
Host smart-e979b8e9-9d78-4949-beec-1c982c35331d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801321048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3801321048
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.43419639
Short name T1076
Test name
Test status
Simulation time 3598928669 ps
CPU time 7.27 seconds
Started Jul 28 05:04:37 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 214296 kb
Host smart-b6ea6b05-7826-4722-ad73-14e80e0a281b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43419639 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_timeout.43419639
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.2323818042
Short name T897
Test name
Test status
Simulation time 438431335 ps
CPU time 5.75 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:04:51 PM PDT 24
Peak memory 221472 kb
Host smart-eebc3408-f084-41f2-8b9b-aeafc5e9bec4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323818042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.2323818042
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1825945622
Short name T606
Test name
Test status
Simulation time 22184678 ps
CPU time 0.63 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:04:47 PM PDT 24
Peak memory 205416 kb
Host smart-5b1ccb86-6105-4881-b3e7-504633e88b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825945622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1825945622
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1953834500
Short name T17
Test name
Test status
Simulation time 816996046 ps
CPU time 3.31 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:48 PM PDT 24
Peak memory 213984 kb
Host smart-d891bdaa-38f0-4590-92ab-88d3ae2b4a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953834500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1953834500
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.476836111
Short name T784
Test name
Test status
Simulation time 409104877 ps
CPU time 5.21 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:04:48 PM PDT 24
Peak memory 251656 kb
Host smart-877cd8a4-b8ed-4f31-839a-dc9ae73916e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476836111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.476836111
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1391549171
Short name T1104
Test name
Test status
Simulation time 14804173379 ps
CPU time 190.68 seconds
Started Jul 28 05:04:32 PM PDT 24
Finished Jul 28 05:07:43 PM PDT 24
Peak memory 532760 kb
Host smart-7cfb931e-4c2c-4e83-9dcf-8647cbb1166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391549171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1391549171
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3829723541
Short name T1713
Test name
Test status
Simulation time 9120760751 ps
CPU time 159.72 seconds
Started Jul 28 05:04:37 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 722624 kb
Host smart-41e10cd3-c510-4cca-8202-17463c6505fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829723541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3829723541
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.938396344
Short name T1074
Test name
Test status
Simulation time 901912143 ps
CPU time 6.63 seconds
Started Jul 28 05:04:41 PM PDT 24
Finished Jul 28 05:04:48 PM PDT 24
Peak memory 250372 kb
Host smart-8859b0bd-810f-412f-a2f1-cf0c197be4ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938396344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
938396344
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1260079401
Short name T1182
Test name
Test status
Simulation time 34693049748 ps
CPU time 72.86 seconds
Started Jul 28 05:04:55 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 870072 kb
Host smart-38c34570-0d39-4b44-8850-d5c69434c114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260079401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1260079401
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_override.2462326408
Short name T1385
Test name
Test status
Simulation time 57808461 ps
CPU time 0.65 seconds
Started Jul 28 05:04:38 PM PDT 24
Finished Jul 28 05:04:38 PM PDT 24
Peak memory 205488 kb
Host smart-866447b9-b4f3-4950-a75b-89d28704ce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462326408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2462326408
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1138641663
Short name T1611
Test name
Test status
Simulation time 5080684182 ps
CPU time 36.47 seconds
Started Jul 28 05:04:36 PM PDT 24
Finished Jul 28 05:05:13 PM PDT 24
Peak memory 223516 kb
Host smart-c1f8270d-3863-4800-be86-287334d47da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138641663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1138641663
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.1626918710
Short name T1675
Test name
Test status
Simulation time 75208603 ps
CPU time 1.91 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 205712 kb
Host smart-a957cf8d-0f59-42f1-a781-dd6486c5804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626918710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1626918710
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.4075125538
Short name T913
Test name
Test status
Simulation time 7253914978 ps
CPU time 86.79 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:06:16 PM PDT 24
Peak memory 355612 kb
Host smart-ab46bf54-6aef-4c42-8ea2-4c7e29098d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075125538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.4075125538
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.2457601334
Short name T386
Test name
Test status
Simulation time 665233656 ps
CPU time 11.65 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 213988 kb
Host smart-4840d0fb-93fa-4165-8e72-6288701c78b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457601334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2457601334
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.125571408
Short name T1595
Test name
Test status
Simulation time 797653522 ps
CPU time 4.29 seconds
Started Jul 28 05:04:41 PM PDT 24
Finished Jul 28 05:04:45 PM PDT 24
Peak memory 214348 kb
Host smart-4281e690-659d-4f0f-a094-7061fff88cc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125571408 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.125571408
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.158355410
Short name T661
Test name
Test status
Simulation time 134966231 ps
CPU time 1.06 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:04:50 PM PDT 24
Peak memory 205728 kb
Host smart-a25eac8b-9c82-4668-b749-89feb50faf71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158355410 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.158355410
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2885144927
Short name T1014
Test name
Test status
Simulation time 173118635 ps
CPU time 0.98 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 205768 kb
Host smart-24afc386-f56f-4711-9de9-fac0550fec24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885144927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2885144927
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.1862607187
Short name T399
Test name
Test status
Simulation time 491128628 ps
CPU time 2.44 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:04:52 PM PDT 24
Peak memory 205892 kb
Host smart-b9ff956f-fd31-4dd7-ad7d-8a661aa9d830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862607187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.1862607187
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.3740283953
Short name T751
Test name
Test status
Simulation time 1205773403 ps
CPU time 1.22 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 205684 kb
Host smart-30ac6534-7a0b-4096-ba83-81a9d1d3a973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740283953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.3740283953
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.833242181
Short name T615
Test name
Test status
Simulation time 112895028 ps
CPU time 1.14 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:04:47 PM PDT 24
Peak memory 205708 kb
Host smart-c8e8b5e7-c262-4bcf-b20e-a01c631ced6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833242181 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.833242181
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.2102404687
Short name T1545
Test name
Test status
Simulation time 866020947 ps
CPU time 5.89 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:04:52 PM PDT 24
Peak memory 218052 kb
Host smart-bfb2c84f-b0bd-4ad1-bd54-e664b141bdc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102404687 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.2102404687
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3273369734
Short name T667
Test name
Test status
Simulation time 18015530904 ps
CPU time 437.63 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:11:57 PM PDT 24
Peak memory 4423840 kb
Host smart-6a689fdd-1947-4b0f-8b78-2bf43673ffd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273369734 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3273369734
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.2112306458
Short name T151
Test name
Test status
Simulation time 490327072 ps
CPU time 2.98 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:04:42 PM PDT 24
Peak memory 214092 kb
Host smart-e9ce1d8b-a0a8-4341-98f6-6a01ff331e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112306458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.2112306458
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.3092594408
Short name T915
Test name
Test status
Simulation time 2050475839 ps
CPU time 2.84 seconds
Started Jul 28 05:04:53 PM PDT 24
Finished Jul 28 05:04:56 PM PDT 24
Peak memory 205840 kb
Host smart-d7529693-64e2-4b33-b9f7-af32e39fbc88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092594408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.3092594408
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.1275422499
Short name T571
Test name
Test status
Simulation time 2041450076 ps
CPU time 3.26 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:04:53 PM PDT 24
Peak memory 214184 kb
Host smart-4bae89df-8e39-453c-848e-5b858696d0c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275422499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.1275422499
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.1642687753
Short name T1614
Test name
Test status
Simulation time 8723056629 ps
CPU time 2.49 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:48 PM PDT 24
Peak memory 205864 kb
Host smart-4702db75-4dd8-4634-88d9-c0d19934bd1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642687753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_smbus_maxlen.1642687753
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1416356090
Short name T935
Test name
Test status
Simulation time 885146917 ps
CPU time 5.96 seconds
Started Jul 28 05:04:51 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 222256 kb
Host smart-3527cc0c-e4e5-40c9-a24d-8abcd6328df2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416356090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1416356090
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.2129392568
Short name T174
Test name
Test status
Simulation time 49913195689 ps
CPU time 84.62 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:06:09 PM PDT 24
Peak memory 776852 kb
Host smart-e6cb9775-d7a0-47c8-ad03-b11b2b4a378c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129392568 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.2129392568
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2725908972
Short name T272
Test name
Test status
Simulation time 1669165668 ps
CPU time 13.44 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:58 PM PDT 24
Peak memory 222292 kb
Host smart-072dbf3a-d146-4182-aee4-f67ad91ce3e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725908972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2725908972
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2156778827
Short name T1252
Test name
Test status
Simulation time 56454028513 ps
CPU time 204.68 seconds
Started Jul 28 05:04:39 PM PDT 24
Finished Jul 28 05:08:04 PM PDT 24
Peak memory 2298600 kb
Host smart-dc0320fc-3f53-4fd7-ab9a-129fec5bd6c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156778827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2156778827
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.187011559
Short name T1446
Test name
Test status
Simulation time 5091744854 ps
CPU time 5.4 seconds
Started Jul 28 05:04:35 PM PDT 24
Finished Jul 28 05:04:41 PM PDT 24
Peak memory 243008 kb
Host smart-e8474292-a77b-4262-a7db-92ffaf80f881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187011559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t
arget_stretch.187011559
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.4188751130
Short name T1323
Test name
Test status
Simulation time 1214759422 ps
CPU time 6.89 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:52 PM PDT 24
Peak memory 218444 kb
Host smart-1fa7cfb6-a06e-411d-a093-65f0ae37df5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188751130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.4188751130
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.1941073681
Short name T298
Test name
Test status
Simulation time 144476938 ps
CPU time 2.08 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:04:49 PM PDT 24
Peak memory 205848 kb
Host smart-af657789-b81d-4e6a-9489-701860c3988b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941073681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.1941073681
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2429777890
Short name T1154
Test name
Test status
Simulation time 33964057 ps
CPU time 0.61 seconds
Started Jul 28 05:04:55 PM PDT 24
Finished Jul 28 05:04:56 PM PDT 24
Peak memory 204840 kb
Host smart-a9b95194-e0a4-44f5-98d0-cf049478c620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429777890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2429777890
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.2496172150
Short name T1557
Test name
Test status
Simulation time 952696058 ps
CPU time 8.48 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:04:56 PM PDT 24
Peak memory 251624 kb
Host smart-9bddc2bd-8114-4b2d-9951-4e237728beb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496172150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2496172150
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1070295369
Short name T127
Test name
Test status
Simulation time 969625393 ps
CPU time 12.45 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:04:58 PM PDT 24
Peak memory 243268 kb
Host smart-ba053a13-9750-4fe9-b127-b992faf5f8a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070295369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1070295369
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.667312381
Short name T26
Test name
Test status
Simulation time 10547499000 ps
CPU time 165.96 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:07:32 PM PDT 24
Peak memory 604160 kb
Host smart-1d116b2a-532e-4b35-96bb-5c0589ad7849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667312381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.667312381
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3050246340
Short name T1724
Test name
Test status
Simulation time 258492042 ps
CPU time 0.94 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:04:48 PM PDT 24
Peak memory 205504 kb
Host smart-c9523f9a-e9d6-4fd8-a65d-4fd6046520f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050246340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3050246340
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.4175660285
Short name T1473
Test name
Test status
Simulation time 190118327 ps
CPU time 3.96 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:49 PM PDT 24
Peak memory 205740 kb
Host smart-9779836e-bb59-4ce9-a132-cc473bb4b9bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175660285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.4175660285
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2400447935
Short name T172
Test name
Test status
Simulation time 10513247869 ps
CPU time 163.69 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:07:31 PM PDT 24
Peak memory 1488404 kb
Host smart-07c2716b-e780-42bb-a081-6260de9ff2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400447935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2400447935
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.64561285
Short name T253
Test name
Test status
Simulation time 2485278578 ps
CPU time 5.29 seconds
Started Jul 28 05:04:52 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 205784 kb
Host smart-35c776cc-23b8-46a0-ae52-130f3f1ab1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64561285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.64561285
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.675014925
Short name T585
Test name
Test status
Simulation time 115028892 ps
CPU time 2.09 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:04:56 PM PDT 24
Peak memory 234164 kb
Host smart-07ba095d-9c3e-4687-93dd-4e16c9cab2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675014925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.675014925
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2007991720
Short name T1162
Test name
Test status
Simulation time 33694846 ps
CPU time 0.71 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 205516 kb
Host smart-fbf8b625-3db1-4cae-94ee-437f30c30640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007991720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2007991720
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2784190442
Short name T1510
Test name
Test status
Simulation time 12288651521 ps
CPU time 123.06 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:06:46 PM PDT 24
Peak memory 214056 kb
Host smart-6c888a1e-8d5c-4e80-9e6f-39a4731c20d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784190442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2784190442
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.407373470
Short name T715
Test name
Test status
Simulation time 957044661 ps
CPU time 3.25 seconds
Started Jul 28 05:04:53 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 213888 kb
Host smart-d6e4028b-f99f-46c5-8502-5e57e68e757e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407373470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.407373470
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.967181722
Short name T1596
Test name
Test status
Simulation time 3751679105 ps
CPU time 33.3 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:05:21 PM PDT 24
Peak memory 279052 kb
Host smart-f7b2be4a-7140-4a87-bab5-6176715387b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967181722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.967181722
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2457787665
Short name T1579
Test name
Test status
Simulation time 793962682 ps
CPU time 14.95 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:05:02 PM PDT 24
Peak memory 220172 kb
Host smart-ff790448-155c-4788-8f65-40a94a71f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457787665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2457787665
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.986205252
Short name T908
Test name
Test status
Simulation time 994455927 ps
CPU time 5.56 seconds
Started Jul 28 05:04:55 PM PDT 24
Finished Jul 28 05:05:01 PM PDT 24
Peak memory 214080 kb
Host smart-b3800c44-78db-49d6-8005-5ef4bb6ce196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986205252 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.986205252
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3549765204
Short name T1222
Test name
Test status
Simulation time 181279359 ps
CPU time 1.15 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:04:47 PM PDT 24
Peak memory 205772 kb
Host smart-51317af7-8db0-4ffb-b84a-5bfab8d43de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549765204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3549765204
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3246373312
Short name T685
Test name
Test status
Simulation time 166462037 ps
CPU time 1.25 seconds
Started Jul 28 05:04:53 PM PDT 24
Finished Jul 28 05:04:55 PM PDT 24
Peak memory 205900 kb
Host smart-77ad9e9f-7b05-470f-9c87-37c9007aa547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246373312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3246373312
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.2048476369
Short name T678
Test name
Test status
Simulation time 2005821835 ps
CPU time 1.76 seconds
Started Jul 28 05:04:51 PM PDT 24
Finished Jul 28 05:04:52 PM PDT 24
Peak memory 205688 kb
Host smart-8985c5a7-9992-4ff6-ac4f-18f7c8b7d4a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048476369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.2048476369
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.1006837369
Short name T1712
Test name
Test status
Simulation time 520060261 ps
CPU time 1.17 seconds
Started Jul 28 05:04:55 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 205676 kb
Host smart-0f28cfa4-f300-4c01-aabe-89748264a118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006837369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.1006837369
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.4280324966
Short name T1442
Test name
Test status
Simulation time 257619806 ps
CPU time 2.03 seconds
Started Jul 28 05:04:43 PM PDT 24
Finished Jul 28 05:04:46 PM PDT 24
Peak memory 214156 kb
Host smart-44ccb628-acb5-466b-b4bf-02deba31e29c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280324966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.4280324966
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3488703357
Short name T987
Test name
Test status
Simulation time 1617635188 ps
CPU time 6.18 seconds
Started Jul 28 05:04:44 PM PDT 24
Finished Jul 28 05:04:51 PM PDT 24
Peak memory 214576 kb
Host smart-7e127c84-5eaa-4693-a3e5-e8d760486fdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488703357 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3488703357
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.300744127
Short name T670
Test name
Test status
Simulation time 9346143305 ps
CPU time 33.68 seconds
Started Jul 28 05:04:42 PM PDT 24
Finished Jul 28 05:05:16 PM PDT 24
Peak memory 675516 kb
Host smart-d0735d16-8d83-46a6-a1f5-ba6e53ad1a7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300744127 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.300744127
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.430599565
Short name T149
Test name
Test status
Simulation time 1139498264 ps
CPU time 2.98 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:04:50 PM PDT 24
Peak memory 214108 kb
Host smart-ad206d8f-b618-4179-8b22-e79a21907ea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430599565 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_nack_acqfull.430599565
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.1332343120
Short name T1627
Test name
Test status
Simulation time 2537816972 ps
CPU time 2.76 seconds
Started Jul 28 05:05:23 PM PDT 24
Finished Jul 28 05:05:30 PM PDT 24
Peak memory 206028 kb
Host smart-7d6d72b8-0434-484c-ad49-9549c91417ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332343120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.1332343120
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.1607556771
Short name T490
Test name
Test status
Simulation time 1803374344 ps
CPU time 3.11 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:04:48 PM PDT 24
Peak memory 214148 kb
Host smart-4f2c0794-512b-4dfe-87c8-f195114553e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607556771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.1607556771
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.2388427897
Short name T10
Test name
Test status
Simulation time 882872864 ps
CPU time 2.18 seconds
Started Jul 28 05:04:57 PM PDT 24
Finished Jul 28 05:05:00 PM PDT 24
Peak memory 205676 kb
Host smart-3ea9e336-a6d3-4e20-8fbc-0f44dcc888ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388427897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.2388427897
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.4234749545
Short name T348
Test name
Test status
Simulation time 1062026684 ps
CPU time 14.29 seconds
Started Jul 28 05:04:52 PM PDT 24
Finished Jul 28 05:05:06 PM PDT 24
Peak memory 214172 kb
Host smart-bb1d3d88-3e89-48e7-a0ae-05146b54122a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234749545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.4234749545
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.3134698309
Short name T295
Test name
Test status
Simulation time 29342809298 ps
CPU time 832.35 seconds
Started Jul 28 05:04:37 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 3955072 kb
Host smart-f8ccaa9d-737e-4c63-94d5-52675979a604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134698309 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.3134698309
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2981015801
Short name T1005
Test name
Test status
Simulation time 1035129153 ps
CPU time 16.94 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:05:04 PM PDT 24
Peak memory 230380 kb
Host smart-e421a9bf-e7ae-4184-a790-7b1ea04b3ccf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981015801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2981015801
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1572188698
Short name T625
Test name
Test status
Simulation time 53675247585 ps
CPU time 199.25 seconds
Started Jul 28 05:04:55 PM PDT 24
Finished Jul 28 05:08:15 PM PDT 24
Peak memory 2219724 kb
Host smart-21b0dbed-2a2c-403d-99b7-27babee7173f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572188698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1572188698
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3348059750
Short name T629
Test name
Test status
Simulation time 4767598011 ps
CPU time 61.36 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:06:06 PM PDT 24
Peak memory 1256644 kb
Host smart-a23c0978-b33f-4345-a7a0-7eb0b7897fcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348059750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3348059750
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.117146861
Short name T472
Test name
Test status
Simulation time 4949662430 ps
CPU time 6.36 seconds
Started Jul 28 05:04:52 PM PDT 24
Finished Jul 28 05:04:59 PM PDT 24
Peak memory 222352 kb
Host smart-5d5dc6fd-3e48-40f7-8765-fa828aef9a32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117146861 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_timeout.117146861
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.580373450
Short name T740
Test name
Test status
Simulation time 523277323 ps
CPU time 6.56 seconds
Started Jul 28 05:05:02 PM PDT 24
Finished Jul 28 05:05:14 PM PDT 24
Peak memory 205928 kb
Host smart-10423a02-b4aa-432c-bb06-7f7db412b4d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580373450 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.580373450
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.717025052
Short name T1101
Test name
Test status
Simulation time 24805252 ps
CPU time 0.62 seconds
Started Jul 28 05:04:51 PM PDT 24
Finished Jul 28 05:04:52 PM PDT 24
Peak memory 204988 kb
Host smart-88d3d496-4fac-410a-8d62-f452dda5135c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717025052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.717025052
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2977244727
Short name T468
Test name
Test status
Simulation time 518705863 ps
CPU time 4.89 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:04:54 PM PDT 24
Peak memory 214012 kb
Host smart-808adbb2-a0a2-48c2-b012-495cdebe8c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977244727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2977244727
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1069302812
Short name T1172
Test name
Test status
Simulation time 427594351 ps
CPU time 8.25 seconds
Started Jul 28 05:04:47 PM PDT 24
Finished Jul 28 05:04:56 PM PDT 24
Peak memory 288884 kb
Host smart-1c0218eb-aa5c-4848-bdc3-eaf434c0151e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069302812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1069302812
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3950215463
Short name T1653
Test name
Test status
Simulation time 3080262942 ps
CPU time 195.42 seconds
Started Jul 28 05:04:57 PM PDT 24
Finished Jul 28 05:08:13 PM PDT 24
Peak memory 620432 kb
Host smart-7c6435f8-d5ff-4c24-b8ee-1cd399d3a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950215463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3950215463
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.1195632377
Short name T807
Test name
Test status
Simulation time 7242611624 ps
CPU time 86.13 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:06:34 PM PDT 24
Peak memory 839368 kb
Host smart-fccf4742-e1b9-4d95-8234-b88fdb070bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195632377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1195632377
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2607245831
Short name T1093
Test name
Test status
Simulation time 289432934 ps
CPU time 0.83 seconds
Started Jul 28 05:04:57 PM PDT 24
Finished Jul 28 05:04:58 PM PDT 24
Peak memory 205492 kb
Host smart-bc675d19-5612-4405-8087-5b5bb4b78fc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607245831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2607245831
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2677811115
Short name T1071
Test name
Test status
Simulation time 2656645181 ps
CPU time 10.11 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:16 PM PDT 24
Peak memory 205832 kb
Host smart-640fdb9b-283a-4d3a-8717-1dc405360f0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677811115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2677811115
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3382233759
Short name T1450
Test name
Test status
Simulation time 1078908589 ps
CPU time 8.12 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:15 PM PDT 24
Peak memory 205720 kb
Host smart-5f70c604-ac98-4c20-b1e8-b74853fdfc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382233759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3382233759
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2820618366
Short name T848
Test name
Test status
Simulation time 345973909 ps
CPU time 3.12 seconds
Started Jul 28 05:05:01 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 205732 kb
Host smart-a357d234-e806-4baf-812e-b64cc493c94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820618366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2820618366
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3781290095
Short name T1693
Test name
Test status
Simulation time 33398483 ps
CPU time 0.64 seconds
Started Jul 28 05:04:55 PM PDT 24
Finished Jul 28 05:04:56 PM PDT 24
Peak memory 205448 kb
Host smart-7b106cf7-b9c5-4da0-8653-4b7936c40bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781290095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3781290095
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1507465868
Short name T1262
Test name
Test status
Simulation time 5006595672 ps
CPU time 68.99 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 226652 kb
Host smart-5fa0d8ba-f07a-4b16-ac2c-a07af11eae54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507465868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1507465868
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.2140975830
Short name T899
Test name
Test status
Simulation time 87906576 ps
CPU time 2.23 seconds
Started Jul 28 05:05:12 PM PDT 24
Finished Jul 28 05:05:15 PM PDT 24
Peak memory 230080 kb
Host smart-3c49eb46-13bf-43af-867a-bbabfe2703cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140975830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2140975830
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.246669070
Short name T1517
Test name
Test status
Simulation time 4696731680 ps
CPU time 42.75 seconds
Started Jul 28 05:04:54 PM PDT 24
Finished Jul 28 05:05:37 PM PDT 24
Peak memory 355176 kb
Host smart-7c1cedfd-b549-49bc-9975-ed5af592e08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246669070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.246669070
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1997234755
Short name T124
Test name
Test status
Simulation time 20541665553 ps
CPU time 537.09 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 1646456 kb
Host smart-b333c11d-8585-438c-b023-8163f0496d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997234755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1997234755
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2179023913
Short name T1566
Test name
Test status
Simulation time 868299745 ps
CPU time 6.71 seconds
Started Jul 28 05:04:48 PM PDT 24
Finished Jul 28 05:04:55 PM PDT 24
Peak memory 214052 kb
Host smart-b29d82c8-7a3c-40d8-86d5-e696a272c539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179023913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2179023913
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1159632016
Short name T794
Test name
Test status
Simulation time 2690368433 ps
CPU time 3.61 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 221864 kb
Host smart-045c0825-7841-4301-9a42-133177e7b974
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159632016 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1159632016
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.992668254
Short name T1312
Test name
Test status
Simulation time 400545161 ps
CPU time 1.08 seconds
Started Jul 28 05:04:57 PM PDT 24
Finished Jul 28 05:04:58 PM PDT 24
Peak memory 205680 kb
Host smart-968effd5-ff0e-4654-aafe-523cdb4a3ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992668254 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.992668254
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3535647767
Short name T725
Test name
Test status
Simulation time 300054895 ps
CPU time 0.93 seconds
Started Jul 28 05:04:56 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 213852 kb
Host smart-deedb773-21f0-4720-83ca-31ea64ff53f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535647767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3535647767
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.442355317
Short name T1084
Test name
Test status
Simulation time 849483846 ps
CPU time 2.82 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 205944 kb
Host smart-1407bf5c-e62f-4fc4-8daf-cb2407e55fad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442355317 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.442355317
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.2079033638
Short name T2
Test name
Test status
Simulation time 90796248 ps
CPU time 1.01 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:06 PM PDT 24
Peak memory 205732 kb
Host smart-3cfdf778-a4f1-49c0-8f7a-519aaf163ec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079033638 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.2079033638
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3078880827
Short name T1533
Test name
Test status
Simulation time 1341277174 ps
CPU time 7.48 seconds
Started Jul 28 05:04:53 PM PDT 24
Finished Jul 28 05:05:00 PM PDT 24
Peak memory 224344 kb
Host smart-ad5f74ac-b123-4eee-8f19-1b575b665025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078880827 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3078880827
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3526369025
Short name T167
Test name
Test status
Simulation time 17536902914 ps
CPU time 40.39 seconds
Started Jul 28 05:04:57 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 966972 kb
Host smart-1b62486f-b69d-4b83-9edc-8e89718fabb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526369025 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3526369025
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.3493062507
Short name T804
Test name
Test status
Simulation time 1107350091 ps
CPU time 2.77 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:05:10 PM PDT 24
Peak memory 214092 kb
Host smart-b0de1c6e-6102-40cf-a89b-c0d609774afa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493062507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_nack_acqfull.3493062507
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.1980416755
Short name T955
Test name
Test status
Simulation time 1072848195 ps
CPU time 2.63 seconds
Started Jul 28 05:04:54 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 205896 kb
Host smart-e6f085dd-dfca-4431-98ce-9912da058e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980416755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.1980416755
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_txstretch.4063582328
Short name T162
Test name
Test status
Simulation time 133437335 ps
CPU time 1.56 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:05:06 PM PDT 24
Peak memory 222748 kb
Host smart-65f8c8a7-3ac9-416d-ab56-79446d081c01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063582328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_nack_txstretch.4063582328
Directory /workspace/27.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/27.i2c_target_perf.201763050
Short name T990
Test name
Test status
Simulation time 587143507 ps
CPU time 2.52 seconds
Started Jul 28 05:05:10 PM PDT 24
Finished Jul 28 05:05:12 PM PDT 24
Peak memory 214144 kb
Host smart-34df609b-b1f4-4f63-8d5f-3e0b6648ad4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201763050 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_perf.201763050
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.2447924651
Short name T1629
Test name
Test status
Simulation time 423110276 ps
CPU time 2.22 seconds
Started Jul 28 05:04:53 PM PDT 24
Finished Jul 28 05:04:55 PM PDT 24
Peak memory 205764 kb
Host smart-8abe69d6-0373-4242-b0ff-86601aea68d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447924651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_smbus_maxlen.2447924651
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.2298055084
Short name T528
Test name
Test status
Simulation time 3349136319 ps
CPU time 10.12 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:05:15 PM PDT 24
Peak memory 218284 kb
Host smart-6442616a-2eb3-4c78-9717-68939d40a5f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298055084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.2298055084
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.468657052
Short name T1618
Test name
Test status
Simulation time 60093948225 ps
CPU time 1000.75 seconds
Started Jul 28 05:04:45 PM PDT 24
Finished Jul 28 05:21:26 PM PDT 24
Peak memory 3991320 kb
Host smart-b9f139f9-e4e2-4098-b2c8-db8dab4be8a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468657052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_target_stress_all.468657052
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.2034179888
Short name T1270
Test name
Test status
Simulation time 5834745632 ps
CPU time 60.64 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:06:10 PM PDT 24
Peak memory 215652 kb
Host smart-6e7828f1-b55a-4185-9c32-4dc2fdf28e9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034179888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.2034179888
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.864736102
Short name T1086
Test name
Test status
Simulation time 30068470103 ps
CPU time 198.82 seconds
Started Jul 28 05:04:46 PM PDT 24
Finished Jul 28 05:08:05 PM PDT 24
Peak memory 2519040 kb
Host smart-a4c46fed-5e6a-408d-9cbd-ba16294a571b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864736102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_wr.864736102
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.106583848
Short name T392
Test name
Test status
Simulation time 766865501 ps
CPU time 5.87 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:12 PM PDT 24
Peak memory 223472 kb
Host smart-8da3fe62-5c29-4039-ab6a-f0d9cdaa7b57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106583848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_t
arget_stretch.106583848
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.4128511786
Short name T116
Test name
Test status
Simulation time 3660427728 ps
CPU time 6.61 seconds
Started Jul 28 05:04:58 PM PDT 24
Finished Jul 28 05:05:04 PM PDT 24
Peak memory 214184 kb
Host smart-2a935aa0-7fe1-4040-9137-1b5e2bfe013f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128511786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.4128511786
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.1571898704
Short name T1107
Test name
Test status
Simulation time 320874226 ps
CPU time 4.42 seconds
Started Jul 28 05:04:49 PM PDT 24
Finished Jul 28 05:04:54 PM PDT 24
Peak memory 215116 kb
Host smart-2527f109-c5d9-4106-8277-72bbb33f60b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571898704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.1571898704
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1862242626
Short name T1405
Test name
Test status
Simulation time 125089217 ps
CPU time 0.62 seconds
Started Jul 28 05:04:57 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 205060 kb
Host smart-df0eed5b-3253-4730-bbde-167f1c1e632d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862242626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1862242626
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1690528860
Short name T633
Test name
Test status
Simulation time 149454073 ps
CPU time 1.67 seconds
Started Jul 28 05:04:58 PM PDT 24
Finished Jul 28 05:04:59 PM PDT 24
Peak memory 214968 kb
Host smart-c9e33da5-ead1-4ba4-9c94-025e66063933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690528860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1690528860
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2758988618
Short name T738
Test name
Test status
Simulation time 1799662466 ps
CPU time 9.9 seconds
Started Jul 28 05:04:59 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 309372 kb
Host smart-d91f0f35-f9e6-49a7-80d7-90a69992defb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758988618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2758988618
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.927044001
Short name T502
Test name
Test status
Simulation time 18093998018 ps
CPU time 71.65 seconds
Started Jul 28 05:05:23 PM PDT 24
Finished Jul 28 05:06:35 PM PDT 24
Peak memory 424768 kb
Host smart-7bb134de-346f-4166-ac83-6eb28e951fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927044001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.927044001
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3516475930
Short name T871
Test name
Test status
Simulation time 4205654501 ps
CPU time 153.5 seconds
Started Jul 28 05:04:59 PM PDT 24
Finished Jul 28 05:07:32 PM PDT 24
Peak memory 692200 kb
Host smart-72b0f783-27ec-450b-b21f-29e3f289cf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516475930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3516475930
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.4005288879
Short name T129
Test name
Test status
Simulation time 163922523 ps
CPU time 1.38 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 205648 kb
Host smart-9ad9e81c-7bd9-42fe-bc58-776310dda962
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005288879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.4005288879
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2811925617
Short name T354
Test name
Test status
Simulation time 1556425496 ps
CPU time 4.61 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 237480 kb
Host smart-fb5f33a9-c1b6-4324-aa42-6223ed0b51d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811925617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2811925617
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.4171382373
Short name T1539
Test name
Test status
Simulation time 5079041307 ps
CPU time 125.32 seconds
Started Jul 28 05:04:48 PM PDT 24
Finished Jul 28 05:06:54 PM PDT 24
Peak memory 1234504 kb
Host smart-431f414e-2cf5-4a44-aeac-586ac8303709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171382373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.4171382373
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.328564626
Short name T1271
Test name
Test status
Simulation time 581597617 ps
CPU time 7.14 seconds
Started Jul 28 05:04:57 PM PDT 24
Finished Jul 28 05:05:04 PM PDT 24
Peak memory 205624 kb
Host smart-09d642a1-c1fe-439f-b396-b9c2cbf2a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328564626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.328564626
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_override.2314576645
Short name T1501
Test name
Test status
Simulation time 27374234 ps
CPU time 0.67 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 205388 kb
Host smart-1ccf7405-c6ba-43f8-8184-7a1781e4c119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314576645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2314576645
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.431918063
Short name T879
Test name
Test status
Simulation time 24254358646 ps
CPU time 437.07 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:12:27 PM PDT 24
Peak memory 1484916 kb
Host smart-48058043-e93f-4585-a9a1-371f1896c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431918063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.431918063
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.1549215508
Short name T706
Test name
Test status
Simulation time 182349392 ps
CPU time 2.15 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 226128 kb
Host smart-4ad70dd1-b713-4ce1-8e62-068c12ab6397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549215508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.1549215508
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1911315751
Short name T1394
Test name
Test status
Simulation time 1109301701 ps
CPU time 51.88 seconds
Started Jul 28 05:05:02 PM PDT 24
Finished Jul 28 05:05:54 PM PDT 24
Peak memory 324720 kb
Host smart-373aa4e7-00b0-42e2-973e-5d7ab9c21ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911315751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1911315751
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1469084027
Short name T240
Test name
Test status
Simulation time 16962281072 ps
CPU time 140.75 seconds
Started Jul 28 05:04:53 PM PDT 24
Finished Jul 28 05:07:14 PM PDT 24
Peak memory 856856 kb
Host smart-9c670a61-3229-42d3-ac1b-ad2e89cd7d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469084027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1469084027
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1269767638
Short name T274
Test name
Test status
Simulation time 3012099033 ps
CPU time 33.07 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:05:40 PM PDT 24
Peak memory 214036 kb
Host smart-65cafd6b-7a95-403d-bc66-1a62d19a8685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269767638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1269767638
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.227285958
Short name T1635
Test name
Test status
Simulation time 13260997367 ps
CPU time 6.17 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:05:13 PM PDT 24
Peak memory 222340 kb
Host smart-a776f724-dbcb-4bbf-a21b-4cc831809301
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227285958 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.227285958
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2387513682
Short name T523
Test name
Test status
Simulation time 713380948 ps
CPU time 1.64 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:10 PM PDT 24
Peak memory 205924 kb
Host smart-c7b4814a-269e-469c-bfe8-945d178a883f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387513682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2387513682
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1125204753
Short name T608
Test name
Test status
Simulation time 590428495 ps
CPU time 1.03 seconds
Started Jul 28 05:05:03 PM PDT 24
Finished Jul 28 05:05:04 PM PDT 24
Peak memory 205748 kb
Host smart-49e5d2ff-e3a8-4cbb-9e58-f3081881b250
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125204753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1125204753
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.1527467837
Short name T933
Test name
Test status
Simulation time 363326921 ps
CPU time 2.63 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:08 PM PDT 24
Peak memory 205836 kb
Host smart-da791af1-d36d-46e0-89cb-bf4c7fbb065f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527467837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.1527467837
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.3027473285
Short name T168
Test name
Test status
Simulation time 799789045 ps
CPU time 1.53 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:05:08 PM PDT 24
Peak memory 205764 kb
Host smart-09b8c0e5-5018-43c2-aea8-90a7a53a382b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027473285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.3027473285
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2848883137
Short name T45
Test name
Test status
Simulation time 335040749 ps
CPU time 2.81 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:11 PM PDT 24
Peak memory 214100 kb
Host smart-8b2fe98a-c32d-44aa-843a-a2d207b4f229
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848883137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2848883137
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.334926229
Short name T1228
Test name
Test status
Simulation time 1058315560 ps
CPU time 6.97 seconds
Started Jul 28 05:05:01 PM PDT 24
Finished Jul 28 05:05:08 PM PDT 24
Peak memory 214692 kb
Host smart-d30d1e33-7202-4b70-a7f5-ac7cd989c9a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334926229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.334926229
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1914422658
Short name T656
Test name
Test status
Simulation time 13143706777 ps
CPU time 260.8 seconds
Started Jul 28 05:04:54 PM PDT 24
Finished Jul 28 05:09:15 PM PDT 24
Peak memory 3191028 kb
Host smart-649cdeac-6dc6-4673-989d-264534d5737b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914422658 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1914422658
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.3291858869
Short name T1207
Test name
Test status
Simulation time 2039491251 ps
CPU time 3.1 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:08 PM PDT 24
Peak memory 214200 kb
Host smart-e439209b-cbf8-48d7-861d-9e287289e072
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291858869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_nack_acqfull.3291858869
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.690133058
Short name T1412
Test name
Test status
Simulation time 440020366 ps
CPU time 2.64 seconds
Started Jul 28 05:05:03 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 205816 kb
Host smart-968558c2-2030-4909-9666-67683e504dd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690133058 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.690133058
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_txstretch.742611274
Short name T1521
Test name
Test status
Simulation time 543508311 ps
CPU time 1.43 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 222408 kb
Host smart-ee85f53d-2fc9-413c-97d2-8ffbf5032bf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742611274 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_nack_txstretch.742611274
Directory /workspace/28.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/28.i2c_target_perf.1738487942
Short name T724
Test name
Test status
Simulation time 1157608826 ps
CPU time 4.65 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:05:14 PM PDT 24
Peak memory 220440 kb
Host smart-8b66bf41-65cf-47b9-ae6c-79ae2f57f94c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738487942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.1738487942
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.1386763678
Short name T1078
Test name
Test status
Simulation time 3241934674 ps
CPU time 2.46 seconds
Started Jul 28 05:04:57 PM PDT 24
Finished Jul 28 05:05:00 PM PDT 24
Peak memory 205764 kb
Host smart-a62d8d48-b300-459d-884c-db52f34252f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386763678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_smbus_maxlen.1386763678
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1812215018
Short name T802
Test name
Test status
Simulation time 673041605 ps
CPU time 8.41 seconds
Started Jul 28 05:04:53 PM PDT 24
Finished Jul 28 05:05:02 PM PDT 24
Peak memory 214192 kb
Host smart-5ba0a7af-98f4-49a3-a851-b240f9a769a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812215018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1812215018
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.2483568667
Short name T1718
Test name
Test status
Simulation time 28878034911 ps
CPU time 33.25 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:39 PM PDT 24
Peak memory 240188 kb
Host smart-18062090-55d5-4c57-91a9-b6942791012f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483568667 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_stress_all.2483568667
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.151364171
Short name T1141
Test name
Test status
Simulation time 11192104971 ps
CPU time 16.87 seconds
Started Jul 28 05:04:52 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 223696 kb
Host smart-837c23a2-9ec6-4c10-8de4-25aecc428e77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151364171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.151364171
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1168450149
Short name T214
Test name
Test status
Simulation time 22220749363 ps
CPU time 49.8 seconds
Started Jul 28 05:04:56 PM PDT 24
Finished Jul 28 05:05:46 PM PDT 24
Peak memory 570124 kb
Host smart-506a9bf4-6b01-4087-beb5-76f91286218e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168450149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1168450149
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3257966955
Short name T1589
Test name
Test status
Simulation time 2929643366 ps
CPU time 70.37 seconds
Started Jul 28 05:05:14 PM PDT 24
Finished Jul 28 05:06:24 PM PDT 24
Peak memory 539332 kb
Host smart-3ccad882-b1c1-452c-8ffc-58b847f20c99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257966955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3257966955
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3253047157
Short name T1253
Test name
Test status
Simulation time 1466805147 ps
CPU time 7.16 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:13 PM PDT 24
Peak memory 214156 kb
Host smart-6f871c31-3d5c-49b0-9c62-8ce5f4e7a495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253047157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3253047157
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.2647470134
Short name T1122
Test name
Test status
Simulation time 132407495 ps
CPU time 1.91 seconds
Started Jul 28 05:05:02 PM PDT 24
Finished Jul 28 05:05:04 PM PDT 24
Peak memory 205944 kb
Host smart-bb27befd-0099-472e-ae29-72ecf9125e4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647470134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.2647470134
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1852654718
Short name T1236
Test name
Test status
Simulation time 16310959 ps
CPU time 0.62 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 204932 kb
Host smart-3950433d-1a72-419b-adfc-a980a182113b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852654718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1852654718
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3849782598
Short name T29
Test name
Test status
Simulation time 151353986 ps
CPU time 2.23 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 215000 kb
Host smart-fcaa1070-3505-4637-87e8-d074e6afe7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849782598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3849782598
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.4014498890
Short name T1259
Test name
Test status
Simulation time 1068403665 ps
CPU time 4.58 seconds
Started Jul 28 05:05:02 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 259264 kb
Host smart-3e04bf7e-13b1-4b98-9662-e6ace97b9b19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014498890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.4014498890
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3898999931
Short name T27
Test name
Test status
Simulation time 7784875164 ps
CPU time 114.24 seconds
Started Jul 28 05:05:12 PM PDT 24
Finished Jul 28 05:07:07 PM PDT 24
Peak memory 473056 kb
Host smart-16f5ba64-a093-4cbc-bc96-faf5b87e600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898999931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3898999931
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.42835636
Short name T128
Test name
Test status
Simulation time 1461518462 ps
CPU time 44.51 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 540448 kb
Host smart-6ccb6349-fff1-41cc-bb9e-1af1b0a8d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42835636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.42835636
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3037326055
Short name T662
Test name
Test status
Simulation time 425259782 ps
CPU time 0.95 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 205504 kb
Host smart-b8d708c5-b581-4036-b343-5d73e9a52b09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037326055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3037326055
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2853667158
Short name T385
Test name
Test status
Simulation time 2522651539 ps
CPU time 10.27 seconds
Started Jul 28 05:05:10 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 239988 kb
Host smart-2473331a-fdad-4f2c-9454-568a066f7c18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853667158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2853667158
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.251952192
Short name T36
Test name
Test status
Simulation time 11807972949 ps
CPU time 116.98 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 1164520 kb
Host smart-68946231-0c3d-4dae-8cd5-b7489288f7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251952192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.251952192
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_override.3905745815
Short name T1144
Test name
Test status
Simulation time 29104613 ps
CPU time 0.7 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:05:10 PM PDT 24
Peak memory 205408 kb
Host smart-6b84175f-6069-436c-ad98-94cdea417a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905745815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3905745815
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3553723301
Short name T40
Test name
Test status
Simulation time 2629802871 ps
CPU time 99.07 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:06:46 PM PDT 24
Peak memory 224096 kb
Host smart-cca0c2fb-61d5-4948-8359-c25ec1164e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553723301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3553723301
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.1128974344
Short name T334
Test name
Test status
Simulation time 334966528 ps
CPU time 14.85 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 206416 kb
Host smart-ecd2f136-2a96-48ef-8118-d04ac008fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128974344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.1128974344
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.725969311
Short name T1593
Test name
Test status
Simulation time 6700261519 ps
CPU time 30.17 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:41 PM PDT 24
Peak memory 390640 kb
Host smart-e51e3ad2-0193-435e-8fd7-c0753713f589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725969311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.725969311
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.1687452722
Short name T286
Test name
Test status
Simulation time 189360514499 ps
CPU time 2438.49 seconds
Started Jul 28 05:05:15 PM PDT 24
Finished Jul 28 05:45:54 PM PDT 24
Peak memory 3248632 kb
Host smart-24b8f9f2-e2c5-4c70-a243-2514c688c59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687452722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.1687452722
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3860970062
Short name T969
Test name
Test status
Simulation time 865406062 ps
CPU time 16.8 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:25 PM PDT 24
Peak memory 222056 kb
Host smart-ff449a70-c279-4f3f-915d-ae9f0e581d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860970062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3860970062
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.483716995
Short name T351
Test name
Test status
Simulation time 213307397 ps
CPU time 0.98 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 205704 kb
Host smart-4880609f-e6fc-4d5d-86ca-8098075e4f67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483716995 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.483716995
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.2844193893
Short name T1744
Test name
Test status
Simulation time 238215420 ps
CPU time 1.11 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:10 PM PDT 24
Peak memory 205916 kb
Host smart-9c54fd45-3b54-4978-91cf-b8b733de0a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844193893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.2844193893
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.1317837777
Short name T1337
Test name
Test status
Simulation time 1667176091 ps
CPU time 2.48 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 205864 kb
Host smart-d47ead45-768a-4062-bd81-12ed5209723b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317837777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.1317837777
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2126885843
Short name T664
Test name
Test status
Simulation time 360525522 ps
CPU time 0.99 seconds
Started Jul 28 05:05:12 PM PDT 24
Finished Jul 28 05:05:18 PM PDT 24
Peak memory 205688 kb
Host smart-d9011366-1db9-4c27-9fbe-6d31ac0ab87b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126885843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2126885843
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3539758979
Short name T813
Test name
Test status
Simulation time 359691495 ps
CPU time 2.63 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:11 PM PDT 24
Peak memory 214188 kb
Host smart-13246bde-992f-40aa-a6e1-526439d0d60e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539758979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3539758979
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2224568065
Short name T1315
Test name
Test status
Simulation time 3482679346 ps
CPU time 5.06 seconds
Started Jul 28 05:05:10 PM PDT 24
Finished Jul 28 05:05:15 PM PDT 24
Peak memory 214280 kb
Host smart-97394404-bc74-49ff-9b2b-34924dd9c752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224568065 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2224568065
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.410821880
Short name T467
Test name
Test status
Simulation time 22505293219 ps
CPU time 499.75 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:13:25 PM PDT 24
Peak memory 3880148 kb
Host smart-671f2d39-8cf3-4521-b92f-bc0de85a0043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410821880 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.410821880
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.225046135
Short name T673
Test name
Test status
Simulation time 550105055 ps
CPU time 3.03 seconds
Started Jul 28 05:05:00 PM PDT 24
Finished Jul 28 05:05:04 PM PDT 24
Peak memory 214056 kb
Host smart-3d27149a-879c-4bda-93d0-dfe5ca80fd35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225046135 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_nack_acqfull.225046135
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.2110021598
Short name T1334
Test name
Test status
Simulation time 993945248 ps
CPU time 2.71 seconds
Started Jul 28 05:05:02 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 205964 kb
Host smart-aa3b33d9-4cdb-4103-a9d7-87c7c5276fae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110021598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.2110021598
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_txstretch.1331756992
Short name T164
Test name
Test status
Simulation time 580786068 ps
CPU time 1.4 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:08 PM PDT 24
Peak memory 222676 kb
Host smart-dfbb3bf0-0334-47b8-8d14-e02cf58f5ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331756992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_nack_txstretch.1331756992
Directory /workspace/29.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/29.i2c_target_perf.1728648733
Short name T317
Test name
Test status
Simulation time 4782953863 ps
CPU time 5.57 seconds
Started Jul 28 05:05:01 PM PDT 24
Finished Jul 28 05:05:07 PM PDT 24
Peak memory 222376 kb
Host smart-ae410cb9-b884-49fb-a5e4-bf097aaadbee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728648733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.1728648733
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.2371295949
Short name T321
Test name
Test status
Simulation time 443562760 ps
CPU time 2.14 seconds
Started Jul 28 05:05:03 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 205648 kb
Host smart-1cf46718-f968-4cee-906c-66cf94d73878
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371295949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.2371295949
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.4204973239
Short name T891
Test name
Test status
Simulation time 986266938 ps
CPU time 30.88 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 222316 kb
Host smart-cb6fadab-b102-4a60-8648-5d68b726d7db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204973239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.4204973239
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.3477451454
Short name T1300
Test name
Test status
Simulation time 22460614670 ps
CPU time 428.33 seconds
Started Jul 28 05:04:55 PM PDT 24
Finished Jul 28 05:12:03 PM PDT 24
Peak memory 3322460 kb
Host smart-e84c1023-036b-42a0-a87a-5316f2673a63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477451454 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.3477451454
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1204178360
Short name T1191
Test name
Test status
Simulation time 1483645185 ps
CPU time 67.71 seconds
Started Jul 28 05:05:13 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 217984 kb
Host smart-0f59f5eb-3e9f-457c-a2cb-a7acb5cb92fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204178360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1204178360
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2185074449
Short name T1296
Test name
Test status
Simulation time 31805919261 ps
CPU time 42.59 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:54 PM PDT 24
Peak memory 821168 kb
Host smart-20e8c2fd-f4ab-4468-9619-6ae200f5ad3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185074449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2185074449
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1902526838
Short name T703
Test name
Test status
Simulation time 257324598 ps
CPU time 1.15 seconds
Started Jul 28 05:05:19 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 205704 kb
Host smart-0fd56d10-40c4-44d1-8e0a-3d3baf0c2d89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902526838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1902526838
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2745213566
Short name T389
Test name
Test status
Simulation time 1407973321 ps
CPU time 7.02 seconds
Started Jul 28 05:05:02 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 222236 kb
Host smart-ae534385-3b89-4fbf-a11c-7f1cf01b4dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745213566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2745213566
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.1072859399
Short name T509
Test name
Test status
Simulation time 589060888 ps
CPU time 8.16 seconds
Started Jul 28 05:05:03 PM PDT 24
Finished Jul 28 05:05:12 PM PDT 24
Peak memory 205944 kb
Host smart-df021084-bf92-495a-b945-adfd2f702be8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072859399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.1072859399
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3726007325
Short name T756
Test name
Test status
Simulation time 18370241 ps
CPU time 0.62 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:02:56 PM PDT 24
Peak memory 204944 kb
Host smart-72f8782f-5399-4867-ac62-e788a9cbe2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726007325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3726007325
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.157205861
Short name T1360
Test name
Test status
Simulation time 610372505 ps
CPU time 2.64 seconds
Started Jul 28 05:02:39 PM PDT 24
Finished Jul 28 05:02:42 PM PDT 24
Peak memory 225256 kb
Host smart-6263a408-0bfb-4abb-90b5-639ffc054f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157205861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.157205861
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2035701005
Short name T482
Test name
Test status
Simulation time 415701657 ps
CPU time 7.85 seconds
Started Jul 28 05:03:00 PM PDT 24
Finished Jul 28 05:03:08 PM PDT 24
Peak memory 296236 kb
Host smart-6d1e07b6-d91f-4614-b7a7-e33d6aa185a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035701005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2035701005
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.164969500
Short name T943
Test name
Test status
Simulation time 11791145535 ps
CPU time 101.96 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:04:36 PM PDT 24
Peak memory 754884 kb
Host smart-61079135-3b60-4393-8393-a53e2b2d296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164969500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.164969500
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.386493045
Short name T1046
Test name
Test status
Simulation time 5235095181 ps
CPU time 97.2 seconds
Started Jul 28 05:03:06 PM PDT 24
Finished Jul 28 05:04:44 PM PDT 24
Peak memory 846204 kb
Host smart-41519786-32fe-4add-b926-e21b59adb4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386493045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.386493045
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.405783206
Short name T1692
Test name
Test status
Simulation time 736604539 ps
CPU time 0.96 seconds
Started Jul 28 05:03:00 PM PDT 24
Finished Jul 28 05:03:01 PM PDT 24
Peak memory 205408 kb
Host smart-7b353d29-3d8c-4a4b-9774-7c62e316e94d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405783206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.405783206
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1235826049
Short name T592
Test name
Test status
Simulation time 695186232 ps
CPU time 7.43 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:03:03 PM PDT 24
Peak memory 228492 kb
Host smart-f5a49320-4e84-4581-a0b2-af59e173285b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235826049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1235826049
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2778660429
Short name T1477
Test name
Test status
Simulation time 18859223349 ps
CPU time 48.23 seconds
Started Jul 28 05:02:45 PM PDT 24
Finished Jul 28 05:03:34 PM PDT 24
Peak memory 698676 kb
Host smart-c5c8444a-91f1-4477-82b9-ecda29a0bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778660429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2778660429
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.763757913
Short name T262
Test name
Test status
Simulation time 414246668 ps
CPU time 15.92 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:03:09 PM PDT 24
Peak memory 205748 kb
Host smart-b5ad16b6-9eb9-47fb-92b9-170920801edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763757913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.763757913
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_override.3763755522
Short name T1470
Test name
Test status
Simulation time 30327629 ps
CPU time 0.64 seconds
Started Jul 28 05:02:45 PM PDT 24
Finished Jul 28 05:02:46 PM PDT 24
Peak memory 205440 kb
Host smart-8dcad54f-9598-41b4-8556-f219c01f5b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763755522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3763755522
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3763008284
Short name T886
Test name
Test status
Simulation time 2775479691 ps
CPU time 16.54 seconds
Started Jul 28 05:02:46 PM PDT 24
Finished Jul 28 05:03:03 PM PDT 24
Peak memory 241952 kb
Host smart-82bc2fc3-1c4f-4d48-ae53-d860dff1f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763008284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3763008284
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.2811320485
Short name T113
Test name
Test status
Simulation time 997160628 ps
CPU time 2.99 seconds
Started Jul 28 05:03:09 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 228240 kb
Host smart-0f1712ee-ad3b-4357-9319-7bfd980b91e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811320485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.2811320485
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3929854431
Short name T1487
Test name
Test status
Simulation time 2128929141 ps
CPU time 103.88 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:04:33 PM PDT 24
Peak memory 387648 kb
Host smart-22d68ef5-b378-4c90-8704-5723210ef434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929854431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3929854431
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1613365176
Short name T1110
Test name
Test status
Simulation time 2009366173 ps
CPU time 44.14 seconds
Started Jul 28 05:02:50 PM PDT 24
Finished Jul 28 05:03:35 PM PDT 24
Peak memory 213944 kb
Host smart-43f065b1-2e3e-4dbe-b0df-91a82a38d761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613365176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1613365176
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1011439747
Short name T187
Test name
Test status
Simulation time 70506984 ps
CPU time 0.93 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:02:52 PM PDT 24
Peak memory 224164 kb
Host smart-7bfc1f29-9f79-4a3f-8f14-377bdd463ba6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011439747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1011439747
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3583733626
Short name T1079
Test name
Test status
Simulation time 849195449 ps
CPU time 3.84 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:02:55 PM PDT 24
Peak memory 214868 kb
Host smart-c217f209-7b9a-44c4-a647-b6fab75a7bf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583733626 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3583733626
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2362595512
Short name T911
Test name
Test status
Simulation time 297695859 ps
CPU time 1.12 seconds
Started Jul 28 05:02:58 PM PDT 24
Finished Jul 28 05:02:59 PM PDT 24
Peak memory 205940 kb
Host smart-38430a98-0fd6-4516-b34b-00db8c223ec2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362595512 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2362595512
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.4135019781
Short name T1116
Test name
Test status
Simulation time 694506316 ps
CPU time 1.31 seconds
Started Jul 28 05:02:52 PM PDT 24
Finished Jul 28 05:02:53 PM PDT 24
Peak memory 205880 kb
Host smart-184a1b23-4f91-4fe5-9c06-7588bb7a320f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135019781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.4135019781
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.144232604
Short name T542
Test name
Test status
Simulation time 386996524 ps
CPU time 2.31 seconds
Started Jul 28 05:02:43 PM PDT 24
Finished Jul 28 05:02:45 PM PDT 24
Peak memory 205920 kb
Host smart-0989ec9e-afe8-45d9-a4a7-bbf54f914d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144232604 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.144232604
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.1592896426
Short name T1274
Test name
Test status
Simulation time 579449619 ps
CPU time 1.61 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:05 PM PDT 24
Peak memory 205768 kb
Host smart-4dcd08e8-a61f-4b5f-ba7c-2a43d088ca8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592896426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1592896426
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2858237080
Short name T799
Test name
Test status
Simulation time 904192166 ps
CPU time 4.71 seconds
Started Jul 28 05:03:12 PM PDT 24
Finished Jul 28 05:03:17 PM PDT 24
Peak memory 222264 kb
Host smart-6cc72946-e0e7-46e7-9ffc-d369c85234e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858237080 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2858237080
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2336256140
Short name T1711
Test name
Test status
Simulation time 1408487817 ps
CPU time 1.77 seconds
Started Jul 28 05:02:50 PM PDT 24
Finished Jul 28 05:02:52 PM PDT 24
Peak memory 205940 kb
Host smart-d3d7c49a-e5a9-4045-905c-b12a3fb8a8c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336256140 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2336256140
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.3415865120
Short name T711
Test name
Test status
Simulation time 504625119 ps
CPU time 2.72 seconds
Started Jul 28 05:03:12 PM PDT 24
Finished Jul 28 05:03:15 PM PDT 24
Peak memory 214160 kb
Host smart-1c64c151-0d16-471a-91a3-83613a7e49fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415865120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_acqfull.3415865120
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.919462078
Short name T1506
Test name
Test status
Simulation time 1237526031 ps
CPU time 2.79 seconds
Started Jul 28 05:02:58 PM PDT 24
Finished Jul 28 05:03:01 PM PDT 24
Peak memory 205960 kb
Host smart-e7c8774a-7792-4e6c-a396-90b054a05379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919462078 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.919462078
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_txstretch.991686197
Short name T160
Test name
Test status
Simulation time 145737349 ps
CPU time 1.36 seconds
Started Jul 28 05:03:12 PM PDT 24
Finished Jul 28 05:03:14 PM PDT 24
Peak memory 222672 kb
Host smart-492d26da-92b7-4c94-b876-f7eb4a2bcc5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991686197 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_nack_txstretch.991686197
Directory /workspace/3.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/3.i2c_target_perf.4100756954
Short name T1264
Test name
Test status
Simulation time 2533785952 ps
CPU time 4.89 seconds
Started Jul 28 05:02:59 PM PDT 24
Finished Jul 28 05:03:04 PM PDT 24
Peak memory 222216 kb
Host smart-73f6f1cd-2a06-4584-a0f5-6ea3bf27e050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100756954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.4100756954
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.3729516941
Short name T1092
Test name
Test status
Simulation time 4506083682 ps
CPU time 2 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:02:58 PM PDT 24
Peak memory 205848 kb
Host smart-138aaf87-9f75-4355-8a5a-85dc686a0472
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729516941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_smbus_maxlen.3729516941
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1006608402
Short name T1082
Test name
Test status
Simulation time 830421870 ps
CPU time 12.02 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:03:00 PM PDT 24
Peak memory 214200 kb
Host smart-d6471319-f326-4b35-9e97-21cc0acfca4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006608402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1006608402
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.2808072306
Short name T833
Test name
Test status
Simulation time 54703677120 ps
CPU time 1380.93 seconds
Started Jul 28 05:03:17 PM PDT 24
Finished Jul 28 05:26:18 PM PDT 24
Peak memory 4755584 kb
Host smart-b1ba201c-0479-4399-9446-5c6597fbd05f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808072306 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.2808072306
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1968543794
Short name T605
Test name
Test status
Simulation time 1486456920 ps
CPU time 21.85 seconds
Started Jul 28 05:03:06 PM PDT 24
Finished Jul 28 05:03:28 PM PDT 24
Peak memory 205876 kb
Host smart-ae52af60-e7f1-4531-a547-02fe0f5b31d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968543794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1968543794
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2665487646
Short name T1097
Test name
Test status
Simulation time 10183833166 ps
CPU time 6.17 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:03:03 PM PDT 24
Peak memory 206080 kb
Host smart-0aaf278c-6109-45f7-acb4-5ec84d31bb4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665487646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2665487646
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.252843428
Short name T1155
Test name
Test status
Simulation time 1594971979 ps
CPU time 1.27 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:02:55 PM PDT 24
Peak memory 214132 kb
Host smart-be07c12b-8187-431d-ad1d-709d61c30c45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252843428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.252843428
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2971276314
Short name T709
Test name
Test status
Simulation time 2684846338 ps
CPU time 6.51 seconds
Started Jul 28 05:02:52 PM PDT 24
Finished Jul 28 05:02:59 PM PDT 24
Peak memory 214172 kb
Host smart-83936a2f-5671-47f8-8da6-7d81f2ad41a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971276314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2971276314
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.3749016001
Short name T1659
Test name
Test status
Simulation time 763143891 ps
CPU time 9.03 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:03:10 PM PDT 24
Peak memory 205912 kb
Host smart-4046e6ee-b118-4618-8f8b-af13a869c0ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749016001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.3749016001
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.895485881
Short name T1117
Test name
Test status
Simulation time 17772346 ps
CPU time 0.68 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:12 PM PDT 24
Peak memory 205052 kb
Host smart-f6ded2e9-bff9-4435-8a88-ad06e16e6f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895485881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.895485881
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.703165786
Short name T421
Test name
Test status
Simulation time 259512940 ps
CPU time 1.97 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 214052 kb
Host smart-44b06148-18f3-4519-b4cf-51a16dbce509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703165786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.703165786
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2042141960
Short name T1454
Test name
Test status
Simulation time 658719085 ps
CPU time 16.19 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 271728 kb
Host smart-b45da2a0-789c-401f-aaf3-8c62c53efb4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042141960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2042141960
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.704284258
Short name T1318
Test name
Test status
Simulation time 10678915605 ps
CPU time 158.67 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:07:45 PM PDT 24
Peak memory 517588 kb
Host smart-f5af17a6-ccbf-41c7-8e2f-9eb42758d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704284258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.704284258
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3583626125
Short name T1354
Test name
Test status
Simulation time 9401610153 ps
CPU time 179.32 seconds
Started Jul 28 05:04:58 PM PDT 24
Finished Jul 28 05:07:58 PM PDT 24
Peak memory 764048 kb
Host smart-47eec167-6436-4158-ba6c-bd241c474a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583626125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3583626125
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3272100380
Short name T1279
Test name
Test status
Simulation time 146670730 ps
CPU time 1.27 seconds
Started Jul 28 05:05:01 PM PDT 24
Finished Jul 28 05:05:02 PM PDT 24
Peak memory 205480 kb
Host smart-b46da279-7d46-4b63-9964-00ec0176c0a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272100380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3272100380
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.4199767844
Short name T716
Test name
Test status
Simulation time 142640657 ps
CPU time 7.45 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:05:17 PM PDT 24
Peak memory 228380 kb
Host smart-1011dfb8-771e-4ed4-898f-d7dd85bb313e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199767844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.4199767844
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2927854351
Short name T1425
Test name
Test status
Simulation time 10822435609 ps
CPU time 64.84 seconds
Started Jul 28 05:05:04 PM PDT 24
Finished Jul 28 05:06:09 PM PDT 24
Peak memory 896596 kb
Host smart-37c646c4-a9cd-4a46-bea4-862969d1699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927854351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2927854351
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.17460685
Short name T612
Test name
Test status
Simulation time 1974462042 ps
CPU time 6.22 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:17 PM PDT 24
Peak memory 205712 kb
Host smart-49a807e8-6d0e-4360-a66d-ec52d3c80d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17460685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.17460685
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.4200464374
Short name T654
Test name
Test status
Simulation time 18849272 ps
CPU time 0.66 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 205428 kb
Host smart-7cae6d9d-2c40-467f-9cfa-d91a321fe319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200464374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.4200464374
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2098539675
Short name T1348
Test name
Test status
Simulation time 51933320971 ps
CPU time 494.32 seconds
Started Jul 28 05:05:02 PM PDT 24
Finished Jul 28 05:13:16 PM PDT 24
Peak memory 1394852 kb
Host smart-406bbed0-6e3a-481a-8cc1-8d0fe17521a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098539675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2098539675
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.863309236
Short name T87
Test name
Test status
Simulation time 23177832293 ps
CPU time 882.44 seconds
Started Jul 28 05:05:12 PM PDT 24
Finished Jul 28 05:19:54 PM PDT 24
Peak memory 205728 kb
Host smart-9b774802-d4ed-429f-8b4a-067d323093ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863309236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.863309236
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.4017728156
Short name T1390
Test name
Test status
Simulation time 1481915895 ps
CPU time 69.36 seconds
Started Jul 28 05:05:14 PM PDT 24
Finished Jul 28 05:06:24 PM PDT 24
Peak memory 331976 kb
Host smart-c859ee0b-437f-4984-81ae-8b501056a498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017728156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.4017728156
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2835981102
Short name T1644
Test name
Test status
Simulation time 50918187976 ps
CPU time 301.87 seconds
Started Jul 28 05:05:45 PM PDT 24
Finished Jul 28 05:10:47 PM PDT 24
Peak memory 1032116 kb
Host smart-15cb4826-0046-4365-a03e-cdd4d02114c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835981102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2835981102
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2217375811
Short name T1725
Test name
Test status
Simulation time 2941486962 ps
CPU time 13.95 seconds
Started Jul 28 05:05:20 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 217796 kb
Host smart-ab8efa1c-1d6d-4844-8969-ba9f4efc3470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217375811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2217375811
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2034798008
Short name T411
Test name
Test status
Simulation time 2938013274 ps
CPU time 7.2 seconds
Started Jul 28 05:05:10 PM PDT 24
Finished Jul 28 05:05:17 PM PDT 24
Peak memory 216072 kb
Host smart-4ef73332-3004-4429-8192-427a8d0ab7e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034798008 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2034798008
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2951265231
Short name T301
Test name
Test status
Simulation time 231334310 ps
CPU time 1.38 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:10 PM PDT 24
Peak memory 205904 kb
Host smart-fd256215-1709-434e-a02f-ebf91f12a0db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951265231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2951265231
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.972069227
Short name T744
Test name
Test status
Simulation time 784889694 ps
CPU time 0.89 seconds
Started Jul 28 05:05:25 PM PDT 24
Finished Jul 28 05:05:26 PM PDT 24
Peak memory 205752 kb
Host smart-b6a68670-9965-4ad4-a7f9-0236264010f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972069227 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.972069227
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.175091940
Short name T341
Test name
Test status
Simulation time 693185399 ps
CPU time 2.31 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 205924 kb
Host smart-2a656113-3f1f-4ce4-8a16-70aaecf1c3be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175091940 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.175091940
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.1278627579
Short name T1226
Test name
Test status
Simulation time 158584708 ps
CPU time 0.98 seconds
Started Jul 28 05:05:16 PM PDT 24
Finished Jul 28 05:05:18 PM PDT 24
Peak memory 205728 kb
Host smart-ec93c84f-fd90-4e8a-8949-394a566c4d62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278627579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.1278627579
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2755253060
Short name T1498
Test name
Test status
Simulation time 1496855402 ps
CPU time 2.16 seconds
Started Jul 28 05:05:10 PM PDT 24
Finished Jul 28 05:05:12 PM PDT 24
Peak memory 214056 kb
Host smart-6283ba02-1ae0-40a4-af25-7379c59490eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755253060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2755253060
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.92628961
Short name T854
Test name
Test status
Simulation time 1124109297 ps
CPU time 6.1 seconds
Started Jul 28 05:05:28 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 218184 kb
Host smart-dd8fa2d8-6bbe-4bb3-be4f-5b5baf4d7cb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92628961 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.92628961
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1186576275
Short name T1393
Test name
Test status
Simulation time 8562812157 ps
CPU time 39.32 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 1017332 kb
Host smart-25c28bca-33d7-493c-9270-69af55055906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186576275 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1186576275
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.2334388573
Short name T1755
Test name
Test status
Simulation time 705206212 ps
CPU time 2.47 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 205912 kb
Host smart-424e5dea-ac4f-417e-a95e-8589eb8693b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334388573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.2334388573
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.2566840444
Short name T397
Test name
Test status
Simulation time 795853365 ps
CPU time 5.77 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:17 PM PDT 24
Peak memory 222284 kb
Host smart-e38e1fec-8ae5-4efa-aab4-87c41b89fd74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566840444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.2566840444
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.1016112018
Short name T1306
Test name
Test status
Simulation time 577390774 ps
CPU time 2.61 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:33 PM PDT 24
Peak memory 205676 kb
Host smart-1865717b-9810-46b7-a165-52388dd43fb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016112018 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_smbus_maxlen.1016112018
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2417513387
Short name T323
Test name
Test status
Simulation time 5738232438 ps
CPU time 20.63 seconds
Started Jul 28 05:05:07 PM PDT 24
Finished Jul 28 05:05:28 PM PDT 24
Peak memory 214252 kb
Host smart-8bea56fe-ba64-437e-ad65-010369866cfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417513387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2417513387
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.3738323273
Short name T1048
Test name
Test status
Simulation time 17888435228 ps
CPU time 261.23 seconds
Started Jul 28 05:05:13 PM PDT 24
Finished Jul 28 05:09:35 PM PDT 24
Peak memory 2711368 kb
Host smart-1a396e20-1cc1-4ffb-92a0-dd8d8d6c180e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738323273 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.3738323273
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.4182316585
Short name T1750
Test name
Test status
Simulation time 4712761945 ps
CPU time 61.17 seconds
Started Jul 28 05:05:15 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 217072 kb
Host smart-6b0e4b93-6e64-4360-9cc5-daf99fab8507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182316585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.4182316585
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2096174685
Short name T376
Test name
Test status
Simulation time 27727214688 ps
CPU time 31.34 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:48 PM PDT 24
Peak memory 623744 kb
Host smart-8bed7360-759f-45b6-9823-9fa4fdf27742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096174685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2096174685
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3691107802
Short name T1329
Test name
Test status
Simulation time 2784217057 ps
CPU time 2.23 seconds
Started Jul 28 05:05:13 PM PDT 24
Finished Jul 28 05:05:15 PM PDT 24
Peak memory 205792 kb
Host smart-18dc27d5-5cb4-4fbd-844f-c737e7daa233
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691107802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3691107802
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1042907046
Short name T1023
Test name
Test status
Simulation time 5228899344 ps
CPU time 6.56 seconds
Started Jul 28 05:05:08 PM PDT 24
Finished Jul 28 05:05:15 PM PDT 24
Peak memory 222424 kb
Host smart-41567fb1-cdda-4218-a33e-a62735ce2656
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042907046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1042907046
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.602147852
Short name T524
Test name
Test status
Simulation time 186188167 ps
CPU time 3.62 seconds
Started Jul 28 05:05:05 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 206064 kb
Host smart-7263ffb0-88bd-40fe-949e-685f9fd12761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602147852 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.602147852
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.55612204
Short name T367
Test name
Test status
Simulation time 21447720 ps
CPU time 0.61 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:30 PM PDT 24
Peak memory 204900 kb
Host smart-f05a4430-52a6-470b-a27c-875c56ed65de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55612204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.55612204
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.388925764
Short name T1542
Test name
Test status
Simulation time 190572487 ps
CPU time 5.79 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:05:33 PM PDT 24
Peak memory 230152 kb
Host smart-a0b9601d-8db4-42a0-b73a-3077a7dee9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388925764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.388925764
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3603656568
Short name T881
Test name
Test status
Simulation time 4136377211 ps
CPU time 3.88 seconds
Started Jul 28 05:05:10 PM PDT 24
Finished Jul 28 05:05:14 PM PDT 24
Peak memory 240916 kb
Host smart-02b2327c-5b29-4898-9727-b97107ef992c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603656568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3603656568
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1293635038
Short name T841
Test name
Test status
Simulation time 19985871668 ps
CPU time 56.32 seconds
Started Jul 28 05:05:21 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 330708 kb
Host smart-61d734c3-5049-4262-85ba-b0b4eb91b92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293635038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1293635038
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.725975523
Short name T1313
Test name
Test status
Simulation time 9328180042 ps
CPU time 49.83 seconds
Started Jul 28 05:05:06 PM PDT 24
Finished Jul 28 05:05:55 PM PDT 24
Peak memory 648176 kb
Host smart-cc5642ea-d319-4b34-911d-edcc0c426fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725975523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.725975523
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1859926945
Short name T1224
Test name
Test status
Simulation time 661437378 ps
CPU time 1.35 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:05:11 PM PDT 24
Peak memory 205676 kb
Host smart-3b722d15-f772-4d70-9195-a43547aa006d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859926945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1859926945
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.4083084703
Short name T450
Test name
Test status
Simulation time 146358058 ps
CPU time 4.5 seconds
Started Jul 28 05:05:12 PM PDT 24
Finished Jul 28 05:05:16 PM PDT 24
Peak memory 231484 kb
Host smart-6879beb0-28d5-45ff-ab37-4b37db80cad1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083084703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.4083084703
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3583164648
Short name T104
Test name
Test status
Simulation time 4447214459 ps
CPU time 110.49 seconds
Started Jul 28 05:05:10 PM PDT 24
Finished Jul 28 05:07:01 PM PDT 24
Peak memory 1276468 kb
Host smart-39fc8fec-8132-4ecb-93f4-1e56e32daa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583164648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3583164648
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3225279940
Short name T566
Test name
Test status
Simulation time 1233599470 ps
CPU time 12.72 seconds
Started Jul 28 05:05:20 PM PDT 24
Finished Jul 28 05:05:33 PM PDT 24
Peak memory 205704 kb
Host smart-e82cc4ae-7d54-4e23-b50b-0dc65f83b609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225279940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3225279940
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_override.1414040693
Short name T142
Test name
Test status
Simulation time 51516479 ps
CPU time 0.64 seconds
Started Jul 28 05:05:15 PM PDT 24
Finished Jul 28 05:05:16 PM PDT 24
Peak memory 205516 kb
Host smart-150d1b14-9a41-408c-9beb-a04bcca09ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414040693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1414040693
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3688254974
Short name T41
Test name
Test status
Simulation time 7225515109 ps
CPU time 339.04 seconds
Started Jul 28 05:05:16 PM PDT 24
Finished Jul 28 05:10:55 PM PDT 24
Peak memory 597436 kb
Host smart-e0b7f507-1c01-4942-bcd3-a847af2e80a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688254974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3688254974
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.1856078075
Short name T520
Test name
Test status
Simulation time 646183840 ps
CPU time 6.85 seconds
Started Jul 28 05:05:18 PM PDT 24
Finished Jul 28 05:05:25 PM PDT 24
Peak memory 205676 kb
Host smart-66a9b9d8-678c-4b37-81ea-0c26e53e19d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856078075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.1856078075
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2214333972
Short name T600
Test name
Test status
Simulation time 7461608470 ps
CPU time 94.32 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:06:51 PM PDT 24
Peak memory 419512 kb
Host smart-cfad3883-5277-42d3-bf6a-e3fba0136bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214333972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2214333972
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1069356350
Short name T861
Test name
Test status
Simulation time 659740392 ps
CPU time 19.28 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:30 PM PDT 24
Peak memory 213880 kb
Host smart-4862e4c5-31b6-463c-9599-f0a8e4cbbba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069356350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1069356350
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3713836014
Short name T496
Test name
Test status
Simulation time 427190982 ps
CPU time 1.7 seconds
Started Jul 28 05:05:22 PM PDT 24
Finished Jul 28 05:05:24 PM PDT 24
Peak memory 206048 kb
Host smart-f57b2c20-af75-4c13-9c55-c5ede639d19e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713836014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3713836014
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2028053741
Short name T853
Test name
Test status
Simulation time 669898449 ps
CPU time 1.35 seconds
Started Jul 28 05:05:14 PM PDT 24
Finished Jul 28 05:05:15 PM PDT 24
Peak memory 205868 kb
Host smart-1cf8a11a-97f5-4f08-a73a-c6bd614de8b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028053741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2028053741
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.1713135618
Short name T693
Test name
Test status
Simulation time 479489452 ps
CPU time 1.75 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:05:28 PM PDT 24
Peak memory 205708 kb
Host smart-bc04fe6f-a353-40df-8dd6-2445243b70f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713135618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.1713135618
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.1034171110
Short name T1687
Test name
Test status
Simulation time 123363803 ps
CPU time 1.32 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:05:29 PM PDT 24
Peak memory 205724 kb
Host smart-7d2aa67f-176a-4de3-814d-0031a19cb51e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034171110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.1034171110
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2551108892
Short name T964
Test name
Test status
Simulation time 1920828563 ps
CPU time 3.02 seconds
Started Jul 28 05:05:18 PM PDT 24
Finished Jul 28 05:05:21 PM PDT 24
Peak memory 214148 kb
Host smart-bc3d575a-b6e5-4e11-874b-b5666ce88dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551108892 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2551108892
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3491945863
Short name T1169
Test name
Test status
Simulation time 28977848778 ps
CPU time 274.08 seconds
Started Jul 28 05:05:13 PM PDT 24
Finished Jul 28 05:09:48 PM PDT 24
Peak memory 2855364 kb
Host smart-692ae5b4-2c5b-4bad-b64b-f932b0cd2803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491945863 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3491945863
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.4264461531
Short name T1058
Test name
Test status
Simulation time 1717835172 ps
CPU time 2.59 seconds
Started Jul 28 05:05:18 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 214012 kb
Host smart-1875e12a-70db-48b3-94a2-800d836ae11d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264461531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_nack_acqfull.4264461531
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.2084726299
Short name T1410
Test name
Test status
Simulation time 2707336638 ps
CPU time 2.43 seconds
Started Jul 28 05:05:19 PM PDT 24
Finished Jul 28 05:05:22 PM PDT 24
Peak memory 206264 kb
Host smart-101343ac-c281-4f91-bf8c-56b89c10608f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084726299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.2084726299
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_txstretch.1625786848
Short name T1170
Test name
Test status
Simulation time 139689346 ps
CPU time 1.36 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:13 PM PDT 24
Peak memory 222436 kb
Host smart-f3a4c97a-823f-4d1d-996d-3fdef0261824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625786848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_nack_txstretch.1625786848
Directory /workspace/31.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/31.i2c_target_perf.580155591
Short name T1302
Test name
Test status
Simulation time 1606635360 ps
CPU time 5.99 seconds
Started Jul 28 05:05:16 PM PDT 24
Finished Jul 28 05:05:23 PM PDT 24
Peak memory 221020 kb
Host smart-d11bc898-a751-49b7-af36-3c9e11057dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580155591 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_perf.580155591
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.4184954728
Short name T481
Test name
Test status
Simulation time 3073330407 ps
CPU time 2.04 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:05:29 PM PDT 24
Peak memory 205804 kb
Host smart-dc9bd65e-4a84-4d9d-8e2a-8bbfc5236714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184954728 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.4184954728
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.664077322
Short name T1035
Test name
Test status
Simulation time 2111497206 ps
CPU time 8.75 seconds
Started Jul 28 05:05:11 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 214084 kb
Host smart-7dc0229a-079f-4077-a57e-bd0574bb77b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664077322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.664077322
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.2135999967
Short name T464
Test name
Test status
Simulation time 53551597473 ps
CPU time 2514.19 seconds
Started Jul 28 05:05:13 PM PDT 24
Finished Jul 28 05:47:08 PM PDT 24
Peak memory 10306636 kb
Host smart-4e48d11a-a766-4824-bdc3-7a2455330525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135999967 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.2135999967
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.3161726886
Short name T1674
Test name
Test status
Simulation time 1295028272 ps
CPU time 23.18 seconds
Started Jul 28 05:05:18 PM PDT 24
Finished Jul 28 05:05:42 PM PDT 24
Peak memory 230920 kb
Host smart-6f27dd0e-502a-415f-91df-d3cb7d18966c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161726886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.3161726886
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3727594292
Short name T1366
Test name
Test status
Simulation time 9093951328 ps
CPU time 5.58 seconds
Started Jul 28 05:05:29 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 206016 kb
Host smart-f9e3f3b0-6edd-4e75-b864-04215f7536c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727594292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3727594292
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1321685433
Short name T1639
Test name
Test status
Simulation time 2266852775 ps
CPU time 111.35 seconds
Started Jul 28 05:05:21 PM PDT 24
Finished Jul 28 05:07:13 PM PDT 24
Peak memory 705356 kb
Host smart-b076195d-0394-40c0-8135-efe9a9ca9bd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321685433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1321685433
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2770090604
Short name T1413
Test name
Test status
Simulation time 6910990520 ps
CPU time 7.52 seconds
Started Jul 28 05:05:14 PM PDT 24
Finished Jul 28 05:05:21 PM PDT 24
Peak memory 214204 kb
Host smart-e6d6798f-f364-4ed9-8077-5d79cacb108b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770090604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2770090604
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.1867238690
Short name T1293
Test name
Test status
Simulation time 160786871 ps
CPU time 2.73 seconds
Started Jul 28 05:05:15 PM PDT 24
Finished Jul 28 05:05:18 PM PDT 24
Peak memory 205988 kb
Host smart-4d908afc-0f04-4785-b6da-e4cea148cd75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867238690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.1867238690
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.702964603
Short name T327
Test name
Test status
Simulation time 23040595 ps
CPU time 0.65 seconds
Started Jul 28 05:05:15 PM PDT 24
Finished Jul 28 05:05:16 PM PDT 24
Peak memory 204960 kb
Host smart-6998f948-ceca-4166-b778-0cbcbe46383e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702964603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.702964603
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.4055135973
Short name T962
Test name
Test status
Simulation time 253234746 ps
CPU time 3.36 seconds
Started Jul 28 05:05:16 PM PDT 24
Finished Jul 28 05:05:19 PM PDT 24
Peak memory 216992 kb
Host smart-ff83be2b-52a1-43d4-b2a5-6827201d2c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055135973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.4055135973
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3394756000
Short name T413
Test name
Test status
Simulation time 274602046 ps
CPU time 13.36 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:31 PM PDT 24
Peak memory 258620 kb
Host smart-85e97916-b1af-4ea7-8255-8aafa4e91aa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394756000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3394756000
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.4026660140
Short name T1272
Test name
Test status
Simulation time 4735973214 ps
CPU time 74.29 seconds
Started Jul 28 05:05:24 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 542200 kb
Host smart-5ace3302-560a-4666-a491-943dbc80f1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026660140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.4026660140
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3048938243
Short name T1113
Test name
Test status
Simulation time 11887751652 ps
CPU time 65.6 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 740288 kb
Host smart-f32e8b4d-455c-46e3-9411-3efdfc45ef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048938243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3048938243
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.667384707
Short name T704
Test name
Test status
Simulation time 550092357 ps
CPU time 1.09 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:05:29 PM PDT 24
Peak memory 205660 kb
Host smart-03158854-edd8-4ea0-9a6f-4ef8414256e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667384707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.667384707
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3282851254
Short name T346
Test name
Test status
Simulation time 154327303 ps
CPU time 8.9 seconds
Started Jul 28 05:05:09 PM PDT 24
Finished Jul 28 05:05:18 PM PDT 24
Peak memory 232512 kb
Host smart-11190829-a99d-4818-9bf8-7a36dad6422c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282851254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3282851254
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3848746264
Short name T1559
Test name
Test status
Simulation time 20995992099 ps
CPU time 71.37 seconds
Started Jul 28 05:05:20 PM PDT 24
Finished Jul 28 05:06:32 PM PDT 24
Peak memory 955156 kb
Host smart-5d13a045-3f4e-4ab4-8992-303ca73f11c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848746264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3848746264
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2119839828
Short name T1265
Test name
Test status
Simulation time 1505634202 ps
CPU time 4.77 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:22 PM PDT 24
Peak memory 205752 kb
Host smart-09ae6fcc-7d15-489b-84a7-def983346eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119839828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2119839828
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.4159907123
Short name T1685
Test name
Test status
Simulation time 26720607 ps
CPU time 0.73 seconds
Started Jul 28 05:05:10 PM PDT 24
Finished Jul 28 05:05:11 PM PDT 24
Peak memory 205404 kb
Host smart-85b6b5fa-a5a5-46de-8c31-91fb35b97c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159907123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.4159907123
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3799643320
Short name T1024
Test name
Test status
Simulation time 1764518965 ps
CPU time 9.57 seconds
Started Jul 28 05:05:41 PM PDT 24
Finished Jul 28 05:05:51 PM PDT 24
Peak memory 236340 kb
Host smart-7d4dcb28-27d4-4d6c-b3e5-80467720041f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799643320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3799643320
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.350118072
Short name T1541
Test name
Test status
Simulation time 6537384388 ps
CPU time 36.69 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:54 PM PDT 24
Peak memory 566476 kb
Host smart-ce1984f7-b97c-4521-8af4-2e63f5e03571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350118072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.350118072
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4181877146
Short name T776
Test name
Test status
Simulation time 4493311456 ps
CPU time 61.29 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 348768 kb
Host smart-c613e2f9-0f7f-4cb1-8232-53684a5bb3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181877146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4181877146
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1235661552
Short name T700
Test name
Test status
Simulation time 873266717 ps
CPU time 16.49 seconds
Started Jul 28 05:05:21 PM PDT 24
Finished Jul 28 05:05:42 PM PDT 24
Peak memory 222064 kb
Host smart-0d6686e3-f66a-46fa-902e-5bd87cb1074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235661552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1235661552
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.452886191
Short name T832
Test name
Test status
Simulation time 3394152899 ps
CPU time 5.06 seconds
Started Jul 28 05:05:25 PM PDT 24
Finished Jul 28 05:05:30 PM PDT 24
Peak memory 218620 kb
Host smart-2ca803d6-da51-485a-9ade-4b47a15dc3fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452886191 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.452886191
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3672939489
Short name T1456
Test name
Test status
Simulation time 160734156 ps
CPU time 1 seconds
Started Jul 28 05:05:38 PM PDT 24
Finished Jul 28 05:05:39 PM PDT 24
Peak memory 205744 kb
Host smart-4581fe2f-deb3-44bc-a289-1aa449885484
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672939489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3672939489
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.4174412873
Short name T1054
Test name
Test status
Simulation time 163497145 ps
CPU time 0.96 seconds
Started Jul 28 05:05:35 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 205668 kb
Host smart-e8e4ff62-a9e6-43ad-9276-985438860cc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174412873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.4174412873
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.4009462968
Short name T1386
Test name
Test status
Simulation time 876072232 ps
CPU time 2.54 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 205940 kb
Host smart-6ac46620-879b-4660-8d53-911c7c013506
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009462968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.4009462968
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.2928410025
Short name T589
Test name
Test status
Simulation time 100274953 ps
CPU time 1.11 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:31 PM PDT 24
Peak memory 205712 kb
Host smart-5405e7e2-91d1-4866-98df-cae81c6b8d3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928410025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.2928410025
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.1369382632
Short name T917
Test name
Test status
Simulation time 3592880538 ps
CPU time 1.64 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:19 PM PDT 24
Peak memory 214288 kb
Host smart-6fdcb1c6-80fc-4c64-a949-6ff3ddf8f3fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369382632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.1369382632
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.383764631
Short name T1307
Test name
Test status
Simulation time 5551910574 ps
CPU time 5.26 seconds
Started Jul 28 05:05:35 PM PDT 24
Finished Jul 28 05:05:40 PM PDT 24
Peak memory 219776 kb
Host smart-d2c720d3-7a71-4036-8e29-42548594e03f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383764631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.383764631
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1919014195
Short name T84
Test name
Test status
Simulation time 10516795911 ps
CPU time 49.35 seconds
Started Jul 28 05:05:24 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 940380 kb
Host smart-795202e4-14fb-4b1e-98c1-2caf4463f8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919014195 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1919014195
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.3787173615
Short name T55
Test name
Test status
Simulation time 1936910541 ps
CPU time 2.99 seconds
Started Jul 28 05:05:18 PM PDT 24
Finished Jul 28 05:05:22 PM PDT 24
Peak memory 214216 kb
Host smart-47d3e4ca-51eb-4594-b190-116c37faab84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787173615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_nack_acqfull.3787173615
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.3376165691
Short name T1238
Test name
Test status
Simulation time 569126809 ps
CPU time 2.77 seconds
Started Jul 28 05:05:35 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 205928 kb
Host smart-56fb2e6d-20b9-4f2c-8912-48ae1eeab06c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376165691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.3376165691
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_txstretch.491513026
Short name T857
Test name
Test status
Simulation time 279259388 ps
CPU time 1.59 seconds
Started Jul 28 05:05:25 PM PDT 24
Finished Jul 28 05:05:27 PM PDT 24
Peak memory 222500 kb
Host smart-edfc0c74-3208-46af-bbc3-07a562184a32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491513026 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_nack_txstretch.491513026
Directory /workspace/32.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/32.i2c_target_perf.2627587428
Short name T118
Test name
Test status
Simulation time 1270471664 ps
CPU time 2.51 seconds
Started Jul 28 05:05:16 PM PDT 24
Finished Jul 28 05:05:19 PM PDT 24
Peak memory 214256 kb
Host smart-6043df90-84a3-428f-9e93-e2d7c33006e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627587428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.2627587428
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.3679198930
Short name T1514
Test name
Test status
Simulation time 1817486622 ps
CPU time 2.2 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 205684 kb
Host smart-91d188d5-24bc-4638-ad63-d3622f832976
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679198930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_smbus_maxlen.3679198930
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.1988976115
Short name T189
Test name
Test status
Simulation time 827778686 ps
CPU time 25.36 seconds
Started Jul 28 05:05:28 PM PDT 24
Finished Jul 28 05:05:53 PM PDT 24
Peak memory 214160 kb
Host smart-4a39738b-dd11-45b5-94ec-df7c1ae44548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988976115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.1988976115
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.2181943089
Short name T126
Test name
Test status
Simulation time 18309764110 ps
CPU time 243.11 seconds
Started Jul 28 05:05:25 PM PDT 24
Finished Jul 28 05:09:28 PM PDT 24
Peak memory 2141768 kb
Host smart-e6034cc0-68a6-4f5a-b87f-ea797ec0d7ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181943089 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.2181943089
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1174634875
Short name T610
Test name
Test status
Simulation time 4726943348 ps
CPU time 5.96 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:05:23 PM PDT 24
Peak memory 206148 kb
Host smart-f7f7749a-205e-4340-af8d-239daa452d98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174634875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1174634875
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3374432041
Short name T1669
Test name
Test status
Simulation time 34824086526 ps
CPU time 132.52 seconds
Started Jul 28 05:05:17 PM PDT 24
Finished Jul 28 05:07:30 PM PDT 24
Peak memory 1984692 kb
Host smart-77541299-36cc-493f-b714-f5fbd7c8bf6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374432041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3374432041
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3768548770
Short name T88
Test name
Test status
Simulation time 2502816916 ps
CPU time 8.09 seconds
Started Jul 28 05:05:24 PM PDT 24
Finished Jul 28 05:05:33 PM PDT 24
Peak memory 233248 kb
Host smart-fc824324-af60-4f18-a04e-76b027a34598
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768548770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3768548770
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2431272223
Short name T863
Test name
Test status
Simulation time 1685979836 ps
CPU time 7.49 seconds
Started Jul 28 05:05:19 PM PDT 24
Finished Jul 28 05:05:27 PM PDT 24
Peak memory 222336 kb
Host smart-e586fa3e-9ba9-4a19-942e-30a9df57d36e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431272223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2431272223
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.1171728009
Short name T1537
Test name
Test status
Simulation time 83218374 ps
CPU time 1.91 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 205884 kb
Host smart-1b1b09bc-be52-4f74-8efd-fedb835f775a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171728009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.1171728009
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3560879025
Short name T441
Test name
Test status
Simulation time 39063671 ps
CPU time 0.64 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:32 PM PDT 24
Peak memory 204960 kb
Host smart-8e3b1867-98e6-447a-9dcc-4228f9a9b830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560879025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3560879025
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2913696725
Short name T16
Test name
Test status
Simulation time 273460374 ps
CPU time 1.21 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 205784 kb
Host smart-40d4a2d2-6a59-46ae-a531-448a5e7a9ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913696725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2913696725
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2469872848
Short name T613
Test name
Test status
Simulation time 567498431 ps
CPU time 4.98 seconds
Started Jul 28 05:05:15 PM PDT 24
Finished Jul 28 05:05:20 PM PDT 24
Peak memory 264756 kb
Host smart-03ef0275-a03b-4e20-9d95-d3967558ba65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469872848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2469872848
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3691135676
Short name T971
Test name
Test status
Simulation time 7846781385 ps
CPU time 54.06 seconds
Started Jul 28 05:05:19 PM PDT 24
Finished Jul 28 05:06:13 PM PDT 24
Peak memory 506900 kb
Host smart-d69f28f7-ac00-4110-9d3e-dc8c85bea85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691135676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3691135676
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3207069961
Short name T859
Test name
Test status
Simulation time 7561051881 ps
CPU time 66.47 seconds
Started Jul 28 05:05:21 PM PDT 24
Finished Jul 28 05:06:28 PM PDT 24
Peak memory 698224 kb
Host smart-e9a1519e-16b0-41f7-920e-0199b036857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207069961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3207069961
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.729649096
Short name T803
Test name
Test status
Simulation time 100674304 ps
CPU time 0.89 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 205476 kb
Host smart-0fbe96fb-1c37-4348-acd9-8314b446b88b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729649096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.729649096
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2831713961
Short name T241
Test name
Test status
Simulation time 139979840 ps
CPU time 3.27 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:05:43 PM PDT 24
Peak memory 205768 kb
Host smart-493cf202-08e2-4cb1-be98-a6fbb58af6db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831713961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2831713961
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.4185951192
Short name T1103
Test name
Test status
Simulation time 4769944125 ps
CPU time 145.81 seconds
Started Jul 28 05:05:18 PM PDT 24
Finished Jul 28 05:07:44 PM PDT 24
Peak memory 1360888 kb
Host smart-ab7c56d3-14c8-4b59-83b6-8f5b67e8dc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185951192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.4185951192
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.3092179170
Short name T1256
Test name
Test status
Simulation time 1163683361 ps
CPU time 13.93 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:46 PM PDT 24
Peak memory 205960 kb
Host smart-5fe495ac-fdec-42e6-8da2-9bd6acf5c9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092179170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.3092179170
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.126527179
Short name T131
Test name
Test status
Simulation time 19412139 ps
CPU time 0.67 seconds
Started Jul 28 05:05:28 PM PDT 24
Finished Jul 28 05:05:29 PM PDT 24
Peak memory 205452 kb
Host smart-e0130a85-2307-4503-aae1-250ed3dfccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126527179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.126527179
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3025467166
Short name T1147
Test name
Test status
Simulation time 7400288154 ps
CPU time 177.85 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:08:29 PM PDT 24
Peak memory 822048 kb
Host smart-dcb8cbaa-bd42-474e-a311-fcd2155252d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025467166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3025467166
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.1917241530
Short name T626
Test name
Test status
Simulation time 462797205 ps
CPU time 3.93 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:37 PM PDT 24
Peak memory 213932 kb
Host smart-c5e10fb3-6b41-4bef-abc7-475dcb3720d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917241530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.1917241530
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2063209650
Short name T1568
Test name
Test status
Simulation time 933561673 ps
CPU time 13.75 seconds
Started Jul 28 05:05:20 PM PDT 24
Finished Jul 28 05:05:33 PM PDT 24
Peak memory 262596 kb
Host smart-bd875934-f40a-4def-b294-184400dfbbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063209650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2063209650
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.2544946704
Short name T122
Test name
Test status
Simulation time 115001727699 ps
CPU time 2062.12 seconds
Started Jul 28 05:05:19 PM PDT 24
Finished Jul 28 05:39:42 PM PDT 24
Peak memory 3850428 kb
Host smart-627c9f31-9bb5-42b1-8f5f-a27a002fa657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544946704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.2544946704
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1008986787
Short name T1053
Test name
Test status
Simulation time 3356923158 ps
CPU time 14.25 seconds
Started Jul 28 05:05:37 PM PDT 24
Finished Jul 28 05:05:51 PM PDT 24
Peak memory 217216 kb
Host smart-1ddbe780-d419-4bf5-a059-28769d175edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008986787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1008986787
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3145999150
Short name T970
Test name
Test status
Simulation time 814711103 ps
CPU time 3.78 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:37 PM PDT 24
Peak memory 222232 kb
Host smart-f39751cf-98ba-477a-9fd0-7192f9c3e093
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145999150 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3145999150
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.4178528172
Short name T1019
Test name
Test status
Simulation time 436075298 ps
CPU time 1.47 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 214116 kb
Host smart-aa97ee94-f897-4d2a-acc3-3311bbcd686e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178528172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.4178528172
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3956042598
Short name T827
Test name
Test status
Simulation time 171555312 ps
CPU time 1.07 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:32 PM PDT 24
Peak memory 205796 kb
Host smart-4f11412f-a26a-4b49-a4fd-4461079a468a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956042598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3956042598
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.666373021
Short name T1523
Test name
Test status
Simulation time 779664107 ps
CPU time 3.36 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 205924 kb
Host smart-2aa26170-e62e-4a4c-b480-c4511c20daf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666373021 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.666373021
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.839472556
Short name T811
Test name
Test status
Simulation time 178103440 ps
CPU time 1.55 seconds
Started Jul 28 05:05:43 PM PDT 24
Finished Jul 28 05:05:45 PM PDT 24
Peak memory 205948 kb
Host smart-12829425-8e6e-4a1c-970b-b8ee49c63f47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839472556 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.839472556
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.900922299
Short name T603
Test name
Test status
Simulation time 479625367 ps
CPU time 1.37 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 205972 kb
Host smart-8b71e3a7-5a2c-442f-9fd8-44a1c9317bd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900922299 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_hrst.900922299
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.209150280
Short name T1183
Test name
Test status
Simulation time 3277879573 ps
CPU time 5.64 seconds
Started Jul 28 05:05:28 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 214696 kb
Host smart-57240256-03e6-48b3-bde9-674656b9bb9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209150280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.209150280
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.1297331332
Short name T599
Test name
Test status
Simulation time 17576044573 ps
CPU time 259 seconds
Started Jul 28 05:05:26 PM PDT 24
Finished Jul 28 05:09:45 PM PDT 24
Peak memory 2708160 kb
Host smart-d8ee2c08-7dc9-4e6e-bf1a-069391e9a6a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297331332 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1297331332
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.3750880505
Short name T561
Test name
Test status
Simulation time 619091636 ps
CPU time 2.99 seconds
Started Jul 28 05:05:38 PM PDT 24
Finished Jul 28 05:05:41 PM PDT 24
Peak memory 214132 kb
Host smart-21f3b64b-daa4-4826-b5c1-9fa10badfb59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750880505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.3750880505
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.2501730411
Short name T1705
Test name
Test status
Simulation time 1030659398 ps
CPU time 2.56 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:05:37 PM PDT 24
Peak memory 205848 kb
Host smart-d9b77f4c-4aad-417f-9d43-c233cb4b752e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501730411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.2501730411
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_txstretch.603587113
Short name T1345
Test name
Test status
Simulation time 584813558 ps
CPU time 1.41 seconds
Started Jul 28 05:05:37 PM PDT 24
Finished Jul 28 05:05:39 PM PDT 24
Peak memory 222756 kb
Host smart-5097d3d1-f16c-4fb0-8356-b03aeb5de50d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603587113 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_nack_txstretch.603587113
Directory /workspace/33.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/33.i2c_target_perf.318371236
Short name T563
Test name
Test status
Simulation time 6443395178 ps
CPU time 6.25 seconds
Started Jul 28 05:05:25 PM PDT 24
Finished Jul 28 05:05:31 PM PDT 24
Peak memory 214432 kb
Host smart-709d9a84-33f6-4a50-953f-470a487fa017
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318371236 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_perf.318371236
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.1764341288
Short name T306
Test name
Test status
Simulation time 904614712 ps
CPU time 2.33 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:05:42 PM PDT 24
Peak memory 205652 kb
Host smart-932e05b9-187e-4a2c-8aa1-011a562eadae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764341288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.1764341288
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.187482170
Short name T763
Test name
Test status
Simulation time 1878258261 ps
CPU time 46.87 seconds
Started Jul 28 05:05:23 PM PDT 24
Finished Jul 28 05:06:10 PM PDT 24
Peak memory 214172 kb
Host smart-d108893b-1079-47bb-a5bf-ac0fb21d31ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187482170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.187482170
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.402964602
Short name T1588
Test name
Test status
Simulation time 171536099478 ps
CPU time 53.46 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:06:26 PM PDT 24
Peak memory 287864 kb
Host smart-323e7a03-e080-4f6a-a3ba-869a45c2f3ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402964602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_target_stress_all.402964602
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.2203747134
Short name T780
Test name
Test status
Simulation time 6849957413 ps
CPU time 29.33 seconds
Started Jul 28 05:05:24 PM PDT 24
Finished Jul 28 05:05:53 PM PDT 24
Peak memory 230576 kb
Host smart-2499b7ed-84b7-4ac5-9fe1-bfbf9dd8c683
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203747134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.2203747134
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2037926275
Short name T1398
Test name
Test status
Simulation time 53807918754 ps
CPU time 197.51 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:08:44 PM PDT 24
Peak memory 2130656 kb
Host smart-e4d7df94-5fa3-4ede-a54b-3b8b2db18cf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037926275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2037926275
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3054160484
Short name T974
Test name
Test status
Simulation time 1111590739 ps
CPU time 16.69 seconds
Started Jul 28 05:05:29 PM PDT 24
Finished Jul 28 05:05:46 PM PDT 24
Peak memory 422716 kb
Host smart-7d55066c-186b-4ef4-a21f-15a23dadb0c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054160484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3054160484
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3472593467
Short name T4
Test name
Test status
Simulation time 2488545697 ps
CPU time 7.21 seconds
Started Jul 28 05:05:36 PM PDT 24
Finished Jul 28 05:05:44 PM PDT 24
Peak memory 214224 kb
Host smart-86dc4e1e-7438-47b5-a386-da3307420a53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472593467 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3472593467
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.875839980
Short name T383
Test name
Test status
Simulation time 170483705 ps
CPU time 2.77 seconds
Started Jul 28 05:05:37 PM PDT 24
Finished Jul 28 05:05:40 PM PDT 24
Peak memory 205900 kb
Host smart-19f9c7c8-58fa-40bb-bf45-ff271bac17dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875839980 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.875839980
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.496037381
Short name T538
Test name
Test status
Simulation time 38656434 ps
CPU time 0.61 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 204792 kb
Host smart-222e6b4b-8a50-4815-a00c-725aa87dfd96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496037381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.496037381
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.601063104
Short name T1648
Test name
Test status
Simulation time 94041485 ps
CPU time 1.41 seconds
Started Jul 28 05:05:29 PM PDT 24
Finished Jul 28 05:05:30 PM PDT 24
Peak memory 214072 kb
Host smart-ffec729b-d878-4776-9421-bd6531d0f097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601063104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.601063104
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.534762204
Short name T1175
Test name
Test status
Simulation time 724910029 ps
CPU time 9.11 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 239044 kb
Host smart-0ace0629-a116-47f4-a11c-10a97c7ce6c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534762204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.534762204
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2786212922
Short name T1118
Test name
Test status
Simulation time 2751855695 ps
CPU time 65.82 seconds
Started Jul 28 05:05:20 PM PDT 24
Finished Jul 28 05:06:26 PM PDT 24
Peak memory 263816 kb
Host smart-a35c38f8-be8e-4c8d-8369-b84df3154611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786212922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2786212922
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2115183445
Short name T93
Test name
Test status
Simulation time 1598992946 ps
CPU time 109.34 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:07:23 PM PDT 24
Peak memory 587636 kb
Host smart-5f78bd2e-10d4-4f7d-b455-1605f0c06baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115183445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2115183445
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2227389842
Short name T1013
Test name
Test status
Simulation time 148156089 ps
CPU time 1.2 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:32 PM PDT 24
Peak memory 205380 kb
Host smart-5eb582d5-8144-448c-9b90-395045ed2d4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227389842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2227389842
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.858458452
Short name T994
Test name
Test status
Simulation time 239628325 ps
CPU time 3.14 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 205836 kb
Host smart-8249c802-f3be-475d-bc11-46485e41f06d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858458452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
858458452
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1903568732
Short name T929
Test name
Test status
Simulation time 19688791403 ps
CPU time 364.47 seconds
Started Jul 28 05:05:23 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 1409096 kb
Host smart-a67630a9-8465-4f54-b70b-d7b674032cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903568732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1903568732
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.2281314680
Short name T192
Test name
Test status
Simulation time 3081874302 ps
CPU time 10.07 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:43 PM PDT 24
Peak memory 205912 kb
Host smart-4193e597-3191-44a8-9944-ce61466aaa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281314680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2281314680
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.475968037
Short name T1225
Test name
Test status
Simulation time 32762884 ps
CPU time 0.72 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:32 PM PDT 24
Peak memory 205648 kb
Host smart-3c5c0da0-99b5-4048-adf5-23284252858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475968037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.475968037
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.558732712
Short name T1709
Test name
Test status
Simulation time 3048927719 ps
CPU time 35.25 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:06:05 PM PDT 24
Peak memory 366676 kb
Host smart-1f2295aa-8096-4a78-a7da-0bffcf1a68e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558732712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.558732712
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.2248580514
Short name T924
Test name
Test status
Simulation time 41838753 ps
CPU time 1.21 seconds
Started Jul 28 05:05:43 PM PDT 24
Finished Jul 28 05:05:45 PM PDT 24
Peak memory 206592 kb
Host smart-f76944bf-a25b-4e0b-b0c3-c966a4e239a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248580514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.2248580514
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2394740580
Short name T494
Test name
Test status
Simulation time 7614651428 ps
CPU time 16.23 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 250440 kb
Host smart-a4b36576-8301-4a90-b9d6-cb8eeca0590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394740580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2394740580
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.223702627
Short name T288
Test name
Test status
Simulation time 52181060639 ps
CPU time 779.21 seconds
Started Jul 28 05:05:28 PM PDT 24
Finished Jul 28 05:18:28 PM PDT 24
Peak memory 1239516 kb
Host smart-499317ad-6e4d-4073-82fc-6f79a4fb36e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223702627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.223702627
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.388009649
Short name T1115
Test name
Test status
Simulation time 2956338084 ps
CPU time 12.35 seconds
Started Jul 28 05:05:36 PM PDT 24
Finished Jul 28 05:05:48 PM PDT 24
Peak memory 221848 kb
Host smart-da8a5696-fd1a-4ec1-9cdb-cfbdbc717938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388009649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.388009649
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.32181636
Short name T437
Test name
Test status
Simulation time 3858007854 ps
CPU time 5.13 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 222416 kb
Host smart-28eb43d8-de5c-4cfa-8b78-d7cee8a50022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32181636 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.32181636
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1813330458
Short name T708
Test name
Test status
Simulation time 172506210 ps
CPU time 1.04 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:33 PM PDT 24
Peak memory 205728 kb
Host smart-6505aa3d-cc1a-49d3-af2a-cb35ea1b128d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813330458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1813330458
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1434867886
Short name T1367
Test name
Test status
Simulation time 590485611 ps
CPU time 1.21 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 205768 kb
Host smart-4dee3dcf-ece1-4176-beb7-bf935191203e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434867886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1434867886
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.1232958631
Short name T513
Test name
Test status
Simulation time 785186115 ps
CPU time 2.99 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 205952 kb
Host smart-7316fa40-3905-430d-ae18-ff7521d141e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232958631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.1232958631
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.1319605468
Short name T735
Test name
Test status
Simulation time 558391044 ps
CPU time 1.22 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:05:41 PM PDT 24
Peak memory 205684 kb
Host smart-c1177fd2-a898-4987-9114-4b501959d409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319605468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1319605468
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1167819632
Short name T1213
Test name
Test status
Simulation time 1161431103 ps
CPU time 2.14 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:32 PM PDT 24
Peak memory 207292 kb
Host smart-50388486-4f35-470f-aa92-11e8899644b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167819632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1167819632
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3688581460
Short name T1603
Test name
Test status
Simulation time 10095902599 ps
CPU time 6.38 seconds
Started Jul 28 05:05:29 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 222320 kb
Host smart-acc618ee-3732-4acb-8f5a-5c2418ebe05b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688581460 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3688581460
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1561392830
Short name T1536
Test name
Test status
Simulation time 23238993357 ps
CPU time 775.38 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:18:26 PM PDT 24
Peak memory 5426144 kb
Host smart-05599221-f170-42f8-be0a-967b4539841b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561392830 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1561392830
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.3816945228
Short name T1190
Test name
Test status
Simulation time 2132792613 ps
CPU time 2.6 seconds
Started Jul 28 05:05:45 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 214192 kb
Host smart-a77e725f-7205-43f5-849a-1f02f8a402a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816945228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.3816945228
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.181297873
Short name T731
Test name
Test status
Simulation time 508809567 ps
CPU time 2.54 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 205868 kb
Host smart-dcec5397-38d6-48c5-9013-0d2c6f856165
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181297873 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.181297873
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.3341017064
Short name T282
Test name
Test status
Simulation time 2835891413 ps
CPU time 5.29 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 215852 kb
Host smart-d4a62f32-4d34-4f8a-9faa-75bdca54d5bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341017064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.3341017064
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.4174992904
Short name T1261
Test name
Test status
Simulation time 680472222 ps
CPU time 2.05 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 205632 kb
Host smart-672700f7-5222-4c88-9d8a-00c2776df6ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174992904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_smbus_maxlen.4174992904
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.863333690
Short name T1694
Test name
Test status
Simulation time 3976423852 ps
CPU time 30.25 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:06:02 PM PDT 24
Peak memory 217992 kb
Host smart-d8ec3a59-9a08-4646-8d4c-4431b48b9e22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863333690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.863333690
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.397002881
Short name T1042
Test name
Test status
Simulation time 62994964485 ps
CPU time 112.08 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 1310644 kb
Host smart-f8ca6f71-91d5-4e31-bd3a-8961e42bb709
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397002881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_target_stress_all.397002881
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3324083113
Short name T1156
Test name
Test status
Simulation time 1717900134 ps
CPU time 32.15 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:06:05 PM PDT 24
Peak memory 230424 kb
Host smart-65a27bad-39be-4cfb-928a-baf804770c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324083113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3324083113
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.504292548
Short name T1125
Test name
Test status
Simulation time 30441455262 ps
CPU time 208.66 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:09:02 PM PDT 24
Peak memory 2628244 kb
Host smart-b9c395e7-9ca6-4fed-8ec5-11cebbcf54eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504292548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.504292548
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.4069260618
Short name T332
Test name
Test status
Simulation time 2178698742 ps
CPU time 9.58 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:40 PM PDT 24
Peak memory 237168 kb
Host smart-352e7021-d991-4dce-a7fb-b37975735bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069260618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.4069260618
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.891283127
Short name T573
Test name
Test status
Simulation time 7775315306 ps
CPU time 6.82 seconds
Started Jul 28 05:05:27 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 222360 kb
Host smart-a0cbf6b4-686d-47fd-98eb-c3197f544418
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891283127 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.891283127
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.642060333
Short name T1638
Test name
Test status
Simulation time 89697216 ps
CPU time 2.08 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 205948 kb
Host smart-b4bf9de2-0baf-4fc4-94c5-a2adf2f63bfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642060333 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.642060333
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.4095860346
Short name T1461
Test name
Test status
Simulation time 17754182 ps
CPU time 0.65 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:31 PM PDT 24
Peak memory 205360 kb
Host smart-96eb6dbf-5ddd-4903-b7a3-03b0bbe51b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095860346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.4095860346
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.725496526
Short name T823
Test name
Test status
Simulation time 607011014 ps
CPU time 6.25 seconds
Started Jul 28 05:05:35 PM PDT 24
Finished Jul 28 05:05:41 PM PDT 24
Peak memory 231164 kb
Host smart-4e7f0e16-2601-4352-b74b-77a173a47384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725496526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.725496526
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1805512941
Short name T1414
Test name
Test status
Simulation time 1411811700 ps
CPU time 9.24 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:42 PM PDT 24
Peak memory 300880 kb
Host smart-cd5dcf41-9ceb-4964-b421-24a60fd92585
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805512941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1805512941
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2804968191
Short name T1280
Test name
Test status
Simulation time 2839245032 ps
CPU time 202.53 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:08:56 PM PDT 24
Peak memory 731576 kb
Host smart-eadfc0a7-4f41-44e6-bedf-1272d88bb6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804968191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2804968191
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2037554019
Short name T380
Test name
Test status
Simulation time 7782116419 ps
CPU time 49.76 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:06:23 PM PDT 24
Peak memory 596532 kb
Host smart-40eea244-441a-4d0e-92d7-18e9157457e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037554019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2037554019
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1613613582
Short name T792
Test name
Test status
Simulation time 371927504 ps
CPU time 1.12 seconds
Started Jul 28 05:05:50 PM PDT 24
Finished Jul 28 05:05:51 PM PDT 24
Peak memory 205436 kb
Host smart-34323789-120e-4859-b482-b62c1e71c47d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613613582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1613613582
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2420577100
Short name T495
Test name
Test status
Simulation time 814410686 ps
CPU time 4.84 seconds
Started Jul 28 05:05:38 PM PDT 24
Finished Jul 28 05:05:43 PM PDT 24
Peak memory 244832 kb
Host smart-9a909ee5-16c4-44bf-b2a7-d9240d739c6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420577100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2420577100
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.625785372
Short name T727
Test name
Test status
Simulation time 2926227359 ps
CPU time 183.18 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:08:37 PM PDT 24
Peak memory 911432 kb
Host smart-12d0b003-51a2-4303-91c1-b25d122c9982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625785372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.625785372
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2101778482
Short name T866
Test name
Test status
Simulation time 348461042 ps
CPU time 5.43 seconds
Started Jul 28 05:05:51 PM PDT 24
Finished Jul 28 05:05:57 PM PDT 24
Peak memory 205708 kb
Host smart-dd6dd505-565d-47ae-a34e-f1f057f795c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101778482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2101778482
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1665500082
Short name T273
Test name
Test status
Simulation time 720123042 ps
CPU time 2.39 seconds
Started Jul 28 05:05:41 PM PDT 24
Finished Jul 28 05:05:44 PM PDT 24
Peak memory 213888 kb
Host smart-f5906f2d-f0a1-4cf2-9177-261147023f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665500082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1665500082
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2480337836
Short name T1667
Test name
Test status
Simulation time 18413331 ps
CPU time 0.68 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:33 PM PDT 24
Peak memory 205444 kb
Host smart-b92fb9ce-fddb-450d-be7c-1644c79d47c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480337836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2480337836
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2224019868
Short name T1250
Test name
Test status
Simulation time 49103898824 ps
CPU time 619.7 seconds
Started Jul 28 05:05:45 PM PDT 24
Finished Jul 28 05:16:05 PM PDT 24
Peak memory 205832 kb
Host smart-becfdbcc-b675-4487-9c9c-f14c125c014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224019868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2224019868
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.2938231918
Short name T1688
Test name
Test status
Simulation time 1217809058 ps
CPU time 46.43 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:06:26 PM PDT 24
Peak memory 205652 kb
Host smart-f39545fd-6eee-4856-9a91-5c5889f75356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938231918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2938231918
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1083256505
Short name T1066
Test name
Test status
Simulation time 7197195772 ps
CPU time 23.04 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:54 PM PDT 24
Peak memory 301424 kb
Host smart-43e7dbf0-d89f-41de-8120-e6b25e7e54da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083256505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1083256505
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1541668482
Short name T284
Test name
Test status
Simulation time 10323204824 ps
CPU time 1039.14 seconds
Started Jul 28 05:05:46 PM PDT 24
Finished Jul 28 05:23:05 PM PDT 24
Peak memory 1760488 kb
Host smart-705e7997-0c0a-47a6-a087-5d4e8a5cff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541668482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1541668482
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.2329375973
Short name T493
Test name
Test status
Simulation time 1207190560 ps
CPU time 20.16 seconds
Started Jul 28 05:05:42 PM PDT 24
Finished Jul 28 05:06:02 PM PDT 24
Peak memory 222068 kb
Host smart-a8351e14-f026-4155-afc5-d436767f1519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329375973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2329375973
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.4134814652
Short name T906
Test name
Test status
Simulation time 2699103240 ps
CPU time 5.61 seconds
Started Jul 28 05:05:35 PM PDT 24
Finished Jul 28 05:05:41 PM PDT 24
Peak memory 214220 kb
Host smart-9bba997c-1be8-483d-a207-1e2278df848c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134814652 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.4134814652
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2572499441
Short name T1531
Test name
Test status
Simulation time 501366578 ps
CPU time 1.08 seconds
Started Jul 28 05:05:47 PM PDT 24
Finished Jul 28 05:05:48 PM PDT 24
Peak memory 205724 kb
Host smart-639dcef2-bf75-436f-a8dc-92b2620e6a3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572499441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2572499441
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2996576332
Short name T778
Test name
Test status
Simulation time 157111031 ps
CPU time 1.02 seconds
Started Jul 28 05:05:30 PM PDT 24
Finished Jul 28 05:05:31 PM PDT 24
Peak memory 205636 kb
Host smart-07a10ff4-33e6-4ec6-b7c8-3fb914f101ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996576332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2996576332
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.886782272
Short name T876
Test name
Test status
Simulation time 404394802 ps
CPU time 2.36 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 205728 kb
Host smart-47a92740-766e-468a-b8eb-35343091c58c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886782272 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.886782272
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.709867967
Short name T572
Test name
Test status
Simulation time 132153087 ps
CPU time 1.37 seconds
Started Jul 28 05:05:44 PM PDT 24
Finished Jul 28 05:05:45 PM PDT 24
Peak memory 205704 kb
Host smart-d1aa1d67-6e1e-462f-accf-e8bef19696b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709867967 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.709867967
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3696490426
Short name T388
Test name
Test status
Simulation time 681350425 ps
CPU time 5.11 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:37 PM PDT 24
Peak memory 211304 kb
Host smart-f62d2a50-8fb5-4247-a522-b25cd4a86ef2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696490426 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3696490426
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.289647881
Short name T1106
Test name
Test status
Simulation time 1922799021 ps
CPU time 3 seconds
Started Jul 28 05:05:53 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 214140 kb
Host smart-7ab7a7f8-ea47-4342-97b3-28677f3918e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289647881 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_nack_acqfull.289647881
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.3807641860
Short name T940
Test name
Test status
Simulation time 553665545 ps
CPU time 2.69 seconds
Started Jul 28 05:05:35 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 206220 kb
Host smart-17d1bfe0-05ef-4398-9cf8-c4115a0dacc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807641860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.3807641860
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_txstretch.273853749
Short name T1038
Test name
Test status
Simulation time 527045689 ps
CPU time 1.55 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 222680 kb
Host smart-65ce9cbe-c489-4072-ad50-112dc07cf2ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273853749 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_nack_txstretch.273853749
Directory /workspace/35.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/35.i2c_target_perf.1091027190
Short name T1126
Test name
Test status
Simulation time 663537371 ps
CPU time 4.89 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:05:45 PM PDT 24
Peak memory 218892 kb
Host smart-24c0eca4-f2d9-4415-9edb-6171bca639ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091027190 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.1091027190
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.3182978152
Short name T579
Test name
Test status
Simulation time 419507269 ps
CPU time 2.21 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 205620 kb
Host smart-39115855-753d-4f31-90b8-67f738860d2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182978152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_smbus_maxlen.3182978152
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2294334314
Short name T1553
Test name
Test status
Simulation time 1251201798 ps
CPU time 16.27 seconds
Started Jul 28 05:05:39 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 218284 kb
Host smart-083dbd69-3b81-4948-bf58-248e289234c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294334314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2294334314
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.4208175903
Short name T1742
Test name
Test status
Simulation time 28194297280 ps
CPU time 365.24 seconds
Started Jul 28 05:05:39 PM PDT 24
Finished Jul 28 05:11:45 PM PDT 24
Peak memory 2917752 kb
Host smart-115a7661-94fe-4e56-a524-62970151a6f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208175903 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.4208175903
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.225709336
Short name T270
Test name
Test status
Simulation time 1106135394 ps
CPU time 21.68 seconds
Started Jul 28 05:05:49 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 214128 kb
Host smart-c89393a7-6e95-4e7f-9d54-b58ccfae25a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225709336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.225709336
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2543474721
Short name T1532
Test name
Test status
Simulation time 54621797572 ps
CPU time 1768.31 seconds
Started Jul 28 05:05:45 PM PDT 24
Finished Jul 28 05:35:13 PM PDT 24
Peak memory 9005984 kb
Host smart-9470e10e-4e6e-497d-9d55-293eada700c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543474721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2543474721
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.715976952
Short name T968
Test name
Test status
Simulation time 350545113 ps
CPU time 1.48 seconds
Started Jul 28 05:05:53 PM PDT 24
Finished Jul 28 05:05:54 PM PDT 24
Peak memory 205852 kb
Host smart-396bb390-e600-43a7-a043-752efe83972e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715976952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.715976952
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3710987609
Short name T1136
Test name
Test status
Simulation time 5595273076 ps
CPU time 6.61 seconds
Started Jul 28 05:05:41 PM PDT 24
Finished Jul 28 05:05:48 PM PDT 24
Peak memory 214228 kb
Host smart-9f9cccd8-57b9-4c95-9f4f-800361a2e8a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710987609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3710987609
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.3651977132
Short name T193
Test name
Test status
Simulation time 186794593 ps
CPU time 2.4 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 205840 kb
Host smart-1436789f-b988-4ab3-8f0e-019be0734a7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651977132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.3651977132
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3322269888
Short name T882
Test name
Test status
Simulation time 19022605 ps
CPU time 0.65 seconds
Started Jul 28 05:05:46 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 204920 kb
Host smart-c69a115e-ab8b-4c1a-af00-2c1ad4e3daf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322269888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3322269888
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3577686804
Short name T1507
Test name
Test status
Simulation time 133228710 ps
CPU time 2.1 seconds
Started Jul 28 05:05:54 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 222032 kb
Host smart-ffb0fba1-7009-410e-97ff-988367724c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577686804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3577686804
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1747971700
Short name T1395
Test name
Test status
Simulation time 553334903 ps
CPU time 7.39 seconds
Started Jul 28 05:05:41 PM PDT 24
Finished Jul 28 05:05:49 PM PDT 24
Peak memory 231432 kb
Host smart-86ccbf3e-79f2-43da-995b-733825bcf5a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747971700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1747971700
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2417058841
Short name T1100
Test name
Test status
Simulation time 10384425310 ps
CPU time 148.44 seconds
Started Jul 28 05:05:35 PM PDT 24
Finished Jul 28 05:08:04 PM PDT 24
Peak memory 511764 kb
Host smart-65c2f6bc-2919-489e-bbcb-3e5440c23331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417058841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2417058841
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2084693905
Short name T849
Test name
Test status
Simulation time 8325766019 ps
CPU time 128.71 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:07:41 PM PDT 24
Peak memory 640528 kb
Host smart-a624a848-31d8-4b0c-a4e4-f9a3cfd6ec33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084693905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2084693905
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2196704699
Short name T1714
Test name
Test status
Simulation time 130229976 ps
CPU time 0.92 seconds
Started Jul 28 05:05:31 PM PDT 24
Finished Jul 28 05:05:32 PM PDT 24
Peak memory 205440 kb
Host smart-f1e2ec53-32b5-4d0c-b750-10dae873f545
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196704699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2196704699
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3431201027
Short name T1426
Test name
Test status
Simulation time 178786580 ps
CPU time 4.86 seconds
Started Jul 28 05:05:42 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 238144 kb
Host smart-99817d67-50b1-4560-b2f5-bdb03126e9bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431201027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3431201027
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.3095745695
Short name T1131
Test name
Test status
Simulation time 5039055072 ps
CPU time 153.47 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:08:07 PM PDT 24
Peak memory 832584 kb
Host smart-67d7ffe8-744d-4a05-af03-9f947cc25026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095745695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.3095745695
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.775635993
Short name T1729
Test name
Test status
Simulation time 2032295667 ps
CPU time 8.23 seconds
Started Jul 28 05:05:47 PM PDT 24
Finished Jul 28 05:05:55 PM PDT 24
Peak memory 205796 kb
Host smart-583a298b-9da9-42b1-a0b0-066939219ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775635993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.775635993
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.1269687095
Short name T77
Test name
Test status
Simulation time 29168928 ps
CPU time 0.71 seconds
Started Jul 28 05:05:38 PM PDT 24
Finished Jul 28 05:05:39 PM PDT 24
Peak memory 205468 kb
Host smart-fd6a551e-aa76-46e5-b43e-f2fa6bdebd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269687095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1269687095
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.701061760
Short name T1623
Test name
Test status
Simulation time 12379209766 ps
CPU time 91.08 seconds
Started Jul 28 05:05:48 PM PDT 24
Finished Jul 28 05:07:19 PM PDT 24
Peak memory 269076 kb
Host smart-50fea055-011c-414e-ad17-961cf987855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701061760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.701061760
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.2149411650
Short name T765
Test name
Test status
Simulation time 64527052 ps
CPU time 1.44 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 205708 kb
Host smart-f18feea8-102c-4be7-aa2d-6141f0647146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149411650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.2149411650
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1801677236
Short name T1010
Test name
Test status
Simulation time 1582046772 ps
CPU time 70.28 seconds
Started Jul 28 05:05:32 PM PDT 24
Finished Jul 28 05:06:43 PM PDT 24
Peak memory 334700 kb
Host smart-d9812e47-e3a5-48ab-88aa-f4e1c7c4616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801677236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1801677236
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.2975590713
Short name T275
Test name
Test status
Simulation time 2622236901 ps
CPU time 30.23 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:06:28 PM PDT 24
Peak memory 214220 kb
Host smart-435a973a-094b-45e4-b35d-9a76e9ab0416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975590713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2975590713
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.585686805
Short name T1091
Test name
Test status
Simulation time 2031553351 ps
CPU time 4.71 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:04 PM PDT 24
Peak memory 214092 kb
Host smart-7632787b-b809-4c1f-8327-e7c9056c30c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585686805 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.585686805
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3795024400
Short name T534
Test name
Test status
Simulation time 1063558298 ps
CPU time 1.59 seconds
Started Jul 28 05:05:48 PM PDT 24
Finished Jul 28 05:05:49 PM PDT 24
Peak memory 216156 kb
Host smart-891a6acc-190e-46c4-a81b-217c4a244cbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795024400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3795024400
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.514691048
Short name T790
Test name
Test status
Simulation time 223426113 ps
CPU time 1.68 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:05:36 PM PDT 24
Peak memory 205868 kb
Host smart-50367758-06a1-4ebf-8669-92b6a9cb959e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514691048 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.514691048
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.2005425238
Short name T1061
Test name
Test status
Simulation time 405985072 ps
CPU time 2.44 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:05:58 PM PDT 24
Peak memory 205896 kb
Host smart-ee703ac3-8d49-4c87-a351-5cc705420e0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005425238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.2005425238
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.1360063398
Short name T1288
Test name
Test status
Simulation time 141387881 ps
CPU time 1.52 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:35 PM PDT 24
Peak memory 205796 kb
Host smart-815e0b2c-d4e9-4f7b-a1d6-f1dfd0d195cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360063398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.1360063398
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.816156038
Short name T1027
Test name
Test status
Simulation time 1216482492 ps
CPU time 2.07 seconds
Started Jul 28 05:05:43 PM PDT 24
Finished Jul 28 05:05:45 PM PDT 24
Peak memory 214100 kb
Host smart-62ae75fa-b64c-4b05-9f7d-ef89610b8235
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816156038 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.816156038
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3952310857
Short name T550
Test name
Test status
Simulation time 3840450502 ps
CPU time 5.19 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:05:40 PM PDT 24
Peak memory 220056 kb
Host smart-0e72de65-e210-4e81-901c-b60df3ea6570
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952310857 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3952310857
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.2452988421
Short name T786
Test name
Test status
Simulation time 20773381139 ps
CPU time 103.28 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:07:23 PM PDT 24
Peak memory 1810300 kb
Host smart-4b8c15d1-a04d-4243-9b7f-f4479d6002e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452988421 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2452988421
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.2883610253
Short name T1277
Test name
Test status
Simulation time 575269894 ps
CPU time 2.97 seconds
Started Jul 28 05:05:44 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 214200 kb
Host smart-ae3efbe3-cfd5-459b-8649-1e7dc1336523
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883610253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_nack_acqfull.2883610253
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.1524104609
Short name T1239
Test name
Test status
Simulation time 1991600851 ps
CPU time 2.82 seconds
Started Jul 28 05:05:47 PM PDT 24
Finished Jul 28 05:05:50 PM PDT 24
Peak memory 205868 kb
Host smart-5f9e0e6e-3e71-4bff-adfc-6a6c462e0a4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524104609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.1524104609
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_txstretch.745586767
Short name T49
Test name
Test status
Simulation time 297879436 ps
CPU time 1.44 seconds
Started Jul 28 05:05:39 PM PDT 24
Finished Jul 28 05:05:40 PM PDT 24
Peak memory 222752 kb
Host smart-3279b6e4-fc60-4193-a405-a622feb67e97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745586767 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_nack_txstretch.745586767
Directory /workspace/36.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/36.i2c_target_perf.1516123472
Short name T720
Test name
Test status
Simulation time 743210525 ps
CPU time 4.8 seconds
Started Jul 28 05:05:39 PM PDT 24
Finished Jul 28 05:05:44 PM PDT 24
Peak memory 219152 kb
Host smart-5dace9a1-4faa-40ae-9dec-d7924503e0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516123472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.1516123472
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.3520658752
Short name T598
Test name
Test status
Simulation time 3066454042 ps
CPU time 1.93 seconds
Started Jul 28 05:05:39 PM PDT 24
Finished Jul 28 05:05:41 PM PDT 24
Peak memory 205780 kb
Host smart-4070c2a4-ee88-472d-8df5-c86141ae5360
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520658752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_smbus_maxlen.3520658752
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1290044501
Short name T412
Test name
Test status
Simulation time 1860772842 ps
CPU time 28.07 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 214156 kb
Host smart-3743a3c5-45c5-4c00-a865-65787a3d449a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290044501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1290044501
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.1709629960
Short name T1380
Test name
Test status
Simulation time 21284057137 ps
CPU time 30.67 seconds
Started Jul 28 05:05:43 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 260212 kb
Host smart-8b78f2bd-a370-414e-906e-f0eefefabd4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709629960 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.1709629960
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3573007904
Short name T989
Test name
Test status
Simulation time 607647154 ps
CPU time 4.75 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:06:01 PM PDT 24
Peak memory 205960 kb
Host smart-a17b9fba-5487-43f5-a3f6-9ae178dba9f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573007904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3573007904
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2342134777
Short name T753
Test name
Test status
Simulation time 29565277849 ps
CPU time 32.67 seconds
Started Jul 28 05:05:52 PM PDT 24
Finished Jul 28 05:06:25 PM PDT 24
Peak memory 666728 kb
Host smart-131bad17-d093-4e4d-a22d-54b24726566f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342134777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2342134777
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2487944629
Short name T1248
Test name
Test status
Simulation time 450368104 ps
CPU time 1.58 seconds
Started Jul 28 05:05:45 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 205976 kb
Host smart-79c05b3a-4c1f-4a5a-8dbd-9702ed2df02f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487944629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2487944629
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.3954559558
Short name T820
Test name
Test status
Simulation time 927257095 ps
CPU time 5.9 seconds
Started Jul 28 05:05:47 PM PDT 24
Finished Jul 28 05:05:53 PM PDT 24
Peak memory 214096 kb
Host smart-f33a0b50-eae3-4de5-b32c-47f93aca3287
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954559558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.3954559558
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.84564577
Short name T1211
Test name
Test status
Simulation time 140842822 ps
CPU time 2.46 seconds
Started Jul 28 05:05:35 PM PDT 24
Finished Jul 28 05:05:37 PM PDT 24
Peak memory 215132 kb
Host smart-4f5a02b5-8553-455b-85d2-d1d4457f3eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84564577 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.84564577
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3512688228
Short name T398
Test name
Test status
Simulation time 24862348 ps
CPU time 0.62 seconds
Started Jul 28 05:05:47 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 204872 kb
Host smart-640d8d76-c11f-4b87-a993-80c1147aa085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512688228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3512688228
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1269496841
Short name T867
Test name
Test status
Simulation time 188798315 ps
CPU time 3.25 seconds
Started Jul 28 05:05:47 PM PDT 24
Finished Jul 28 05:05:50 PM PDT 24
Peak memory 235768 kb
Host smart-9663cddd-23c0-4c84-9976-c8107893dd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269496841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1269496841
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.4171067197
Short name T1369
Test name
Test status
Simulation time 439305380 ps
CPU time 9.01 seconds
Started Jul 28 05:05:47 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 282456 kb
Host smart-cd059866-3022-4476-b805-0eed1e66f307
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171067197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.4171067197
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2548493249
Short name T1243
Test name
Test status
Simulation time 43304005237 ps
CPU time 50.17 seconds
Started Jul 28 05:05:54 PM PDT 24
Finished Jul 28 05:06:45 PM PDT 24
Peak memory 417148 kb
Host smart-575e2e08-7bc1-4f1b-8d5b-3b06eee7f972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548493249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2548493249
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1977481896
Short name T1343
Test name
Test status
Simulation time 6557246726 ps
CPU time 104.22 seconds
Started Jul 28 05:05:34 PM PDT 24
Finished Jul 28 05:07:19 PM PDT 24
Peak memory 523768 kb
Host smart-6889a5da-f69a-4e58-8770-227e9352e13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977481896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1977481896
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2228296016
Short name T1123
Test name
Test status
Simulation time 131666101 ps
CPU time 3.61 seconds
Started Jul 28 05:05:42 PM PDT 24
Finished Jul 28 05:05:45 PM PDT 24
Peak memory 224196 kb
Host smart-c2ffc559-8612-46fb-9ee7-5bffdf066f5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228296016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2228296016
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3528480588
Short name T108
Test name
Test status
Simulation time 15742681098 ps
CPU time 102.15 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:07:23 PM PDT 24
Peak memory 1228772 kb
Host smart-9a33e8dd-14a1-4f53-881c-360ab8251f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528480588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3528480588
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3962260118
Short name T1747
Test name
Test status
Simulation time 2490590642 ps
CPU time 7.93 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:25 PM PDT 24
Peak memory 205780 kb
Host smart-44180a9b-4e3a-42a9-b945-02f5da5b49cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962260118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3962260118
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.4172465773
Short name T1524
Test name
Test status
Simulation time 77612294 ps
CPU time 1.23 seconds
Started Jul 28 05:05:58 PM PDT 24
Finished Jul 28 05:05:59 PM PDT 24
Peak memory 214224 kb
Host smart-28d7ed5a-5f3b-4b53-93b6-a3a0b1da0fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172465773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.4172465773
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.4016253651
Short name T1695
Test name
Test status
Simulation time 19134835 ps
CPU time 0.71 seconds
Started Jul 28 05:05:33 PM PDT 24
Finished Jul 28 05:05:34 PM PDT 24
Peak memory 205440 kb
Host smart-da195a32-a782-4a66-b8cc-29fe51946d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016253651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.4016253651
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.431052999
Short name T1242
Test name
Test status
Simulation time 445963812 ps
CPU time 6.99 seconds
Started Jul 28 05:05:46 PM PDT 24
Finished Jul 28 05:05:53 PM PDT 24
Peak memory 267892 kb
Host smart-01df1712-0324-4390-9553-3f216a33fc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431052999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.431052999
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.2950044682
Short name T1370
Test name
Test status
Simulation time 519545402 ps
CPU time 7.51 seconds
Started Jul 28 05:05:53 PM PDT 24
Finished Jul 28 05:06:01 PM PDT 24
Peak memory 205632 kb
Host smart-51b907d5-0ad8-4224-a65f-f6d1219bb15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950044682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.2950044682
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2838540554
Short name T7
Test name
Test status
Simulation time 1782349252 ps
CPU time 83.09 seconds
Started Jul 28 05:05:38 PM PDT 24
Finished Jul 28 05:07:01 PM PDT 24
Peak memory 346792 kb
Host smart-bc0901b3-a616-48e0-a58b-d52f465a56f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838540554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2838540554
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.482411280
Short name T179
Test name
Test status
Simulation time 7793626567 ps
CPU time 346.78 seconds
Started Jul 28 05:05:38 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 839284 kb
Host smart-9667bbc0-4bec-4941-921a-359897fc6b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482411280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.482411280
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3862530155
Short name T1661
Test name
Test status
Simulation time 9503714796 ps
CPU time 18.29 seconds
Started Jul 28 05:05:53 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 220700 kb
Host smart-f31456b2-b554-432c-9799-994dfa5ff14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862530155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3862530155
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1882386767
Short name T442
Test name
Test status
Simulation time 1306879214 ps
CPU time 5.81 seconds
Started Jul 28 05:05:53 PM PDT 24
Finished Jul 28 05:05:59 PM PDT 24
Peak memory 214264 kb
Host smart-4c1f4db0-a6de-428a-a4eb-ac5a03d42255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882386767 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1882386767
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1854665450
Short name T1235
Test name
Test status
Simulation time 437645729 ps
CPU time 1.02 seconds
Started Jul 28 05:05:46 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 205748 kb
Host smart-dedef8c4-838b-42b9-86f2-c89eb7791c93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854665450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1854665450
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2166536818
Short name T1640
Test name
Test status
Simulation time 935667052 ps
CPU time 1.72 seconds
Started Jul 28 05:05:49 PM PDT 24
Finished Jul 28 05:05:51 PM PDT 24
Peak memory 217416 kb
Host smart-864551b8-ea5f-4dd1-aaf8-9d5f5c9ba350
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166536818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2166536818
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.1674566633
Short name T1417
Test name
Test status
Simulation time 1228223183 ps
CPU time 2.31 seconds
Started Jul 28 05:05:42 PM PDT 24
Finished Jul 28 05:05:44 PM PDT 24
Peak memory 205688 kb
Host smart-9953c965-2048-4e7a-98a8-23ee2a4d0a42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674566633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.1674566633
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.1365934303
Short name T1700
Test name
Test status
Simulation time 523721656 ps
CPU time 1.18 seconds
Started Jul 28 05:05:39 PM PDT 24
Finished Jul 28 05:05:41 PM PDT 24
Peak memory 205632 kb
Host smart-f5d1c7bd-5df3-4fe1-882b-93269381ea32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365934303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.1365934303
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2014864337
Short name T1607
Test name
Test status
Simulation time 3278509566 ps
CPU time 9.29 seconds
Started Jul 28 05:05:42 PM PDT 24
Finished Jul 28 05:05:51 PM PDT 24
Peak memory 230560 kb
Host smart-052454e2-c6cf-4624-b717-84060b3206bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014864337 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2014864337
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.1478487325
Short name T451
Test name
Test status
Simulation time 6392671448 ps
CPU time 29.48 seconds
Started Jul 28 05:05:48 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 874552 kb
Host smart-53221348-8a46-4002-9ac6-2202082807eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478487325 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1478487325
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.3466654194
Short name T491
Test name
Test status
Simulation time 4596019204 ps
CPU time 2.9 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:06:00 PM PDT 24
Peak memory 214184 kb
Host smart-2f253ae4-9b6f-4a5b-8dff-e70818a995e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466654194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.3466654194
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.1333571973
Short name T1196
Test name
Test status
Simulation time 2219464982 ps
CPU time 2.57 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:05:43 PM PDT 24
Peak memory 206084 kb
Host smart-a6225192-7f28-417e-8362-e9fdeab811a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333571973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.1333571973
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.3171399630
Short name T1152
Test name
Test status
Simulation time 6796234764 ps
CPU time 5.78 seconds
Started Jul 28 05:05:47 PM PDT 24
Finished Jul 28 05:05:53 PM PDT 24
Peak memory 214656 kb
Host smart-cc5cc0e6-b99c-4ae6-89aa-20b6f42828b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171399630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.3171399630
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.3260563249
Short name T1129
Test name
Test status
Simulation time 566834895 ps
CPU time 2.62 seconds
Started Jul 28 05:05:40 PM PDT 24
Finished Jul 28 05:05:43 PM PDT 24
Peak memory 205760 kb
Host smart-4a23bb97-48e2-47fa-9cc3-f7ec83f5d175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260563249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_smbus_maxlen.3260563249
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3258874425
Short name T752
Test name
Test status
Simulation time 1017969528 ps
CPU time 31.88 seconds
Started Jul 28 05:05:43 PM PDT 24
Finished Jul 28 05:06:15 PM PDT 24
Peak memory 214132 kb
Host smart-ad78b1f8-350f-4e3b-adda-bca2568c9a1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258874425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3258874425
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.749506238
Short name T1701
Test name
Test status
Simulation time 31632277719 ps
CPU time 270.18 seconds
Started Jul 28 05:05:38 PM PDT 24
Finished Jul 28 05:10:09 PM PDT 24
Peak memory 2307680 kb
Host smart-fb9c9fda-c38b-4ae5-abcc-7aa5d1e28369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749506238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_target_stress_all.749506238
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1352937062
Short name T910
Test name
Test status
Simulation time 2642430060 ps
CPU time 55.23 seconds
Started Jul 28 05:05:39 PM PDT 24
Finished Jul 28 05:06:34 PM PDT 24
Peak memory 215664 kb
Host smart-d059eb03-e0c9-44f9-b065-008ac2c3b870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352937062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1352937062
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.955510390
Short name T303
Test name
Test status
Simulation time 14150117099 ps
CPU time 29.36 seconds
Started Jul 28 05:05:45 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 206132 kb
Host smart-77fa9d03-5273-4d97-a4f0-5e1a01b19cb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955510390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_wr.955510390
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.406027913
Short name T690
Test name
Test status
Simulation time 3516313027 ps
CPU time 14.24 seconds
Started Jul 28 05:05:42 PM PDT 24
Finished Jul 28 05:05:57 PM PDT 24
Peak memory 348080 kb
Host smart-98eff4f7-7c60-45a0-b090-eb2f353e3fb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406027913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.406027913
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.338228843
Short name T1330
Test name
Test status
Simulation time 19645399479 ps
CPU time 7.53 seconds
Started Jul 28 05:05:39 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 214252 kb
Host smart-9fe64498-2d4e-402f-a434-3348d368b55f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338228843 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.338228843
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.455020265
Short name T1745
Test name
Test status
Simulation time 143990694 ps
CPU time 2.87 seconds
Started Jul 28 05:05:54 PM PDT 24
Finished Jul 28 05:05:57 PM PDT 24
Peak memory 205976 kb
Host smart-346bbe04-008f-44a3-9ce2-619d37200bd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455020265 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.455020265
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.4125609904
Short name T1690
Test name
Test status
Simulation time 29724770 ps
CPU time 0.62 seconds
Started Jul 28 05:05:55 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 205068 kb
Host smart-dac6fb7e-539c-450a-946f-d9dafe71de3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125609904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.4125609904
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3500632224
Short name T1301
Test name
Test status
Simulation time 77001854 ps
CPU time 1.45 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:05:58 PM PDT 24
Peak memory 213936 kb
Host smart-29093b96-b0a2-4281-b3cb-b33dec8d6e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500632224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3500632224
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3946682315
Short name T956
Test name
Test status
Simulation time 1332477713 ps
CPU time 6.12 seconds
Started Jul 28 05:06:11 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 264220 kb
Host smart-5f890a99-3399-4e6b-ad52-581a5f70eeff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946682315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3946682315
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1493570913
Short name T559
Test name
Test status
Simulation time 2199001140 ps
CPU time 62.85 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:07:02 PM PDT 24
Peak memory 542404 kb
Host smart-20fcd4e3-6a22-492f-a215-40ebd54b182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493570913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1493570913
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2304259646
Short name T712
Test name
Test status
Simulation time 5130309870 ps
CPU time 93.18 seconds
Started Jul 28 05:05:52 PM PDT 24
Finished Jul 28 05:07:25 PM PDT 24
Peak memory 835516 kb
Host smart-8d674d6b-9740-4f8a-9483-fa2cc2d5ff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304259646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2304259646
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2679205006
Short name T759
Test name
Test status
Simulation time 102349285 ps
CPU time 1.11 seconds
Started Jul 28 05:05:54 PM PDT 24
Finished Jul 28 05:05:55 PM PDT 24
Peak memory 205504 kb
Host smart-a4449a04-2fc4-4fa5-8282-8f1fffe4c3e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679205006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2679205006
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4124683170
Short name T324
Test name
Test status
Simulation time 242224752 ps
CPU time 13.87 seconds
Started Jul 28 05:05:58 PM PDT 24
Finished Jul 28 05:06:12 PM PDT 24
Peak memory 254668 kb
Host smart-fad0a94e-602c-4771-8d49-37a743262d0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124683170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4124683170
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.3077008015
Short name T1702
Test name
Test status
Simulation time 9828779575 ps
CPU time 134.82 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:08:14 PM PDT 24
Peak memory 1409884 kb
Host smart-72e64a09-0593-40b9-80f4-34e72e799110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077008015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3077008015
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2451141729
Short name T1282
Test name
Test status
Simulation time 136389638 ps
CPU time 1 seconds
Started Jul 28 05:06:02 PM PDT 24
Finished Jul 28 05:06:03 PM PDT 24
Peak memory 213876 kb
Host smart-4ac2153d-e17d-4dd9-883d-b03496ff5526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451141729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2451141729
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.950975190
Short name T660
Test name
Test status
Simulation time 43398614 ps
CPU time 0.68 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:05:58 PM PDT 24
Peak memory 205384 kb
Host smart-b5300b26-6964-48e9-81e1-33ef151503f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950975190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.950975190
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.907445348
Short name T1740
Test name
Test status
Simulation time 3599507708 ps
CPU time 9.12 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:26 PM PDT 24
Peak memory 236464 kb
Host smart-7e42c91f-b63f-40ba-8a71-2788c5e272eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907445348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.907445348
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.554113506
Short name T537
Test name
Test status
Simulation time 2644148780 ps
CPU time 26.91 seconds
Started Jul 28 05:05:51 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 223404 kb
Host smart-51068ba1-0ba4-488f-bfd2-eb6738d9b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554113506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.554113506
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3281982269
Short name T1325
Test name
Test status
Simulation time 2571531507 ps
CPU time 22.68 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:06:19 PM PDT 24
Peak memory 270640 kb
Host smart-bebb8da0-6059-478d-8642-cd7bcf7523e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281982269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3281982269
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1661561022
Short name T506
Test name
Test status
Simulation time 3903423186 ps
CPU time 14.7 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:06:12 PM PDT 24
Peak memory 222148 kb
Host smart-ef94834f-b2d9-4e5b-9cc7-d9641ff9390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661561022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1661561022
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3534315712
Short name T65
Test name
Test status
Simulation time 3441871931 ps
CPU time 4.89 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:04 PM PDT 24
Peak memory 216864 kb
Host smart-1860188d-fb6f-4fad-8e31-c826f38e9e54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534315712 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3534315712
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2455254855
Short name T590
Test name
Test status
Simulation time 494809392 ps
CPU time 1.24 seconds
Started Jul 28 05:06:23 PM PDT 24
Finished Jul 28 05:06:25 PM PDT 24
Peak memory 205956 kb
Host smart-fda7123d-5239-47d0-8ab9-1b3bdf92fae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455254855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2455254855
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2427146201
Short name T551
Test name
Test status
Simulation time 301020893 ps
CPU time 0.97 seconds
Started Jul 28 05:05:55 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 205896 kb
Host smart-bca99a18-a11f-4316-b831-e66552ed2bd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427146201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2427146201
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.1812720407
Short name T169
Test name
Test status
Simulation time 1684053661 ps
CPU time 2.49 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:06:03 PM PDT 24
Peak memory 205928 kb
Host smart-cb7f5366-d1f5-46aa-9c38-31801ebf7437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812720407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.1812720407
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.1944501864
Short name T812
Test name
Test status
Simulation time 251629628 ps
CPU time 1.59 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:05:58 PM PDT 24
Peak memory 205652 kb
Host smart-a60473be-9ce9-486b-b743-d0f2adf408bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944501864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.1944501864
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3996238048
Short name T1161
Test name
Test status
Simulation time 1365847205 ps
CPU time 5.67 seconds
Started Jul 28 05:06:12 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 222300 kb
Host smart-1192e1e6-155b-486c-a4b1-019e774b59f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996238048 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3996238048
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3941119961
Short name T1686
Test name
Test status
Simulation time 21299384166 ps
CPU time 432.69 seconds
Started Jul 28 05:06:02 PM PDT 24
Finished Jul 28 05:13:15 PM PDT 24
Peak memory 3507636 kb
Host smart-25f8b717-3a7c-4601-8d88-f014b2beeeca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941119961 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3941119961
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.2204794819
Short name T1424
Test name
Test status
Simulation time 1113826528 ps
CPU time 2.9 seconds
Started Jul 28 05:06:08 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 214236 kb
Host smart-2f387795-84d3-4c62-86e8-39752ee79b77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204794819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_acqfull.2204794819
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.1309433841
Short name T909
Test name
Test status
Simulation time 2141321714 ps
CPU time 2.75 seconds
Started Jul 28 05:05:55 PM PDT 24
Finished Jul 28 05:05:58 PM PDT 24
Peak memory 205864 kb
Host smart-824f8fe1-2c99-4d68-9357-2372229f3b8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309433841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.1309433841
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_txstretch.1885742517
Short name T1479
Test name
Test status
Simulation time 531590268 ps
CPU time 1.34 seconds
Started Jul 28 05:05:50 PM PDT 24
Finished Jul 28 05:05:52 PM PDT 24
Peak memory 222476 kb
Host smart-4d7f4367-bbe2-4254-99fb-e2838d55e317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885742517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_nack_txstretch.1885742517
Directory /workspace/38.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/38.i2c_target_perf.1611553243
Short name T90
Test name
Test status
Simulation time 660494585 ps
CPU time 5.01 seconds
Started Jul 28 05:05:55 PM PDT 24
Finished Jul 28 05:06:00 PM PDT 24
Peak memory 222292 kb
Host smart-b49e8651-d6a9-45db-8ef6-c06091b24390
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611553243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.1611553243
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.670719803
Short name T1630
Test name
Test status
Simulation time 562431209 ps
CPU time 2.52 seconds
Started Jul 28 05:05:52 PM PDT 24
Finished Jul 28 05:05:55 PM PDT 24
Peak memory 205708 kb
Host smart-cd003037-80a1-411f-a51f-d01b9741e15a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670719803 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_smbus_maxlen.670719803
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1971318974
Short name T310
Test name
Test status
Simulation time 1375002285 ps
CPU time 17.25 seconds
Started Jul 28 05:05:53 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 214148 kb
Host smart-e13f3304-2636-4810-b91e-11dd4ca5f28d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971318974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1971318974
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.765098974
Short name T1364
Test name
Test status
Simulation time 14839585475 ps
CPU time 45.77 seconds
Started Jul 28 05:05:53 PM PDT 24
Finished Jul 28 05:06:39 PM PDT 24
Peak memory 265808 kb
Host smart-7729bd1d-5565-4dfb-bf5b-d9b5fa03e1d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765098974 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_stress_all.765098974
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.949720953
Short name T1292
Test name
Test status
Simulation time 1650051897 ps
CPU time 11.77 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 210244 kb
Host smart-20d0f519-5b50-4f46-aed1-e86e68fcd50a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949720953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.949720953
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.641446577
Short name T409
Test name
Test status
Simulation time 64775906805 ps
CPU time 1187.62 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:25:47 PM PDT 24
Peak memory 6716124 kb
Host smart-6e7cdb0b-dded-4a5a-b5f1-ea4e3f9dc35c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641446577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.641446577
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1168094116
Short name T954
Test name
Test status
Simulation time 212113481 ps
CPU time 1.78 seconds
Started Jul 28 05:06:12 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 205904 kb
Host smart-eaec811c-16ee-4378-b16f-e0346357b8af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168094116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1168094116
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3482598537
Short name T889
Test name
Test status
Simulation time 1815295979 ps
CPU time 6.21 seconds
Started Jul 28 05:05:50 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 214092 kb
Host smart-4227463c-a70a-45fc-b076-4294c5e7e4da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482598537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3482598537
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.1154558721
Short name T58
Test name
Test status
Simulation time 864066313 ps
CPU time 10.29 seconds
Started Jul 28 05:06:16 PM PDT 24
Finished Jul 28 05:06:26 PM PDT 24
Peak memory 205880 kb
Host smart-9dfdcd9b-859e-45d5-bc96-3329fadd2f9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154558721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.1154558721
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.4293064951
Short name T1558
Test name
Test status
Simulation time 35187602 ps
CPU time 0.64 seconds
Started Jul 28 05:06:14 PM PDT 24
Finished Jul 28 05:06:15 PM PDT 24
Peak memory 204896 kb
Host smart-fe2d6d7d-4cba-4fba-bcf0-58c5189145c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293064951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.4293064951
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2265613138
Short name T584
Test name
Test status
Simulation time 157054738 ps
CPU time 2.76 seconds
Started Jul 28 05:06:11 PM PDT 24
Finished Jul 28 05:06:13 PM PDT 24
Peak memory 230256 kb
Host smart-49247c96-fed9-47ce-b36a-38f75fbf08b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265613138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2265613138
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.3904173334
Short name T1016
Test name
Test status
Simulation time 729053458 ps
CPU time 6.76 seconds
Started Jul 28 05:06:22 PM PDT 24
Finished Jul 28 05:06:29 PM PDT 24
Peak memory 282364 kb
Host smart-2bb53bb2-ffdb-4d46-8fae-ec591d4b3048
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904173334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.3904173334
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.904075614
Short name T25
Test name
Test status
Simulation time 14402280436 ps
CPU time 85.77 seconds
Started Jul 28 05:06:14 PM PDT 24
Finished Jul 28 05:07:40 PM PDT 24
Peak memory 678728 kb
Host smart-1c258ca8-c780-4d7e-9139-4bab02fc1e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904075614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.904075614
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2935797810
Short name T173
Test name
Test status
Simulation time 3709046251 ps
CPU time 68.05 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:07:07 PM PDT 24
Peak memory 718496 kb
Host smart-0ec7d38b-e07b-4e0a-b191-aa8161672846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935797810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2935797810
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3962608232
Short name T38
Test name
Test status
Simulation time 147734107 ps
CPU time 0.99 seconds
Started Jul 28 05:06:02 PM PDT 24
Finished Jul 28 05:06:03 PM PDT 24
Peak memory 205404 kb
Host smart-9effda2b-4b76-45e5-897e-0be96ef9396f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962608232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3962608232
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1716233524
Short name T1017
Test name
Test status
Simulation time 363388275 ps
CPU time 12.01 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 246236 kb
Host smart-b4a9368c-4eaf-4385-845d-83f0dee1adae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716233524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1716233524
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.163034947
Short name T119
Test name
Test status
Simulation time 3030708336 ps
CPU time 196.18 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:09:13 PM PDT 24
Peak memory 954404 kb
Host smart-f849ecfb-503e-40ce-a359-229b2bca11dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163034947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.163034947
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3228897915
Short name T1518
Test name
Test status
Simulation time 1138260142 ps
CPU time 11.88 seconds
Started Jul 28 05:05:54 PM PDT 24
Finished Jul 28 05:06:06 PM PDT 24
Peak memory 205712 kb
Host smart-ee6f95c7-94de-44b7-b939-8ee4ad7b5478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228897915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3228897915
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_override.2366663802
Short name T1455
Test name
Test status
Simulation time 15490912 ps
CPU time 0.71 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:06:01 PM PDT 24
Peak memory 205408 kb
Host smart-846d2a0d-f339-48fb-9eba-1af081b0a1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366663802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2366663802
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3695112615
Short name T1439
Test name
Test status
Simulation time 7441727997 ps
CPU time 68 seconds
Started Jul 28 05:05:54 PM PDT 24
Finished Jul 28 05:07:02 PM PDT 24
Peak memory 214068 kb
Host smart-597b8b31-f5c6-4012-854a-0d6660e9d51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695112615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3695112615
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.2495789036
Short name T1036
Test name
Test status
Simulation time 224022299 ps
CPU time 9.15 seconds
Started Jul 28 05:06:08 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 213924 kb
Host smart-829cf5cf-4ae5-4c7a-9ad2-7add0e2c0fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495789036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.2495789036
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1234455657
Short name T1491
Test name
Test status
Simulation time 1685907361 ps
CPU time 27 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:06:24 PM PDT 24
Peak memory 358556 kb
Host smart-5dc2c0ea-5649-42eb-b613-5e6fbda29f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234455657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1234455657
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.1113330033
Short name T1511
Test name
Test status
Simulation time 219186686620 ps
CPU time 1241.98 seconds
Started Jul 28 05:05:52 PM PDT 24
Finished Jul 28 05:26:34 PM PDT 24
Peak memory 1895148 kb
Host smart-1867c8db-a2b3-46c1-9a27-3d2fd70fda7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113330033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.1113330033
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1636602652
Short name T1281
Test name
Test status
Simulation time 519547226 ps
CPU time 22.47 seconds
Started Jul 28 05:06:11 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 214000 kb
Host smart-b9041199-c7ea-432b-8f51-09d149a01942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636602652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1636602652
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2349991729
Short name T1397
Test name
Test status
Simulation time 860050842 ps
CPU time 4.78 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:04 PM PDT 24
Peak memory 218884 kb
Host smart-a00e9c22-3420-44e8-95f9-d2c7585cca9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349991729 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2349991729
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2567103127
Short name T117
Test name
Test status
Simulation time 129201584 ps
CPU time 0.75 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 205720 kb
Host smart-646e7d53-8ca7-4376-9f06-90e46aae82aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567103127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2567103127
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.351039616
Short name T916
Test name
Test status
Simulation time 1002616829 ps
CPU time 1.05 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:06:02 PM PDT 24
Peak memory 205652 kb
Host smart-8c9b26e1-4dff-4519-bef2-2cc3c78f8597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351039616 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.351039616
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.3383932064
Short name T594
Test name
Test status
Simulation time 615155964 ps
CPU time 1.74 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:05:57 PM PDT 24
Peak memory 205676 kb
Host smart-2e265b1d-0787-4a40-b09e-2957ca6b2deb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383932064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.3383932064
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.3219622025
Short name T549
Test name
Test status
Simulation time 676419022 ps
CPU time 1.6 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:01 PM PDT 24
Peak memory 205724 kb
Host smart-5fb3ab02-a913-4236-9cfb-4d9cc3904064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219622025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.3219622025
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.3705473827
Short name T470
Test name
Test status
Simulation time 883492978 ps
CPU time 1.71 seconds
Started Jul 28 05:05:55 PM PDT 24
Finished Jul 28 05:05:57 PM PDT 24
Peak memory 214108 kb
Host smart-0b6f67c6-2063-4f8f-862f-f41d2229ad5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705473827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.3705473827
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1250885037
Short name T747
Test name
Test status
Simulation time 817890014 ps
CPU time 4.51 seconds
Started Jul 28 05:05:55 PM PDT 24
Finished Jul 28 05:06:00 PM PDT 24
Peak memory 214180 kb
Host smart-c8e4cbea-3363-4722-ad9d-985cc9fda20e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250885037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1250885037
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.862432249
Short name T562
Test name
Test status
Simulation time 10033926535 ps
CPU time 190.56 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:09:07 PM PDT 24
Peak memory 2541164 kb
Host smart-46296a3b-3ebd-4972-b193-21366116f808
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862432249 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.862432249
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.3986814441
Short name T89
Test name
Test status
Simulation time 531926924 ps
CPU time 2.7 seconds
Started Jul 28 05:06:08 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 214128 kb
Host smart-925d378d-b102-40ed-9f53-22369755b1ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986814441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_nack_acqfull.3986814441
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.2792036183
Short name T415
Test name
Test status
Simulation time 420959842 ps
CPU time 2.53 seconds
Started Jul 28 05:06:19 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 205880 kb
Host smart-0dfcf361-dc63-4ba4-bc54-2a3fdf14d8cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792036183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.2792036183
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_txstretch.2049961367
Short name T894
Test name
Test status
Simulation time 672730471 ps
CPU time 1.42 seconds
Started Jul 28 05:05:54 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 222752 kb
Host smart-312721a6-4d9d-4eb6-9c62-3725196e250f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049961367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_nack_txstretch.2049961367
Directory /workspace/39.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/39.i2c_target_perf.3840169671
Short name T729
Test name
Test status
Simulation time 8548702867 ps
CPU time 6.64 seconds
Started Jul 28 05:06:04 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 222412 kb
Host smart-2635b143-1331-4d13-b529-7efb02798d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840169671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.3840169671
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.3506212340
Short name T645
Test name
Test status
Simulation time 1734180268 ps
CPU time 2.14 seconds
Started Jul 28 05:06:11 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 205672 kb
Host smart-389e8246-206e-4983-aa70-84b721212ab3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506212340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_smbus_maxlen.3506212340
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3480510326
Short name T280
Test name
Test status
Simulation time 1021683405 ps
CPU time 32.66 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:32 PM PDT 24
Peak memory 214152 kb
Host smart-a329cbaf-6589-4bcf-a689-1e8a7c5411e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480510326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3480510326
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.213982691
Short name T973
Test name
Test status
Simulation time 43385898174 ps
CPU time 238.61 seconds
Started Jul 28 05:05:52 PM PDT 24
Finished Jul 28 05:09:51 PM PDT 24
Peak memory 1986868 kb
Host smart-34a96143-ac27-4692-98ff-4d5ba59caa2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213982691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.i2c_target_stress_all.213982691
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1747471373
Short name T1212
Test name
Test status
Simulation time 3241150716 ps
CPU time 10.83 seconds
Started Jul 28 05:06:23 PM PDT 24
Finished Jul 28 05:06:34 PM PDT 24
Peak memory 206040 kb
Host smart-e753bb19-5487-4e2b-89a3-babc4e0a26a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747471373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1747471373
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.160220468
Short name T1723
Test name
Test status
Simulation time 36071502614 ps
CPU time 438.54 seconds
Started Jul 28 05:06:04 PM PDT 24
Finished Jul 28 05:13:23 PM PDT 24
Peak memory 3959148 kb
Host smart-b2c612a2-25cf-48b0-81a5-f55bb888ecf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160220468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.160220468
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3291780433
Short name T462
Test name
Test status
Simulation time 1843143429 ps
CPU time 14.07 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:06:10 PM PDT 24
Peak memory 410312 kb
Host smart-aa08d4e6-3a77-406f-8cd0-ef93c9d8d204
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291780433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3291780433
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3588561331
Short name T403
Test name
Test status
Simulation time 1403817935 ps
CPU time 7.3 seconds
Started Jul 28 05:06:11 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 218764 kb
Host smart-4eb7ce47-c61c-4ee4-9b72-7ec98570f8e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588561331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3588561331
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.1298020269
Short name T925
Test name
Test status
Simulation time 182564920 ps
CPU time 2.54 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:06:00 PM PDT 24
Peak memory 205892 kb
Host smart-4b52c778-12ab-48f7-9224-efc528f395cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298020269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.1298020269
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3287914157
Short name T702
Test name
Test status
Simulation time 15196387 ps
CPU time 0.61 seconds
Started Jul 28 05:03:13 PM PDT 24
Finished Jul 28 05:03:14 PM PDT 24
Peak memory 204908 kb
Host smart-8354c828-a39a-45bb-b3f7-f3fb5a9fe14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287914157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3287914157
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3820339310
Short name T568
Test name
Test status
Simulation time 177951148 ps
CPU time 1.8 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:06 PM PDT 24
Peak memory 217852 kb
Host smart-88825dad-2cc9-4169-86da-00312c7f8158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820339310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3820339310
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.986416088
Short name T307
Test name
Test status
Simulation time 1745593376 ps
CPU time 21.73 seconds
Started Jul 28 05:02:59 PM PDT 24
Finished Jul 28 05:03:26 PM PDT 24
Peak memory 282296 kb
Host smart-e7aeb6e5-6326-4c39-bc10-e5b9bbba2c8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986416088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.986416088
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.872708585
Short name T408
Test name
Test status
Simulation time 3263059064 ps
CPU time 106.07 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:04:55 PM PDT 24
Peak memory 705932 kb
Host smart-a925e4a2-30b1-4f9d-b9bb-9df09370a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872708585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.872708585
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1164630642
Short name T1326
Test name
Test status
Simulation time 1974733753 ps
CPU time 67.28 seconds
Started Jul 28 05:02:58 PM PDT 24
Finished Jul 28 05:04:05 PM PDT 24
Peak memory 679572 kb
Host smart-aee951da-c6e9-40eb-824d-6e2df3091e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164630642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1164630642
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.3158672938
Short name T246
Test name
Test status
Simulation time 212447760 ps
CPU time 1.1 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 205520 kb
Host smart-9b06de0a-f769-4496-a98c-64704e4a746b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158672938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.3158672938
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1151124423
Short name T1756
Test name
Test status
Simulation time 220919415 ps
CPU time 4.2 seconds
Started Jul 28 05:02:57 PM PDT 24
Finished Jul 28 05:03:01 PM PDT 24
Peak memory 205696 kb
Host smart-cf9a3752-e5b2-4100-b591-c4de7c1b7a71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151124423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1151124423
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2323637868
Short name T1432
Test name
Test status
Simulation time 20108526696 ps
CPU time 155.76 seconds
Started Jul 28 05:03:02 PM PDT 24
Finished Jul 28 05:05:38 PM PDT 24
Peak memory 1378840 kb
Host smart-85eb7f91-acd9-4446-a0dd-8eebb2975e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323637868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2323637868
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3365244006
Short name T1752
Test name
Test status
Simulation time 537468728 ps
CPU time 9.01 seconds
Started Jul 28 05:02:50 PM PDT 24
Finished Jul 28 05:03:00 PM PDT 24
Peak memory 205660 kb
Host smart-c3745cda-4f03-48a8-9a88-791fd3cd2eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365244006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3365244006
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1399420931
Short name T1650
Test name
Test status
Simulation time 213600480 ps
CPU time 1.87 seconds
Started Jul 28 05:03:10 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 222124 kb
Host smart-165911af-7f18-4b04-934b-648c11332d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399420931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1399420931
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2439300391
Short name T1418
Test name
Test status
Simulation time 90308264 ps
CPU time 0.69 seconds
Started Jul 28 05:03:11 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 205436 kb
Host smart-fadaf2bd-4f70-4d59-a437-2f6e00a1890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439300391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2439300391
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.4273437467
Short name T516
Test name
Test status
Simulation time 7076234234 ps
CPU time 26.56 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:31 PM PDT 24
Peak memory 228328 kb
Host smart-90a40966-976f-49c0-b47d-576ec7389c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273437467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.4273437467
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.2539121886
Short name T1415
Test name
Test status
Simulation time 213108124 ps
CPU time 8.36 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:57 PM PDT 24
Peak memory 205648 kb
Host smart-d6357572-672b-451c-9b9a-55f13d4fb821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539121886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.2539121886
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1930247825
Short name T1003
Test name
Test status
Simulation time 2285643738 ps
CPU time 45.84 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:03:42 PM PDT 24
Peak memory 416372 kb
Host smart-dc068656-999f-420f-9c5d-ab71613c8fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930247825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1930247825
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1800215783
Short name T847
Test name
Test status
Simulation time 8096618396 ps
CPU time 15.6 seconds
Started Jul 28 05:03:05 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 218564 kb
Host smart-c0e87aef-178c-48d3-86ca-a5054fff3052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800215783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1800215783
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1215822974
Short name T186
Test name
Test status
Simulation time 140683426 ps
CPU time 0.86 seconds
Started Jul 28 05:03:00 PM PDT 24
Finished Jul 28 05:03:01 PM PDT 24
Peak memory 224044 kb
Host smart-409e168c-794e-49a5-9b72-19bc2997ab2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215822974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1215822974
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.2627926853
Short name T1181
Test name
Test status
Simulation time 2945898641 ps
CPU time 4.15 seconds
Started Jul 28 05:03:13 PM PDT 24
Finished Jul 28 05:03:17 PM PDT 24
Peak memory 214252 kb
Host smart-caa6dd7c-599c-457b-b444-9d524d6bae0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627926853 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.2627926853
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2665679234
Short name T717
Test name
Test status
Simulation time 194402681 ps
CPU time 1.22 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:17 PM PDT 24
Peak memory 205728 kb
Host smart-3adce67e-2563-4886-8ce3-8d693b50a0ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665679234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2665679234
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3501272514
Short name T1133
Test name
Test status
Simulation time 491417074 ps
CPU time 1.23 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:02:52 PM PDT 24
Peak memory 205852 kb
Host smart-2be5b367-09b4-4b50-a4f5-fe9f20426c1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501272514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3501272514
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.108136320
Short name T1421
Test name
Test status
Simulation time 439462216 ps
CPU time 2.35 seconds
Started Jul 28 05:03:05 PM PDT 24
Finished Jul 28 05:03:07 PM PDT 24
Peak memory 205920 kb
Host smart-f1f2337e-ed56-48ef-b72d-eece10c11e7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108136320 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.108136320
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.2553659557
Short name T395
Test name
Test status
Simulation time 313122173 ps
CPU time 1.32 seconds
Started Jul 28 05:02:52 PM PDT 24
Finished Jul 28 05:02:54 PM PDT 24
Peak memory 205696 kb
Host smart-ed28e200-c8ef-49ea-ae50-1473bf4cf51a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553659557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.2553659557
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3145583617
Short name T487
Test name
Test status
Simulation time 853221996 ps
CPU time 5.15 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:03:02 PM PDT 24
Peak memory 222236 kb
Host smart-0865a080-dc62-45ba-89ff-b1c9f2410984
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145583617 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3145583617
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3077735345
Short name T378
Test name
Test status
Simulation time 8514688370 ps
CPU time 109.77 seconds
Started Jul 28 05:03:07 PM PDT 24
Finished Jul 28 05:04:57 PM PDT 24
Peak memory 2130712 kb
Host smart-a4c36d48-2c2d-4c0e-97ea-9ff69553298b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077735345 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3077735345
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.2586639818
Short name T1099
Test name
Test status
Simulation time 475503328 ps
CPU time 2.68 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:18 PM PDT 24
Peak memory 214080 kb
Host smart-79a447df-d20b-4322-bbdf-840c271ab464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586639818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.2586639818
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.630461617
Short name T1043
Test name
Test status
Simulation time 512514825 ps
CPU time 2.54 seconds
Started Jul 28 05:03:01 PM PDT 24
Finished Jul 28 05:03:04 PM PDT 24
Peak memory 205960 kb
Host smart-b143d9ef-67cc-416f-857e-1cc145203666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630461617 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.630461617
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.2562466146
Short name T1601
Test name
Test status
Simulation time 2574412326 ps
CPU time 4.64 seconds
Started Jul 28 05:03:00 PM PDT 24
Finished Jul 28 05:03:04 PM PDT 24
Peak memory 214164 kb
Host smart-8e321867-1743-4480-a7c4-a67584717de5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562466146 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.2562466146
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.1149523343
Short name T1331
Test name
Test status
Simulation time 3407676219 ps
CPU time 2.24 seconds
Started Jul 28 05:03:13 PM PDT 24
Finished Jul 28 05:03:15 PM PDT 24
Peak memory 205832 kb
Host smart-8fbee8a7-568c-46c4-ad0b-d87e64082b5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149523343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_smbus_maxlen.1149523343
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2847380857
Short name T1677
Test name
Test status
Simulation time 2896315152 ps
CPU time 14.16 seconds
Started Jul 28 05:02:58 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 214228 kb
Host smart-4c79bf52-958b-44eb-9cdb-c0d5daca8a2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847380857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2847380857
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.1277804897
Short name T1502
Test name
Test status
Simulation time 39270381508 ps
CPU time 672.18 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 3394688 kb
Host smart-b2e85ab7-daf8-451b-a176-87404de01115
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277804897 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.1277804897
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3069811171
Short name T1340
Test name
Test status
Simulation time 3955423365 ps
CPU time 8.06 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:23 PM PDT 24
Peak memory 206028 kb
Host smart-c727b620-e8cd-4bf3-bff4-708592c4e398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069811171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3069811171
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3644663024
Short name T1555
Test name
Test status
Simulation time 27790263328 ps
CPU time 154.49 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:05:26 PM PDT 24
Peak memory 1994156 kb
Host smart-f6321fc7-a292-423d-b522-529f7c196d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644663024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3644663024
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.4212386835
Short name T316
Test name
Test status
Simulation time 4564153195 ps
CPU time 85.52 seconds
Started Jul 28 05:02:47 PM PDT 24
Finished Jul 28 05:04:12 PM PDT 24
Peak memory 1228772 kb
Host smart-a1115f75-14bf-4327-a144-a9ba00e4c695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212386835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.4212386835
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.321112489
Short name T1649
Test name
Test status
Simulation time 1504930337 ps
CPU time 7.46 seconds
Started Jul 28 05:03:09 PM PDT 24
Finished Jul 28 05:03:16 PM PDT 24
Peak memory 217680 kb
Host smart-674d6fa5-18b1-4d1f-9efd-46f0b3224852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321112489 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_timeout.321112489
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.4222577000
Short name T985
Test name
Test status
Simulation time 1265229031 ps
CPU time 14.6 seconds
Started Jul 28 05:02:55 PM PDT 24
Finished Jul 28 05:03:10 PM PDT 24
Peak memory 214116 kb
Host smart-6c4554d4-12ec-41e0-934d-816fa907c120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222577000 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.4222577000
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.829575940
Short name T1040
Test name
Test status
Simulation time 52654225 ps
CPU time 0.69 seconds
Started Jul 28 05:06:02 PM PDT 24
Finished Jul 28 05:06:02 PM PDT 24
Peak memory 205008 kb
Host smart-3a9fbe99-c061-4789-a163-1f647e706ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829575940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.829575940
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2428040697
Short name T132
Test name
Test status
Simulation time 769957284 ps
CPU time 3.39 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:05:59 PM PDT 24
Peak memory 223808 kb
Host smart-5a0c5c66-ea20-4d6a-9745-9100e056ba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428040697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2428040697
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.4074957765
Short name T1249
Test name
Test status
Simulation time 488501894 ps
CPU time 10.14 seconds
Started Jul 28 05:06:03 PM PDT 24
Finished Jul 28 05:06:13 PM PDT 24
Peak memory 295820 kb
Host smart-b61a0b2e-9e6c-4c2a-8c1d-65b4d1e831d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074957765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.4074957765
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.20240124
Short name T1609
Test name
Test status
Simulation time 3484747693 ps
CPU time 117.01 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 623376 kb
Host smart-9b693513-d983-4f91-884a-a2ce58de0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20240124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.20240124
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3503925334
Short name T343
Test name
Test status
Simulation time 8370170969 ps
CPU time 60.85 seconds
Started Jul 28 05:06:10 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 709864 kb
Host smart-f0ef6d12-7ca0-4ec2-9bb8-d793843a39cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503925334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3503925334
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.321829039
Short name T1105
Test name
Test status
Simulation time 96993559 ps
CPU time 0.9 seconds
Started Jul 28 05:06:19 PM PDT 24
Finished Jul 28 05:06:20 PM PDT 24
Peak memory 205452 kb
Host smart-67cfaca0-ed1c-44bc-9bef-f18ee4168ced
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321829039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.321829039
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.800940012
Short name T1582
Test name
Test status
Simulation time 894628620 ps
CPU time 5.33 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:06:20 PM PDT 24
Peak memory 249708 kb
Host smart-136cee71-c6e8-477a-8d2c-4221527de8f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800940012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
800940012
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3678669998
Short name T1520
Test name
Test status
Simulation time 3626946925 ps
CPU time 236.16 seconds
Started Jul 28 05:05:54 PM PDT 24
Finished Jul 28 05:09:50 PM PDT 24
Peak memory 1010340 kb
Host smart-d0b324ad-8c0b-4583-9961-594a3c6af712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678669998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3678669998
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1427734223
Short name T268
Test name
Test status
Simulation time 262282009 ps
CPU time 11.04 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:06:09 PM PDT 24
Peak memory 205840 kb
Host smart-34aa098d-5a5f-4b93-a944-b873c8046dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427734223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1427734223
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_override.2380808672
Short name T1127
Test name
Test status
Simulation time 53251267 ps
CPU time 0.69 seconds
Started Jul 28 05:05:53 PM PDT 24
Finished Jul 28 05:05:54 PM PDT 24
Peak memory 205388 kb
Host smart-dbd1c688-5a4e-44ea-9d2a-204067461b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380808672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2380808672
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1430398055
Short name T1371
Test name
Test status
Simulation time 2770276458 ps
CPU time 28.62 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:06:42 PM PDT 24
Peak memory 258196 kb
Host smart-6a76aea8-28f8-48dc-9aaf-8fd5db9f4d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430398055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1430398055
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.1109580232
Short name T926
Test name
Test status
Simulation time 51449390 ps
CPU time 1.49 seconds
Started Jul 28 05:06:09 PM PDT 24
Finished Jul 28 05:06:10 PM PDT 24
Peak memory 214324 kb
Host smart-b709c08c-3b81-44e4-b15f-5f396d285964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109580232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.1109580232
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.435159487
Short name T1733
Test name
Test status
Simulation time 3829880293 ps
CPU time 85.63 seconds
Started Jul 28 05:06:19 PM PDT 24
Finished Jul 28 05:07:45 PM PDT 24
Peak memory 334336 kb
Host smart-7538cc12-85c8-4023-913d-fdd25cca8eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435159487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.435159487
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.56682189
Short name T885
Test name
Test status
Simulation time 68293326495 ps
CPU time 1154.52 seconds
Started Jul 28 05:06:11 PM PDT 24
Finished Jul 28 05:25:26 PM PDT 24
Peak memory 3162528 kb
Host smart-d5fa3b1c-bcc0-4e43-a08a-43d39ff7eaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56682189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.56682189
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.1073598140
Short name T302
Test name
Test status
Simulation time 1918553663 ps
CPU time 21 seconds
Started Jul 28 05:06:00 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 213976 kb
Host smart-5a50d635-b5c6-4b65-914c-6e5572d3c709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073598140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.1073598140
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2489271213
Short name T47
Test name
Test status
Simulation time 3272389143 ps
CPU time 4.39 seconds
Started Jul 28 05:06:08 PM PDT 24
Finished Jul 28 05:06:12 PM PDT 24
Peak memory 214224 kb
Host smart-dc14804f-b78a-4eca-b3bf-cefdf2f4be03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489271213 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2489271213
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.133843553
Short name T1363
Test name
Test status
Simulation time 422993439 ps
CPU time 1.02 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 205676 kb
Host smart-cf0dc791-b3b7-4665-a850-185e967c1ce8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133843553 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.133843553
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.4291631452
Short name T1193
Test name
Test status
Simulation time 368224846 ps
CPU time 1.16 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:06:16 PM PDT 24
Peak memory 205656 kb
Host smart-a39eee37-6311-41ae-8f2d-599d13dedf9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291631452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.4291631452
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.463537941
Short name T1645
Test name
Test status
Simulation time 764952403 ps
CPU time 2.08 seconds
Started Jul 28 05:06:09 PM PDT 24
Finished Jul 28 05:06:12 PM PDT 24
Peak memory 205660 kb
Host smart-e8f3310d-e61d-4470-a119-9bba1c277ec9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463537941 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.463537941
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.2398342752
Short name T293
Test name
Test status
Simulation time 116290509 ps
CPU time 1.21 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:06:23 PM PDT 24
Peak memory 205776 kb
Host smart-6a1f36e6-32f1-4758-a0cb-1b00688ff5b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398342752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.2398342752
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3459564949
Short name T1680
Test name
Test status
Simulation time 411915116 ps
CPU time 2.62 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 208720 kb
Host smart-7b215b75-663c-45f1-8551-54544a8a0efa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459564949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3459564949
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2131076811
Short name T641
Test name
Test status
Simulation time 3230357882 ps
CPU time 8.24 seconds
Started Jul 28 05:06:05 PM PDT 24
Finished Jul 28 05:06:13 PM PDT 24
Peak memory 214268 kb
Host smart-da97d847-fe81-4859-8c42-2e56d242917b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131076811 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2131076811
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.1244271030
Short name T1525
Test name
Test status
Simulation time 11056105678 ps
CPU time 65.47 seconds
Started Jul 28 05:06:20 PM PDT 24
Finished Jul 28 05:07:26 PM PDT 24
Peak memory 1392904 kb
Host smart-d7404bea-9d5b-402f-8906-b40a523b62fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244271030 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.1244271030
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.1377254771
Short name T1319
Test name
Test status
Simulation time 8565298939 ps
CPU time 2.5 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:06:04 PM PDT 24
Peak memory 214208 kb
Host smart-302d605f-e723-4daa-827d-406082f91b20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377254771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_acqfull.1377254771
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.2708037975
Short name T1552
Test name
Test status
Simulation time 509607638 ps
CPU time 2.62 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:06:03 PM PDT 24
Peak memory 206888 kb
Host smart-2306a915-0edf-4c28-9f74-b8eaef165c78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708037975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.2708037975
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_txstretch.221032243
Short name T1163
Test name
Test status
Simulation time 522321455 ps
CPU time 1.39 seconds
Started Jul 28 05:06:07 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 222340 kb
Host smart-5c0f94bf-497a-4f44-860d-d99d3b68938a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221032243 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_nack_txstretch.221032243
Directory /workspace/40.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/40.i2c_target_perf.2822326068
Short name T311
Test name
Test status
Simulation time 1133912454 ps
CPU time 3.95 seconds
Started Jul 28 05:06:12 PM PDT 24
Finished Jul 28 05:06:16 PM PDT 24
Peak memory 216096 kb
Host smart-097600c8-b308-4671-b8ad-972433c04d1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822326068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.2822326068
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.2881243031
Short name T1173
Test name
Test status
Simulation time 1266697430 ps
CPU time 1.98 seconds
Started Jul 28 05:06:02 PM PDT 24
Finished Jul 28 05:06:04 PM PDT 24
Peak memory 205696 kb
Host smart-4b690726-2f9f-4744-aaf6-2eb9896909c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881243031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.2881243031
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3052944773
Short name T923
Test name
Test status
Simulation time 3444078612 ps
CPU time 19.61 seconds
Started Jul 28 05:05:57 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 214180 kb
Host smart-8b73ef2b-c4b5-45d2-9bc3-ae240e8db48e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052944773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3052944773
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.4174764329
Short name T898
Test name
Test status
Simulation time 42028137821 ps
CPU time 96.27 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:07:33 PM PDT 24
Peak memory 681152 kb
Host smart-73988054-fb4d-4435-8d74-4dd276c34487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174764329 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.4174764329
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.15797422
Short name T1655
Test name
Test status
Simulation time 7841799170 ps
CPU time 38.29 seconds
Started Jul 28 05:06:09 PM PDT 24
Finished Jul 28 05:06:48 PM PDT 24
Peak memory 238512 kb
Host smart-3b4bbb9a-c9c7-4f84-86da-dad282fee74f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15797422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stress_rd.15797422
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.1951701131
Short name T1448
Test name
Test status
Simulation time 16620709427 ps
CPU time 18.73 seconds
Started Jul 28 05:06:22 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 206276 kb
Host smart-5a6ed1e3-16a1-4820-bac3-3d97fba2ceb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951701131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.1951701131
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.273383127
Short name T1178
Test name
Test status
Simulation time 238769060 ps
CPU time 1.05 seconds
Started Jul 28 05:05:58 PM PDT 24
Finished Jul 28 05:05:59 PM PDT 24
Peak memory 205612 kb
Host smart-64845e02-c2ab-4ff4-b1d1-8a1a5480b70c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273383127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.273383127
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.2052227624
Short name T787
Test name
Test status
Simulation time 4653602075 ps
CPU time 6.09 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:05 PM PDT 24
Peak memory 219068 kb
Host smart-ad3a6ce7-d051-48c3-8288-9cd09dd1344f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052227624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.2052227624
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.1961478327
Short name T1430
Test name
Test status
Simulation time 43344059 ps
CPU time 1.2 seconds
Started Jul 28 05:06:02 PM PDT 24
Finished Jul 28 05:06:03 PM PDT 24
Peak memory 205996 kb
Host smart-2cd8ebc9-bf87-4ecf-be32-6909451ea04a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961478327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.1961478327
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2614825714
Short name T591
Test name
Test status
Simulation time 54235810 ps
CPU time 0.64 seconds
Started Jul 28 05:06:04 PM PDT 24
Finished Jul 28 05:06:05 PM PDT 24
Peak memory 204996 kb
Host smart-61ad5a33-ad76-472e-afa7-f1810dd7e070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614825714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2614825714
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.784862207
Short name T1652
Test name
Test status
Simulation time 3030794376 ps
CPU time 10.75 seconds
Started Jul 28 05:06:20 PM PDT 24
Finished Jul 28 05:06:31 PM PDT 24
Peak memory 214112 kb
Host smart-54ba08fe-effd-4738-8be3-a01586d3530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784862207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.784862207
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3567561762
Short name T1544
Test name
Test status
Simulation time 1823855473 ps
CPU time 9.86 seconds
Started Jul 28 05:06:00 PM PDT 24
Finished Jul 28 05:06:10 PM PDT 24
Peak memory 306016 kb
Host smart-93ccfec6-5a41-440a-839b-74ce45fb6c2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567561762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3567561762
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2668577425
Short name T950
Test name
Test status
Simulation time 16257817693 ps
CPU time 142.11 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 811292 kb
Host smart-c2da60e2-a77b-479c-a740-1de747080b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668577425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2668577425
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3978770379
Short name T1465
Test name
Test status
Simulation time 4638517880 ps
CPU time 71.38 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:07:13 PM PDT 24
Peak memory 772736 kb
Host smart-ba37ee34-ec33-4e17-9deb-b7cf906f0ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978770379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3978770379
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3030612618
Short name T977
Test name
Test status
Simulation time 101579356 ps
CPU time 1.06 seconds
Started Jul 28 05:06:06 PM PDT 24
Finished Jul 28 05:06:07 PM PDT 24
Peak memory 205436 kb
Host smart-05e0f756-db8e-4ce3-abd9-0888d6617c6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030612618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3030612618
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1160699305
Short name T1080
Test name
Test status
Simulation time 2041928415 ps
CPU time 12.36 seconds
Started Jul 28 05:06:14 PM PDT 24
Finished Jul 28 05:06:26 PM PDT 24
Peak memory 248720 kb
Host smart-75df947c-8429-4eb3-86d9-8667482e1112
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160699305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1160699305
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2314703689
Short name T110
Test name
Test status
Simulation time 12104180501 ps
CPU time 57.85 seconds
Started Jul 28 05:06:22 PM PDT 24
Finished Jul 28 05:07:20 PM PDT 24
Peak memory 807684 kb
Host smart-edb71a92-fa77-44fa-a2ca-ae660e6b6d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314703689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2314703689
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.559676701
Short name T264
Test name
Test status
Simulation time 748281796 ps
CPU time 12.27 seconds
Started Jul 28 05:06:05 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 205712 kb
Host smart-01f0877d-588f-40ca-91b2-691a90dbdf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559676701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.559676701
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.2185535260
Short name T1114
Test name
Test status
Simulation time 19512966 ps
CPU time 0.71 seconds
Started Jul 28 05:05:56 PM PDT 24
Finished Jul 28 05:05:57 PM PDT 24
Peak memory 205508 kb
Host smart-0af40740-44f3-49ba-bf94-e6497ee54666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185535260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2185535260
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2354421547
Short name T1621
Test name
Test status
Simulation time 781842109 ps
CPU time 16.41 seconds
Started Jul 28 05:06:11 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 370728 kb
Host smart-e970296a-023c-42e9-8d74-efb51817678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354421547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2354421547
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.3690195772
Short name T148
Test name
Test status
Simulation time 6106343804 ps
CPU time 472.61 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 1549916 kb
Host smart-a97a147d-2739-418d-ae40-e4f34b70a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690195772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.3690195772
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2339914626
Short name T154
Test name
Test status
Simulation time 1768331178 ps
CPU time 30.51 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:06:46 PM PDT 24
Peak memory 327440 kb
Host smart-285e54bd-3d20-44ff-87a7-f8b9499b8632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339914626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2339914626
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.3627669835
Short name T565
Test name
Test status
Simulation time 20915509543 ps
CPU time 1436.46 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:29:57 PM PDT 24
Peak memory 2996860 kb
Host smart-ce23ea30-3533-4e88-a4fc-71d29ee99728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627669835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.3627669835
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.2983685968
Short name T713
Test name
Test status
Simulation time 3572234610 ps
CPU time 13.92 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:13 PM PDT 24
Peak memory 237284 kb
Host smart-abe6e68a-43b7-451b-bd2a-9d6b34d33ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983685968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2983685968
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.1932651440
Short name T294
Test name
Test status
Simulation time 1335009260 ps
CPU time 6.49 seconds
Started Jul 28 05:06:04 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 214172 kb
Host smart-d35b504a-0bc3-408f-a62c-6ad0626c0355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932651440 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.1932651440
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1776705567
Short name T1391
Test name
Test status
Simulation time 747858130 ps
CPU time 1.62 seconds
Started Jul 28 05:06:06 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 214068 kb
Host smart-ae12ac04-70c5-413e-ae7a-69b904ab1735
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776705567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1776705567
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.417033855
Short name T158
Test name
Test status
Simulation time 791947249 ps
CPU time 1.46 seconds
Started Jul 28 05:06:04 PM PDT 24
Finished Jul 28 05:06:05 PM PDT 24
Peak memory 205936 kb
Host smart-13107823-835d-4747-ad08-4261e11b3b34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417033855 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.417033855
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.414235079
Short name T1697
Test name
Test status
Simulation time 454876603 ps
CPU time 2.6 seconds
Started Jul 28 05:06:02 PM PDT 24
Finished Jul 28 05:06:05 PM PDT 24
Peak memory 205932 kb
Host smart-335ca9a2-a994-4ecd-8aa4-b820512434b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414235079 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.414235079
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.43246126
Short name T1420
Test name
Test status
Simulation time 164514362 ps
CPU time 1.39 seconds
Started Jul 28 05:06:07 PM PDT 24
Finished Jul 28 05:06:09 PM PDT 24
Peak memory 205784 kb
Host smart-7ba9fa64-47fb-42d9-af9e-7889a9741327
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43246126 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.43246126
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3770964223
Short name T1020
Test name
Test status
Simulation time 1065525196 ps
CPU time 6.62 seconds
Started Jul 28 05:06:02 PM PDT 24
Finished Jul 28 05:06:09 PM PDT 24
Peak memory 214072 kb
Host smart-ee80bbcb-d8ed-4e44-ba39-a37e0aea741e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770964223 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3770964223
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2576391739
Short name T304
Test name
Test status
Simulation time 614116692 ps
CPU time 1.87 seconds
Started Jul 28 05:06:06 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 205696 kb
Host smart-681f7ea6-334c-4ed0-bd29-78db80c7e3a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576391739 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2576391739
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.4103429030
Short name T1751
Test name
Test status
Simulation time 4628344691 ps
CPU time 2.77 seconds
Started Jul 28 05:06:06 PM PDT 24
Finished Jul 28 05:06:09 PM PDT 24
Peak memory 214360 kb
Host smart-d9623a86-7ef9-4293-81f1-187b7dee3085
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103429030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_acqfull.4103429030
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.2838862330
Short name T1159
Test name
Test status
Simulation time 565919619 ps
CPU time 2.92 seconds
Started Jul 28 05:06:18 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 205896 kb
Host smart-98bddb8f-de2a-4437-9d7c-01fc2a599e84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838862330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.2838862330
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.2613243158
Short name T653
Test name
Test status
Simulation time 1005546530 ps
CPU time 4.01 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 214120 kb
Host smart-9c84f8be-346d-4eab-841b-f7dc4e07c2ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613243158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.2613243158
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.1641000830
Short name T1691
Test name
Test status
Simulation time 383735021 ps
CPU time 1.94 seconds
Started Jul 28 05:06:31 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 205652 kb
Host smart-dc1b3b72-a7ca-47c7-9a9a-536c37cd03fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641000830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.1641000830
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.67993868
Short name T337
Test name
Test status
Simulation time 1885203200 ps
CPU time 28.62 seconds
Started Jul 28 05:06:30 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 214092 kb
Host smart-a0ff5f68-1c14-413b-b07b-aca50c318207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67993868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_targ
et_smoke.67993868
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.3091584358
Short name T1174
Test name
Test status
Simulation time 58661759901 ps
CPU time 342.83 seconds
Started Jul 28 05:06:07 PM PDT 24
Finished Jul 28 05:11:50 PM PDT 24
Peak memory 2437624 kb
Host smart-7e887583-a920-4df3-8cca-a32c6c8c7c15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091584358 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.3091584358
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.976327846
Short name T1409
Test name
Test status
Simulation time 1081787475 ps
CPU time 8.29 seconds
Started Jul 28 05:06:08 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 218140 kb
Host smart-18e8f4f1-c74b-4294-bca4-6c1fd64b5bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976327846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.976327846
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.666043775
Short name T1286
Test name
Test status
Simulation time 16058369491 ps
CPU time 7.2 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 206128 kb
Host smart-a55d20fb-ea22-471e-a69a-aab89e75a073
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666043775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.666043775
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.141023099
Short name T1443
Test name
Test status
Simulation time 2159960101 ps
CPU time 39.45 seconds
Started Jul 28 05:06:01 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 658704 kb
Host smart-9862c353-d687-42e4-bdbe-290a3b69c9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141023099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.141023099
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.110212169
Short name T1349
Test name
Test status
Simulation time 2003524150 ps
CPU time 5.86 seconds
Started Jul 28 05:05:59 PM PDT 24
Finished Jul 28 05:06:05 PM PDT 24
Peak memory 214048 kb
Host smart-b71a62c9-923c-40f6-8df5-6dbafa939877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110212169 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_timeout.110212169
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.243997226
Short name T1682
Test name
Test status
Simulation time 148129691 ps
CPU time 3.28 seconds
Started Jul 28 05:06:03 PM PDT 24
Finished Jul 28 05:06:07 PM PDT 24
Peak memory 206828 kb
Host smart-e8069083-10aa-433f-9c69-30bf8364bd44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243997226 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.243997226
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2131899941
Short name T814
Test name
Test status
Simulation time 48536361 ps
CPU time 0.65 seconds
Started Jul 28 05:06:09 PM PDT 24
Finished Jul 28 05:06:10 PM PDT 24
Peak memory 204972 kb
Host smart-e8358c01-c6f3-42f1-9a70-7b29ad387bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131899941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2131899941
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3545237617
Short name T937
Test name
Test status
Simulation time 895038320 ps
CPU time 3.22 seconds
Started Jul 28 05:06:23 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 214068 kb
Host smart-8770d414-465b-4f70-8df4-69b22ff5f98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545237617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3545237617
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2266872486
Short name T387
Test name
Test status
Simulation time 491648355 ps
CPU time 10.4 seconds
Started Jul 28 05:06:10 PM PDT 24
Finished Jul 28 05:06:20 PM PDT 24
Peak memory 309556 kb
Host smart-d8129bd7-eb06-4cc6-910a-839ea1c567fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266872486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2266872486
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1592503809
Short name T433
Test name
Test status
Simulation time 2965514168 ps
CPU time 184.72 seconds
Started Jul 28 05:06:16 PM PDT 24
Finished Jul 28 05:09:21 PM PDT 24
Peak memory 634444 kb
Host smart-a9404df4-e898-49e3-a523-1602b521c615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592503809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1592503809
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.464970742
Short name T583
Test name
Test status
Simulation time 2077577287 ps
CPU time 69.55 seconds
Started Jul 28 05:06:20 PM PDT 24
Finished Jul 28 05:07:30 PM PDT 24
Peak memory 713928 kb
Host smart-d1c86a8d-2426-46da-b89f-4bcbff7e4964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464970742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.464970742
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1807759071
Short name T489
Test name
Test status
Simulation time 109265104 ps
CPU time 1.08 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 205448 kb
Host smart-a73dbe27-da8e-409f-9412-f1ba173f1e5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807759071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1807759071
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3153935246
Short name T1626
Test name
Test status
Simulation time 190570400 ps
CPU time 4.54 seconds
Started Jul 28 05:06:12 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 205720 kb
Host smart-9d991999-66fd-49bb-8c9b-f6d70b3b06d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153935246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3153935246
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.4061073428
Short name T1376
Test name
Test status
Simulation time 9471919907 ps
CPU time 119.08 seconds
Started Jul 28 05:06:03 PM PDT 24
Finished Jul 28 05:08:02 PM PDT 24
Peak memory 1354888 kb
Host smart-c29e3585-c77a-4d00-888a-7d7140bcc62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061073428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.4061073428
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3471168210
Short name T258
Test name
Test status
Simulation time 398813046 ps
CPU time 7.82 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 205680 kb
Host smart-1263ab39-6b5c-442c-a79f-460e89263cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471168210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3471168210
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.940442892
Short name T1535
Test name
Test status
Simulation time 157217992 ps
CPU time 0.68 seconds
Started Jul 28 05:06:07 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 205484 kb
Host smart-f6fcc60d-8547-4520-b1c6-132eaec846ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940442892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.940442892
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.635520024
Short name T875
Test name
Test status
Simulation time 5605771146 ps
CPU time 324.91 seconds
Started Jul 28 05:06:07 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 885024 kb
Host smart-2053b2f5-e80f-49eb-bfc8-76317367462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635520024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.635520024
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.3569233817
Short name T860
Test name
Test status
Simulation time 5910084433 ps
CPU time 213.41 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:09:49 PM PDT 24
Peak memory 1544132 kb
Host smart-9757b85e-b981-4aa7-9f73-abf204638a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569233817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.3569233817
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.346797275
Short name T1738
Test name
Test status
Simulation time 15270590607 ps
CPU time 20.42 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:06:46 PM PDT 24
Peak memory 311272 kb
Host smart-bb5307ec-7beb-411b-8624-4034735fbb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346797275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.346797275
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.604885926
Short name T586
Test name
Test status
Simulation time 2509223976 ps
CPU time 12.03 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 221692 kb
Host smart-f869b5b4-c171-4b3d-a332-2f78d3b46d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604885926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.604885926
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2583310302
Short name T358
Test name
Test status
Simulation time 3415666826 ps
CPU time 5.63 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 214356 kb
Host smart-d736ffdc-e006-4780-bfde-6aa5dff4bef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583310302 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2583310302
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.4021418061
Short name T877
Test name
Test status
Simulation time 222122370 ps
CPU time 1.33 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 213952 kb
Host smart-7bb253f7-9850-488c-ad0a-8e33c7885ff4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021418061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.4021418061
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.4124546634
Short name T1563
Test name
Test status
Simulation time 503564090 ps
CPU time 1.04 seconds
Started Jul 28 05:06:09 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 205632 kb
Host smart-11dda344-0055-4de5-8953-5e063dcd7da7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124546634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.4124546634
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.3911624931
Short name T339
Test name
Test status
Simulation time 550293476 ps
CPU time 2.92 seconds
Started Jul 28 05:06:14 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 205980 kb
Host smart-8faa841f-fe32-4d94-9a01-013df44717a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911624931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.3911624931
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.3614228548
Short name T466
Test name
Test status
Simulation time 135319917 ps
CPU time 1.34 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:06:14 PM PDT 24
Peak memory 205720 kb
Host smart-021aad40-79c2-4c4a-ac8f-9824e0e39669
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614228548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.3614228548
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3591439665
Short name T1089
Test name
Test status
Simulation time 699355152 ps
CPU time 1.97 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:06:16 PM PDT 24
Peak memory 214112 kb
Host smart-6263c58e-4269-4545-b947-c69ced5cba2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591439665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3591439665
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3928022526
Short name T296
Test name
Test status
Simulation time 2344522766 ps
CPU time 7.14 seconds
Started Jul 28 05:06:20 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 219152 kb
Host smart-cabcebe6-3a99-46be-984e-5621bcbb3b40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928022526 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.3928022526
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.930078214
Short name T1357
Test name
Test status
Simulation time 4244786479 ps
CPU time 8.05 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 206156 kb
Host smart-5168b095-cfa7-4509-a7da-683da707ecac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930078214 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.930078214
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.1454931654
Short name T830
Test name
Test status
Simulation time 3388628417 ps
CPU time 2.73 seconds
Started Jul 28 05:06:30 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 214244 kb
Host smart-52f561f9-93b5-4f00-a75f-53cd19676911
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454931654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.1454931654
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.2149275497
Short name T730
Test name
Test status
Simulation time 3791816764 ps
CPU time 2.59 seconds
Started Jul 28 05:06:31 PM PDT 24
Finished Jul 28 05:06:34 PM PDT 24
Peak memory 206264 kb
Host smart-4984f94e-52b9-4ed5-80bf-1af8d050f0d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149275497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.2149275497
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_txstretch.2806465740
Short name T893
Test name
Test status
Simulation time 240810612 ps
CPU time 1.49 seconds
Started Jul 28 05:06:33 PM PDT 24
Finished Jul 28 05:06:35 PM PDT 24
Peak memory 222732 kb
Host smart-d63cdce1-81f7-4910-bef7-c2fa845ec3b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806465740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_nack_txstretch.2806465740
Directory /workspace/42.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/42.i2c_target_perf.1948736658
Short name T800
Test name
Test status
Simulation time 1496507008 ps
CPU time 5.56 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:23 PM PDT 24
Peak memory 214148 kb
Host smart-c38b99e6-7f39-4711-a1a4-0275237d3823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948736658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.1948736658
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.1623012659
Short name T996
Test name
Test status
Simulation time 1024098696 ps
CPU time 2.33 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:06:37 PM PDT 24
Peak memory 205632 kb
Host smart-ad4865fc-8626-410e-8fe1-18f52b73ff9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623012659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_smbus_maxlen.1623012659
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2867421866
Short name T942
Test name
Test status
Simulation time 938259219 ps
CPU time 11.97 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:06:37 PM PDT 24
Peak memory 214128 kb
Host smart-d5692cc2-1d66-4f7d-a335-9bbc66aa079b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867421866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2867421866
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.521839084
Short name T1620
Test name
Test status
Simulation time 4377389102 ps
CPU time 48.52 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:07:02 PM PDT 24
Peak memory 215340 kb
Host smart-83c47be7-678e-4875-a6c8-ed008fae855c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521839084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.521839084
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2657540333
Short name T947
Test name
Test status
Simulation time 35325712587 ps
CPU time 59.06 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:07:24 PM PDT 24
Peak memory 1063968 kb
Host smart-13af2b39-35d0-407b-b349-35524af70b86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657540333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2657540333
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2141348089
Short name T1012
Test name
Test status
Simulation time 2903753174 ps
CPU time 145.55 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 867976 kb
Host smart-aa8e6050-b963-4a2f-b15f-1da53a25a649
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141348089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2141348089
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.3172865341
Short name T444
Test name
Test status
Simulation time 1420663136 ps
CPU time 7.64 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 235176 kb
Host smart-d482187b-a688-414b-a6ac-105b9ccdd93e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172865341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.3172865341
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.932239499
Short name T677
Test name
Test status
Simulation time 148271039 ps
CPU time 2.51 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:06:39 PM PDT 24
Peak memory 222008 kb
Host smart-7b7f5995-f397-4bdb-b776-97864dc082e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932239499 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.932239499
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3444748254
Short name T170
Test name
Test status
Simulation time 26778915 ps
CPU time 0.64 seconds
Started Jul 28 05:06:29 PM PDT 24
Finished Jul 28 05:06:30 PM PDT 24
Peak memory 204984 kb
Host smart-6691d270-5165-4e52-ab0b-713cae532ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444748254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3444748254
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.369391995
Short name T595
Test name
Test status
Simulation time 669079338 ps
CPU time 2.96 seconds
Started Jul 28 05:06:09 PM PDT 24
Finished Jul 28 05:06:12 PM PDT 24
Peak memory 233688 kb
Host smart-76f1b529-1a8f-4613-a3ad-02d6214ba84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369391995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.369391995
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.993077627
Short name T810
Test name
Test status
Simulation time 1018793968 ps
CPU time 4.38 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:06:30 PM PDT 24
Peak memory 253780 kb
Host smart-631cbece-2413-4fd3-abd8-a60f7f10707f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993077627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.993077627
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3467630271
Short name T1310
Test name
Test status
Simulation time 6991903550 ps
CPU time 48.04 seconds
Started Jul 28 05:06:23 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 513736 kb
Host smart-ae4bd40f-1e8e-4fb0-87a3-09277b903ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467630271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3467630271
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.418357452
Short name T1303
Test name
Test status
Simulation time 2357065644 ps
CPU time 70.89 seconds
Started Jul 28 05:06:10 PM PDT 24
Finished Jul 28 05:07:21 PM PDT 24
Peak memory 767216 kb
Host smart-9d65843e-441b-487e-91ae-ef5e354b58cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418357452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.418357452
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.148140598
Short name T769
Test name
Test status
Simulation time 357346861 ps
CPU time 0.9 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:06:22 PM PDT 24
Peak memory 205444 kb
Host smart-757a3f6b-8c4e-4868-8f2e-1f493735f8ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148140598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.148140598
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2429399895
Short name T1447
Test name
Test status
Simulation time 129030621 ps
CPU time 7.57 seconds
Started Jul 28 05:06:10 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 227752 kb
Host smart-5b851c3f-fb48-4c71-a8f1-1d6039a4463a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429399895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2429399895
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2891726668
Short name T1574
Test name
Test status
Simulation time 4615336874 ps
CPU time 122.53 seconds
Started Jul 28 05:06:19 PM PDT 24
Finished Jul 28 05:08:22 PM PDT 24
Peak memory 1300336 kb
Host smart-54dbd999-541f-4981-b88d-d78528c6c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891726668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2891726668
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2800222690
Short name T266
Test name
Test status
Simulation time 1461677899 ps
CPU time 15.74 seconds
Started Jul 28 05:06:19 PM PDT 24
Finished Jul 28 05:06:35 PM PDT 24
Peak memory 205792 kb
Host smart-1a7d22ca-3507-429e-9758-dae08525172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800222690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2800222690
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.643991699
Short name T791
Test name
Test status
Simulation time 253254362 ps
CPU time 1.79 seconds
Started Jul 28 05:06:28 PM PDT 24
Finished Jul 28 05:06:30 PM PDT 24
Peak memory 222088 kb
Host smart-60fe6f6c-3852-43cc-a6da-a742d63f293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643991699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.643991699
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3551027655
Short name T139
Test name
Test status
Simulation time 56227908 ps
CPU time 0.68 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:06:22 PM PDT 24
Peak memory 205400 kb
Host smart-9c0c493c-aa18-47fa-aa10-37b183195bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551027655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3551027655
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1130369127
Short name T1083
Test name
Test status
Simulation time 7606376786 ps
CPU time 215.97 seconds
Started Jul 28 05:06:28 PM PDT 24
Finished Jul 28 05:10:04 PM PDT 24
Peak memory 1393028 kb
Host smart-62c72233-f72b-4b61-8923-f9250b200326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130369127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1130369127
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.1092760194
Short name T828
Test name
Test status
Simulation time 5874584337 ps
CPU time 84.69 seconds
Started Jul 28 05:06:12 PM PDT 24
Finished Jul 28 05:07:37 PM PDT 24
Peak memory 564104 kb
Host smart-79f10ff7-476a-4a15-8c5f-456231e50053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092760194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1092760194
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3544040294
Short name T1466
Test name
Test status
Simulation time 6385703468 ps
CPU time 32.97 seconds
Started Jul 28 05:06:08 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 303260 kb
Host smart-8fc938b2-334d-4362-a231-943a3cc810e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544040294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3544040294
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.746443970
Short name T896
Test name
Test status
Simulation time 1419676624 ps
CPU time 10.32 seconds
Started Jul 28 05:06:10 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 217560 kb
Host smart-62e6a227-448f-4637-8439-6a0e47aa6a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746443970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.746443970
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2958636311
Short name T448
Test name
Test status
Simulation time 4340561171 ps
CPU time 5.38 seconds
Started Jul 28 05:06:22 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 210532 kb
Host smart-a863f33d-4d39-4711-bb8c-23d42cce7675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958636311 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2958636311
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3806958923
Short name T335
Test name
Test status
Simulation time 1594801623 ps
CPU time 1.32 seconds
Started Jul 28 05:06:14 PM PDT 24
Finished Jul 28 05:06:15 PM PDT 24
Peak memory 205720 kb
Host smart-8230d0e6-f14b-4c14-bf05-37bdd7906732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806958923 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3806958923
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3170235095
Short name T1295
Test name
Test status
Simulation time 590935225 ps
CPU time 1.33 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:06:23 PM PDT 24
Peak memory 205880 kb
Host smart-bfeba2e0-c4cf-460f-aa92-b7576a6ec512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170235095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3170235095
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.2031047018
Short name T329
Test name
Test status
Simulation time 633809811 ps
CPU time 3.37 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:20 PM PDT 24
Peak memory 205944 kb
Host smart-01edbf92-a751-4360-be1a-1c44b618769a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031047018 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.2031047018
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.1811518955
Short name T71
Test name
Test status
Simulation time 646686972 ps
CPU time 1.5 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:19 PM PDT 24
Peak memory 205704 kb
Host smart-dcf36235-bded-4af7-bda6-c6976bbefcd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811518955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.1811518955
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2348693702
Short name T632
Test name
Test status
Simulation time 207538221 ps
CPU time 1.61 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:06:23 PM PDT 24
Peak memory 214140 kb
Host smart-3e958889-85ce-4cbb-b91f-be4bb50b9b55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348693702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2348693702
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3504618709
Short name T707
Test name
Test status
Simulation time 2598651556 ps
CPU time 7.78 seconds
Started Jul 28 05:06:26 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 221044 kb
Host smart-a41fde05-8b76-4f42-baa1-824172947925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504618709 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3504618709
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2834519480
Short name T687
Test name
Test status
Simulation time 13138709027 ps
CPU time 238.6 seconds
Started Jul 28 05:06:31 PM PDT 24
Finished Jul 28 05:10:30 PM PDT 24
Peak memory 3272760 kb
Host smart-cc1508ea-1605-4f2b-b5de-14af98646fe5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834519480 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2834519480
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.1898124679
Short name T1592
Test name
Test status
Simulation time 448791838 ps
CPU time 2.59 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 214128 kb
Host smart-6cf34cbf-fe8c-4532-900d-54bf9f17e5b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898124679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.1898124679
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.596619074
Short name T1135
Test name
Test status
Simulation time 3261433388 ps
CPU time 2.53 seconds
Started Jul 28 05:06:27 PM PDT 24
Finished Jul 28 05:06:30 PM PDT 24
Peak memory 206100 kb
Host smart-fc6de3eb-936a-479d-a0f3-256a0bcaf4e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596619074 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.596619074
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_txstretch.567988320
Short name T163
Test name
Test status
Simulation time 375149784 ps
CPU time 1.45 seconds
Started Jul 28 05:06:14 PM PDT 24
Finished Jul 28 05:06:16 PM PDT 24
Peak memory 222232 kb
Host smart-918a0d0b-96e8-46da-8c62-beebd9744254
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567988320 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_nack_txstretch.567988320
Directory /workspace/43.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/43.i2c_target_perf.3964495881
Short name T1735
Test name
Test status
Simulation time 635612124 ps
CPU time 4.53 seconds
Started Jul 28 05:06:13 PM PDT 24
Finished Jul 28 05:06:18 PM PDT 24
Peak memory 214060 kb
Host smart-00eade30-58c9-42e7-a9c1-95a35d092ad5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964495881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.3964495881
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.342889980
Short name T1706
Test name
Test status
Simulation time 454585908 ps
CPU time 2.26 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 205768 kb
Host smart-44e95e9e-963f-4e6c-b707-949740f46385
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342889980 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_smbus_maxlen.342889980
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.663851716
Short name T1721
Test name
Test status
Simulation time 3895062912 ps
CPU time 31.51 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:06:47 PM PDT 24
Peak memory 214368 kb
Host smart-e65a8567-1ca0-42ac-9ba0-f60e26738c7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663851716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.663851716
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.1002100761
Short name T278
Test name
Test status
Simulation time 23881655339 ps
CPU time 356.96 seconds
Started Jul 28 05:06:32 PM PDT 24
Finished Jul 28 05:12:29 PM PDT 24
Peak memory 2716796 kb
Host smart-69579bfb-4e01-46d0-8168-73e02a01b3ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002100761 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.1002100761
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.325535017
Short name T364
Test name
Test status
Simulation time 303976943 ps
CPU time 5.05 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:06:26 PM PDT 24
Peak memory 205872 kb
Host smart-6bf449e4-20ea-44c8-9d7a-13b823ec5e07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325535017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.325535017
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2759802816
Short name T1128
Test name
Test status
Simulation time 32920080198 ps
CPU time 301.01 seconds
Started Jul 28 05:06:09 PM PDT 24
Finished Jul 28 05:11:11 PM PDT 24
Peak memory 3303560 kb
Host smart-556fcde6-8929-4b46-b350-dc9384e1d08e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759802816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2759802816
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1890744505
Short name T191
Test name
Test status
Simulation time 3897137488 ps
CPU time 28.82 seconds
Started Jul 28 05:06:22 PM PDT 24
Finished Jul 28 05:06:50 PM PDT 24
Peak memory 343340 kb
Host smart-651faad8-e1ce-488a-8140-67e4457d5211
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890744505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1890744505
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2800600215
Short name T1663
Test name
Test status
Simulation time 5739937214 ps
CPU time 6.52 seconds
Started Jul 28 05:06:32 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 222364 kb
Host smart-f96a05f0-0290-46a9-adbb-497bb4094e71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800600215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2800600215
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.3344577033
Short name T1320
Test name
Test status
Simulation time 147635720 ps
CPU time 3.34 seconds
Started Jul 28 05:06:18 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 206420 kb
Host smart-f41e4115-a770-4015-9d5a-bf67de9f0b52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344577033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.3344577033
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.471505678
Short name T477
Test name
Test status
Simulation time 15256652 ps
CPU time 0.62 seconds
Started Jul 28 05:06:33 PM PDT 24
Finished Jul 28 05:06:34 PM PDT 24
Peak memory 204964 kb
Host smart-3bcc4adc-7c2f-483a-8f5e-532146b4dc43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471505678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.471505678
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.407786785
Short name T1185
Test name
Test status
Simulation time 510734347 ps
CPU time 4.88 seconds
Started Jul 28 05:06:48 PM PDT 24
Finished Jul 28 05:06:53 PM PDT 24
Peak memory 213968 kb
Host smart-0aa52007-7b22-4fae-9f61-bdb1e86c5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407786785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.407786785
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.616928110
Short name T640
Test name
Test status
Simulation time 225831308 ps
CPU time 4.37 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:06:20 PM PDT 24
Peak memory 245204 kb
Host smart-d3eaff22-be71-4e06-aa42-9a892c3674ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616928110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.616928110
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2929297721
Short name T675
Test name
Test status
Simulation time 7719967269 ps
CPU time 256.68 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:10:38 PM PDT 24
Peak memory 684692 kb
Host smart-d7a79b6a-30a5-4cba-849a-3bd0262fe0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929297721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2929297721
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3239835555
Short name T333
Test name
Test status
Simulation time 3453214037 ps
CPU time 124.39 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:08:22 PM PDT 24
Peak memory 634656 kb
Host smart-d8c8a569-24f0-4148-a807-c7d5ce8f07f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239835555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3239835555
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1892636549
Short name T1365
Test name
Test status
Simulation time 199308983 ps
CPU time 0.98 seconds
Started Jul 28 05:06:27 PM PDT 24
Finished Jul 28 05:06:28 PM PDT 24
Peak memory 205468 kb
Host smart-8d0c4de7-2ff9-45c4-a3d1-c5e02c303937
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892636549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1892636549
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.433625222
Short name T511
Test name
Test status
Simulation time 1644846022 ps
CPU time 6.67 seconds
Started Jul 28 05:06:16 PM PDT 24
Finished Jul 28 05:06:22 PM PDT 24
Peak memory 250788 kb
Host smart-9a14cf15-0c38-4a9b-9b44-a6a7d4059093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433625222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
433625222
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2269358537
Short name T1051
Test name
Test status
Simulation time 2953623880 ps
CPU time 186.99 seconds
Started Jul 28 05:06:24 PM PDT 24
Finished Jul 28 05:09:31 PM PDT 24
Peak memory 884196 kb
Host smart-03daa816-c780-41fc-a3f7-88b4d016d797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269358537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2269358537
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1865398279
Short name T1684
Test name
Test status
Simulation time 509972060 ps
CPU time 2.74 seconds
Started Jul 28 05:06:27 PM PDT 24
Finished Jul 28 05:06:30 PM PDT 24
Peak memory 214188 kb
Host smart-3709c74f-b08e-4fb2-8a89-e7c370ed75fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865398279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1865398279
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.1260764309
Short name T137
Test name
Test status
Simulation time 90645168 ps
CPU time 0.66 seconds
Started Jul 28 05:06:19 PM PDT 24
Finished Jul 28 05:06:19 PM PDT 24
Peak memory 205368 kb
Host smart-135e4f65-2099-477d-949c-5f630f07bb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260764309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1260764309
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.552198869
Short name T581
Test name
Test status
Simulation time 2643760377 ps
CPU time 74.7 seconds
Started Jul 28 05:06:24 PM PDT 24
Finished Jul 28 05:07:44 PM PDT 24
Peak memory 526256 kb
Host smart-1e6c0e9d-fb80-423e-812f-af7872681bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552198869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.552198869
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.3234794574
Short name T1490
Test name
Test status
Simulation time 223255114 ps
CPU time 8.69 seconds
Started Jul 28 05:06:23 PM PDT 24
Finished Jul 28 05:06:32 PM PDT 24
Peak memory 205724 kb
Host smart-210a13b2-453b-4fd8-b195-2caa6f063d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234794574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.3234794574
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3384084137
Short name T290
Test name
Test status
Simulation time 5244838239 ps
CPU time 59.99 seconds
Started Jul 28 05:06:24 PM PDT 24
Finished Jul 28 05:07:24 PM PDT 24
Peak memory 332192 kb
Host smart-c324b364-7349-4934-875b-f7d2d53bd80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384084137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3384084137
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.2307205715
Short name T531
Test name
Test status
Simulation time 454278763 ps
CPU time 8.51 seconds
Started Jul 28 05:06:31 PM PDT 24
Finished Jul 28 05:06:40 PM PDT 24
Peak memory 214040 kb
Host smart-d8a6eeee-f672-48c2-ba42-57d5cda38660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307205715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2307205715
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3551554680
Short name T1298
Test name
Test status
Simulation time 2460505659 ps
CPU time 6.7 seconds
Started Jul 28 05:06:18 PM PDT 24
Finished Jul 28 05:06:25 PM PDT 24
Peak memory 214220 kb
Host smart-9e0c4186-72fd-4931-8663-40ffc69d0000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551554680 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3551554680
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.635662303
Short name T161
Test name
Test status
Simulation time 231495021 ps
CPU time 1.71 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:06:17 PM PDT 24
Peak memory 214124 kb
Host smart-2ea520d5-eddd-4d80-b978-60b007076607
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635662303 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.635662303
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.414437627
Short name T963
Test name
Test status
Simulation time 253557357 ps
CPU time 1.59 seconds
Started Jul 28 05:06:22 PM PDT 24
Finished Jul 28 05:06:24 PM PDT 24
Peak memory 211052 kb
Host smart-7135ce20-e17d-4e7e-8d85-16859e3cf295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414437627 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.414437627
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.4230286098
Short name T420
Test name
Test status
Simulation time 282681056 ps
CPU time 1.65 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 205740 kb
Host smart-6b1fca18-87b9-41c3-bc51-27b914f6be1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230286098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.4230286098
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3600949278
Short name T359
Test name
Test status
Simulation time 7489441215 ps
CPU time 6.37 seconds
Started Jul 28 05:06:26 PM PDT 24
Finished Jul 28 05:06:32 PM PDT 24
Peak memory 230784 kb
Host smart-2900e47b-74e7-4439-8818-e88591f8def3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600949278 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3600949278
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3394602810
Short name T1140
Test name
Test status
Simulation time 8790590969 ps
CPU time 135.66 seconds
Started Jul 28 05:06:27 PM PDT 24
Finished Jul 28 05:08:43 PM PDT 24
Peak memory 2238724 kb
Host smart-b64666b6-ec7f-4a9b-84ca-92ffd900a4ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394602810 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3394602810
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.3573356507
Short name T429
Test name
Test status
Simulation time 2508011292 ps
CPU time 2.91 seconds
Started Jul 28 05:06:18 PM PDT 24
Finished Jul 28 05:06:21 PM PDT 24
Peak memory 214280 kb
Host smart-e51fef1f-5ec9-4d70-8982-ede0fda31a01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573356507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_nack_acqfull.3573356507
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.1934891126
Short name T1554
Test name
Test status
Simulation time 2570889893 ps
CPU time 2.93 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:06:24 PM PDT 24
Peak memory 206028 kb
Host smart-3c66aa66-744a-4b81-a072-a379a7b39fb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934891126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.1934891126
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_txstretch.246175301
Short name T159
Test name
Test status
Simulation time 1442639842 ps
CPU time 1.52 seconds
Started Jul 28 05:06:23 PM PDT 24
Finished Jul 28 05:06:25 PM PDT 24
Peak memory 222404 kb
Host smart-99a58659-4b21-4bd1-b2d7-be41238079d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246175301 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_nack_txstretch.246175301
Directory /workspace/44.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/44.i2c_target_perf.4212912674
Short name T63
Test name
Test status
Simulation time 1524342849 ps
CPU time 2.72 seconds
Started Jul 28 05:06:23 PM PDT 24
Finished Jul 28 05:06:25 PM PDT 24
Peak memory 214204 kb
Host smart-8bf8c4eb-df47-4b5c-8a6e-0e59e36263a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212912674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.4212912674
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.54793560
Short name T630
Test name
Test status
Simulation time 4057502099 ps
CPU time 2.36 seconds
Started Jul 28 05:06:30 PM PDT 24
Finished Jul 28 05:06:32 PM PDT 24
Peak memory 205844 kb
Host smart-9fa6d215-2cbc-4ff5-9fa1-5f0b143dffde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54793560 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_smbus_maxlen.54793560
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2973295893
Short name T422
Test name
Test status
Simulation time 4811406327 ps
CPU time 18.09 seconds
Started Jul 28 05:06:17 PM PDT 24
Finished Jul 28 05:06:35 PM PDT 24
Peak memory 214236 kb
Host smart-621635be-db88-46a5-91ae-2d422055b3e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973295893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2973295893
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.1521169972
Short name T484
Test name
Test status
Simulation time 86584373373 ps
CPU time 519.62 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:15:01 PM PDT 24
Peak memory 2494816 kb
Host smart-e35512b8-ebe6-411f-9244-0643c3739909
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521169972 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_stress_all.1521169972
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.139968510
Short name T1689
Test name
Test status
Simulation time 5238893768 ps
CPU time 25.97 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:07:02 PM PDT 24
Peak memory 224792 kb
Host smart-6d1503c6-924f-44d4-b2d7-9a42f83efcf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139968510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.139968510
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2166876052
Short name T837
Test name
Test status
Simulation time 49651475341 ps
CPU time 1244.37 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:27:10 PM PDT 24
Peak memory 6742832 kb
Host smart-afec60fb-8164-4e2b-986a-978a7a145bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166876052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2166876052
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3906730809
Short name T402
Test name
Test status
Simulation time 5147198626 ps
CPU time 303.66 seconds
Started Jul 28 05:06:25 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 1375024 kb
Host smart-48ad880d-fe19-4e5d-952e-a40fddf40ecd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906730809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3906730809
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.625958556
Short name T1431
Test name
Test status
Simulation time 6830653606 ps
CPU time 7.93 seconds
Started Jul 28 05:06:19 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 222508 kb
Host smart-ba43ea84-d318-4a46-9ff2-37dfb010571f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625958556 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.625958556
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3457193969
Short name T1728
Test name
Test status
Simulation time 148219937 ps
CPU time 2.93 seconds
Started Jul 28 05:06:22 PM PDT 24
Finished Jul 28 05:06:25 PM PDT 24
Peak memory 205916 kb
Host smart-88779c9b-72a0-4610-a66b-debea6d383ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457193969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3457193969
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2947216792
Short name T3
Test name
Test status
Simulation time 27988183 ps
CPU time 0.64 seconds
Started Jul 28 05:06:37 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 204884 kb
Host smart-cdaef205-96c8-4d04-8c43-d43b8a97a088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947216792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2947216792
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2909390019
Short name T1221
Test name
Test status
Simulation time 190259352 ps
CPU time 3.76 seconds
Started Jul 28 05:06:28 PM PDT 24
Finished Jul 28 05:06:32 PM PDT 24
Peak memory 222156 kb
Host smart-f32011c5-2969-473f-b444-501a920a0b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909390019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2909390019
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.4206217136
Short name T1570
Test name
Test status
Simulation time 412813006 ps
CPU time 20.27 seconds
Started Jul 28 05:06:30 PM PDT 24
Finished Jul 28 05:06:50 PM PDT 24
Peak memory 284664 kb
Host smart-6e5d092c-3471-43c8-b8ab-263adecaa073
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206217136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.4206217136
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1394491335
Short name T835
Test name
Test status
Simulation time 13253014506 ps
CPU time 183.4 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:09:40 PM PDT 24
Peak memory 420508 kb
Host smart-b26e29e7-db7b-4528-9362-72a719b7576b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394491335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1394491335
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1672372456
Short name T1480
Test name
Test status
Simulation time 9710142494 ps
CPU time 173.64 seconds
Started Jul 28 05:06:15 PM PDT 24
Finished Jul 28 05:09:09 PM PDT 24
Peak memory 743996 kb
Host smart-9c999bfa-50bd-49b7-9ff8-eccaf8909e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672372456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1672372456
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2159216473
Short name T39
Test name
Test status
Simulation time 512843607 ps
CPU time 1.03 seconds
Started Jul 28 05:06:27 PM PDT 24
Finished Jul 28 05:06:28 PM PDT 24
Peak memory 205520 kb
Host smart-a55f9488-8479-459b-9127-3ee2c190aa25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159216473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2159216473
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2451960419
Short name T834
Test name
Test status
Simulation time 302174117 ps
CPU time 3.81 seconds
Started Jul 28 05:06:44 PM PDT 24
Finished Jul 28 05:06:48 PM PDT 24
Peak memory 205728 kb
Host smart-570483b5-e34f-43a4-85c3-ac6a8ac43c17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451960419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2451960419
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.3001120935
Short name T826
Test name
Test status
Simulation time 8712023975 ps
CPU time 134.63 seconds
Started Jul 28 05:06:21 PM PDT 24
Finished Jul 28 05:08:36 PM PDT 24
Peak memory 1304464 kb
Host smart-1e00fde4-f0ba-4cbf-8c09-b1ddd8a3964b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001120935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.3001120935
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.551074972
Short name T1208
Test name
Test status
Simulation time 885237300 ps
CPU time 16.05 seconds
Started Jul 28 05:06:51 PM PDT 24
Finished Jul 28 05:07:07 PM PDT 24
Peak memory 205768 kb
Host smart-f6a281ef-6f29-4bba-8737-6048ba68623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551074972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.551074972
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_override.2821652234
Short name T135
Test name
Test status
Simulation time 47332994 ps
CPU time 0.67 seconds
Started Jul 28 05:06:24 PM PDT 24
Finished Jul 28 05:06:25 PM PDT 24
Peak memory 205464 kb
Host smart-ea1742bf-4310-4f54-8c1e-5563dcd69421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821652234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2821652234
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.288334694
Short name T587
Test name
Test status
Simulation time 12761237904 ps
CPU time 165.97 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:09:22 PM PDT 24
Peak memory 848772 kb
Host smart-02f5a614-f24e-4211-9857-e37a000d3824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288334694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.288334694
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.3894524294
Short name T424
Test name
Test status
Simulation time 53543004 ps
CPU time 1.26 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 224192 kb
Host smart-d72be214-2dab-4178-86b5-d497f6c0f902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894524294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.3894524294
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.935200617
Short name T1388
Test name
Test status
Simulation time 2936239859 ps
CPU time 62.78 seconds
Started Jul 28 05:06:27 PM PDT 24
Finished Jul 28 05:07:30 PM PDT 24
Peak memory 381928 kb
Host smart-32c077b0-1913-4bee-8ae2-a531f358c26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935200617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.935200617
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.619539188
Short name T417
Test name
Test status
Simulation time 3692766035 ps
CPU time 16.05 seconds
Started Jul 28 05:06:27 PM PDT 24
Finished Jul 28 05:06:43 PM PDT 24
Peak memory 219196 kb
Host smart-849eb41b-3f12-4c4e-8e93-06f85f0149d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619539188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.619539188
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1974321168
Short name T463
Test name
Test status
Simulation time 1213080839 ps
CPU time 3.81 seconds
Started Jul 28 05:06:39 PM PDT 24
Finished Jul 28 05:06:43 PM PDT 24
Peak memory 214336 kb
Host smart-b8af9ba5-9ba5-49db-8ac2-26f63b98bbfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974321168 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1974321168
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3762643539
Short name T1567
Test name
Test status
Simulation time 351303436 ps
CPU time 1.24 seconds
Started Jul 28 05:06:26 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 205948 kb
Host smart-2d1a64f3-e67f-457a-92e2-8d9d36dff27b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762643539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3762643539
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.19660883
Short name T966
Test name
Test status
Simulation time 766575242 ps
CPU time 1 seconds
Started Jul 28 05:06:29 PM PDT 24
Finished Jul 28 05:06:30 PM PDT 24
Peak memory 213796 kb
Host smart-387dbc8c-8758-4d4d-a4ce-d7730bd93b31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19660883 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_fifo_reset_tx.19660883
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.2950881161
Short name T1199
Test name
Test status
Simulation time 249969542 ps
CPU time 1.52 seconds
Started Jul 28 05:06:27 PM PDT 24
Finished Jul 28 05:06:29 PM PDT 24
Peak memory 205716 kb
Host smart-bbaded81-c091-4bd8-b87b-69373fe9b306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950881161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.2950881161
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.3020419712
Short name T648
Test name
Test status
Simulation time 324389588 ps
CPU time 0.97 seconds
Started Jul 28 05:06:40 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 205708 kb
Host smart-9647b04f-063e-4f80-8f87-7ef8bea54471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020419712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.3020419712
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1207332781
Short name T1378
Test name
Test status
Simulation time 2319638065 ps
CPU time 6.21 seconds
Started Jul 28 05:06:26 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 214280 kb
Host smart-f545014e-e7bc-4f6f-a55a-e4b826586a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207332781 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1207332781
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.1098927023
Short name T1522
Test name
Test status
Simulation time 2129756377 ps
CPU time 2.83 seconds
Started Jul 28 05:06:24 PM PDT 24
Finished Jul 28 05:06:27 PM PDT 24
Peak memory 214080 kb
Host smart-023bf5d0-c329-4a17-8bfa-db0df4544a58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098927023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_nack_acqfull.1098927023
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.948633402
Short name T62
Test name
Test status
Simulation time 2618693365 ps
CPU time 2.52 seconds
Started Jul 28 05:06:40 PM PDT 24
Finished Jul 28 05:06:43 PM PDT 24
Peak memory 206044 kb
Host smart-92f6ed04-f239-4b79-882c-5fee9f83f5c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948633402 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.948633402
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.2947744882
Short name T474
Test name
Test status
Simulation time 860961376 ps
CPU time 6.47 seconds
Started Jul 28 05:06:32 PM PDT 24
Finished Jul 28 05:06:39 PM PDT 24
Peak memory 222328 kb
Host smart-4b3fb984-45b6-43ac-975d-2632c8bdf778
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947744882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.2947744882
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.3032060096
Short name T1167
Test name
Test status
Simulation time 2031652664 ps
CPU time 2.29 seconds
Started Jul 28 05:06:47 PM PDT 24
Finished Jul 28 05:06:50 PM PDT 24
Peak memory 205656 kb
Host smart-9251d898-3d49-4a21-94f7-dae8235c2184
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032060096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_smbus_maxlen.3032060096
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1584549420
Short name T672
Test name
Test status
Simulation time 1416477321 ps
CPU time 19.5 seconds
Started Jul 28 05:06:28 PM PDT 24
Finished Jul 28 05:06:48 PM PDT 24
Peak memory 214136 kb
Host smart-c11bc47b-6d37-4188-a39e-8f5272de6edd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584549420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1584549420
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.2880693681
Short name T710
Test name
Test status
Simulation time 10472083095 ps
CPU time 28.43 seconds
Started Jul 28 05:06:42 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 238724 kb
Host smart-867ea844-283e-4dfd-9021-645e46c00a33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880693681 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.2880693681
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.1100047284
Short name T904
Test name
Test status
Simulation time 20648776537 ps
CPU time 74.86 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 219432 kb
Host smart-ff25eb1a-9c9e-4805-991f-8a3af6d3c896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100047284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.1100047284
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.3079697785
Short name T681
Test name
Test status
Simulation time 44028839328 ps
CPU time 944.18 seconds
Started Jul 28 05:06:30 PM PDT 24
Finished Jul 28 05:22:14 PM PDT 24
Peak memory 6170336 kb
Host smart-60ad4634-65ee-44c8-8a10-75bb07c889b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079697785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.3079697785
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.4052985708
Short name T401
Test name
Test status
Simulation time 4872755794 ps
CPU time 8.09 seconds
Started Jul 28 05:06:30 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 297812 kb
Host smart-2fe38a5f-0795-4609-bee8-414cbff005ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052985708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.4052985708
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.4065710879
Short name T637
Test name
Test status
Simulation time 1487844069 ps
CPU time 6.38 seconds
Started Jul 28 05:06:28 PM PDT 24
Finished Jul 28 05:06:34 PM PDT 24
Peak memory 218824 kb
Host smart-d15aff72-a46f-44f2-88d7-b9c06ee1084a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065710879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.4065710879
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.3121631060
Short name T1251
Test name
Test status
Simulation time 870456684 ps
CPU time 10.58 seconds
Started Jul 28 05:06:31 PM PDT 24
Finished Jul 28 05:06:42 PM PDT 24
Peak memory 207224 kb
Host smart-aea6f9ee-14b2-465e-965b-45fa2661591c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121631060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.3121631060
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1914180594
Short name T755
Test name
Test status
Simulation time 32001176 ps
CPU time 0.61 seconds
Started Jul 28 05:06:30 PM PDT 24
Finished Jul 28 05:06:31 PM PDT 24
Peak memory 205012 kb
Host smart-93c7d89a-33a9-4dd4-bac1-03d0ac824b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914180594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1914180594
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2119716233
Short name T19
Test name
Test status
Simulation time 417252342 ps
CPU time 3.14 seconds
Started Jul 28 05:06:46 PM PDT 24
Finished Jul 28 05:06:49 PM PDT 24
Peak memory 226232 kb
Host smart-82057937-01c3-47ef-85ea-4887ba29ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119716233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2119716233
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.4274143009
Short name T313
Test name
Test status
Simulation time 346513851 ps
CPU time 6.6 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:06:45 PM PDT 24
Peak memory 276160 kb
Host smart-1646ef0c-7fa7-48da-a45b-a2399feb21ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274143009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.4274143009
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.4040471120
Short name T793
Test name
Test status
Simulation time 7016906324 ps
CPU time 95.48 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:08:09 PM PDT 24
Peak memory 562124 kb
Host smart-b39a9f56-4ea1-4da9-baf8-bfd6e7beaf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040471120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.4040471120
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1317270201
Short name T580
Test name
Test status
Simulation time 5114641501 ps
CPU time 85.21 seconds
Started Jul 28 05:06:29 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 522700 kb
Host smart-4e3ed9b9-9c25-42fe-9e4f-41c214a537bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317270201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1317270201
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3799872000
Short name T1291
Test name
Test status
Simulation time 582032904 ps
CPU time 1.25 seconds
Started Jul 28 05:06:32 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 205448 kb
Host smart-d74c66b8-36b9-42c1-bba0-599f257c5823
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799872000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3799872000
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2526713561
Short name T1088
Test name
Test status
Simulation time 199078767 ps
CPU time 11.07 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:06:48 PM PDT 24
Peak memory 205708 kb
Host smart-270e4332-b97e-4a9e-88fe-7e02a37d86f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526713561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2526713561
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1382674697
Short name T1496
Test name
Test status
Simulation time 3344115966 ps
CPU time 77.99 seconds
Started Jul 28 05:06:31 PM PDT 24
Finished Jul 28 05:07:49 PM PDT 24
Peak memory 1040404 kb
Host smart-72ceeac9-eef9-460b-bca5-78ca08e4fa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382674697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1382674697
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3740773368
Short name T1069
Test name
Test status
Simulation time 1181321398 ps
CPU time 12.38 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:06:47 PM PDT 24
Peak memory 205700 kb
Host smart-11676f02-7d43-4951-a08a-47b902ebb4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740773368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3740773368
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.2975840711
Short name T1381
Test name
Test status
Simulation time 29043400 ps
CPU time 0.63 seconds
Started Jul 28 05:06:32 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 205388 kb
Host smart-4c2c6181-8a1c-4abf-93cd-e46adf3f85e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975840711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2975840711
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1037363852
Short name T1195
Test name
Test status
Simulation time 25560910406 ps
CPU time 90.53 seconds
Started Jul 28 05:06:24 PM PDT 24
Finished Jul 28 05:07:55 PM PDT 24
Peak memory 953212 kb
Host smart-ff75a8ac-78b2-4ea2-9e53-df537f570bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037363852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1037363852
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.3152804188
Short name T1546
Test name
Test status
Simulation time 255000690 ps
CPU time 10.3 seconds
Started Jul 28 05:06:28 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 206332 kb
Host smart-99a46293-80f7-4361-b807-7ceec60f785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152804188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.3152804188
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2209938131
Short name T1189
Test name
Test status
Simulation time 11126691020 ps
CPU time 22.92 seconds
Started Jul 28 05:06:50 PM PDT 24
Finished Jul 28 05:07:13 PM PDT 24
Peak memory 358212 kb
Host smart-af4ef4bf-7afd-428a-aa2b-d92fcdf7906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209938131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2209938131
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.1973839274
Short name T34
Test name
Test status
Simulation time 37954015659 ps
CPU time 405.72 seconds
Started Jul 28 05:06:49 PM PDT 24
Finished Jul 28 05:13:35 PM PDT 24
Peak memory 521040 kb
Host smart-93f5190d-8568-4b5d-93f8-2123abfff5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973839274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.1973839274
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2405601658
Short name T1045
Test name
Test status
Simulation time 3095455368 ps
CPU time 13.88 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:06:48 PM PDT 24
Peak memory 218956 kb
Host smart-0673d42f-7b15-4dfb-b00a-ef69d2fdd394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405601658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2405601658
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1327310140
Short name T1037
Test name
Test status
Simulation time 2536970618 ps
CPU time 5.59 seconds
Started Jul 28 05:06:33 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 214820 kb
Host smart-a1faf817-819d-4548-bbeb-0aebb7a5eb74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327310140 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1327310140
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3472966133
Short name T938
Test name
Test status
Simulation time 163000859 ps
CPU time 0.87 seconds
Started Jul 28 05:06:39 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 205720 kb
Host smart-3fd04a6f-873b-41fa-a293-7cbe466a589f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472966133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3472966133
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3582835958
Short name T705
Test name
Test status
Simulation time 128986806 ps
CPU time 0.98 seconds
Started Jul 28 05:06:53 PM PDT 24
Finished Jul 28 05:06:54 PM PDT 24
Peak memory 205768 kb
Host smart-537f496e-edc3-46de-86d3-373f4b430e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582835958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3582835958
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.1661547538
Short name T498
Test name
Test status
Simulation time 3131341634 ps
CPU time 2.53 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:06:37 PM PDT 24
Peak memory 206008 kb
Host smart-0f5fc441-b0b2-4f41-a277-3f9fb434ec4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661547538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.1661547538
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.2106989014
Short name T1683
Test name
Test status
Simulation time 390682253 ps
CPU time 1.16 seconds
Started Jul 28 05:06:45 PM PDT 24
Finished Jul 28 05:06:46 PM PDT 24
Peak memory 205748 kb
Host smart-a7b17f37-8f4f-4ca5-925e-9036136d84aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106989014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.2106989014
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1084067421
Short name T1217
Test name
Test status
Simulation time 3138961097 ps
CPU time 2.48 seconds
Started Jul 28 05:06:41 PM PDT 24
Finished Jul 28 05:06:44 PM PDT 24
Peak memory 218792 kb
Host smart-5eafc8e0-3190-4c0d-b318-1eee4931eb26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084067421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1084067421
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3686507227
Short name T547
Test name
Test status
Simulation time 4525130300 ps
CPU time 6.64 seconds
Started Jul 28 05:06:40 PM PDT 24
Finished Jul 28 05:06:47 PM PDT 24
Peak memory 217728 kb
Host smart-b532546d-57ab-44f9-b22b-dd6bb569375b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686507227 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3686507227
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.3973818211
Short name T647
Test name
Test status
Simulation time 26443631074 ps
CPU time 79.34 seconds
Started Jul 28 05:06:44 PM PDT 24
Finished Jul 28 05:08:03 PM PDT 24
Peak memory 1516244 kb
Host smart-571237b0-4a26-4736-9bc3-df3d7f5c2ed4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973818211 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.3973818211
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.510625217
Short name T818
Test name
Test status
Simulation time 7000696718 ps
CPU time 2.77 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:06:39 PM PDT 24
Peak memory 214220 kb
Host smart-8d761408-2c99-4a48-aa5c-f96656c93119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510625217 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_nack_acqfull.510625217
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.1853398118
Short name T480
Test name
Test status
Simulation time 2121364801 ps
CPU time 2.82 seconds
Started Jul 28 05:06:29 PM PDT 24
Finished Jul 28 05:06:32 PM PDT 24
Peak memory 205940 kb
Host smart-5ada28bf-6471-4328-bc03-30ed28eee817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853398118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.1853398118
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_txstretch.1073384986
Short name T888
Test name
Test status
Simulation time 354334348 ps
CPU time 1.42 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:06:36 PM PDT 24
Peak memory 222760 kb
Host smart-a8ed2be1-6f76-4b3f-be96-20b90c6dab52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073384986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_nack_txstretch.1073384986
Directory /workspace/46.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/46.i2c_target_perf.3928168631
Short name T1758
Test name
Test status
Simulation time 2148535044 ps
CPU time 6.26 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 230556 kb
Host smart-5edad954-daf6-4a20-b752-7833a0d960ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928168631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.3928168631
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.19671052
Short name T1610
Test name
Test status
Simulation time 1975593031 ps
CPU time 2.01 seconds
Started Jul 28 05:06:32 PM PDT 24
Finished Jul 28 05:06:34 PM PDT 24
Peak memory 205696 kb
Host smart-de5c83e6-d52e-4636-b4ee-9b2f8bc6031a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19671052 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_target_smbus_maxlen.19671052
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1854883902
Short name T1598
Test name
Test status
Simulation time 19903565391 ps
CPU time 15.23 seconds
Started Jul 28 05:06:37 PM PDT 24
Finished Jul 28 05:06:53 PM PDT 24
Peak memory 214340 kb
Host smart-3d806ed0-d550-4356-bed8-96cd6e1cc665
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854883902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1854883902
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.2364175375
Short name T535
Test name
Test status
Simulation time 17906287409 ps
CPU time 164.67 seconds
Started Jul 28 05:06:33 PM PDT 24
Finished Jul 28 05:09:18 PM PDT 24
Peak memory 1366776 kb
Host smart-60301a90-233b-49d6-ba21-d01d57535f65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364175375 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.2364175375
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.984968565
Short name T271
Test name
Test status
Simulation time 4536639516 ps
CPU time 21.99 seconds
Started Jul 28 05:06:34 PM PDT 24
Finished Jul 28 05:06:56 PM PDT 24
Peak memory 230536 kb
Host smart-4b0b32da-ca6f-4207-996d-b1b2c332fd17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984968565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.984968565
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.218136139
Short name T1096
Test name
Test status
Simulation time 13700850865 ps
CPU time 2.54 seconds
Started Jul 28 05:06:39 PM PDT 24
Finished Jul 28 05:06:42 PM PDT 24
Peak memory 205952 kb
Host smart-69e8ea5f-da0e-44a1-99e5-ab48eae89005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218136139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.218136139
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2274463573
Short name T669
Test name
Test status
Simulation time 673514366 ps
CPU time 2.19 seconds
Started Jul 28 05:06:49 PM PDT 24
Finished Jul 28 05:06:52 PM PDT 24
Peak memory 215844 kb
Host smart-f730092e-7b86-4354-b4c6-c63d8769e2c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274463573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2274463573
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2340948738
Short name T748
Test name
Test status
Simulation time 4335995657 ps
CPU time 6.44 seconds
Started Jul 28 05:06:41 PM PDT 24
Finished Jul 28 05:06:47 PM PDT 24
Peak memory 221624 kb
Host smart-40b9fde0-4c97-4feb-a95d-5be5b3233cbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340948738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2340948738
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.3394782479
Short name T941
Test name
Test status
Simulation time 19714930 ps
CPU time 0.65 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:06:39 PM PDT 24
Peak memory 204912 kb
Host smart-501513d6-7192-48e2-8775-8727e7cd3876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394782479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3394782479
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2009990252
Short name T845
Test name
Test status
Simulation time 4161723095 ps
CPU time 4.8 seconds
Started Jul 28 05:06:39 PM PDT 24
Finished Jul 28 05:06:44 PM PDT 24
Peak memory 251164 kb
Host smart-31eff98c-5564-4b99-993c-b50559fbe0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009990252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2009990252
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.2557820153
Short name T1438
Test name
Test status
Simulation time 1344518189 ps
CPU time 11.72 seconds
Started Jul 28 05:06:44 PM PDT 24
Finished Jul 28 05:06:55 PM PDT 24
Peak memory 243092 kb
Host smart-011d7e50-77f3-45ad-856d-a3124a3d14ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557820153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.2557820153
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.261043692
Short name T721
Test name
Test status
Simulation time 26028359360 ps
CPU time 73.4 seconds
Started Jul 28 05:06:33 PM PDT 24
Finished Jul 28 05:07:47 PM PDT 24
Peak memory 507040 kb
Host smart-0ec158eb-9db5-4723-a010-c4bea1e870f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261043692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.261043692
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2364286655
Short name T774
Test name
Test status
Simulation time 2698575993 ps
CPU time 81.16 seconds
Started Jul 28 05:06:33 PM PDT 24
Finished Jul 28 05:07:55 PM PDT 24
Peak memory 811480 kb
Host smart-2e86e10c-a2a3-4a99-a8f8-03f5480feecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364286655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2364286655
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1249932882
Short name T914
Test name
Test status
Simulation time 465972101 ps
CPU time 1.29 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:06:39 PM PDT 24
Peak memory 205696 kb
Host smart-5ba6600b-e266-4fc0-be8b-473a159d0ddc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249932882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1249932882
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1094132389
Short name T83
Test name
Test status
Simulation time 138496411 ps
CPU time 3.65 seconds
Started Jul 28 05:06:33 PM PDT 24
Finished Jul 28 05:06:37 PM PDT 24
Peak memory 228284 kb
Host smart-a4ffe122-6d83-4c05-8e4f-0cacd1629149
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094132389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1094132389
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.347686136
Short name T80
Test name
Test status
Simulation time 11592163968 ps
CPU time 111.81 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:08:30 PM PDT 24
Peak memory 1304484 kb
Host smart-ba045384-868e-4212-817c-11aa9824c6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347686136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.347686136
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.3867344922
Short name T1530
Test name
Test status
Simulation time 422559666 ps
CPU time 17.76 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:06:56 PM PDT 24
Peak memory 205660 kb
Host smart-979f5709-e507-4706-b764-9226b383ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867344922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3867344922
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.2090426866
Short name T140
Test name
Test status
Simulation time 88620680 ps
CPU time 0.67 seconds
Started Jul 28 05:06:37 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 205504 kb
Host smart-7a0bfcc8-96d7-4a39-ba61-eea9276cb5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090426866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2090426866
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1065471015
Short name T1289
Test name
Test status
Simulation time 1408222627 ps
CPU time 18.47 seconds
Started Jul 28 05:06:40 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 218572 kb
Host smart-0c834b7f-09fe-4824-8867-5d4c9acc6b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065471015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1065471015
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.448527846
Short name T1375
Test name
Test status
Simulation time 983764598 ps
CPU time 8.75 seconds
Started Jul 28 05:06:39 PM PDT 24
Finished Jul 28 05:06:48 PM PDT 24
Peak memory 205716 kb
Host smart-782fa89e-6995-42e3-af01-fa7f9905b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448527846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.448527846
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.4148070024
Short name T817
Test name
Test status
Simulation time 4727453737 ps
CPU time 30.95 seconds
Started Jul 28 05:06:48 PM PDT 24
Finished Jul 28 05:07:19 PM PDT 24
Peak memory 312844 kb
Host smart-523589f5-4dda-486d-a212-1501a6bf20bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148070024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.4148070024
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.2105449961
Short name T443
Test name
Test status
Simulation time 12481024668 ps
CPU time 1135.37 seconds
Started Jul 28 05:06:41 PM PDT 24
Finished Jul 28 05:25:37 PM PDT 24
Peak memory 1751828 kb
Host smart-b62c2e6e-ecea-4f3c-9a5a-0f9f29ef2900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105449961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.2105449961
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.4183079984
Short name T540
Test name
Test status
Simulation time 884186632 ps
CPU time 13.3 seconds
Started Jul 28 05:06:56 PM PDT 24
Finished Jul 28 05:07:09 PM PDT 24
Peak memory 222176 kb
Host smart-ee851334-7bf0-4ffc-b314-a5078ae35227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183079984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.4183079984
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3564907342
Short name T1753
Test name
Test status
Simulation time 788368577 ps
CPU time 3.89 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:06:40 PM PDT 24
Peak memory 214104 kb
Host smart-ab4b0a46-996e-43b4-acc2-8ab008b3251e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564907342 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3564907342
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1841594927
Short name T1540
Test name
Test status
Simulation time 532183646 ps
CPU time 0.94 seconds
Started Jul 28 05:06:37 PM PDT 24
Finished Jul 28 05:06:38 PM PDT 24
Peak memory 213904 kb
Host smart-d817637b-e5a7-4eed-93f3-80ad5035f37d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841594927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1841594927
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.4266473612
Short name T1240
Test name
Test status
Simulation time 229553698 ps
CPU time 0.82 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:06:39 PM PDT 24
Peak memory 205648 kb
Host smart-388d710e-1169-4ade-b9cf-3edfc1e8b6f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266473612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.4266473612
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.3444355965
Short name T1157
Test name
Test status
Simulation time 739198330 ps
CPU time 2.16 seconds
Started Jul 28 05:06:46 PM PDT 24
Finished Jul 28 05:06:49 PM PDT 24
Peak memory 205628 kb
Host smart-5b84f545-b054-404c-b6aa-d1fa13d73751
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444355965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.3444355965
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.1712952058
Short name T1562
Test name
Test status
Simulation time 135975598 ps
CPU time 1.24 seconds
Started Jul 28 05:06:44 PM PDT 24
Finished Jul 28 05:06:45 PM PDT 24
Peak memory 205708 kb
Host smart-8b5e242d-7ea4-47c5-9130-4c9bb1b31f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712952058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.1712952058
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1699746695
Short name T851
Test name
Test status
Simulation time 5253925517 ps
CPU time 8.69 seconds
Started Jul 28 05:06:40 PM PDT 24
Finished Jul 28 05:06:50 PM PDT 24
Peak memory 234100 kb
Host smart-e7dfab66-0f54-48bf-99d4-d6232f1219e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699746695 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1699746695
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2847606222
Short name T616
Test name
Test status
Simulation time 8360689149 ps
CPU time 5.57 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:06:44 PM PDT 24
Peak memory 205976 kb
Host smart-b7a473c6-3d00-4e43-9c5a-c3de3aef1889
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847606222 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2847606222
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.1829373088
Short name T732
Test name
Test status
Simulation time 1580390851 ps
CPU time 2.27 seconds
Started Jul 28 05:06:33 PM PDT 24
Finished Jul 28 05:06:35 PM PDT 24
Peak memory 214132 kb
Host smart-06d4ef42-2dce-4392-bd96-7c21c09f4dc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829373088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_nack_acqfull.1829373088
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.3294164668
Short name T659
Test name
Test status
Simulation time 468877802 ps
CPU time 2.48 seconds
Started Jul 28 05:06:47 PM PDT 24
Finished Jul 28 05:06:49 PM PDT 24
Peak memory 206292 kb
Host smart-84a41162-ec8f-413f-a7a4-1e2b44b5ec27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294164668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.3294164668
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_txstretch.3252191377
Short name T1119
Test name
Test status
Simulation time 639015919 ps
CPU time 1.54 seconds
Started Jul 28 05:06:40 PM PDT 24
Finished Jul 28 05:06:42 PM PDT 24
Peak memory 222532 kb
Host smart-148b81ee-3ac9-4db2-88d0-056e3bf4a409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252191377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_nack_txstretch.3252191377
Directory /workspace/47.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/47.i2c_target_perf.1603622630
Short name T1120
Test name
Test status
Simulation time 722756730 ps
CPU time 4.88 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:07:05 PM PDT 24
Peak memory 222288 kb
Host smart-6d933f91-47f1-4146-8e32-cb2ecb2b8f9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603622630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.1603622630
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.961350469
Short name T515
Test name
Test status
Simulation time 2054525819 ps
CPU time 2.3 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:06:41 PM PDT 24
Peak memory 205708 kb
Host smart-0fda201d-2b4e-465c-9bbc-c900e22f2706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961350469 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_smbus_maxlen.961350469
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2790961661
Short name T614
Test name
Test status
Simulation time 1118771139 ps
CPU time 16.61 seconds
Started Jul 28 05:06:39 PM PDT 24
Finished Jul 28 05:06:56 PM PDT 24
Peak memory 218736 kb
Host smart-4bd1b81d-a016-4863-a135-7b9a2562b380
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790961661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2790961661
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.3516889315
Short name T998
Test name
Test status
Simulation time 21035341199 ps
CPU time 160.71 seconds
Started Jul 28 05:07:03 PM PDT 24
Finished Jul 28 05:09:44 PM PDT 24
Peak memory 1269980 kb
Host smart-bd8fff8e-1374-4970-8eaa-df5a44eeea96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516889315 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.3516889315
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2197686142
Short name T1081
Test name
Test status
Simulation time 1355426922 ps
CPU time 27.71 seconds
Started Jul 28 05:06:38 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 230408 kb
Host smart-2974d49c-465c-498f-9939-1691747fab67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197686142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2197686142
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1204299040
Short name T796
Test name
Test status
Simulation time 49618393961 ps
CPU time 1560.52 seconds
Started Jul 28 05:06:40 PM PDT 24
Finished Jul 28 05:32:42 PM PDT 24
Peak memory 7454184 kb
Host smart-283a1ba6-579d-4631-9ea6-7fead79e8281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204299040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1204299040
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.325336519
Short name T1726
Test name
Test status
Simulation time 1066034379 ps
CPU time 16.84 seconds
Started Jul 28 05:06:52 PM PDT 24
Finished Jul 28 05:07:09 PM PDT 24
Peak memory 401180 kb
Host smart-176d75be-235f-4d4f-a90b-87180756289f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325336519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_t
arget_stretch.325336519
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1300297401
Short name T425
Test name
Test status
Simulation time 1182001512 ps
CPU time 6.5 seconds
Started Jul 28 05:06:53 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 214108 kb
Host smart-ab8ebc8d-94b8-40a5-8b18-62fca720c02a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300297401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1300297401
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2725932587
Short name T362
Test name
Test status
Simulation time 17466637 ps
CPU time 0.68 seconds
Started Jul 28 05:06:43 PM PDT 24
Finished Jul 28 05:06:44 PM PDT 24
Peak memory 205068 kb
Host smart-2ae32c10-18d7-4f89-b330-663b13c46fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725932587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2725932587
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1505364597
Short name T188
Test name
Test status
Simulation time 833992862 ps
CPU time 12.14 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:07:11 PM PDT 24
Peak memory 250832 kb
Host smart-2aeed6fb-f23f-4040-b049-f22843ad2348
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505364597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1505364597
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3665522771
Short name T5
Test name
Test status
Simulation time 28224448630 ps
CPU time 78.97 seconds
Started Jul 28 05:06:49 PM PDT 24
Finished Jul 28 05:08:08 PM PDT 24
Peak memory 540840 kb
Host smart-b3a09ecb-eebb-4ba3-b8e2-dc7154f287ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665522771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3665522771
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2829634997
Short name T473
Test name
Test status
Simulation time 7887050862 ps
CPU time 46.63 seconds
Started Jul 28 05:06:36 PM PDT 24
Finished Jul 28 05:07:23 PM PDT 24
Peak memory 512576 kb
Host smart-c1571482-eef3-4e62-83bb-87893b8cf0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829634997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2829634997
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.125214944
Short name T1435
Test name
Test status
Simulation time 196475005 ps
CPU time 1.01 seconds
Started Jul 28 05:06:43 PM PDT 24
Finished Jul 28 05:06:44 PM PDT 24
Peak memory 205388 kb
Host smart-ed5ac37b-8f30-480e-9128-61d15432277d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125214944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.125214944
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.259754487
Short name T1444
Test name
Test status
Simulation time 117615815 ps
CPU time 3.52 seconds
Started Jul 28 05:06:55 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 223596 kb
Host smart-00e200d9-7ce0-4d69-b680-4adadf7d7581
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259754487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
259754487
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2785211035
Short name T345
Test name
Test status
Simulation time 15387870958 ps
CPU time 111.26 seconds
Started Jul 28 05:06:35 PM PDT 24
Finished Jul 28 05:08:26 PM PDT 24
Peak memory 1128684 kb
Host smart-a2ab2761-3066-49fc-b074-ede70eed4fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785211035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2785211035
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.1252217699
Short name T1509
Test name
Test status
Simulation time 345471585 ps
CPU time 13.71 seconds
Started Jul 28 05:06:55 PM PDT 24
Finished Jul 28 05:07:09 PM PDT 24
Peak memory 205788 kb
Host smart-f4440dc9-dad4-45f4-b3f1-ec9260b1e43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252217699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1252217699
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_override.2799557818
Short name T746
Test name
Test status
Simulation time 85078479 ps
CPU time 0.71 seconds
Started Jul 28 05:06:40 PM PDT 24
Finished Jul 28 05:06:42 PM PDT 24
Peak memory 205224 kb
Host smart-a80977e1-15d9-49b8-a167-2a3cf74cf17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799557818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2799557818
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.485823606
Short name T1512
Test name
Test status
Simulation time 6041200786 ps
CPU time 100.22 seconds
Started Jul 28 05:06:41 PM PDT 24
Finished Jul 28 05:08:21 PM PDT 24
Peak memory 214984 kb
Host smart-31c24278-9340-44b9-9de5-52cd6453e5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485823606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.485823606
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.850629963
Short name T1493
Test name
Test status
Simulation time 1632199892 ps
CPU time 4.97 seconds
Started Jul 28 05:06:56 PM PDT 24
Finished Jul 28 05:07:01 PM PDT 24
Peak memory 205696 kb
Host smart-ce646981-d6d3-4059-b85b-43111e0326c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850629963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.850629963
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2967491411
Short name T618
Test name
Test status
Simulation time 2268862202 ps
CPU time 20.07 seconds
Started Jul 28 05:06:50 PM PDT 24
Finished Jul 28 05:07:10 PM PDT 24
Peak memory 285964 kb
Host smart-8b57b947-5b18-4b64-be99-a932d96b4f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967491411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2967491411
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2840632144
Short name T1732
Test name
Test status
Simulation time 792059783 ps
CPU time 14.85 seconds
Started Jul 28 05:06:50 PM PDT 24
Finished Jul 28 05:07:05 PM PDT 24
Peak memory 221820 kb
Host smart-ffd3eb77-f0c2-4aa8-ab04-915a01736fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840632144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2840632144
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.238619949
Short name T838
Test name
Test status
Simulation time 1031258215 ps
CPU time 5.25 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 218588 kb
Host smart-46980588-fb73-44d9-a646-5a64c7f5dd7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238619949 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.238619949
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2892989302
Short name T72
Test name
Test status
Simulation time 227886282 ps
CPU time 1.79 seconds
Started Jul 28 05:06:53 PM PDT 24
Finished Jul 28 05:06:55 PM PDT 24
Peak memory 205816 kb
Host smart-e2808da7-9cdf-428a-9eae-26b86c0e5143
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892989302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2892989302
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.353147214
Short name T609
Test name
Test status
Simulation time 169912061 ps
CPU time 1.18 seconds
Started Jul 28 05:06:52 PM PDT 24
Finished Jul 28 05:06:53 PM PDT 24
Peak memory 205720 kb
Host smart-af46297e-e5ca-4e7e-9c27-eab2e0705cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353147214 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_tx.353147214
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.3031993024
Short name T601
Test name
Test status
Simulation time 2152911057 ps
CPU time 2.97 seconds
Started Jul 28 05:06:44 PM PDT 24
Finished Jul 28 05:06:47 PM PDT 24
Peak memory 206112 kb
Host smart-0c15de2d-e451-42ac-ac23-a0be6bae564a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031993024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.3031993024
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.3936094025
Short name T674
Test name
Test status
Simulation time 276066253 ps
CPU time 0.93 seconds
Started Jul 28 05:06:51 PM PDT 24
Finished Jul 28 05:06:52 PM PDT 24
Peak memory 205776 kb
Host smart-21f2cb7e-880d-4088-92a9-ff2fe8cecb0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936094025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.3936094025
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3862849724
Short name T1572
Test name
Test status
Simulation time 566010041 ps
CPU time 2.19 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 214220 kb
Host smart-8d63f450-5b5c-4d66-a37a-689c9044b2cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862849724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3862849724
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1155632894
Short name T639
Test name
Test status
Simulation time 1717105474 ps
CPU time 3.81 seconds
Started Jul 28 05:06:56 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 214124 kb
Host smart-5c686387-f617-4aba-b30c-b6ac7fa5547d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155632894 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1155632894
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.541568790
Short name T624
Test name
Test status
Simulation time 5124053972 ps
CPU time 10.77 seconds
Started Jul 28 05:06:44 PM PDT 24
Finished Jul 28 05:06:55 PM PDT 24
Peak memory 205984 kb
Host smart-78377d8e-0805-4984-8943-c3b5ce9a5695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541568790 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.541568790
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.2455956681
Short name T67
Test name
Test status
Simulation time 1925869194 ps
CPU time 3.09 seconds
Started Jul 28 05:06:43 PM PDT 24
Finished Jul 28 05:06:47 PM PDT 24
Peak memory 214160 kb
Host smart-663a73cc-82d4-407c-a081-021fe40e34f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455956681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_acqfull.2455956681
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.294014400
Short name T69
Test name
Test status
Simulation time 613403787 ps
CPU time 2.79 seconds
Started Jul 28 05:06:55 PM PDT 24
Finished Jul 28 05:06:58 PM PDT 24
Peak memory 206088 kb
Host smart-7d817d92-09bb-410c-b5cc-08ed9f9fe6b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294014400 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.294014400
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.2133618113
Short name T1025
Test name
Test status
Simulation time 617629020 ps
CPU time 5.06 seconds
Started Jul 28 05:06:47 PM PDT 24
Finished Jul 28 05:06:52 PM PDT 24
Peak memory 222256 kb
Host smart-79b6f957-846c-4f94-af75-c7d11d9ebfbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133618113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.2133618113
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.2473625376
Short name T931
Test name
Test status
Simulation time 504877838 ps
CPU time 2.4 seconds
Started Jul 28 05:06:51 PM PDT 24
Finished Jul 28 05:06:53 PM PDT 24
Peak memory 205700 kb
Host smart-fa718814-e0ec-4d81-b2fe-6da0c1ba53b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473625376 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_smbus_maxlen.2473625376
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2986383849
Short name T1158
Test name
Test status
Simulation time 13845500960 ps
CPU time 12.76 seconds
Started Jul 28 05:06:50 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 214288 kb
Host smart-e161b748-1676-4d13-9d7e-1f3ac207273d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986383849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2986383849
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.2556680780
Short name T1637
Test name
Test status
Simulation time 49522527269 ps
CPU time 120.9 seconds
Started Jul 28 05:06:50 PM PDT 24
Finished Jul 28 05:08:51 PM PDT 24
Peak memory 871916 kb
Host smart-1f8ff84f-d58b-498e-8214-523cb8981b73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556680780 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.2556680780
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.4085545981
Short name T1031
Test name
Test status
Simulation time 930194369 ps
CPU time 11.29 seconds
Started Jul 28 05:06:54 PM PDT 24
Finished Jul 28 05:07:05 PM PDT 24
Peak memory 205900 kb
Host smart-249b337d-c521-4d30-95cd-68b3bb80e123
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085545981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.4085545981
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.1428880778
Short name T1411
Test name
Test status
Simulation time 30305097745 ps
CPU time 34.44 seconds
Started Jul 28 05:06:55 PM PDT 24
Finished Jul 28 05:07:30 PM PDT 24
Peak memory 708304 kb
Host smart-38484f47-d0d9-4dd6-9d8c-3a05f747d6db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428880778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.1428880778
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1300589024
Short name T1087
Test name
Test status
Simulation time 707601969 ps
CPU time 7.33 seconds
Started Jul 28 05:06:44 PM PDT 24
Finished Jul 28 05:06:51 PM PDT 24
Peak memory 298016 kb
Host smart-a3b70c35-f56d-423b-b0b0-0bc3821a8c88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300589024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1300589024
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.396901990
Short name T597
Test name
Test status
Simulation time 5749303117 ps
CPU time 7.05 seconds
Started Jul 28 05:06:52 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 214296 kb
Host smart-8acf0f99-314d-4d30-b4e9-ae814c576d14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396901990 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.396901990
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.1861989
Short name T459
Test name
Test status
Simulation time 159070262 ps
CPU time 3.64 seconds
Started Jul 28 05:06:42 PM PDT 24
Finished Jul 28 05:06:46 PM PDT 24
Peak memory 205976 kb
Host smart-12e12a4f-a701-4cea-aa47-de3f856c88e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861989 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_tx_stretch_ctrl.1861989
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.378069902
Short name T691
Test name
Test status
Simulation time 49513629 ps
CPU time 0.63 seconds
Started Jul 28 05:06:48 PM PDT 24
Finished Jul 28 05:06:49 PM PDT 24
Peak memory 204860 kb
Host smart-a9ceb5bc-789f-4d2e-9e9e-e142d5cc176d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378069902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.378069902
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.966424823
Short name T1002
Test name
Test status
Simulation time 99186876 ps
CPU time 2.18 seconds
Started Jul 28 05:06:48 PM PDT 24
Finished Jul 28 05:06:51 PM PDT 24
Peak memory 214108 kb
Host smart-a4fc2fd6-40c1-4dbc-a1f4-78ddf051fc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966424823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.966424823
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1369727178
Short name T775
Test name
Test status
Simulation time 584320117 ps
CPU time 2.82 seconds
Started Jul 28 05:07:06 PM PDT 24
Finished Jul 28 05:07:09 PM PDT 24
Peak memory 229080 kb
Host smart-a7ebf995-c491-4c75-835d-727bdb39be4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369727178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1369727178
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3732983978
Short name T631
Test name
Test status
Simulation time 4860172046 ps
CPU time 61.89 seconds
Started Jul 28 05:06:57 PM PDT 24
Finished Jul 28 05:07:59 PM PDT 24
Peak memory 526716 kb
Host smart-636db806-47ea-4d58-8d6c-83e5b779b331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732983978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3732983978
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1023004522
Short name T868
Test name
Test status
Simulation time 1263574417 ps
CPU time 82.87 seconds
Started Jul 28 05:07:08 PM PDT 24
Finished Jul 28 05:08:31 PM PDT 24
Peak memory 513936 kb
Host smart-43334c94-f9a0-4099-9ca2-0c69d11a23c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023004522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1023004522
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1852111519
Short name T486
Test name
Test status
Simulation time 132308973 ps
CPU time 1.25 seconds
Started Jul 28 05:06:46 PM PDT 24
Finished Jul 28 05:06:47 PM PDT 24
Peak memory 205520 kb
Host smart-d2e9e7b6-6893-46bb-bc08-93be8dca75f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852111519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1852111519
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1553644234
Short name T86
Test name
Test status
Simulation time 769421349 ps
CPU time 4.4 seconds
Started Jul 28 05:06:57 PM PDT 24
Finished Jul 28 05:07:02 PM PDT 24
Peak memory 205800 kb
Host smart-f8e514e5-4d06-4f2c-b916-535312399450
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553644234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1553644234
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3408994947
Short name T111
Test name
Test status
Simulation time 27503550685 ps
CPU time 103.4 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:08:42 PM PDT 24
Peak memory 1161296 kb
Host smart-dd064a10-4006-4c80-9c05-83241f0cb53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408994947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3408994947
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.1319785297
Short name T948
Test name
Test status
Simulation time 637564855 ps
CPU time 4.99 seconds
Started Jul 28 05:06:51 PM PDT 24
Finished Jul 28 05:06:56 PM PDT 24
Peak memory 205688 kb
Host smart-d3112b21-1979-4a34-bc3a-aed900c3b2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319785297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.1319785297
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3466077859
Short name T267
Test name
Test status
Simulation time 106997294 ps
CPU time 3.84 seconds
Started Jul 28 05:06:49 PM PDT 24
Finished Jul 28 05:06:53 PM PDT 24
Peak memory 213912 kb
Host smart-af72c8e4-b27a-4477-8f70-a9ba130c9631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466077859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3466077859
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1547067583
Short name T1467
Test name
Test status
Simulation time 53091153 ps
CPU time 0.66 seconds
Started Jul 28 05:07:17 PM PDT 24
Finished Jul 28 05:07:18 PM PDT 24
Peak memory 205468 kb
Host smart-3921364a-1293-4827-a3da-1083d37e1ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547067583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1547067583
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.58593526
Short name T1055
Test name
Test status
Simulation time 4096314404 ps
CPU time 154.77 seconds
Started Jul 28 05:06:54 PM PDT 24
Finished Jul 28 05:09:29 PM PDT 24
Peak memory 214044 kb
Host smart-911f048a-3f63-4d46-b761-d36e1ca7ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58593526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.58593526
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.1847264339
Short name T1237
Test name
Test status
Simulation time 1648669962 ps
CPU time 16.69 seconds
Started Jul 28 05:06:49 PM PDT 24
Finished Jul 28 05:07:06 PM PDT 24
Peak memory 205740 kb
Host smart-58ff0510-7d70-4483-8b49-fdc4b866ec11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847264339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.1847264339
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3414384787
Short name T979
Test name
Test status
Simulation time 4753972306 ps
CPU time 59.66 seconds
Started Jul 28 05:06:42 PM PDT 24
Finished Jul 28 05:07:42 PM PDT 24
Peak memory 349524 kb
Host smart-1b2e19d6-4b3f-44e7-9a07-fd998978c674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414384787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3414384787
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.317373416
Short name T325
Test name
Test status
Simulation time 923954023 ps
CPU time 16.35 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 221780 kb
Host smart-a60d3aa6-018d-4a6c-a8a8-65c44d5f4cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317373416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.317373416
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3654799245
Short name T504
Test name
Test status
Simulation time 4910626462 ps
CPU time 5.77 seconds
Started Jul 28 05:06:56 PM PDT 24
Finished Jul 28 05:07:02 PM PDT 24
Peak memory 214296 kb
Host smart-08f4df92-4e70-413e-bc9b-9c7fe658d633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654799245 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3654799245
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3693647578
Short name T842
Test name
Test status
Simulation time 298420705 ps
CPU time 1.19 seconds
Started Jul 28 05:06:59 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 205696 kb
Host smart-e12687be-1a7f-431b-98f2-d33fff3f8450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693647578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3693647578
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.4081325817
Short name T1332
Test name
Test status
Simulation time 680291055 ps
CPU time 1.33 seconds
Started Jul 28 05:06:54 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 205972 kb
Host smart-559bb6d7-ded4-49a5-9a07-43a0c9e80624
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081325817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.4081325817
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.1846645886
Short name T1297
Test name
Test status
Simulation time 1042278285 ps
CPU time 1.8 seconds
Started Jul 28 05:06:53 PM PDT 24
Finished Jul 28 05:06:55 PM PDT 24
Peak memory 205752 kb
Host smart-d9129254-ca9a-4ac5-ad4e-d7aea0590e67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846645886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.1846645886
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.3612723173
Short name T1624
Test name
Test status
Simulation time 945820995 ps
CPU time 0.92 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 205760 kb
Host smart-1ec43e1f-c523-4319-999b-5fe8e3f97427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612723173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.3612723173
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1884973931
Short name T1573
Test name
Test status
Simulation time 329956676 ps
CPU time 2.61 seconds
Started Jul 28 05:06:54 PM PDT 24
Finished Jul 28 05:06:56 PM PDT 24
Peak memory 214048 kb
Host smart-ccc61c5d-35f4-4084-97f5-5cdfcc93c821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884973931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1884973931
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1061890886
Short name T873
Test name
Test status
Simulation time 738962772 ps
CPU time 4.49 seconds
Started Jul 28 05:06:48 PM PDT 24
Finished Jul 28 05:06:52 PM PDT 24
Peak memory 216832 kb
Host smart-4fcda75f-ffd8-4ac7-a0ff-59c9844057ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061890886 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1061890886
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2961151517
Short name T1112
Test name
Test status
Simulation time 19425054129 ps
CPU time 559.35 seconds
Started Jul 28 05:07:00 PM PDT 24
Finished Jul 28 05:16:20 PM PDT 24
Peak memory 4804756 kb
Host smart-27044751-4373-4743-9288-655fcc9b3b97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961151517 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2961151517
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.244858645
Short name T426
Test name
Test status
Simulation time 5455212521 ps
CPU time 2.78 seconds
Started Jul 28 05:07:14 PM PDT 24
Finished Jul 28 05:07:17 PM PDT 24
Peak memory 214196 kb
Host smart-5debfdb5-0c50-4e3a-9220-febbe8fd6f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244858645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_nack_acqfull.244858645
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.1555339462
Short name T57
Test name
Test status
Simulation time 500253318 ps
CPU time 2.61 seconds
Started Jul 28 05:06:56 PM PDT 24
Finished Jul 28 05:06:59 PM PDT 24
Peak memory 205912 kb
Host smart-d0b2ea23-9472-4804-b258-59678c93a4f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555339462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.1555339462
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_txstretch.4000194255
Short name T1255
Test name
Test status
Simulation time 133741486 ps
CPU time 1.37 seconds
Started Jul 28 05:07:01 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 222880 kb
Host smart-2cadeff1-fe3d-4555-a593-63cba75c0468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000194255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_nack_txstretch.4000194255
Directory /workspace/49.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/49.i2c_target_perf.1130041053
Short name T1495
Test name
Test status
Simulation time 714609009 ps
CPU time 5.17 seconds
Started Jul 28 05:06:58 PM PDT 24
Finished Jul 28 05:07:03 PM PDT 24
Peak memory 214168 kb
Host smart-3fe17ca7-3e76-4e50-bc97-a14c41cfe2a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130041053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.1130041053
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.881709063
Short name T1619
Test name
Test status
Simulation time 974478042 ps
CPU time 2.33 seconds
Started Jul 28 05:06:53 PM PDT 24
Finished Jul 28 05:06:55 PM PDT 24
Peak memory 205776 kb
Host smart-152f556b-6b7d-419b-b8f4-47c6ce23fe78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881709063 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_smbus_maxlen.881709063
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2285910451
Short name T525
Test name
Test status
Simulation time 1434596375 ps
CPU time 21.26 seconds
Started Jul 28 05:06:50 PM PDT 24
Finished Jul 28 05:07:12 PM PDT 24
Peak memory 214112 kb
Host smart-3a15d7ac-f024-447e-a09e-4316d5405433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285910451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2285910451
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.283630733
Short name T1379
Test name
Test status
Simulation time 43154803960 ps
CPU time 272.2 seconds
Started Jul 28 05:06:54 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 2991684 kb
Host smart-18aec008-ff0e-45f7-a4b7-3e467b913f09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283630733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_stress_all.283630733
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3071333316
Short name T536
Test name
Test status
Simulation time 1290570059 ps
CPU time 11.33 seconds
Started Jul 28 05:06:49 PM PDT 24
Finished Jul 28 05:07:00 PM PDT 24
Peak memory 216428 kb
Host smart-a9eef25f-decd-4f2e-9798-3317a37f4190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071333316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3071333316
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.262655025
Short name T1006
Test name
Test status
Simulation time 37331415158 ps
CPU time 181.45 seconds
Started Jul 28 05:06:57 PM PDT 24
Finished Jul 28 05:09:59 PM PDT 24
Peak memory 2259556 kb
Host smart-fae71d6e-fb41-4b7c-a686-645588dc5cec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262655025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.262655025
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1975965875
Short name T1176
Test name
Test status
Simulation time 1897179957 ps
CPU time 34.16 seconds
Started Jul 28 05:06:54 PM PDT 24
Finished Jul 28 05:07:28 PM PDT 24
Peak memory 601468 kb
Host smart-3442b1cd-0c57-4d7f-873e-0e2a3134f1dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975965875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1975965875
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3340353774
Short name T1050
Test name
Test status
Simulation time 5490137128 ps
CPU time 8.04 seconds
Started Jul 28 05:06:57 PM PDT 24
Finished Jul 28 05:07:05 PM PDT 24
Peak memory 222360 kb
Host smart-ba295756-73fb-4a37-9800-6f58d4a166e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340353774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3340353774
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.723595073
Short name T1569
Test name
Test status
Simulation time 102512415 ps
CPU time 1.83 seconds
Started Jul 28 05:06:54 PM PDT 24
Finished Jul 28 05:06:56 PM PDT 24
Peak memory 205872 kb
Host smart-700a92d7-3565-43ba-8a7d-12dd8043e99a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723595073 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.723595073
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2803037363
Short name T543
Test name
Test status
Simulation time 90454040 ps
CPU time 0.63 seconds
Started Jul 28 05:03:11 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 204888 kb
Host smart-b75c87bd-0db4-4f3c-928d-b28a2264dfff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803037363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2803037363
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.3787922812
Short name T570
Test name
Test status
Simulation time 2127019303 ps
CPU time 27.76 seconds
Started Jul 28 05:02:52 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 327052 kb
Host smart-ba8d3d1a-38e2-4682-bb15-afbc2da236ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787922812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.3787922812
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.4197748130
Short name T957
Test name
Test status
Simulation time 12742945447 ps
CPU time 184.37 seconds
Started Jul 28 05:03:06 PM PDT 24
Finished Jul 28 05:06:11 PM PDT 24
Peak memory 526368 kb
Host smart-1dc0a5ff-b313-4872-8bb5-0030b51baa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197748130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.4197748130
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.2087002357
Short name T548
Test name
Test status
Simulation time 1407544636 ps
CPU time 91.74 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:04:23 PM PDT 24
Peak memory 491316 kb
Host smart-ecf1988f-5827-41d8-b85e-95e4f199f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087002357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2087002357
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.175129751
Short name T1484
Test name
Test status
Simulation time 164237959 ps
CPU time 1.3 seconds
Started Jul 28 05:03:06 PM PDT 24
Finished Jul 28 05:03:07 PM PDT 24
Peak memory 205648 kb
Host smart-a6e448ca-5309-4526-96aa-f3a098ccea40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175129751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt
.175129751
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1288378699
Short name T532
Test name
Test status
Simulation time 359909204 ps
CPU time 4.99 seconds
Started Jul 28 05:03:14 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 240236 kb
Host smart-ee6c2f6a-7541-4169-aaa1-aebc5e5919c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288378699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1288378699
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1365572490
Short name T112
Test name
Test status
Simulation time 11076346030 ps
CPU time 131.12 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:05:30 PM PDT 24
Peak memory 1450560 kb
Host smart-a42243fb-efa0-47be-a7a1-52dabc0a478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365572490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1365572490
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3190136174
Short name T761
Test name
Test status
Simulation time 1341612962 ps
CPU time 14.35 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:03:06 PM PDT 24
Peak memory 205688 kb
Host smart-efe128ed-0cf6-4182-9dad-2eff75e93265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190136174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3190136174
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.3961267740
Short name T1077
Test name
Test status
Simulation time 270935834 ps
CPU time 1.34 seconds
Started Jul 28 05:03:07 PM PDT 24
Finished Jul 28 05:03:09 PM PDT 24
Peak memory 205684 kb
Host smart-13b57bb2-e2ee-44da-954b-b60586f2d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961267740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.3961267740
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3719429914
Short name T1482
Test name
Test status
Simulation time 18276748 ps
CPU time 0.69 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:02:54 PM PDT 24
Peak memory 205488 kb
Host smart-505ee787-95f0-4e07-b74d-139497827823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719429914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3719429914
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.2516800308
Short name T1382
Test name
Test status
Simulation time 6823465703 ps
CPU time 43.82 seconds
Started Jul 28 05:02:52 PM PDT 24
Finished Jul 28 05:03:36 PM PDT 24
Peak memory 215044 kb
Host smart-714a3c75-e50b-448d-bb50-408b2795ad95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516800308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2516800308
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.2762257218
Short name T1206
Test name
Test status
Simulation time 1766666572 ps
CPU time 24.75 seconds
Started Jul 28 05:03:02 PM PDT 24
Finished Jul 28 05:03:27 PM PDT 24
Peak memory 205600 kb
Host smart-51615e84-d2d9-47fe-bcda-1fe9b67dbd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762257218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.2762257218
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3158268778
Short name T622
Test name
Test status
Simulation time 39645351401 ps
CPU time 41.5 seconds
Started Jul 28 05:02:59 PM PDT 24
Finished Jul 28 05:03:41 PM PDT 24
Peak memory 383340 kb
Host smart-e957686f-f493-4a5b-89cc-f94a952cd4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158268778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3158268778
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2603042114
Short name T682
Test name
Test status
Simulation time 826321348 ps
CPU time 17.69 seconds
Started Jul 28 05:03:10 PM PDT 24
Finished Jul 28 05:03:28 PM PDT 24
Peak memory 213984 kb
Host smart-416b20a0-3638-4176-b329-90ffe2474b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603042114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2603042114
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1273837233
Short name T1215
Test name
Test status
Simulation time 1894950592 ps
CPU time 5.01 seconds
Started Jul 28 05:02:59 PM PDT 24
Finished Jul 28 05:03:04 PM PDT 24
Peak memory 214188 kb
Host smart-799b5fec-d02f-4ceb-96af-4ff4ff103e07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273837233 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1273837233
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3860780480
Short name T557
Test name
Test status
Simulation time 168573772 ps
CPU time 1.08 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 205624 kb
Host smart-59cc3636-6c4d-48ab-b642-6c12d305cae8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860780480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3860780480
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.4290466637
Short name T1472
Test name
Test status
Simulation time 3417637370 ps
CPU time 1.76 seconds
Started Jul 28 05:03:01 PM PDT 24
Finished Jul 28 05:03:03 PM PDT 24
Peak memory 214252 kb
Host smart-4ff5a47e-df03-4b24-b29d-83e81ac9435f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290466637 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.4290466637
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.1018391640
Short name T890
Test name
Test status
Simulation time 1768319258 ps
CPU time 2.65 seconds
Started Jul 28 05:03:12 PM PDT 24
Finished Jul 28 05:03:15 PM PDT 24
Peak memory 205904 kb
Host smart-032f5c97-db5d-4b55-b6dd-9435c891e657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018391640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.1018391640
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.2003966720
Short name T1102
Test name
Test status
Simulation time 502530065 ps
CPU time 0.72 seconds
Started Jul 28 05:03:10 PM PDT 24
Finished Jul 28 05:03:11 PM PDT 24
Peak memory 205724 kb
Host smart-a0d57c0a-80f8-4ac5-847b-0b18efdeb10e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003966720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.2003966720
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.4026102214
Short name T452
Test name
Test status
Simulation time 950835260 ps
CPU time 1.79 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:17 PM PDT 24
Peak memory 205928 kb
Host smart-57b20d4c-6378-4c5c-8ef6-4668e4079bdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026102214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.4026102214
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2142866110
Short name T1585
Test name
Test status
Simulation time 2319113699 ps
CPU time 7.02 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:03:03 PM PDT 24
Peak memory 222480 kb
Host smart-694844e5-f9de-4fc2-9724-162b4e618b96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142866110 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2142866110
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3851791223
Short name T281
Test name
Test status
Simulation time 1408049322 ps
CPU time 10.07 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:03:18 PM PDT 24
Peak memory 476020 kb
Host smart-9c3245fb-a11a-4989-a2e0-c5a25d5005b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851791223 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3851791223
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.664133810
Short name T1373
Test name
Test status
Simulation time 974896036 ps
CPU time 2.98 seconds
Started Jul 28 05:03:07 PM PDT 24
Finished Jul 28 05:03:10 PM PDT 24
Peak memory 214140 kb
Host smart-743da1df-9daf-4c99-82c2-8bc962025051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664133810 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_nack_acqfull.664133810
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.3171782103
Short name T821
Test name
Test status
Simulation time 498863410 ps
CPU time 2.63 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:03:31 PM PDT 24
Peak memory 205912 kb
Host smart-fd3beb00-e006-44b1-aa82-2801607db118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171782103 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.3171782103
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_txstretch.3819553340
Short name T671
Test name
Test status
Simulation time 137206248 ps
CPU time 1.48 seconds
Started Jul 28 05:03:17 PM PDT 24
Finished Jul 28 05:03:18 PM PDT 24
Peak memory 222936 kb
Host smart-5218c7ac-3fe4-4235-b4d5-0f757a8f3497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819553340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_nack_txstretch.3819553340
Directory /workspace/5.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/5.i2c_target_perf.1143330531
Short name T719
Test name
Test status
Simulation time 3522112228 ps
CPU time 4.22 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:08 PM PDT 24
Peak memory 210648 kb
Host smart-632c227b-a34a-4a74-9af7-2b6d0b8628af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143330531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.1143330531
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.793247553
Short name T1722
Test name
Test status
Simulation time 451107376 ps
CPU time 2.18 seconds
Started Jul 28 05:03:20 PM PDT 24
Finished Jul 28 05:03:22 PM PDT 24
Peak memory 205736 kb
Host smart-8539e809-9acf-47c7-8b3e-617d4a782488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793247553 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_smbus_maxlen.793247553
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.4132890558
Short name T1678
Test name
Test status
Simulation time 7914453178 ps
CPU time 41.31 seconds
Started Jul 28 05:03:12 PM PDT 24
Finished Jul 28 05:03:53 PM PDT 24
Peak memory 238800 kb
Host smart-1977a484-daf7-4306-9cf1-509a327276ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132890558 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.4132890558
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3630004608
Short name T1440
Test name
Test status
Simulation time 2083460385 ps
CPU time 7.69 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:25 PM PDT 24
Peak memory 218156 kb
Host smart-25ff6acd-9e61-4416-b1ec-09f202885859
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630004608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3630004608
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1886522428
Short name T801
Test name
Test status
Simulation time 29063728381 ps
CPU time 181.37 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:05:56 PM PDT 24
Peak memory 2280052 kb
Host smart-39cf3a75-b843-4db4-897d-ae0d226eca94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886522428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1886522428
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2724889515
Short name T1219
Test name
Test status
Simulation time 3830839414 ps
CPU time 27.86 seconds
Started Jul 28 05:03:06 PM PDT 24
Finished Jul 28 05:03:34 PM PDT 24
Peak memory 581988 kb
Host smart-43d5da85-f433-4597-8cac-6cc8d0818ad0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724889515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2724889515
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3977207934
Short name T1636
Test name
Test status
Simulation time 1214426176 ps
CPU time 6.46 seconds
Started Jul 28 05:03:13 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 214100 kb
Host smart-af0732f2-647e-4675-948d-051f8f5bbf8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977207934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3977207934
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.4104028868
Short name T986
Test name
Test status
Simulation time 277055903 ps
CPU time 4.42 seconds
Started Jul 28 05:03:21 PM PDT 24
Finished Jul 28 05:03:26 PM PDT 24
Peak memory 206876 kb
Host smart-04e85c16-9e65-4774-8f66-2a8baae2d860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104028868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.4104028868
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.856927620
Short name T365
Test name
Test status
Simulation time 46024693 ps
CPU time 0.63 seconds
Started Jul 28 05:03:03 PM PDT 24
Finished Jul 28 05:03:04 PM PDT 24
Peak memory 204832 kb
Host smart-cb09c5ea-6baf-405f-aa65-407ad7d2a675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856927620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.856927620
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.662829106
Short name T945
Test name
Test status
Simulation time 386417997 ps
CPU time 1.36 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:16 PM PDT 24
Peak memory 205768 kb
Host smart-605c7da3-6fc0-4f56-9902-e00b93957012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662829106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.662829106
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.624524728
Short name T1606
Test name
Test status
Simulation time 325767379 ps
CPU time 6.99 seconds
Started Jul 28 05:03:10 PM PDT 24
Finished Jul 28 05:03:17 PM PDT 24
Peak memory 274144 kb
Host smart-d212d5e0-7692-4db4-b5ab-d0553039138b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624524728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.624524728
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2014504818
Short name T436
Test name
Test status
Simulation time 7198010115 ps
CPU time 286.25 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:07:54 PM PDT 24
Peak memory 981248 kb
Host smart-3b44f51c-9438-4777-b6e3-fea8e4453a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014504818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2014504818
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1148657317
Short name T815
Test name
Test status
Simulation time 1653946679 ps
CPU time 40.95 seconds
Started Jul 28 05:03:07 PM PDT 24
Finished Jul 28 05:03:48 PM PDT 24
Peak memory 548680 kb
Host smart-98a7310a-22ce-481f-8f2b-2d0cdff20202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148657317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1148657317
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3353446905
Short name T1434
Test name
Test status
Simulation time 368091891 ps
CPU time 1.09 seconds
Started Jul 28 05:02:59 PM PDT 24
Finished Jul 28 05:03:00 PM PDT 24
Peak memory 205484 kb
Host smart-867ee4f3-33fb-43b1-beea-24912e881afe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353446905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3353446905
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.734909407
Short name T1699
Test name
Test status
Simulation time 234033027 ps
CPU time 6.35 seconds
Started Jul 28 05:02:58 PM PDT 24
Finished Jul 28 05:03:04 PM PDT 24
Peak memory 250284 kb
Host smart-5bbd2b3c-47fb-42c9-a4a8-c59b82ab7f31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734909407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.734909407
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3417429079
Short name T1269
Test name
Test status
Simulation time 2924054935 ps
CPU time 192.97 seconds
Started Jul 28 05:03:07 PM PDT 24
Finished Jul 28 05:06:20 PM PDT 24
Peak memory 888992 kb
Host smart-0bb1c0d7-8b8c-4664-84a0-5a0337b2732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417429079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3417429079
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3127637966
Short name T257
Test name
Test status
Simulation time 1949116626 ps
CPU time 8 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 205696 kb
Host smart-19bbbe03-54f2-4546-8e82-80350727fa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127637966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3127637966
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1431625132
Short name T567
Test name
Test status
Simulation time 97733993 ps
CPU time 1.75 seconds
Started Jul 28 05:03:05 PM PDT 24
Finished Jul 28 05:03:06 PM PDT 24
Peak memory 221584 kb
Host smart-b0d00ac5-75d5-44fc-95ab-6ab70c5ff894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431625132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1431625132
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1577697292
Short name T642
Test name
Test status
Simulation time 6760223642 ps
CPU time 70.35 seconds
Started Jul 28 05:03:27 PM PDT 24
Finished Jul 28 05:04:37 PM PDT 24
Peak memory 205820 kb
Host smart-ac8a7274-e9e2-443e-ab86-253ca92ce1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577697292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1577697292
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.2757790713
Short name T1427
Test name
Test status
Simulation time 876792975 ps
CPU time 3.22 seconds
Started Jul 28 05:02:57 PM PDT 24
Finished Jul 28 05:03:00 PM PDT 24
Peak memory 219728 kb
Host smart-5bbc4c40-d33b-4b99-8e83-c3b140c72581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757790713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.2757790713
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.628322312
Short name T688
Test name
Test status
Simulation time 963534973 ps
CPU time 18.58 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:03:42 PM PDT 24
Peak memory 315220 kb
Host smart-2b1c1abd-e5e7-4503-9bb5-7497d035d92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628322312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.628322312
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3183125043
Short name T1268
Test name
Test status
Simulation time 607447152 ps
CPU time 25.02 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 214016 kb
Host smart-6aa1379e-0269-4627-9168-416b1db30284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183125043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3183125043
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.187049527
Short name T1665
Test name
Test status
Simulation time 1044789141 ps
CPU time 5.81 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:03:14 PM PDT 24
Peak memory 214056 kb
Host smart-741bd6b2-08b6-4479-8455-12942306f304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187049527 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.187049527
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2585707062
Short name T1171
Test name
Test status
Simulation time 544942771 ps
CPU time 1.11 seconds
Started Jul 28 05:03:10 PM PDT 24
Finished Jul 28 05:03:12 PM PDT 24
Peak memory 205896 kb
Host smart-1105d299-8700-41ae-88b3-84a144a85200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585707062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2585707062
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.979286222
Short name T627
Test name
Test status
Simulation time 223637999 ps
CPU time 1.08 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:16 PM PDT 24
Peak memory 205708 kb
Host smart-77099390-20d6-42b1-a2be-8dcc7d5de282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979286222 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.979286222
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.3686905990
Short name T1353
Test name
Test status
Simulation time 1781753197 ps
CPU time 2.89 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:03:31 PM PDT 24
Peak memory 205908 kb
Host smart-ba83da8a-ca0a-49e1-ab36-c90565f729ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686905990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.3686905990
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.560499070
Short name T1245
Test name
Test status
Simulation time 256400536 ps
CPU time 0.95 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:03:09 PM PDT 24
Peak memory 205784 kb
Host smart-1413289a-4588-4414-94fc-0d22002688d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560499070 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.560499070
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1681574343
Short name T177
Test name
Test status
Simulation time 419439698 ps
CPU time 2.94 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:26 PM PDT 24
Peak memory 214108 kb
Host smart-222c0b5f-d7ba-45f8-9a6c-f248264c127e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681574343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1681574343
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3456709247
Short name T1580
Test name
Test status
Simulation time 6141741660 ps
CPU time 5.24 seconds
Started Jul 28 05:03:21 PM PDT 24
Finished Jul 28 05:03:26 PM PDT 24
Peak memory 222424 kb
Host smart-e0d1ba17-1f9d-4996-908a-b8efa437c43e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456709247 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3456709247
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.80004046
Short name T611
Test name
Test status
Simulation time 11595893247 ps
CPU time 74.51 seconds
Started Jul 28 05:03:03 PM PDT 24
Finished Jul 28 05:04:18 PM PDT 24
Peak memory 1275872 kb
Host smart-10edcd1b-1ed8-4ce8-964b-6700bd20f6ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80004046 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.80004046
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.3536933015
Short name T1508
Test name
Test status
Simulation time 528982496 ps
CPU time 2.9 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:25 PM PDT 24
Peak memory 214124 kb
Host smart-6c09b9fa-27d7-49cb-af98-19254691279f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536933015 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_nack_acqfull.3536933015
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.2880171437
Short name T1044
Test name
Test status
Simulation time 2594980540 ps
CPU time 2.6 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:18 PM PDT 24
Peak memory 205988 kb
Host smart-0607bd7f-06e7-4716-85c1-809e7e4ae4b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880171437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.2880171437
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_txstretch.3606112768
Short name T907
Test name
Test status
Simulation time 180612258 ps
CPU time 1.36 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:03:20 PM PDT 24
Peak memory 222444 kb
Host smart-7aee825d-cdc1-44bb-bad6-90ca0b16dbcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606112768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_nack_txstretch.3606112768
Directory /workspace/6.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/6.i2c_target_perf.1862198150
Short name T1445
Test name
Test status
Simulation time 1478311789 ps
CPU time 4.55 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:20 PM PDT 24
Peak memory 222368 kb
Host smart-98d7f137-6b1a-48cc-b060-fdbd1b7661c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862198150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.1862198150
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.377646658
Short name T1214
Test name
Test status
Simulation time 3130964135 ps
CPU time 1.99 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:03:10 PM PDT 24
Peak memory 205816 kb
Host smart-163c79da-b069-4474-80ea-5368f1a092ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377646658 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_smbus_maxlen.377646658
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2253535191
Short name T1526
Test name
Test status
Simulation time 808913357 ps
CPU time 25 seconds
Started Jul 28 05:03:13 PM PDT 24
Finished Jul 28 05:03:38 PM PDT 24
Peak memory 222228 kb
Host smart-b35d3379-edbf-4f30-95d3-fbfaf2a2a9d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253535191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2253535191
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.1283291795
Short name T431
Test name
Test status
Simulation time 19244890347 ps
CPU time 209.89 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:06:54 PM PDT 24
Peak memory 1568156 kb
Host smart-51b3ac83-e1ea-42d7-a62c-3fc8fe5a40c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283291795 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.1283291795
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3601983649
Short name T604
Test name
Test status
Simulation time 17344093827 ps
CPU time 17.45 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 230512 kb
Host smart-58f6d680-6663-4ed4-960a-8d34abeddc14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601983649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3601983649
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3226686213
Short name T342
Test name
Test status
Simulation time 7932936567 ps
CPU time 9.08 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:03:28 PM PDT 24
Peak memory 205968 kb
Host smart-03577caa-4b4a-41b0-ba7f-05ce9a14f476
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226686213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3226686213
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.4147888398
Short name T1368
Test name
Test status
Simulation time 707236872 ps
CPU time 23.65 seconds
Started Jul 28 05:03:31 PM PDT 24
Finished Jul 28 05:03:55 PM PDT 24
Peak memory 320832 kb
Host smart-a8f993e1-691d-42a7-b1a7-1522375a7cf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147888398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.4147888398
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.964421346
Short name T658
Test name
Test status
Simulation time 2297228632 ps
CPU time 7.45 seconds
Started Jul 28 05:03:14 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 220676 kb
Host smart-189dd7c4-75a2-40cf-b3c1-0a752feab937
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964421346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.964421346
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.4075205881
Short name T505
Test name
Test status
Simulation time 41852357 ps
CPU time 0.63 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 204968 kb
Host smart-c6d76fd9-242e-4e7e-ad94-ce0ee997f335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075205881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.4075205881
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1803240684
Short name T1374
Test name
Test status
Simulation time 296275399 ps
CPU time 5.81 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 231852 kb
Host smart-09efa40c-eddf-4e40-be30-0f6e84351510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803240684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1803240684
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3161045024
Short name T352
Test name
Test status
Simulation time 211691978 ps
CPU time 9.46 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:28 PM PDT 24
Peak memory 231188 kb
Host smart-396aa0a5-bc8d-4b78-848b-f190f0017a2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161045024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.3161045024
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3780330354
Short name T1622
Test name
Test status
Simulation time 45095843631 ps
CPU time 164.75 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 252348 kb
Host smart-a1456003-a46a-4cb2-93dc-ef59fe3cd615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780330354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3780330354
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3022719130
Short name T545
Test name
Test status
Simulation time 16332068533 ps
CPU time 60.43 seconds
Started Jul 28 05:03:14 PM PDT 24
Finished Jul 28 05:04:14 PM PDT 24
Peak memory 699472 kb
Host smart-570da446-d8f7-4327-b5c9-d3b474adb0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022719130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3022719130
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1391247613
Short name T419
Test name
Test status
Simulation time 137993618 ps
CPU time 0.85 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:02:57 PM PDT 24
Peak memory 205520 kb
Host smart-4d432941-869f-454a-b207-99af6e7e2aae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391247613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1391247613
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1336170957
Short name T44
Test name
Test status
Simulation time 606135855 ps
CPU time 3.3 seconds
Started Jul 28 05:03:20 PM PDT 24
Finished Jul 28 05:03:23 PM PDT 24
Peak memory 205732 kb
Host smart-49f83972-0c4a-4c41-8be0-d37b9a2b90d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336170957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1336170957
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3447631180
Short name T1651
Test name
Test status
Simulation time 16049191083 ps
CPU time 265.05 seconds
Started Jul 28 05:03:17 PM PDT 24
Finished Jul 28 05:07:42 PM PDT 24
Peak memory 1166596 kb
Host smart-41540530-f0a6-4e31-94ec-cd24e5e16a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447631180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3447631180
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_override.142696322
Short name T141
Test name
Test status
Simulation time 18404291 ps
CPU time 0.7 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:03:26 PM PDT 24
Peak memory 205372 kb
Host smart-3b8e57d3-71ce-4230-99e1-59d300345ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142696322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.142696322
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2414232126
Short name T578
Test name
Test status
Simulation time 12285198964 ps
CPU time 34.08 seconds
Started Jul 28 05:03:01 PM PDT 24
Finished Jul 28 05:03:36 PM PDT 24
Peak memory 213984 kb
Host smart-139d8e54-165c-4695-878f-d7aa684975c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414232126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2414232126
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.544501506
Short name T1138
Test name
Test status
Simulation time 357521833 ps
CPU time 8.46 seconds
Started Jul 28 05:03:06 PM PDT 24
Finished Jul 28 05:03:15 PM PDT 24
Peak memory 233632 kb
Host smart-3d55da34-8c19-4c9e-a30d-91c527605ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544501506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.544501506
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2951170302
Short name T697
Test name
Test status
Simulation time 4665382985 ps
CPU time 15.66 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:34 PM PDT 24
Peak memory 247892 kb
Host smart-27f01d80-97f6-4439-96af-064509f0df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951170302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2951170302
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2974338036
Short name T456
Test name
Test status
Simulation time 834967688 ps
CPU time 13.91 seconds
Started Jul 28 05:03:16 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 238308 kb
Host smart-626b4659-a4ac-4598-b050-949ccf2e058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974338036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2974338036
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1434098119
Short name T1597
Test name
Test status
Simulation time 852093321 ps
CPU time 4.32 seconds
Started Jul 28 05:03:11 PM PDT 24
Finished Jul 28 05:03:16 PM PDT 24
Peak memory 218780 kb
Host smart-36f30743-80a6-454f-b58e-2ad327056f2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434098119 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1434098119
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1643187408
Short name T552
Test name
Test status
Simulation time 907026255 ps
CPU time 0.92 seconds
Started Jul 28 05:03:10 PM PDT 24
Finished Jul 28 05:03:11 PM PDT 24
Peak memory 205816 kb
Host smart-a22473d0-dcaf-4138-aa34-8f4569d5d6d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643187408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1643187408
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2389240833
Short name T749
Test name
Test status
Simulation time 201894362 ps
CPU time 1.34 seconds
Started Jul 28 05:03:11 PM PDT 24
Finished Jul 28 05:03:13 PM PDT 24
Peak memory 205704 kb
Host smart-29325883-0e33-4a37-8a62-6b67f917f96e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389240833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2389240833
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.3431640753
Short name T166
Test name
Test status
Simulation time 1566856169 ps
CPU time 2.48 seconds
Started Jul 28 05:03:16 PM PDT 24
Finished Jul 28 05:03:19 PM PDT 24
Peak memory 205924 kb
Host smart-76f3f303-2f9a-4e3e-9843-dd1c817112e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431640753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.3431640753
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.3274499463
Short name T195
Test name
Test status
Simulation time 274794999 ps
CPU time 1.45 seconds
Started Jul 28 05:03:31 PM PDT 24
Finished Jul 28 05:03:33 PM PDT 24
Peak memory 205692 kb
Host smart-0b6afc1a-3405-4167-b47c-24c8e29332d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274499463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.3274499463
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.572140140
Short name T1186
Test name
Test status
Simulation time 1956417315 ps
CPU time 6.31 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 215036 kb
Host smart-82c33269-4d66-42ac-8ed8-3c94edac750a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572140140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_intr_smoke.572140140
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.142469394
Short name T839
Test name
Test status
Simulation time 17139492442 ps
CPU time 388.31 seconds
Started Jul 28 05:03:20 PM PDT 24
Finished Jul 28 05:09:48 PM PDT 24
Peak memory 4253344 kb
Host smart-22ede4d9-e237-4710-820e-2f3c68b7a55b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142469394 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.142469394
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.2852615736
Short name T1254
Test name
Test status
Simulation time 2069549573 ps
CPU time 2.83 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 214060 kb
Host smart-13d0fa89-8824-4fb0-81cc-fe4272394ef6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852615736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_acqfull.2852615736
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.723908182
Short name T757
Test name
Test status
Simulation time 2955608527 ps
CPU time 2.8 seconds
Started Jul 28 05:03:41 PM PDT 24
Finished Jul 28 05:03:44 PM PDT 24
Peak memory 206044 kb
Host smart-9a91f73a-710e-462d-8053-1f1dd903ff8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723908182 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.723908182
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.1339379590
Short name T1643
Test name
Test status
Simulation time 550662040 ps
CPU time 4.06 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 222172 kb
Host smart-45564859-c9c3-4953-9f9e-a1b189077bea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339379590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.1339379590
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.2559382254
Short name T762
Test name
Test status
Simulation time 3993840668 ps
CPU time 2.24 seconds
Started Jul 28 05:03:16 PM PDT 24
Finished Jul 28 05:03:18 PM PDT 24
Peak memory 205872 kb
Host smart-8cd0f703-c36a-439e-8c49-995e463dcd5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559382254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_smbus_maxlen.2559382254
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.158300249
Short name T1452
Test name
Test status
Simulation time 527962922 ps
CPU time 16.49 seconds
Started Jul 28 05:03:07 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 214132 kb
Host smart-886cdd0e-6569-4c0d-a33b-03b8a5b5de1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158300249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.158300249
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.2890344352
Short name T497
Test name
Test status
Simulation time 7367345377 ps
CPU time 42.64 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:04:01 PM PDT 24
Peak memory 279608 kb
Host smart-48b77521-2ad4-4323-8660-8032facafb17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890344352 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.2890344352
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3101881896
Short name T1708
Test name
Test status
Simulation time 6327403865 ps
CPU time 22.28 seconds
Started Jul 28 05:03:09 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 230688 kb
Host smart-2c8df45c-d425-4f0e-8c18-ff5f0dc87096
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101881896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3101881896
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.548527919
Short name T60
Test name
Test status
Simulation time 66699571026 ps
CPU time 342.91 seconds
Started Jul 28 05:03:16 PM PDT 24
Finished Jul 28 05:08:59 PM PDT 24
Peak memory 3019576 kb
Host smart-12ce9de7-ba1a-4941-a8fd-aef2b5c3935f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548527919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.548527919
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2001348699
Short name T1130
Test name
Test status
Simulation time 1261909320 ps
CPU time 5.95 seconds
Started Jul 28 05:03:00 PM PDT 24
Finished Jul 28 05:03:06 PM PDT 24
Peak memory 214372 kb
Host smart-49c450f6-7ab5-481c-8fec-9e1510fd7308
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001348699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2001348699
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.1720662560
Short name T927
Test name
Test status
Simulation time 64812909 ps
CPU time 1.43 seconds
Started Jul 28 05:03:21 PM PDT 24
Finished Jul 28 05:03:23 PM PDT 24
Peak memory 205788 kb
Host smart-3ef8cd27-31f2-4a4a-abf2-e48949d482ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720662560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.1720662560
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.89091583
Short name T1399
Test name
Test status
Simulation time 16369760 ps
CPU time 0.62 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 204832 kb
Host smart-099263af-50bc-43c6-93a6-be81ee0dd6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89091583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.89091583
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2037550694
Short name T1516
Test name
Test status
Simulation time 237610314 ps
CPU time 3.6 seconds
Started Jul 28 05:03:16 PM PDT 24
Finished Jul 28 05:03:20 PM PDT 24
Peak memory 213952 kb
Host smart-584f4aed-1e88-44c8-b4d5-df9ea70378e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037550694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2037550694
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2745670560
Short name T602
Test name
Test status
Simulation time 4460768550 ps
CPU time 9.2 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:31 PM PDT 24
Peak memory 297668 kb
Host smart-3f7f6940-c807-47f1-8990-bec1ce8d4e26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745670560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2745670560
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1627667476
Short name T1407
Test name
Test status
Simulation time 1818064188 ps
CPU time 43.74 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:04:01 PM PDT 24
Peak memory 316220 kb
Host smart-6331672e-edc9-40b5-96ef-b043a879777e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627667476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1627667476
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3782030493
Short name T475
Test name
Test status
Simulation time 2847259369 ps
CPU time 104.41 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:05:09 PM PDT 24
Peak memory 880096 kb
Host smart-50a41af3-4bf8-42fe-a683-633e04f00213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782030493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3782030493
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1347930963
Short name T1309
Test name
Test status
Simulation time 173340378 ps
CPU time 1.15 seconds
Started Jul 28 05:03:08 PM PDT 24
Finished Jul 28 05:03:09 PM PDT 24
Peak memory 205404 kb
Host smart-be4d4888-393d-483b-8f47-9f0399cd2cf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347930963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1347930963
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1833183800
Short name T577
Test name
Test status
Simulation time 519850314 ps
CPU time 3.62 seconds
Started Jul 28 05:03:10 PM PDT 24
Finished Jul 28 05:03:14 PM PDT 24
Peak memory 225676 kb
Host smart-f99adc2a-54e5-411e-bde1-bdbf52f85ee2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833183800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1833183800
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3573807858
Short name T328
Test name
Test status
Simulation time 9587047861 ps
CPU time 114.89 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:05:18 PM PDT 24
Peak memory 1188084 kb
Host smart-0e128aef-354c-43b6-8146-d84db84c6ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573807858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3573807858
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1565641698
Short name T1642
Test name
Test status
Simulation time 1867329823 ps
CPU time 9.86 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 205660 kb
Host smart-952012c2-1af4-4188-82ae-c1846fa10cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565641698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1565641698
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_override.1160853096
Short name T836
Test name
Test status
Simulation time 16331877 ps
CPU time 0.64 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:22 PM PDT 24
Peak memory 205452 kb
Host smart-0c2c3788-1406-4058-ab2f-5f22860c0d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160853096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1160853096
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.3795286849
Short name T308
Test name
Test status
Simulation time 5074387235 ps
CPU time 11.04 seconds
Started Jul 28 05:03:17 PM PDT 24
Finished Jul 28 05:03:29 PM PDT 24
Peak memory 216012 kb
Host smart-03e68c14-f4b2-4c96-9c9e-29b7e75905f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795286849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.3795286849
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.2703092426
Short name T485
Test name
Test status
Simulation time 74889148 ps
CPU time 1.74 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 213852 kb
Host smart-e991fca3-fdf6-482b-ac8d-754094176f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703092426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.2703092426
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.952378093
Short name T646
Test name
Test status
Simulation time 1502051394 ps
CPU time 69.4 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:04:29 PM PDT 24
Peak memory 359476 kb
Host smart-01c4f0f2-8c6d-44ad-b75c-6794f86f8a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952378093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.952378093
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2677772718
Short name T1260
Test name
Test status
Simulation time 19815047616 ps
CPU time 1853.48 seconds
Started Jul 28 05:03:11 PM PDT 24
Finished Jul 28 05:34:05 PM PDT 24
Peak memory 3539748 kb
Host smart-1dd245a7-cdd8-4ab5-a5be-0e7ceb9c52c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677772718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2677772718
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.753922548
Short name T1548
Test name
Test status
Simulation time 497355575 ps
CPU time 8.49 seconds
Started Jul 28 05:03:15 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 213964 kb
Host smart-d4cef634-b1b3-4251-b45e-24d26a60302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753922548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.753922548
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2791109019
Short name T992
Test name
Test status
Simulation time 1384424551 ps
CPU time 7.35 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:36 PM PDT 24
Peak memory 222508 kb
Host smart-ab2ff0cc-5659-4efe-bd8a-de5644ae9609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791109019 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2791109019
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.4277479011
Short name T1267
Test name
Test status
Simulation time 251275548 ps
CPU time 1.44 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 205864 kb
Host smart-63a33492-7747-491e-ac01-e85955768c7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277479011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.4277479011
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3227292264
Short name T331
Test name
Test status
Simulation time 510968086 ps
CPU time 0.98 seconds
Started Jul 28 05:03:23 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 205676 kb
Host smart-d8749c69-eea1-4bb2-8c80-65a0576695ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227292264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3227292264
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.3170559243
Short name T556
Test name
Test status
Simulation time 289870860 ps
CPU time 1.75 seconds
Started Jul 28 05:03:26 PM PDT 24
Finished Jul 28 05:03:28 PM PDT 24
Peak memory 205696 kb
Host smart-eb4c531e-baf7-4ab2-b743-b26edabae092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170559243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.3170559243
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.655724900
Short name T1109
Test name
Test status
Simulation time 259672631 ps
CPU time 1.37 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:03:27 PM PDT 24
Peak memory 205736 kb
Host smart-6b0eb29b-2bb4-4921-9057-957b5d05b5b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655724900 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.655724900
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1016345725
Short name T1063
Test name
Test status
Simulation time 566144371 ps
CPU time 2.01 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 215004 kb
Host smart-ef045cc4-14b7-48fe-b8b5-83df4bde9e47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016345725 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1016345725
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3840802564
Short name T574
Test name
Test status
Simulation time 8725330565 ps
CPU time 5.44 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 220792 kb
Host smart-7e2a98c0-9437-4ef1-9f76-a719e3ad52de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840802564 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3840802564
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3096736468
Short name T1646
Test name
Test status
Simulation time 15032894477 ps
CPU time 175.36 seconds
Started Jul 28 05:03:37 PM PDT 24
Finished Jul 28 05:06:33 PM PDT 24
Peak memory 2206760 kb
Host smart-44420644-2ceb-4c68-9ae2-80d354103587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096736468 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3096736468
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.2332231383
Short name T68
Test name
Test status
Simulation time 2159976843 ps
CPU time 3.19 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 214228 kb
Host smart-d903f2c5-2536-4ce5-be3f-c59ad5664e62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332231383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.2332231383
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.959741258
Short name T1633
Test name
Test status
Simulation time 1769643535 ps
CPU time 2.6 seconds
Started Jul 28 05:03:34 PM PDT 24
Finished Jul 28 05:03:37 PM PDT 24
Peak memory 205368 kb
Host smart-10ebe6a5-025a-46ad-bc68-8f62a5221d5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959741258 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.959741258
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_txstretch.42193381
Short name T51
Test name
Test status
Simulation time 1266884733 ps
CPU time 1.42 seconds
Started Jul 28 05:03:12 PM PDT 24
Finished Jul 28 05:03:13 PM PDT 24
Peak memory 222616 kb
Host smart-28375bc3-e4ca-40fd-ae62-ff4039dd1bbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42193381 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_txstretch.42193381
Directory /workspace/8.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/8.i2c_target_perf.514761247
Short name T455
Test name
Test status
Simulation time 697554216 ps
CPU time 4.84 seconds
Started Jul 28 05:03:21 PM PDT 24
Finished Jul 28 05:03:26 PM PDT 24
Peak memory 218824 kb
Host smart-ba5762ab-d577-42c4-8c2a-ffcb6d4fbf43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514761247 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_perf.514761247
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.4200033050
Short name T980
Test name
Test status
Simulation time 877091032 ps
CPU time 2.12 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 205772 kb
Host smart-076d3315-91cb-4054-968f-4dc54372dcb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200033050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.4200033050
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2279563413
Short name T1754
Test name
Test status
Simulation time 1007021225 ps
CPU time 31.79 seconds
Started Jul 28 05:03:10 PM PDT 24
Finished Jul 28 05:03:42 PM PDT 24
Peak memory 222352 kb
Host smart-2e7b0f70-2bc0-457a-b409-ae8f2c452f8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279563413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2279563413
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.830661776
Short name T736
Test name
Test status
Simulation time 29659360019 ps
CPU time 258.42 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:07:36 PM PDT 24
Peak memory 1661116 kb
Host smart-8e26add9-e58f-41ab-93bb-938939c8d23c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830661776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.i2c_target_stress_all.830661776
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2243213429
Short name T773
Test name
Test status
Simulation time 1492203608 ps
CPU time 66.73 seconds
Started Jul 28 05:03:33 PM PDT 24
Finished Jul 28 05:04:40 PM PDT 24
Peak memory 215780 kb
Host smart-21b4dc89-8613-4ffc-a8a6-a5496a1bf564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243213429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2243213429
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.2848890202
Short name T305
Test name
Test status
Simulation time 15656362166 ps
CPU time 15 seconds
Started Jul 28 05:03:49 PM PDT 24
Finished Jul 28 05:04:04 PM PDT 24
Peak memory 206048 kb
Host smart-ee93cfa6-e459-43e0-b900-467565b00c0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848890202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.2848890202
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2588042233
Short name T1344
Test name
Test status
Simulation time 2950897498 ps
CPU time 39.19 seconds
Started Jul 28 05:03:12 PM PDT 24
Finished Jul 28 05:03:51 PM PDT 24
Peak memory 406296 kb
Host smart-7e15d178-8cf4-4e05-b193-55bc44e26d60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588042233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2588042233
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3602239971
Short name T1734
Test name
Test status
Simulation time 1454171517 ps
CPU time 7.32 seconds
Started Jul 28 05:03:21 PM PDT 24
Finished Jul 28 05:03:29 PM PDT 24
Peak memory 222304 kb
Host smart-79fc0320-9a84-4b42-b712-b056c1506144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602239971 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3602239971
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.1918969477
Short name T1389
Test name
Test status
Simulation time 604734851 ps
CPU time 8.18 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:37 PM PDT 24
Peak memory 206452 kb
Host smart-b3deb07c-c4f0-479f-aae8-ba6f8e6abc93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918969477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.1918969477
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1708911619
Short name T369
Test name
Test status
Simulation time 36882240 ps
CPU time 0.64 seconds
Started Jul 28 05:03:35 PM PDT 24
Finished Jul 28 05:03:36 PM PDT 24
Peak memory 204916 kb
Host smart-f6607834-ef3b-41ba-93d6-5bacff7072c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708911619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1708911619
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1228823712
Short name T544
Test name
Test status
Simulation time 105130210 ps
CPU time 1.88 seconds
Started Jul 28 05:03:12 PM PDT 24
Finished Jul 28 05:03:14 PM PDT 24
Peak memory 214096 kb
Host smart-c0aa12bf-0378-443d-a2e0-8e140a6d9dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228823712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1228823712
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1409341644
Short name T1602
Test name
Test status
Simulation time 365062351 ps
CPU time 18.51 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:03:38 PM PDT 24
Peak memory 286056 kb
Host smart-d1ddc331-0b3b-48d9-81a6-7c7bfb367048
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409341644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1409341644
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3111194790
Short name T1704
Test name
Test status
Simulation time 9437753772 ps
CPU time 56.24 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:04:14 PM PDT 24
Peak memory 380720 kb
Host smart-d211c63f-6b70-4516-81e0-1f589c51cdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111194790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3111194790
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.25374661
Short name T1324
Test name
Test status
Simulation time 2220195455 ps
CPU time 158.52 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:06:08 PM PDT 24
Peak memory 737828 kb
Host smart-2c70c680-0e5a-49be-ab50-6e1dfecc82bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25374661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.25374661
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2816338424
Short name T1463
Test name
Test status
Simulation time 135495169 ps
CPU time 1.11 seconds
Started Jul 28 05:03:20 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 205492 kb
Host smart-7aff6bd8-bd23-4617-a484-c1d7d902b064
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816338424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2816338424
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2060258502
Short name T1547
Test name
Test status
Simulation time 864082590 ps
CPU time 8.3 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 231304 kb
Host smart-3541245e-aadd-4da2-89a8-16511157fc18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060258502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2060258502
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2216542871
Short name T1029
Test name
Test status
Simulation time 6852708578 ps
CPU time 92.95 seconds
Started Jul 28 05:03:20 PM PDT 24
Finished Jul 28 05:04:53 PM PDT 24
Peak memory 1025252 kb
Host smart-42ae758c-0f56-4ad3-b813-a6ff141d9212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216542871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2216542871
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1018128846
Short name T1387
Test name
Test status
Simulation time 2081421083 ps
CPU time 7.59 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:03:33 PM PDT 24
Peak memory 205748 kb
Host smart-93a1153d-5a0a-4ca1-9518-f73fba596e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018128846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1018128846
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.3367700691
Short name T91
Test name
Test status
Simulation time 17488033 ps
CPU time 0.65 seconds
Started Jul 28 05:03:27 PM PDT 24
Finished Jul 28 05:03:28 PM PDT 24
Peak memory 205468 kb
Host smart-256ab1b7-4ecd-40a5-a392-89ed19be61df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367700691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3367700691
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2744796698
Short name T1153
Test name
Test status
Simulation time 7267152037 ps
CPU time 142.47 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:05:47 PM PDT 24
Peak memory 1007296 kb
Host smart-7df3d28d-a4f7-4dd4-a597-6e7d00eec657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744796698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2744796698
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.472860200
Short name T1471
Test name
Test status
Simulation time 315987452 ps
CPU time 7.27 seconds
Started Jul 28 05:03:42 PM PDT 24
Finished Jul 28 05:03:50 PM PDT 24
Peak memory 214512 kb
Host smart-5b8c25ec-617e-4c2e-bed5-87a2f03e1781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472860200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.472860200
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.787320714
Short name T1075
Test name
Test status
Simulation time 8391525265 ps
CPU time 94.74 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:05:03 PM PDT 24
Peak memory 384832 kb
Host smart-a994c69d-3831-41e3-9d29-34ee3bad117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787320714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.787320714
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.1106535094
Short name T666
Test name
Test status
Simulation time 3660479725 ps
CPU time 13.13 seconds
Started Jul 28 05:03:30 PM PDT 24
Finished Jul 28 05:03:44 PM PDT 24
Peak memory 222300 kb
Host smart-443611c4-c4a7-4902-9263-f383fb298513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106535094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1106535094
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2293698758
Short name T1305
Test name
Test status
Simulation time 3461303375 ps
CPU time 5.04 seconds
Started Jul 28 05:03:21 PM PDT 24
Finished Jul 28 05:03:26 PM PDT 24
Peak memory 219032 kb
Host smart-f682ca22-08c4-433b-befa-1510a0d80207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293698758 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2293698758
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.661849363
Short name T558
Test name
Test status
Simulation time 400817101 ps
CPU time 1.37 seconds
Started Jul 28 05:03:26 PM PDT 24
Finished Jul 28 05:03:27 PM PDT 24
Peak memory 213996 kb
Host smart-26c84cdf-14a0-4c57-8168-3febb02067ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661849363 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.661849363
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2227272362
Short name T1124
Test name
Test status
Simulation time 185276860 ps
CPU time 1.24 seconds
Started Jul 28 05:03:27 PM PDT 24
Finished Jul 28 05:03:29 PM PDT 24
Peak memory 214132 kb
Host smart-8c5ffc02-ca00-4700-b0dc-2232e07891a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227272362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2227272362
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.2273794189
Short name T843
Test name
Test status
Simulation time 2369767651 ps
CPU time 3.26 seconds
Started Jul 28 05:03:18 PM PDT 24
Finished Jul 28 05:03:21 PM PDT 24
Peak memory 205964 kb
Host smart-620bcd05-8b75-4c7c-a591-b3c5fcdf2b8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273794189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.2273794189
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.2873268103
Short name T855
Test name
Test status
Simulation time 746379161 ps
CPU time 1.55 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:30 PM PDT 24
Peak memory 205656 kb
Host smart-3769ed7d-8d8f-4acc-a297-562a2e81d9c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873268103 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.2873268103
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2553561515
Short name T315
Test name
Test status
Simulation time 867416632 ps
CPU time 4.47 seconds
Started Jul 28 05:03:34 PM PDT 24
Finished Jul 28 05:03:38 PM PDT 24
Peak memory 217036 kb
Host smart-23c24031-c933-45bc-a68d-07515b515311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553561515 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2553561515
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.179299392
Short name T949
Test name
Test status
Simulation time 7396282925 ps
CPU time 9.94 seconds
Started Jul 28 05:03:35 PM PDT 24
Finished Jul 28 05:03:45 PM PDT 24
Peak memory 450080 kb
Host smart-bfacc152-3cd0-45cf-b564-5201e3b5ad33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179299392 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.179299392
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.1365415152
Short name T1489
Test name
Test status
Simulation time 2461326267 ps
CPU time 2.62 seconds
Started Jul 28 05:03:22 PM PDT 24
Finished Jul 28 05:03:24 PM PDT 24
Peak memory 214164 kb
Host smart-fefee1a3-54fb-4ee8-8efc-9602ab59c8a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365415152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.1365415152
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.1115684207
Short name T1041
Test name
Test status
Simulation time 560628103 ps
CPU time 2.92 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 205928 kb
Host smart-5c7ae1d0-f7fb-45d4-b83b-e13b28ffa39d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115684207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.1115684207
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.3022230546
Short name T517
Test name
Test status
Simulation time 1383080006 ps
CPU time 2.69 seconds
Started Jul 28 05:03:37 PM PDT 24
Finished Jul 28 05:03:40 PM PDT 24
Peak memory 221372 kb
Host smart-2f747914-e9b9-4a77-b888-7525bf0a23fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022230546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.3022230546
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.1706674588
Short name T1132
Test name
Test status
Simulation time 492506702 ps
CPU time 2.33 seconds
Started Jul 28 05:03:28 PM PDT 24
Finished Jul 28 05:03:31 PM PDT 24
Peak memory 205668 kb
Host smart-70f0bd8b-4d64-4640-8036-dba465be38ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706674588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_smbus_maxlen.1706674588
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1430364301
Short name T357
Test name
Test status
Simulation time 1797171709 ps
CPU time 13.05 seconds
Started Jul 28 05:03:19 PM PDT 24
Finished Jul 28 05:03:32 PM PDT 24
Peak memory 214124 kb
Host smart-5d513fe9-d03b-44b2-8f3e-349909e9df2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430364301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1430364301
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.776408155
Short name T981
Test name
Test status
Simulation time 31762061968 ps
CPU time 1058.95 seconds
Started Jul 28 05:03:30 PM PDT 24
Finished Jul 28 05:21:09 PM PDT 24
Peak memory 5305420 kb
Host smart-fbcb89d4-af15-45ad-8034-d8e620ede433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776408155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_target_stress_all.776408155
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.4046808729
Short name T1247
Test name
Test status
Simulation time 5555903206 ps
CPU time 20.88 seconds
Started Jul 28 05:03:24 PM PDT 24
Finished Jul 28 05:03:45 PM PDT 24
Peak memory 236944 kb
Host smart-8dcbb95b-b99d-4f98-8347-91df5728b9bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046808729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.4046808729
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2614474701
Short name T1352
Test name
Test status
Simulation time 38338479267 ps
CPU time 187.53 seconds
Started Jul 28 05:03:29 PM PDT 24
Finished Jul 28 05:06:37 PM PDT 24
Peak memory 2312812 kb
Host smart-62d5d71a-7c00-44c2-9846-eb29273d5d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614474701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2614474701
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2484224781
Short name T1220
Test name
Test status
Simulation time 2782343947 ps
CPU time 3.46 seconds
Started Jul 28 05:03:30 PM PDT 24
Finished Jul 28 05:03:34 PM PDT 24
Peak memory 222200 kb
Host smart-68f912e2-d7cd-4c58-8df2-8b4945d8ea82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484224781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2484224781
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2364244946
Short name T134
Test name
Test status
Simulation time 1168207651 ps
CPU time 6.85 seconds
Started Jul 28 05:03:20 PM PDT 24
Finished Jul 28 05:03:27 PM PDT 24
Peak memory 230704 kb
Host smart-85e3f405-68be-4148-8e13-8070bc902293
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364244946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2364244946
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.2796181760
Short name T1090
Test name
Test status
Simulation time 188177219 ps
CPU time 3.33 seconds
Started Jul 28 05:03:25 PM PDT 24
Finished Jul 28 05:03:28 PM PDT 24
Peak memory 205836 kb
Host smart-90b866f7-9a1c-4899-a2a8-76a83b4d40c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796181760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2796181760
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%