Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	703587	1			T1	2		T2	2		T3	2
all_values[1]	703587	1			T1	2		T2	2		T3	2
all_values[2]	703587	1			T1	2		T2	2		T3	2
all_values[3]	703587	1			T1	2		T2	2		T3	2
all_values[4]	703587	1			T1	2		T2	2		T3	2
all_values[5]	703587	1			T1	2		T2	2		T3	2
all_values[6]	703587	1			T1	2		T2	2		T3	2
all_values[7]	703587	1			T1	2		T2	2		T3	2
all_values[8]	703587	1			T1	2		T2	2		T3	2
all_values[9]	703587	1			T1	2		T2	2		T3	2
all_values[10]	703587	1			T1	2		T2	2		T3	2
all_values[11]	703587	1			T1	2		T2	2		T3	2
all_values[12]	703587	1			T1	2		T2	2		T3	2
all_values[13]	703587	1			T1	2		T2	2		T3	2
all_values[14]	703587	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8732958

1

T1

26

T2

26

T3

26

auto[1]

1820847

1

T1

4

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10206245

1

T1

30

T2

30

T3

30

auto[1]

347560

1

T37

69

T172

2195

T173

20007

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	111166	1			T5	1		T6	11		T14	1
all_values[0]	auto[0]	auto[1]	4014	1			T37	5		T172	31		T173	512
all_values[0]	auto[1]	auto[0]	568084	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	20323	1			T37	1		T172	126		T173	621
all_values[1]	auto[0]	auto[0]	678851	1			T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	24396	1			T37	4		T172	154		T173	1340
all_values[1]	auto[1]	auto[0]	187	1			T31	17		T256	2		T257	1
all_values[1]	auto[1]	auto[1]	153	1			T37	2		T172	4		T173	7
all_values[2]	auto[0]	auto[0]	678845	1			T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	24414	1			T172	153		T173	1344		T174	7419
all_values[2]	auto[1]	auto[0]	193	1			T148	1		T55	1		T56	1
all_values[2]	auto[1]	auto[1]	135	1			T172	5		T173	3		T174	7
all_values[3]	auto[0]	auto[0]	679032	1			T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	24383	1			T37	2		T172	150		T173	1340
all_values[3]	auto[1]	auto[1]	172	1			T37	4		T172	8		T173	8
all_values[4]	auto[0]	auto[0]	679026	1			T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	24385	1			T37	3		T172	153		T173	1346
all_values[4]	auto[1]	auto[0]	18	1			T22	1		T223	1		T251	1
all_values[4]	auto[1]	auto[1]	158	1			T37	3		T172	5		T173	3
all_values[5]	auto[0]	auto[0]	679033	1			T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	24361	1			T172	150		T173	1338		T174	7416
all_values[5]	auto[1]	auto[1]	193	1			T172	6		T173	9		T174	10
all_values[6]	auto[0]	auto[0]	679058	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	24373	1			T37	4		T172	151		T173	1346
all_values[6]	auto[1]	auto[1]	156	1			T37	1		T172	5		T173	3
all_values[7]	auto[0]	auto[0]	652432	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	22912	1			T37	4		T172	134		T173	1174
all_values[7]	auto[1]	auto[0]	26621	1			T5	1		T14	1		T42	1
all_values[7]	auto[1]	auto[1]	1622	1			T37	2		T172	19		T173	173
all_values[8]	auto[0]	auto[0]	679059	1			T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	24382	1			T37	2		T172	154		T173	1343
all_values[8]	auto[1]	auto[1]	146	1			T37	2		T172	3		T173	6
all_values[9]	auto[0]	auto[0]	198358	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	4236	1			T37	3		T172	140		T173	1288
all_values[9]	auto[1]	auto[0]	487422	1			T5	1		T14	1		T42	1
all_values[9]	auto[1]	auto[1]	13571	1			T37	3		T172	18		T173	61
all_values[10]	auto[0]	auto[0]	685764	1			T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	17677	1			T37	4		T172	155		T173	1345
all_values[10]	auto[1]	auto[1]	146	1			T37	1		T172	3		T173	4
all_values[11]	auto[0]	auto[0]	2312	1			T5	1		T6	11		T14	1
all_values[11]	auto[0]	auto[1]	265	1			T37	3		T172	27		T173	22
all_values[11]	auto[1]	auto[0]	676746	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	24264	1			T37	2		T172	126		T173	1327
all_values[12]	auto[0]	auto[0]	678994	1			T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	24399	1			T37	3		T172	154		T173	1343
all_values[12]	auto[1]	auto[0]	61	1			T55	1		T56	1		T258	1
all_values[12]	auto[1]	auto[1]	133	1			T37	1		T172	4		T173	6
all_values[13]	auto[0]	auto[0]	685783	1			T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	17629	1			T37	2		T172	154		T173	1342
all_values[13]	auto[1]	auto[1]	175	1			T37	3		T172	3		T173	5
all_values[14]	auto[0]	auto[0]	679200	1			T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	24219	1			T37	2		T173	1341		T174	7423
all_values[14]	auto[1]	auto[1]	168	1			T37	3		T173	7		T174	3