Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	703587	1			T1	2		T2	2		T3	2
all_pins[1]	703587	1			T1	2		T2	2		T3	2
all_pins[2]	703587	1			T1	2		T2	2		T3	2
all_pins[3]	703587	1			T1	2		T2	2		T3	2
all_pins[4]	703587	1			T1	2		T2	2		T3	2
all_pins[5]	703587	1			T1	2		T2	2		T3	2
all_pins[6]	703587	1			T1	2		T2	2		T3	2
all_pins[7]	703587	1			T1	2		T2	2		T3	2
all_pins[8]	703587	1			T1	2		T2	2		T3	2
all_pins[9]	703587	1			T1	2		T2	2		T3	2
all_pins[10]	703587	1			T1	2		T2	2		T3	2
all_pins[11]	703587	1			T1	2		T2	2		T3	2
all_pins[12]	703587	1			T1	2		T2	2		T3	2
all_pins[13]	703587	1			T1	2		T2	2		T3	2
all_pins[14]	703587	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8738911	1			T1	26		T2	26		T3	26
values[0x1]	1814894	1			T1	4		T2	4		T3	4
transitions[0x0=>0x1]	1814367	1			T1	4		T2	4		T3	4
transitions[0x1=>0x0]	1813056	1			T1	3		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	118396	1			T5	1		T6	11		T14	1
all_pins[0]	values[0x1]	585191	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	584928	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	53	1			T37	1		T172	1		T173	1
all_pins[1]	values[0x0]	703271	1			T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	316	1			T31	21		T256	2		T257	1
all_pins[1]	transitions[0x0=>0x1]	295	1			T31	21		T256	2		T257	1
all_pins[1]	transitions[0x1=>0x0]	101	1			T148	1		T258	1		T158	1
all_pins[2]	values[0x0]	703465	1			T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	122	1			T148	1		T258	1		T158	1
all_pins[2]	transitions[0x0=>0x1]	100	1			T148	1		T258	1		T158	1
all_pins[2]	transitions[0x1=>0x0]	61	1			T37	1		T172	1		T173	2
all_pins[3]	values[0x0]	703504	1			T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	83	1			T37	1		T172	4		T173	3
all_pins[3]	transitions[0x0=>0x1]	68	1			T172	2		T173	3		T174	1
all_pins[3]	transitions[0x1=>0x0]	86	1			T22	2		T223	1		T251	2
all_pins[4]	values[0x0]	703486	1			T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	101	1			T22	2		T223	1		T251	2
all_pins[4]	transitions[0x0=>0x1]	83	1			T22	2		T223	1		T251	2
all_pins[4]	transitions[0x1=>0x0]	75	1			T172	2		T173	6		T174	2
all_pins[5]	values[0x0]	703494	1			T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	93	1			T172	2		T173	6		T174	3
all_pins[5]	transitions[0x0=>0x1]	71	1			T173	6		T174	3		T114	1
all_pins[5]	transitions[0x1=>0x0]	59	1			T37	1		T172	2		T173	3
all_pins[6]	values[0x0]	703506	1			T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	81	1			T37	1		T172	4		T173	3
all_pins[6]	transitions[0x0=>0x1]	65	1			T37	1		T172	4		T173	3
all_pins[6]	transitions[0x1=>0x0]	30177	1			T5	1		T14	1		T42	1
all_pins[7]	values[0x0]	673394	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	30193	1			T5	1		T14	1		T42	1
all_pins[7]	transitions[0x0=>0x1]	30178	1			T5	1		T14	1		T42	1
all_pins[7]	transitions[0x1=>0x0]	57	1			T172	2		T173	1		T174	2
all_pins[8]	values[0x0]	703515	1			T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	72	1			T37	2		T172	2		T173	2
all_pins[8]	transitions[0x0=>0x1]	51	1			T172	2		T173	1		T174	2
all_pins[8]	transitions[0x1=>0x0]	500905	1			T5	1		T14	1		T42	1
all_pins[9]	values[0x0]	202661	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	500926	1			T5	1		T14	1		T42	1
all_pins[9]	transitions[0x0=>0x1]	500916	1			T5	1		T14	1		T42	1
all_pins[9]	transitions[0x1=>0x0]	54	1			T172	1		T173	2		T174	3
all_pins[10]	values[0x0]	703523	1			T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	64	1			T37	1		T172	1		T173	3
all_pins[10]	transitions[0x0=>0x1]	48	1			T172	1		T173	2		T174	2
all_pins[10]	transitions[0x1=>0x0]	697328	1			T1	2		T2	2		T3	2
all_pins[11]	values[0x0]	6243	1			T5	1		T6	11		T14	1
all_pins[11]	values[0x1]	697344	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	697317	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	108	1			T55	1		T56	1		T57	1
all_pins[12]	values[0x0]	703452	1			T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	135	1			T55	1		T56	1		T258	1
all_pins[12]	transitions[0x0=>0x1]	118	1			T55	1		T56	1		T258	1
all_pins[12]	transitions[0x1=>0x0]	67	1			T37	2		T173	2		T174	3
all_pins[13]	values[0x0]	703503	1			T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	84	1			T37	3		T173	3		T174	4
all_pins[13]	transitions[0x0=>0x1]	65	1			T37	1		T173	3		T174	4
all_pins[13]	transitions[0x1=>0x0]	70	1			T173	4		T174	1		T114	5
all_pins[14]	values[0x0]	703498	1			T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	89	1			T37	2		T173	4		T174	1
all_pins[14]	transitions[0x0=>0x1]	64	1			T37	2		T173	4		T114	3
all_pins[14]	transitions[0x1=>0x0]	583855	1			T1	1		T2	1		T3	1