Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	348	1			T37	4		T172	8		T173	11
all_values[1]	348	1			T37	4		T172	8		T173	11
all_values[2]	348	1			T37	4		T172	8		T173	11
all_values[3]	348	1			T37	4		T172	8		T173	11
all_values[4]	348	1			T37	4		T172	8		T173	11
all_values[5]	348	1			T37	4		T172	8		T173	11
all_values[6]	348	1			T37	4		T172	8		T173	11
all_values[7]	348	1			T37	4		T172	8		T173	11
all_values[8]	348	1			T37	4		T172	8		T173	11
all_values[9]	348	1			T37	4		T172	8		T173	11
all_values[10]	348	1			T37	4		T172	8		T173	11
all_values[11]	348	1			T37	4		T172	8		T173	11
all_values[12]	348	1			T37	4		T172	8		T173	11
all_values[13]	348	1			T37	4		T172	8		T173	11
all_values[14]	348	1			T37	4		T172	8		T173	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2789

1

T37

29

T172

62

T173

93

auto[1]

2431

1

T37

31

T172

58

T173

72

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

869

1

T37

17

T172

23

T173

16

auto[1]

4351

1

T37

43

T172

97

T173

149

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3050

1

T37

37

T172

73

T173

101

auto[1]

2170

1

T37

23

T172

47

T173

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T173	4		T174	2		T261	3
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T172	1		T173	3		T174	3
all_values[0]	auto[0]	auto[1]	auto[0]	22	1			T172	1		T109	1		T261	2
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T37	3		T172	3		T173	1
all_values[0]	auto[1]	auto[0]	auto[1]	80	1			T37	1		T173	1		T174	1
all_values[0]	auto[1]	auto[1]	auto[1]	67	1			T172	3		T173	2		T174	4
all_values[1]	auto[0]	auto[0]	auto[0]	32	1			T173	2		T109	1		T262	1
all_values[1]	auto[0]	auto[0]	auto[1]	72	1			T172	3		T173	3		T174	3
all_values[1]	auto[0]	auto[1]	auto[0]	23	1			T109	1		T261	1		T263	1
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T37	2		T172	1		T174	4
all_values[1]	auto[1]	auto[0]	auto[1]	76	1			T37	1		T172	2		T173	5
all_values[1]	auto[1]	auto[1]	auto[1]	71	1			T37	1		T172	2		T173	1
all_values[2]	auto[0]	auto[0]	auto[0]	30	1			T37	4		T173	1		T264	1
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T172	2		T174	6		T114	11
all_values[2]	auto[0]	auto[1]	auto[0]	22	1			T173	1		T109	2		T114	1
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T172	1		T173	6		T174	1
all_values[2]	auto[1]	auto[0]	auto[1]	63	1			T172	1		T173	1		T174	3
all_values[2]	auto[1]	auto[1]	auto[1]	72	1			T172	4		T173	2		T174	4
all_values[3]	auto[0]	auto[0]	auto[0]	28	1			T173	1		T265	3		T262	1
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T37	1		T172	3		T173	4
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T174	4		T114	1		T266	1
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T172	2		T173	2		T109	2
all_values[3]	auto[1]	auto[0]	auto[1]	83	1			T37	3		T172	2		T173	3
all_values[3]	auto[1]	auto[1]	auto[1]	70	1			T172	1		T173	1		T174	2
all_values[4]	auto[0]	auto[0]	auto[0]	18	1			T265	1		T263	1		T264	1
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T37	1		T173	6		T174	5
all_values[4]	auto[0]	auto[1]	auto[0]	30	1			T114	2		T25	4		T263	2
all_values[4]	auto[0]	auto[1]	auto[1]	71	1			T172	3		T173	2		T174	2
all_values[4]	auto[1]	auto[0]	auto[1]	89	1			T37	2		T172	2		T173	3
all_values[4]	auto[1]	auto[1]	auto[1]	69	1			T37	1		T172	3		T174	5
all_values[5]	auto[0]	auto[0]	auto[0]	32	1			T37	2		T172	2		T173	1
all_values[5]	auto[0]	auto[0]	auto[1]	85	1			T172	2		T173	2		T174	6
all_values[5]	auto[0]	auto[1]	auto[0]	18	1			T37	2		T173	1		T114	2
all_values[5]	auto[0]	auto[1]	auto[1]	60	1			T172	1		T173	4		T114	3
all_values[5]	auto[1]	auto[0]	auto[1]	83	1			T172	2		T173	2		T174	6
all_values[5]	auto[1]	auto[1]	auto[1]	70	1			T172	1		T173	1		T174	2
all_values[6]	auto[0]	auto[0]	auto[0]	42	1			T37	1		T172	1		T114	5
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T37	2		T172	1		T173	6
all_values[6]	auto[0]	auto[1]	auto[0]	30	1			T172	1		T114	1		T261	1
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T172	2		T173	3		T174	4
all_values[6]	auto[1]	auto[0]	auto[1]	60	1			T172	1		T173	1		T174	6
all_values[6]	auto[1]	auto[1]	auto[1]	76	1			T37	1		T172	2		T173	1
all_values[7]	auto[0]	auto[0]	auto[0]	32	1			T172	1		T173	1		T25	2
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T172	3		T173	3		T174	2
all_values[7]	auto[0]	auto[1]	auto[0]	24	1			T172	3		T173	1		T174	2
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T37	2		T173	3		T174	3
all_values[7]	auto[1]	auto[0]	auto[1]	82	1			T37	1		T172	1		T173	1
all_values[7]	auto[1]	auto[1]	auto[1]	58	1			T37	1		T173	2		T174	4
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T37	2		T172	1		T114	3
all_values[8]	auto[0]	auto[0]	auto[1]	78	1			T172	1		T173	3		T174	5
all_values[8]	auto[0]	auto[1]	auto[0]	34	1			T109	1		T114	1		T263	2
all_values[8]	auto[0]	auto[1]	auto[1]	66	1			T37	1		T172	4		T173	4
all_values[8]	auto[1]	auto[0]	auto[1]	65	1			T172	1		T173	2		T174	3
all_values[8]	auto[1]	auto[1]	auto[1]	69	1			T37	1		T172	1		T173	2
all_values[9]	auto[0]	auto[0]	auto[0]	43	1			T114	4		T266	4		T262	1
all_values[9]	auto[0]	auto[0]	auto[1]	66	1			T172	1		T173	4		T174	1
all_values[9]	auto[0]	auto[1]	auto[0]	25	1			T174	3		T109	1		T266	2
all_values[9]	auto[0]	auto[1]	auto[1]	78	1			T37	1		T172	2		T173	2
all_values[9]	auto[1]	auto[0]	auto[1]	81	1			T37	1		T172	3		T173	2
all_values[9]	auto[1]	auto[1]	auto[1]	55	1			T37	2		T172	2		T173	3
all_values[10]	auto[0]	auto[0]	auto[0]	30	1			T37	1		T114	1		T266	1
all_values[10]	auto[0]	auto[0]	auto[1]	81	1			T172	3		T173	3		T174	4
all_values[10]	auto[0]	auto[1]	auto[0]	23	1			T174	1		T109	1		T261	1
all_values[10]	auto[0]	auto[1]	auto[1]	68	1			T37	2		T172	2		T173	4
all_values[10]	auto[1]	auto[0]	auto[1]	89	1			T172	3		T173	2		T174	5
all_values[10]	auto[1]	auto[1]	auto[1]	57	1			T37	1		T173	2		T174	3
all_values[11]	auto[0]	auto[0]	auto[0]	36	1			T37	1		T172	1		T262	2
all_values[11]	auto[0]	auto[0]	auto[1]	68	1			T173	2		T174	3		T114	6
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T172	3		T109	2		T25	4
all_values[11]	auto[0]	auto[1]	auto[1]	70	1			T37	1		T172	1		T173	2
all_values[11]	auto[1]	auto[0]	auto[1]	80	1			T172	1		T173	3		T174	5
all_values[11]	auto[1]	auto[1]	auto[1]	69	1			T37	2		T172	2		T173	4
all_values[12]	auto[0]	auto[0]	auto[0]	34	1			T37	2		T174	1		T261	3
all_values[12]	auto[0]	auto[0]	auto[1]	75	1			T172	2		T173	3		T174	1
all_values[12]	auto[0]	auto[1]	auto[0]	34	1			T174	2		T114	2		T261	2
all_values[12]	auto[0]	auto[1]	auto[1]	72	1			T37	1		T172	2		T173	2
all_values[12]	auto[1]	auto[0]	auto[1]	64	1			T172	2		T173	3		T174	3
all_values[12]	auto[1]	auto[1]	auto[1]	69	1			T37	1		T172	2		T173	3
all_values[13]	auto[0]	auto[0]	auto[0]	34	1			T37	1		T173	1		T266	2
all_values[13]	auto[0]	auto[0]	auto[1]	74	1			T172	2		T173	2		T174	3
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T172	1		T173	1		T261	1
all_values[13]	auto[0]	auto[1]	auto[1]	61	1			T37	1		T172	2		T173	2
all_values[13]	auto[1]	auto[0]	auto[1]	96	1			T172	3		T173	4		T174	4
all_values[13]	auto[1]	auto[1]	auto[1]	59	1			T37	2		T173	1		T174	6
all_values[14]	auto[0]	auto[0]	auto[0]	39	1			T37	1		T172	8		T173	1
all_values[14]	auto[0]	auto[0]	auto[1]	65	1			T173	3		T174	5		T114	1
all_values[14]	auto[0]	auto[1]	auto[0]	15	1			T266	1		T25	2		T263	1
all_values[14]	auto[0]	auto[1]	auto[1]	81	1			T37	2		T173	1		T174	4
all_values[14]	auto[1]	auto[0]	auto[1]	77	1			T37	1		T173	1		T174	3
all_values[14]	auto[1]	auto[1]	auto[1]	71	1			T173	5		T174	2		T109	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal