Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	743207	1			T1	3		T2	2		T3	3
all_values[1]	743207	1			T1	3		T2	2		T3	3
all_values[2]	743207	1			T1	3		T2	2		T3	3
all_values[3]	743207	1			T1	3		T2	2		T3	3
all_values[4]	743207	1			T1	3		T2	2		T3	3
all_values[5]	743207	1			T1	3		T2	2		T3	3
all_values[6]	743207	1			T1	3		T2	2		T3	3
all_values[7]	743207	1			T1	3		T2	2		T3	3
all_values[8]	743207	1			T1	3		T2	2		T3	3
all_values[9]	743207	1			T1	3		T2	2		T3	3
all_values[10]	743207	1			T1	3		T2	2		T3	3
all_values[11]	743207	1			T1	3		T2	2		T3	3
all_values[12]	743207	1			T1	3		T2	2		T3	3
all_values[13]	743207	1			T1	3		T2	2		T3	3
all_values[14]	743207	1			T1	3		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9198867

1

T1

39

T2

26

T3

39

auto[1]

1949238

1

T1

6

T2

4

T3

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9310118

1

T1

45

T2

30

T3

45

auto[1]

1837987

1

T21

57047

T16

13158

T17

71

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102342	1			T1	1		T3	1		T8	1
all_values[0]	auto[0]	auto[1]	9335	1			T21	15		T16	3		T269	2
all_values[0]	auto[1]	auto[0]	508761	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	122769	1			T21	3789		T16	1090		T238	6
all_values[1]	auto[0]	auto[0]	610882	1			T1	3		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	131904	1			T21	3800		T16	1087		T17	4
all_values[1]	auto[1]	auto[0]	224	1			T9	29		T95	50		T17	6
all_values[1]	auto[1]	auto[1]	197	1			T21	4		T16	4		T17	2
all_values[2]	auto[0]	auto[0]	621194	1			T1	3		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	121671	1			T21	3799		T16	1087		T17	3
all_values[2]	auto[1]	auto[0]	187	1			T173	1		T270	1		T59	1
all_values[2]	auto[1]	auto[1]	155	1			T21	4		T16	6		T17	3
all_values[3]	auto[0]	auto[0]	611099	1			T1	3		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	131944	1			T21	3799		T16	1088		T238	5
all_values[3]	auto[1]	auto[1]	164	1			T21	5		T16	5		T238	2
all_values[4]	auto[0]	auto[0]	611085	1			T1	3		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	131955	1			T21	3800		T16	1089		T17	3
all_values[4]	auto[1]	auto[0]	19	1			T255	1		T263	1		T262	1
all_values[4]	auto[1]	auto[1]	148	1			T21	3		T16	3		T17	2
all_values[5]	auto[0]	auto[0]	612170	1			T1	3		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	130869	1			T21	3797		T16	15		T17	5
all_values[5]	auto[1]	auto[1]	168	1			T21	3		T16	3		T17	1
all_values[6]	auto[0]	auto[0]	624157	1			T1	3		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	118908	1			T21	3802		T16	1084		T17	4
all_values[6]	auto[1]	auto[1]	142	1			T21	1		T16	9		T238	3
all_values[7]	auto[0]	auto[0]	587082	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	129509	1			T21	3685		T16	1082		T17	2
all_values[7]	auto[1]	auto[0]	24007	1			T1	1		T3	1		T8	1
all_values[7]	auto[1]	auto[1]	2609	1			T21	119		T16	10		T17	4
all_values[8]	auto[0]	auto[0]	612164	1			T1	3		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	130867	1			T21	3801		T16	17		T17	2
all_values[8]	auto[1]	auto[1]	176	1			T21	3		T16	1		T17	3
all_values[9]	auto[0]	auto[0]	186757	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	8279	1			T21	542		T16	8		T17	2
all_values[9]	auto[1]	auto[0]	448746	1			T1	1		T3	1		T8	1
all_values[9]	auto[1]	auto[1]	99425	1			T21	3261		T16	8		T17	4
all_values[10]	auto[0]	auto[0]	647860	1			T1	3		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	95199	1			T21	3799		T16	1087		T17	5
all_values[10]	auto[1]	auto[1]	148	1			T21	4		T16	6		T17	1
all_values[11]	auto[0]	auto[0]	2251	1			T1	1		T3	1		T8	1
all_values[11]	auto[0]	auto[1]	306	1			T21	16		T16	3		T17	4
all_values[11]	auto[1]	auto[0]	610482	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	130168	1			T21	3786		T16	1089		T17	1
all_values[12]	auto[0]	auto[0]	611018	1			T1	3		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	131957	1			T21	3798		T16	1087		T17	3
all_values[12]	auto[1]	auto[0]	68	1			T59	1		T271	1		T272	1
all_values[12]	auto[1]	auto[1]	164	1			T21	5		T16	4		T17	2
all_values[13]	auto[0]	auto[0]	666475	1			T1	3		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	76576	1			T21	3800		T16	1089		T17	4
all_values[13]	auto[1]	auto[1]	156	1			T21	3		T16	3		T17	2
all_values[14]	auto[0]	auto[0]	611088	1			T1	3		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	131964	1			T21	3802		T16	1086		T17	2
all_values[14]	auto[1]	auto[1]	155	1			T21	2		T16	5		T17	3