Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	743207	1			T1	3		T2	2		T3	3
all_pins[1]	743207	1			T1	3		T2	2		T3	3
all_pins[2]	743207	1			T1	3		T2	2		T3	3
all_pins[3]	743207	1			T1	3		T2	2		T3	3
all_pins[4]	743207	1			T1	3		T2	2		T3	3
all_pins[5]	743207	1			T1	3		T2	2		T3	3
all_pins[6]	743207	1			T1	3		T2	2		T3	3
all_pins[7]	743207	1			T1	3		T2	2		T3	3
all_pins[8]	743207	1			T1	3		T2	2		T3	3
all_pins[9]	743207	1			T1	3		T2	2		T3	3
all_pins[10]	743207	1			T1	3		T2	2		T3	3
all_pins[11]	743207	1			T1	3		T2	2		T3	3
all_pins[12]	743207	1			T1	3		T2	2		T3	3
all_pins[13]	743207	1			T1	3		T2	2		T3	3
all_pins[14]	743207	1			T1	3		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9205308	1			T1	39		T2	26		T3	39
values[0x1]	1942797	1			T1	6		T2	4		T3	6
transitions[0x0=>0x1]	1942125	1			T1	6		T2	4		T3	6
transitions[0x1=>0x0]	1940809	1			T1	5		T2	3		T3	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	115222	1			T1	1		T3	1		T8	1
all_pins[0]	values[0x1]	627985	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	627627	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	44	1			T21	1		T17	1		T236	1
all_pins[1]	values[0x0]	742805	1			T1	3		T2	2		T3	3
all_pins[1]	values[0x1]	402	1			T9	38		T95	59		T21	2
all_pins[1]	transitions[0x0=>0x1]	379	1			T9	38		T95	59		T21	1
all_pins[1]	transitions[0x1=>0x0]	109	1			T173	1		T270	1		T271	1
all_pins[2]	values[0x0]	743075	1			T1	3		T2	2		T3	3
all_pins[2]	values[0x1]	132	1			T173	1		T270	1		T271	1
all_pins[2]	transitions[0x0=>0x1]	117	1			T173	1		T270	1		T271	1
all_pins[2]	transitions[0x1=>0x0]	57	1			T21	3		T16	2		T238	2
all_pins[3]	values[0x0]	743135	1			T1	3		T2	2		T3	3
all_pins[3]	values[0x1]	72	1			T21	4		T16	3		T238	2
all_pins[3]	transitions[0x0=>0x1]	56	1			T21	3		T16	3		T238	2
all_pins[3]	transitions[0x1=>0x0]	87	1			T21	1		T16	1		T17	1
all_pins[4]	values[0x0]	743104	1			T1	3		T2	2		T3	3
all_pins[4]	values[0x1]	103	1			T21	2		T16	1		T17	1
all_pins[4]	transitions[0x0=>0x1]	80	1			T21	1		T16	1		T17	1
all_pins[4]	transitions[0x1=>0x0]	82	1			T21	2		T16	2		T269	1
all_pins[5]	values[0x0]	743102	1			T1	3		T2	2		T3	3
all_pins[5]	values[0x1]	105	1			T21	3		T16	2		T269	1
all_pins[5]	transitions[0x0=>0x1]	85	1			T21	3		T16	2		T269	1
all_pins[5]	transitions[0x1=>0x0]	43	1			T16	4		T238	1		T236	1
all_pins[6]	values[0x0]	743144	1			T1	3		T2	2		T3	3
all_pins[6]	values[0x1]	63	1			T16	4		T238	1		T236	2
all_pins[6]	transitions[0x0=>0x1]	44	1			T16	2		T238	1		T236	1
all_pins[6]	transitions[0x1=>0x0]	28853	1			T1	1		T3	1		T8	1
all_pins[7]	values[0x0]	714335	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	28872	1			T1	1		T3	1		T8	1
all_pins[7]	transitions[0x0=>0x1]	28847	1			T1	1		T3	1		T8	1
all_pins[7]	transitions[0x1=>0x0]	63	1			T21	1		T17	3		T238	1
all_pins[8]	values[0x0]	743119	1			T1	3		T2	2		T3	3
all_pins[8]	values[0x1]	88	1			T21	2		T17	3		T238	1
all_pins[8]	transitions[0x0=>0x1]	65	1			T21	2		T17	3		T238	1
all_pins[8]	transitions[0x1=>0x0]	548070	1			T1	1		T3	1		T8	1
all_pins[9]	values[0x0]	195114	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	548093	1			T1	1		T3	1		T8	1
all_pins[9]	transitions[0x0=>0x1]	548077	1			T1	1		T3	1		T8	1
all_pins[9]	transitions[0x1=>0x0]	54	1			T21	1		T16	4		T17	1
all_pins[10]	values[0x0]	743137	1			T1	3		T2	2		T3	3
all_pins[10]	values[0x1]	70	1			T21	1		T16	4		T17	1
all_pins[10]	transitions[0x0=>0x1]	47	1			T16	3		T17	1		T236	1
all_pins[10]	transitions[0x1=>0x0]	736471	1			T1	2		T2	2		T3	2
all_pins[11]	values[0x0]	6713	1			T1	1		T3	1		T8	1
all_pins[11]	values[0x1]	736494	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	736455	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	112	1			T59	1		T21	1		T71	1
all_pins[12]	values[0x0]	743056	1			T1	3		T2	2		T3	3
all_pins[12]	values[0x1]	151	1			T59	1		T271	1		T21	3
all_pins[12]	transitions[0x0=>0x1]	133	1			T59	1		T271	1		T21	2
all_pins[12]	transitions[0x1=>0x0]	64	1			T21	1		T16	2		T17	1
all_pins[13]	values[0x0]	743125	1			T1	3		T2	2		T3	3
all_pins[13]	values[0x1]	82	1			T21	2		T16	2		T17	1
all_pins[13]	transitions[0x0=>0x1]	63	1			T21	1		T238	2		T269	2
all_pins[13]	transitions[0x1=>0x0]	66	1			T21	1		T16	2		T236	3
all_pins[14]	values[0x0]	743122	1			T1	3		T2	2		T3	3
all_pins[14]	values[0x1]	85	1			T21	2		T16	4		T17	1
all_pins[14]	transitions[0x0=>0x1]	50	1			T16	1		T17	1		T236	2
all_pins[14]	transitions[0x1=>0x0]	626634	1			T1	1		T2	1		T3	1