Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	358	1			T21	7		T16	11		T17	4
all_values[1]	358	1			T21	7		T16	11		T17	4
all_values[2]	358	1			T21	7		T16	11		T17	4
all_values[3]	358	1			T21	7		T16	11		T17	4
all_values[4]	358	1			T21	7		T16	11		T17	4
all_values[5]	358	1			T21	7		T16	11		T17	4
all_values[6]	358	1			T21	7		T16	11		T17	4
all_values[7]	358	1			T21	7		T16	11		T17	4
all_values[8]	358	1			T21	7		T16	11		T17	4
all_values[9]	358	1			T21	7		T16	11		T17	4
all_values[10]	358	1			T21	7		T16	11		T17	4
all_values[11]	358	1			T21	7		T16	11		T17	4
all_values[12]	358	1			T21	7		T16	11		T17	4
all_values[13]	358	1			T21	7		T16	11		T17	4
all_values[14]	358	1			T21	7		T16	11		T17	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2928

1

T21

33

T16

68

T17

38

auto[1]

2442

1

T21

72

T16

97

T17

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

914

1

T21

13

T16

24

T17

15

auto[1]

4456

1

T21

92

T16

141

T17

45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3116

1

T21

56

T16

102

T17

38

auto[1]

2254

1

T21

49

T16

63

T17

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	40	1			T17	2		T37	2		T282	1
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T21	1		T16	1		T26	4
all_values[0]	auto[0]	auto[1]	auto[0]	24	1			T17	2		T238	3		T237	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T21	4		T16	6		T238	2
all_values[0]	auto[1]	auto[0]	auto[1]	82	1			T16	2		T236	2		T26	3
all_values[0]	auto[1]	auto[1]	auto[1]	63	1			T21	2		T16	2		T238	2
all_values[1]	auto[0]	auto[0]	auto[0]	43	1			T16	1		T237	1		T26	1
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T21	2		T16	1		T17	2
all_values[1]	auto[0]	auto[1]	auto[0]	24	1			T16	1		T283	1		T26	1
all_values[1]	auto[0]	auto[1]	auto[1]	64	1			T21	1		T16	4		T269	2
all_values[1]	auto[1]	auto[0]	auto[1]	89	1			T21	1		T16	3		T17	2
all_values[1]	auto[1]	auto[1]	auto[1]	58	1			T21	3		T16	1		T238	1
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T238	1		T269	3		T26	2
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T21	1		T16	3		T238	3
all_values[2]	auto[0]	auto[1]	auto[0]	22	1			T21	1		T238	1		T269	1
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T21	1		T16	2		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	86	1			T21	1		T16	2		T17	2
all_values[2]	auto[1]	auto[1]	auto[1]	69	1			T21	3		T16	4		T17	1
all_values[3]	auto[0]	auto[0]	auto[0]	39	1			T17	2		T238	1		T283	1
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T16	2		T236	4		T237	2
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T17	2		T238	1		T284	1
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T21	3		T16	4		T238	1
all_values[3]	auto[1]	auto[0]	auto[1]	89	1			T21	2		T16	2		T238	3
all_values[3]	auto[1]	auto[1]	auto[1]	56	1			T21	2		T16	3		T238	1
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T17	1		T283	1		T133	1
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T21	1		T16	6		T236	1
all_values[4]	auto[0]	auto[1]	auto[0]	34	1			T21	1		T16	1		T238	4
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T21	2		T16	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	85	1			T21	1		T16	1		T17	1
all_values[4]	auto[1]	auto[1]	auto[1]	63	1			T21	2		T16	2		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	36	1			T21	3		T16	1		T238	1
all_values[5]	auto[0]	auto[0]	auto[1]	66	1			T16	1		T17	1		T238	1
all_values[5]	auto[0]	auto[1]	auto[0]	26	1			T21	1		T16	3		T238	1
all_values[5]	auto[0]	auto[1]	auto[1]	84	1			T21	2		T16	3		T17	2
all_values[5]	auto[1]	auto[0]	auto[1]	69	1			T16	1		T17	1		T238	4
all_values[5]	auto[1]	auto[1]	auto[1]	77	1			T21	1		T16	2		T269	1
all_values[6]	auto[0]	auto[0]	auto[0]	42	1			T283	1		T282	1		T133	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T21	2		T16	2		T238	2
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T21	1		T17	2		T269	1
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T21	1		T16	2		T17	1
all_values[6]	auto[1]	auto[0]	auto[1]	74	1			T21	2		T16	3		T236	2
all_values[6]	auto[1]	auto[1]	auto[1]	66	1			T21	1		T16	4		T17	1
all_values[7]	auto[0]	auto[0]	auto[0]	37	1			T238	1		T236	4		T283	1
all_values[7]	auto[0]	auto[0]	auto[1]	81	1			T21	3		T17	3		T269	3
all_values[7]	auto[0]	auto[1]	auto[0]	18	1			T16	1		T238	3		T284	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T21	2		T16	3		T238	1
all_values[7]	auto[1]	auto[0]	auto[1]	85	1			T16	2		T17	1		T238	1
all_values[7]	auto[1]	auto[1]	auto[1]	62	1			T21	2		T16	5		T238	1
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T16	3		T17	1		T26	2
all_values[8]	auto[0]	auto[0]	auto[1]	76	1			T21	2		T16	4		T238	4
all_values[8]	auto[0]	auto[1]	auto[0]	21	1			T16	1		T237	2		T283	2
all_values[8]	auto[0]	auto[1]	auto[1]	76	1			T21	2		T16	1		T17	1
all_values[8]	auto[1]	auto[0]	auto[1]	87	1			T16	1		T17	1		T238	2
all_values[8]	auto[1]	auto[1]	auto[1]	62	1			T21	3		T16	1		T17	1
all_values[9]	auto[0]	auto[0]	auto[0]	37	1			T16	2		T269	1		T236	2
all_values[9]	auto[0]	auto[0]	auto[1]	68	1			T16	1		T17	1		T238	1
all_values[9]	auto[0]	auto[1]	auto[0]	25	1			T21	1		T16	4		T238	1
all_values[9]	auto[0]	auto[1]	auto[1]	68	1			T21	3		T16	2		T238	1
all_values[9]	auto[1]	auto[0]	auto[1]	89	1			T21	3		T16	2		T17	3
all_values[9]	auto[1]	auto[1]	auto[1]	71	1			T238	2		T236	2		T237	2
all_values[10]	auto[0]	auto[0]	auto[0]	32	1			T236	2		T237	1		T26	1
all_values[10]	auto[0]	auto[0]	auto[1]	71	1			T21	1		T16	3		T238	1
all_values[10]	auto[0]	auto[1]	auto[0]	35	1			T21	1		T238	1		T236	3
all_values[10]	auto[0]	auto[1]	auto[1]	72	1			T21	1		T16	2		T17	3
all_values[10]	auto[1]	auto[0]	auto[1]	90	1			T21	2		T16	1		T238	3
all_values[10]	auto[1]	auto[1]	auto[1]	58	1			T21	2		T16	5		T17	1
all_values[11]	auto[0]	auto[0]	auto[0]	48	1			T17	1		T236	7		T237	1
all_values[11]	auto[0]	auto[0]	auto[1]	79	1			T238	2		T269	2		T26	4
all_values[11]	auto[0]	auto[1]	auto[0]	18	1			T21	2		T16	1		T133	1
all_values[11]	auto[0]	auto[1]	auto[1]	67	1			T21	2		T16	6		T17	2
all_values[11]	auto[1]	auto[0]	auto[1]	82	1			T16	3		T17	1		T238	1
all_values[11]	auto[1]	auto[1]	auto[1]	64	1			T21	3		T16	1		T238	2
all_values[12]	auto[0]	auto[0]	auto[0]	23	1			T16	1		T17	1		T37	1
all_values[12]	auto[0]	auto[0]	auto[1]	72	1			T16	5		T17	1		T238	1
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T21	1		T16	1		T237	2
all_values[12]	auto[0]	auto[1]	auto[1]	73	1			T21	1		T238	3		T269	1
all_values[12]	auto[1]	auto[0]	auto[1]	86	1			T21	3		T16	3		T17	2
all_values[12]	auto[1]	auto[1]	auto[1]	78	1			T21	2		T16	1		T238	3
all_values[13]	auto[0]	auto[0]	auto[0]	39	1			T236	1		T237	4		T26	1
all_values[13]	auto[0]	auto[0]	auto[1]	73	1			T21	1		T17	2		T238	1
all_values[13]	auto[0]	auto[1]	auto[0]	16	1			T21	1		T16	1		T283	1
all_values[13]	auto[0]	auto[1]	auto[1]	70	1			T21	1		T16	7		T238	3
all_values[13]	auto[1]	auto[0]	auto[1]	96	1			T21	1		T16	1		T17	2
all_values[13]	auto[1]	auto[1]	auto[1]	64	1			T21	3		T16	2		T238	1
all_values[14]	auto[0]	auto[0]	auto[0]	35	1			T16	1		T17	1		T237	1
all_values[14]	auto[0]	auto[0]	auto[1]	78	1			T16	2		T17	2		T238	4
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T16	1		T26	1		T285	1
all_values[14]	auto[0]	auto[1]	auto[1]	72	1			T21	3		T16	4		T269	1
all_values[14]	auto[1]	auto[0]	auto[1]	72	1			T16	1		T17	1		T238	2
all_values[14]	auto[1]	auto[1]	auto[1]	82	1			T21	4		T16	2		T238	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal