Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	670145	1			T1	3		T2	30		T3	2
all_values[1]	670145	1			T1	3		T2	30		T3	2
all_values[2]	670145	1			T1	3		T2	30		T3	2
all_values[3]	670145	1			T1	3		T2	30		T3	2
all_values[4]	670145	1			T1	3		T2	30		T3	2
all_values[5]	670145	1			T1	3		T2	30		T3	2
all_values[6]	670145	1			T1	3		T2	30		T3	2
all_values[7]	670145	1			T1	3		T2	30		T3	2
all_values[8]	670145	1			T1	3		T2	30		T3	2
all_values[9]	670145	1			T1	3		T2	30		T3	2
all_values[10]	670145	1			T1	3		T2	30		T3	2
all_values[11]	670145	1			T1	3		T2	30		T3	2
all_values[12]	670145	1			T1	3		T2	30		T3	2
all_values[13]	670145	1			T1	3		T2	30		T3	2
all_values[14]	670145	1			T1	3		T2	30		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8271786

1

T1

39

T2

403

T3

26

auto[1]

1780389

1

T1

6

T2

47

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9411799

1

T1

45

T2

450

T3

30

auto[1]

640376

1

T15

140849

T151

394

T23

194

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	87892	1			T1	1		T2	12		T4	1
all_values[0]	auto[0]	auto[1]	4464	1			T15	110		T151	17		T124	949
all_values[0]	auto[1]	auto[0]	536117	1			T1	2		T2	18		T3	2
all_values[0]	auto[1]	auto[1]	41672	1			T15	9280		T151	10		T23	12
all_values[1]	auto[0]	auto[0]	623671	1			T1	3		T2	30		T3	2
all_values[1]	auto[0]	auto[1]	45989	1			T15	9388		T151	19		T23	8
all_values[1]	auto[1]	auto[0]	329	1			T28	20		T14	48		T15	59
all_values[1]	auto[1]	auto[1]	156	1			T15	3		T151	7		T23	5
all_values[2]	auto[0]	auto[0]	625062	1			T1	3		T2	30		T3	2
all_values[2]	auto[0]	auto[1]	44742	1			T15	9389		T151	20		T23	7
all_values[2]	auto[1]	auto[0]	184	1			T51	1		T52	1		T269	1
all_values[2]	auto[1]	auto[1]	157	1			T15	2		T151	6		T23	7
all_values[3]	auto[0]	auto[0]	640789	1			T1	3		T2	30		T3	2
all_values[3]	auto[0]	auto[1]	29170	1			T15	9384		T151	22		T23	5
all_values[3]	auto[1]	auto[1]	186	1			T15	7		T151	5		T23	4
all_values[4]	auto[0]	auto[0]	640797	1			T1	3		T2	30		T3	2
all_values[4]	auto[0]	auto[1]	29179	1			T15	9387		T151	22		T23	8
all_values[4]	auto[1]	auto[0]	17	1			T259	2		T260	2		T261	1
all_values[4]	auto[1]	auto[1]	152	1			T15	4		T151	5		T23	6
all_values[5]	auto[0]	auto[0]	624039	1			T1	3		T2	30		T3	2
all_values[5]	auto[0]	auto[1]	45938	1			T15	9384		T151	14		T23	6
all_values[5]	auto[1]	auto[1]	168	1			T15	2		T151	12		T23	3
all_values[6]	auto[0]	auto[0]	624042	1			T1	3		T2	30		T3	2
all_values[6]	auto[0]	auto[1]	45922	1			T15	9385		T151	23		T23	4
all_values[6]	auto[1]	auto[1]	181	1			T15	5		T151	4		T23	10
all_values[7]	auto[0]	auto[0]	616333	1			T1	2		T2	30		T3	2
all_values[7]	auto[0]	auto[1]	28258	1			T15	9387		T151	24		T23	8
all_values[7]	auto[1]	auto[0]	24469	1			T1	1		T4	1		T5	342
all_values[7]	auto[1]	auto[1]	1085	1			T151	2		T23	6		T124	582
all_values[8]	auto[0]	auto[0]	623996	1			T1	3		T2	30		T3	2
all_values[8]	auto[0]	auto[1]	45944	1			T15	9387		T151	20		T23	11
all_values[8]	auto[1]	auto[1]	205	1			T15	3		T151	7		T23	2
all_values[9]	auto[0]	auto[0]	144136	1			T1	2		T2	29		T3	2
all_values[9]	auto[0]	auto[1]	18875	1			T15	9384		T151	19		T23	9
all_values[9]	auto[1]	auto[0]	479880	1			T1	1		T2	1		T4	1
all_values[9]	auto[1]	auto[1]	27254	1			T15	5		T151	8		T23	4
all_values[10]	auto[0]	auto[0]	623997	1			T1	3		T2	30		T3	2
all_values[10]	auto[0]	auto[1]	45993	1			T15	9387		T151	18		T23	11
all_values[10]	auto[1]	auto[1]	155	1			T15	4		T151	4		T23	3
all_values[11]	auto[0]	auto[0]	2357	1			T1	1		T2	2		T4	1
all_values[11]	auto[0]	auto[1]	302	1			T15	5		T151	15		T124	18
all_values[11]	auto[1]	auto[0]	621651	1			T1	2		T2	28		T3	2
all_values[11]	auto[1]	auto[1]	45835	1			T15	9385		T151	12		T23	13
all_values[12]	auto[0]	auto[0]	623952	1			T1	3		T2	30		T3	2
all_values[12]	auto[0]	auto[1]	45986	1			T15	9387		T151	18		T23	7
all_values[12]	auto[1]	auto[0]	64	1			T51	1		T52	1		T66	1
all_values[12]	auto[1]	auto[1]	143	1			T15	3		T151	9		T23	7
all_values[13]	auto[0]	auto[0]	623998	1			T1	3		T2	30		T3	2
all_values[13]	auto[0]	auto[1]	45987	1			T15	9385		T151	17		T23	11
all_values[13]	auto[1]	auto[1]	160	1			T15	6		T151	10		T23	3
all_values[14]	auto[0]	auto[0]	624027	1			T1	3		T2	30		T3	2
all_values[14]	auto[0]	auto[1]	45949	1			T15	9387		T151	19		T23	8
all_values[14]	auto[1]	auto[1]	169	1			T15	4		T151	6		T23	6