Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	670145	1			T1	3		T2	30		T3	2
all_pins[1]	670145	1			T1	3		T2	30		T3	2
all_pins[2]	670145	1			T1	3		T2	30		T3	2
all_pins[3]	670145	1			T1	3		T2	30		T3	2
all_pins[4]	670145	1			T1	3		T2	30		T3	2
all_pins[5]	670145	1			T1	3		T2	30		T3	2
all_pins[6]	670145	1			T1	3		T2	30		T3	2
all_pins[7]	670145	1			T1	3		T2	30		T3	2
all_pins[8]	670145	1			T1	3		T2	30		T3	2
all_pins[9]	670145	1			T1	3		T2	30		T3	2
all_pins[10]	670145	1			T1	3		T2	30		T3	2
all_pins[11]	670145	1			T1	3		T2	30		T3	2
all_pins[12]	670145	1			T1	3		T2	30		T3	2
all_pins[13]	670145	1			T1	3		T2	30		T3	2
all_pins[14]	670145	1			T1	3		T2	30		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8278080	1			T1	39		T2	403		T3	26
values[0x1]	1774095	1			T1	6		T2	47		T3	4
transitions[0x0=>0x1]	1773381	1			T1	6		T2	47		T3	4
transitions[0x1=>0x0]	1772081	1			T1	5		T2	46		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95813	1			T1	1		T2	12		T4	1
all_pins[0]	values[0x1]	574332	1			T1	2		T2	18		T3	2
all_pins[0]	transitions[0x0=>0x1]	573943	1			T1	2		T2	18		T3	2
all_pins[0]	transitions[0x1=>0x0]	62	1			T15	2		T151	1		T23	1
all_pins[1]	values[0x0]	669694	1			T1	3		T2	30		T3	2
all_pins[1]	values[0x1]	451	1			T28	22		T14	60		T15	64
all_pins[1]	transitions[0x0=>0x1]	429	1			T28	22		T14	60		T15	63
all_pins[1]	transitions[0x1=>0x0]	109	1			T269	1		T276	1		T86	1
all_pins[2]	values[0x0]	670014	1			T1	3		T2	30		T3	2
all_pins[2]	values[0x1]	131	1			T269	1		T15	1		T276	1
all_pins[2]	transitions[0x0=>0x1]	114	1			T269	1		T15	1		T276	1
all_pins[2]	transitions[0x1=>0x0]	74	1			T15	3		T151	1		T23	2
all_pins[3]	values[0x0]	670054	1			T1	3		T2	30		T3	2
all_pins[3]	values[0x1]	91	1			T15	3		T151	1		T23	2
all_pins[3]	transitions[0x0=>0x1]	63	1			T15	2		T241	2		T248	1
all_pins[3]	transitions[0x1=>0x0]	81	1			T15	2		T151	3		T23	4
all_pins[4]	values[0x0]	670036	1			T1	3		T2	30		T3	2
all_pins[4]	values[0x1]	109	1			T15	3		T151	4		T23	6
all_pins[4]	transitions[0x0=>0x1]	91	1			T15	3		T151	2		T23	6
all_pins[4]	transitions[0x1=>0x0]	65	1			T151	5		T23	1		T124	2
all_pins[5]	values[0x0]	670062	1			T1	3		T2	30		T3	2
all_pins[5]	values[0x1]	83	1			T151	7		T23	1		T124	3
all_pins[5]	transitions[0x0=>0x1]	57	1			T151	7		T277	2		T278	3
all_pins[5]	transitions[0x1=>0x0]	70	1			T15	4		T151	1		T23	1
all_pins[6]	values[0x0]	670049	1			T1	3		T2	30		T3	2
all_pins[6]	values[0x1]	96	1			T15	4		T151	1		T23	2
all_pins[6]	transitions[0x0=>0x1]	72	1			T15	4		T151	1		T23	1
all_pins[6]	transitions[0x1=>0x0]	27623	1			T1	1		T4	1		T5	396
all_pins[7]	values[0x0]	642498	1			T1	2		T2	30		T3	2
all_pins[7]	values[0x1]	27647	1			T1	1		T4	1		T5	396
all_pins[7]	transitions[0x0=>0x1]	27619	1			T1	1		T4	1		T5	396
all_pins[7]	transitions[0x1=>0x0]	71	1			T15	1		T151	6		T23	1
all_pins[8]	values[0x0]	670046	1			T1	3		T2	30		T3	2
all_pins[8]	values[0x1]	99	1			T15	1		T151	6		T23	1
all_pins[8]	transitions[0x0=>0x1]	80	1			T15	1		T151	5		T23	1
all_pins[8]	transitions[0x1=>0x0]	507054	1			T1	1		T2	1		T4	1
all_pins[9]	values[0x0]	163072	1			T1	2		T2	29		T3	2
all_pins[9]	values[0x1]	507073	1			T1	1		T2	1		T4	1
all_pins[9]	transitions[0x0=>0x1]	507049	1			T1	1		T2	1		T4	1
all_pins[9]	transitions[0x1=>0x0]	56	1			T15	2		T151	1		T23	1
all_pins[10]	values[0x0]	670065	1			T1	3		T2	30		T3	2
all_pins[10]	values[0x1]	80	1			T15	3		T151	2		T23	1
all_pins[10]	transitions[0x0=>0x1]	61	1			T15	3		T151	1		T23	1
all_pins[10]	transitions[0x1=>0x0]	663584	1			T1	2		T2	28		T3	2
all_pins[11]	values[0x0]	6542	1			T1	1		T2	2		T4	1
all_pins[11]	values[0x1]	663603	1			T1	2		T2	28		T3	2
all_pins[11]	transitions[0x0=>0x1]	663559	1			T1	2		T2	28		T3	2
all_pins[11]	transitions[0x1=>0x0]	92	1			T51	1		T52	1		T66	1
all_pins[12]	values[0x0]	670009	1			T1	3		T2	30		T3	2
all_pins[12]	values[0x1]	136	1			T51	1		T52	1		T15	1
all_pins[12]	transitions[0x0=>0x1]	125	1			T51	1		T52	1		T15	1
all_pins[12]	transitions[0x1=>0x0]	76	1			T15	4		T151	2		T23	3
all_pins[13]	values[0x0]	670058	1			T1	3		T2	30		T3	2
all_pins[13]	values[0x1]	87	1			T15	4		T151	4		T23	3
all_pins[13]	transitions[0x0=>0x1]	68	1			T15	4		T151	3		T23	1
all_pins[13]	transitions[0x1=>0x0]	58	1			T151	1		T23	2		T124	3
all_pins[14]	values[0x0]	670068	1			T1	3		T2	30		T3	2
all_pins[14]	values[0x1]	77	1			T151	2		T23	4		T124	3
all_pins[14]	transitions[0x0=>0x1]	51	1			T151	2		T23	3		T124	1
all_pins[14]	transitions[0x1=>0x0]	573006	1			T1	1		T2	17		T3	1