Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	374	1			T15	7		T151	14		T23	11
all_values[1]	374	1			T15	7		T151	14		T23	11
all_values[2]	374	1			T15	7		T151	14		T23	11
all_values[3]	374	1			T15	7		T151	14		T23	11
all_values[4]	374	1			T15	7		T151	14		T23	11
all_values[5]	374	1			T15	7		T151	14		T23	11
all_values[6]	374	1			T15	7		T151	14		T23	11
all_values[7]	374	1			T15	7		T151	14		T23	11
all_values[8]	374	1			T15	7		T151	14		T23	11
all_values[9]	374	1			T15	7		T151	14		T23	11
all_values[10]	374	1			T15	7		T151	14		T23	11
all_values[11]	374	1			T15	7		T151	14		T23	11
all_values[12]	374	1			T15	7		T151	14		T23	11
all_values[13]	374	1			T15	7		T151	14		T23	11
all_values[14]	374	1			T15	7		T151	14		T23	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2983

1

T15

48

T151

114

T23

84

auto[1]

2627

1

T15

57

T151

96

T23

81

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

939

1

T15

16

T151

11

T23

14

auto[1]

4671

1

T15

89

T151

199

T23

151

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3314

1

T15

55

T151

113

T23

97

auto[1]

2296

1

T15

50

T151

97

T23

68

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T15	1		T113	3		T115	1
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T15	3		T151	4		T23	4
all_values[0]	auto[0]	auto[1]	auto[0]	25	1			T23	2		T124	1		T278	1
all_values[0]	auto[0]	auto[1]	auto[1]	70	1			T151	5		T23	3		T124	1
all_values[0]	auto[1]	auto[0]	auto[1]	74	1			T15	2		T151	2		T23	1
all_values[0]	auto[1]	auto[1]	auto[1]	77	1			T15	1		T151	3		T23	1
all_values[1]	auto[0]	auto[0]	auto[0]	33	1			T277	1		T279	1		T280	2
all_values[1]	auto[0]	auto[0]	auto[1]	95	1			T15	4		T151	6		T23	3
all_values[1]	auto[0]	auto[1]	auto[0]	19	1			T151	1		T23	1		T113	1
all_values[1]	auto[0]	auto[1]	auto[1]	71	1			T23	2		T124	1		T241	5
all_values[1]	auto[1]	auto[0]	auto[1]	82	1			T151	6		T23	3		T124	2
all_values[1]	auto[1]	auto[1]	auto[1]	74	1			T15	3		T151	1		T23	2
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T241	1		T115	1		T281	3
all_values[2]	auto[0]	auto[0]	auto[1]	65	1			T15	4		T151	3		T241	1
all_values[2]	auto[0]	auto[1]	auto[0]	29	1			T151	1		T278	3		T114	4
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T15	1		T151	4		T23	4
all_values[2]	auto[1]	auto[0]	auto[1]	80	1			T15	1		T151	4		T23	5
all_values[2]	auto[1]	auto[1]	auto[1]	77	1			T15	1		T151	2		T23	2
all_values[3]	auto[0]	auto[0]	auto[0]	31	1			T23	1		T277	2		T113	2
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T15	1		T151	9		T23	1
all_values[3]	auto[0]	auto[1]	auto[0]	18	1			T23	3		T277	2		T278	1
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T15	1		T241	4		T248	2
all_values[3]	auto[1]	auto[0]	auto[1]	102	1			T15	4		T151	3		T23	4
all_values[3]	auto[1]	auto[1]	auto[1]	70	1			T15	1		T151	2		T23	2
all_values[4]	auto[0]	auto[0]	auto[0]	44	1			T277	2		T114	1		T115	1
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T151	3		T23	2		T124	2
all_values[4]	auto[0]	auto[1]	auto[0]	30	1			T277	2		T114	1		T282	1
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T15	3		T151	6		T23	3
all_values[4]	auto[1]	auto[0]	auto[1]	84	1			T15	1		T151	3		T23	1
all_values[4]	auto[1]	auto[1]	auto[1]	68	1			T15	3		T151	2		T23	5
all_values[5]	auto[0]	auto[0]	auto[0]	42	1			T15	2		T23	2		T241	3
all_values[5]	auto[0]	auto[0]	auto[1]	72	1			T15	1		T151	4		T23	3
all_values[5]	auto[0]	auto[1]	auto[0]	44	1			T15	3		T151	1		T23	2
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T151	3		T23	1		T124	2
all_values[5]	auto[1]	auto[0]	auto[1]	84	1			T15	1		T151	3		T23	3
all_values[5]	auto[1]	auto[1]	auto[1]	62	1			T151	3		T124	4		T241	1
all_values[6]	auto[0]	auto[0]	auto[0]	39	1			T124	1		T248	1		T278	1
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T151	6		T23	6		T241	5
all_values[6]	auto[0]	auto[1]	auto[0]	38	1			T15	1		T124	1		T248	3
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T15	2		T151	4		T23	1
all_values[6]	auto[1]	auto[0]	auto[1]	72	1			T151	3		T23	2		T124	2
all_values[6]	auto[1]	auto[1]	auto[1]	79	1			T15	4		T151	1		T23	2
all_values[7]	auto[0]	auto[0]	auto[0]	38	1			T241	1		T277	3		T278	2
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T151	5		T23	6		T124	3
all_values[7]	auto[0]	auto[1]	auto[0]	24	1			T15	4		T151	1		T277	1
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T15	2		T151	3		T241	4
all_values[7]	auto[1]	auto[0]	auto[1]	89	1			T15	1		T151	2		T23	2
all_values[7]	auto[1]	auto[1]	auto[1]	64	1			T151	3		T23	3		T124	1
all_values[8]	auto[0]	auto[0]	auto[0]	32	1			T15	1		T279	1		T280	1
all_values[8]	auto[0]	auto[0]	auto[1]	81	1			T151	5		T23	2		T124	1
all_values[8]	auto[0]	auto[1]	auto[0]	16	1			T23	1		T124	1		T277	1
all_values[8]	auto[0]	auto[1]	auto[1]	86	1			T15	2		T151	2		T23	5
all_values[8]	auto[1]	auto[0]	auto[1]	83	1			T15	2		T151	3		T23	2
all_values[8]	auto[1]	auto[1]	auto[1]	76	1			T15	2		T151	4		T23	1
all_values[9]	auto[0]	auto[0]	auto[0]	45	1			T241	3		T248	1		T277	1
all_values[9]	auto[0]	auto[0]	auto[1]	78	1			T15	1		T151	2		T23	3
all_values[9]	auto[0]	auto[1]	auto[0]	23	1			T15	2		T23	1		T124	2
all_values[9]	auto[0]	auto[1]	auto[1]	78	1			T151	3		T23	2		T124	2
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T15	3		T151	4		T23	1
all_values[9]	auto[1]	auto[1]	auto[1]	76	1			T15	1		T151	5		T23	4
all_values[10]	auto[0]	auto[0]	auto[0]	28	1			T151	2		T281	2		T279	2
all_values[10]	auto[0]	auto[0]	auto[1]	89	1			T151	3		T23	5		T124	1
all_values[10]	auto[0]	auto[1]	auto[0]	23	1			T151	3		T124	1		T248	2
all_values[10]	auto[0]	auto[1]	auto[1]	79	1			T15	3		T151	2		T23	3
all_values[10]	auto[1]	auto[0]	auto[1]	73	1			T151	2		T23	1		T124	2
all_values[10]	auto[1]	auto[1]	auto[1]	82	1			T15	4		T151	2		T23	2
all_values[11]	auto[0]	auto[0]	auto[0]	37	1			T15	1		T113	1		T115	2
all_values[11]	auto[0]	auto[0]	auto[1]	89	1			T15	1		T151	3		T23	4
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T23	1		T278	1		T118	1
all_values[11]	auto[0]	auto[1]	auto[1]	82	1			T15	1		T151	3		T23	2
all_values[11]	auto[1]	auto[0]	auto[1]	79	1			T15	3		T151	4		T23	1
all_values[11]	auto[1]	auto[1]	auto[1]	66	1			T15	1		T151	4		T23	3
all_values[12]	auto[0]	auto[0]	auto[0]	35	1			T241	1		T278	1		T279	3
all_values[12]	auto[0]	auto[0]	auto[1]	87	1			T15	1		T151	3		T23	3
all_values[12]	auto[0]	auto[1]	auto[0]	31	1			T15	1		T248	1		T277	1
all_values[12]	auto[0]	auto[1]	auto[1]	78	1			T15	2		T151	2		T23	1
all_values[12]	auto[1]	auto[0]	auto[1]	70	1			T15	2		T151	4		T23	2
all_values[12]	auto[1]	auto[1]	auto[1]	73	1			T15	1		T151	5		T23	5
all_values[13]	auto[0]	auto[0]	auto[0]	27	1			T115	1		T281	1		T279	1
all_values[13]	auto[0]	auto[0]	auto[1]	98	1			T15	2		T151	1		T23	6
all_values[13]	auto[0]	auto[1]	auto[0]	23	1			T248	2		T114	2		T283	1
all_values[13]	auto[0]	auto[1]	auto[1]	69	1			T15	1		T151	3		T23	3
all_values[13]	auto[1]	auto[0]	auto[1]	79	1			T15	1		T151	5		T124	1
all_values[13]	auto[1]	auto[1]	auto[1]	78	1			T15	3		T151	5		T23	2
all_values[14]	auto[0]	auto[0]	auto[0]	47	1			T115	1		T281	4		T279	4
all_values[14]	auto[0]	auto[0]	auto[1]	67	1			T15	1		T151	2		T23	2
all_values[14]	auto[0]	auto[1]	auto[0]	31	1			T151	2		T124	1		T248	2
all_values[14]	auto[0]	auto[1]	auto[1]	80	1			T15	2		T151	3		T23	3
all_values[14]	auto[1]	auto[0]	auto[1]	86	1			T15	3		T151	5		T23	3
all_values[14]	auto[1]	auto[1]	auto[1]	63	1			T15	1		T151	2		T23	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal