Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	615546	1			T1	15995		T2	2		T3	2
all_values[1]	615546	1			T1	15995		T2	2		T3	2
all_values[2]	615546	1			T1	15995		T2	2		T3	2
all_values[3]	615546	1			T1	15995		T2	2		T3	2
all_values[4]	615546	1			T1	15995		T2	2		T3	2
all_values[5]	615546	1			T1	15995		T2	2		T3	2
all_values[6]	615546	1			T1	15995		T2	2		T3	2
all_values[7]	615546	1			T1	15995		T2	2		T3	2
all_values[8]	615546	1			T1	15995		T2	2		T3	2
all_values[9]	615546	1			T1	15995		T2	2		T3	2
all_values[10]	615546	1			T1	15995		T2	2		T3	2
all_values[11]	615546	1			T1	15995		T2	2		T3	2
all_values[12]	615546	1			T1	15995		T2	2		T3	2
all_values[13]	615546	1			T1	15995		T2	2		T3	2
all_values[14]	615546	1			T1	15995		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7588417

1

T1

194185

T2

26

T3

26

auto[1]

1644773

1

T1

45740

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8753321

1

T1

239925

T2

30

T3

30

auto[1]

479869

1

T7

178352

T26

17531

T20

119

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	82305	1			T1	2071		T7	400		T10	1
all_values[0]	auto[0]	auto[1]	9308	1			T7	1673		T26	841		T20	7
all_values[0]	auto[1]	auto[0]	502485	1			T1	13924		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	21448	1			T7	10217		T26	412		T20	1
all_values[1]	auto[0]	auto[0]	583038	1			T1	15953		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	32107	1			T7	11886		T26	1247		T20	4
all_values[1]	auto[1]	auto[0]	228	1			T1	42		T242	8		T243	2
all_values[1]	auto[1]	auto[1]	173	1			T7	5		T26	3		T20	1
all_values[2]	auto[0]	auto[0]	583094	1			T1	15995		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	32101	1			T7	11887		T26	1250		T20	6
all_values[2]	auto[1]	auto[0]	193	1			T9	1		T127	1		T52	1
all_values[2]	auto[1]	auto[1]	158	1			T7	3		T26	3		T20	3
all_values[3]	auto[0]	auto[0]	583280	1			T1	15995		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	32085	1			T7	11886		T26	1248		T20	7
all_values[3]	auto[1]	auto[1]	181	1			T7	5		T26	5		T20	2
all_values[4]	auto[0]	auto[0]	583264	1			T1	15995		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	32102	1			T7	11887		T26	1249		T20	4
all_values[4]	auto[1]	auto[0]	13	1			T22	1		T24	1		T244	1
all_values[4]	auto[1]	auto[1]	167	1			T7	3		T26	4		T20	3
all_values[5]	auto[0]	auto[0]	583279	1			T1	15995		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	32091	1			T7	11888		T26	1251		T20	6
all_values[5]	auto[1]	auto[1]	176	1			T7	1		T26	1		T20	3
all_values[6]	auto[0]	auto[0]	583263	1			T1	15995		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	32102	1			T7	11888		T26	1246		T20	4
all_values[6]	auto[1]	auto[1]	181	1			T7	2		T26	3		T20	5
all_values[7]	auto[0]	auto[0]	560643	1			T1	15839		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	29183	1			T7	11617		T26	1053		T20	5
all_values[7]	auto[1]	auto[0]	22624	1			T1	156		T7	50		T21	147
all_values[7]	auto[1]	auto[1]	3096	1			T7	274		T26	200		T20	3
all_values[8]	auto[0]	auto[0]	583255	1			T1	15995		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	32087	1			T7	11885		T26	1250		T20	2
all_values[8]	auto[1]	auto[1]	204	1			T7	6		T26	3		T20	5
all_values[9]	auto[0]	auto[0]	123790	1			T1	363		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	12014	1			T7	1194		T26	1212		T20	4
all_values[9]	auto[1]	auto[0]	459498	1			T1	15632		T5	1		T7	7
all_values[9]	auto[1]	auto[1]	20244	1			T7	10697		T26	41		T20	3
all_values[10]	auto[0]	auto[0]	584506	1			T1	15995		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	30866	1			T7	11886		T20	4		T27	1162
all_values[10]	auto[1]	auto[1]	174	1			T7	4		T20	3		T27	7
all_values[11]	auto[0]	auto[0]	2301	1			T1	9		T7	7		T10	1
all_values[11]	auto[0]	auto[1]	306	1			T7	17		T26	1		T20	4
all_values[11]	auto[1]	auto[0]	580968	1			T1	15986		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	31971	1			T7	11869		T26	1252		T20	5
all_values[12]	auto[0]	auto[0]	584720	1			T1	15995		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	30600	1			T7	11887		T26	1250		T20	3
all_values[12]	auto[1]	auto[0]	65	1			T9	1		T52	1		T66	1
all_values[12]	auto[1]	auto[1]	161	1			T7	3		T26	1		T20	5
all_values[13]	auto[0]	auto[0]	583249	1			T1	15995		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	32094	1			T7	11885		T26	1248		T20	5
all_values[13]	auto[1]	auto[1]	203	1			T7	6		T26	4		T20	3
all_values[14]	auto[0]	auto[0]	583260	1			T1	15995		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	32124	1			T7	11891		T26	1251		T20	6
all_values[14]	auto[1]	auto[1]	162	1			T26	2		T20	3		T27	12