Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	615546	1			T1	15995		T2	2		T3	2
all_pins[1]	615546	1			T1	15995		T2	2		T3	2
all_pins[2]	615546	1			T1	15995		T2	2		T3	2
all_pins[3]	615546	1			T1	15995		T2	2		T3	2
all_pins[4]	615546	1			T1	15995		T2	2		T3	2
all_pins[5]	615546	1			T1	15995		T2	2		T3	2
all_pins[6]	615546	1			T1	15995		T2	2		T3	2
all_pins[7]	615546	1			T1	15995		T2	2		T3	2
all_pins[8]	615546	1			T1	15995		T2	2		T3	2
all_pins[9]	615546	1			T1	15995		T2	2		T3	2
all_pins[10]	615546	1			T1	15995		T2	2		T3	2
all_pins[11]	615546	1			T1	15995		T2	2		T3	2
all_pins[12]	615546	1			T1	15995		T2	2		T3	2
all_pins[13]	615546	1			T1	15995		T2	2		T3	2
all_pins[14]	615546	1			T1	15995		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7594035	1			T1	194131		T2	26		T3	26
values[0x1]	1639155	1			T1	45794		T2	4		T3	4
transitions[0x0=>0x1]	1638550	1			T1	45739		T2	4		T3	4
transitions[0x1=>0x0]	1637238	1			T1	45738		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	94974	1			T1	2070		T7	2075		T9	1
all_pins[0]	values[0x1]	520572	1			T1	13925		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	520295	1			T1	13870		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	85	1			T7	2		T20	1		T27	1
all_pins[1]	values[0x0]	615184	1			T1	15940		T2	2		T3	2
all_pins[1]	values[0x1]	362	1			T1	55		T7	2		T26	2
all_pins[1]	transitions[0x0=>0x1]	343	1			T1	55		T7	2		T26	2
all_pins[1]	transitions[0x1=>0x0]	117	1			T7	2		T26	1		T127	1
all_pins[2]	values[0x0]	615410	1			T1	15995		T2	2		T3	2
all_pins[2]	values[0x1]	136	1			T7	2		T26	1		T127	1
all_pins[2]	transitions[0x0=>0x1]	121	1			T7	1		T26	1		T127	1
all_pins[2]	transitions[0x1=>0x0]	80	1			T7	1		T26	1		T20	2
all_pins[3]	values[0x0]	615451	1			T1	15995		T2	2		T3	2
all_pins[3]	values[0x1]	95	1			T7	2		T26	1		T20	2
all_pins[3]	transitions[0x0=>0x1]	79	1			T7	2		T26	1		T20	2
all_pins[3]	transitions[0x1=>0x0]	94	1			T7	3		T22	1		T26	4
all_pins[4]	values[0x0]	615436	1			T1	15995		T2	2		T3	2
all_pins[4]	values[0x1]	110	1			T7	3		T22	1		T26	4
all_pins[4]	transitions[0x0=>0x1]	97	1			T7	3		T22	1		T26	4
all_pins[4]	transitions[0x1=>0x0]	78	1			T27	3		T30	3		T254	3
all_pins[5]	values[0x0]	615455	1			T1	15995		T2	2		T3	2
all_pins[5]	values[0x1]	91	1			T27	3		T30	3		T254	3
all_pins[5]	transitions[0x0=>0x1]	65	1			T27	2		T30	2		T254	1
all_pins[5]	transitions[0x1=>0x0]	64	1			T26	3		T20	4		T27	5
all_pins[6]	values[0x0]	615456	1			T1	15995		T2	2		T3	2
all_pins[6]	values[0x1]	90	1			T26	3		T20	4		T27	6
all_pins[6]	transitions[0x0=>0x1]	69	1			T26	3		T20	4		T27	6
all_pins[6]	transitions[0x1=>0x0]	28324	1			T1	196		T7	366		T21	147
all_pins[7]	values[0x0]	587201	1			T1	15799		T2	2		T3	2
all_pins[7]	values[0x1]	28345	1			T1	196		T7	366		T21	147
all_pins[7]	transitions[0x0=>0x1]	28320	1			T1	196		T7	366		T21	147
all_pins[7]	transitions[0x1=>0x0]	84	1			T20	4		T27	3		T30	2
all_pins[8]	values[0x0]	615437	1			T1	15995		T2	2		T3	2
all_pins[8]	values[0x1]	109	1			T26	2		T20	4		T27	4
all_pins[8]	transitions[0x0=>0x1]	73	1			T26	1		T20	3		T27	3
all_pins[8]	transitions[0x1=>0x0]	479658	1			T1	15632		T5	1		T7	10703
all_pins[9]	values[0x0]	135852	1			T1	363		T2	2		T3	2
all_pins[9]	values[0x1]	479694	1			T1	15632		T5	1		T7	10703
all_pins[9]	transitions[0x0=>0x1]	479675	1			T1	15632		T5	1		T7	10702
all_pins[9]	transitions[0x1=>0x0]	59	1			T20	1		T27	3		T30	3
all_pins[10]	values[0x0]	615468	1			T1	15995		T2	2		T3	2
all_pins[10]	values[0x1]	78	1			T7	1		T20	1		T27	4
all_pins[10]	transitions[0x0=>0x1]	57	1			T7	1		T27	2		T30	3
all_pins[10]	transitions[0x1=>0x0]	609094	1			T1	15986		T2	2		T3	2
all_pins[11]	values[0x0]	6431	1			T1	9		T7	24		T9	1
all_pins[11]	values[0x1]	609115	1			T1	15986		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	609074	1			T1	15986		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	115	1			T7	2		T9	1		T52	1
all_pins[12]	values[0x0]	615390	1			T1	15995		T2	2		T3	2
all_pins[12]	values[0x1]	156	1			T7	2		T9	1		T26	1
all_pins[12]	transitions[0x0=>0x1]	133	1			T7	1		T9	1		T26	1
all_pins[12]	transitions[0x1=>0x0]	92	1			T7	3		T26	2		T20	2
all_pins[13]	values[0x0]	615431	1			T1	15995		T2	2		T3	2
all_pins[13]	values[0x1]	115	1			T7	4		T26	2		T20	2
all_pins[13]	transitions[0x0=>0x1]	89	1			T7	4		T26	2		T20	2
all_pins[13]	transitions[0x1=>0x0]	61	1			T27	4		T254	3		T124	2
all_pins[14]	values[0x0]	615459	1			T1	15995		T2	2		T3	2
all_pins[14]	values[0x1]	87	1			T27	8		T30	1		T254	3
all_pins[14]	transitions[0x0=>0x1]	60	1			T27	5		T254	2		T124	2
all_pins[14]	transitions[0x1=>0x0]	519233	1			T1	13924		T2	1		T3	1