Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	390	1			T7	7		T26	7		T20	7
all_values[1]	390	1			T7	7		T26	7		T20	7
all_values[2]	390	1			T7	7		T26	7		T20	7
all_values[3]	390	1			T7	7		T26	7		T20	7
all_values[4]	390	1			T7	7		T26	7		T20	7
all_values[5]	390	1			T7	7		T26	7		T20	7
all_values[6]	390	1			T7	7		T26	7		T20	7
all_values[7]	390	1			T7	7		T26	7		T20	7
all_values[8]	390	1			T7	7		T26	7		T20	7
all_values[9]	390	1			T7	7		T26	7		T20	7
all_values[10]	390	1			T7	7		T26	7		T20	7
all_values[11]	390	1			T7	7		T26	7		T20	7
all_values[12]	390	1			T7	7		T26	7		T20	7
all_values[13]	390	1			T7	7		T26	7		T20	7
all_values[14]	390	1			T7	7		T26	7		T20	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3039

1

T7

63

T26

66

T20

60

auto[1]

2811

1

T7

42

T26

39

T20

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931

1

T7

13

T26

18

T20

16

auto[1]

4919

1

T7

92

T26

87

T20

89

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3413

1

T7

61

T26

63

T20

61

auto[1]

2437

1

T7

44

T26

42

T20

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	46	1			T7	1		T20	1		T254	1
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T7	1		T26	3		T20	3
all_values[0]	auto[0]	auto[1]	auto[0]	30	1			T25	3		T255	1		T256	3
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T7	3		T26	1		T20	2
all_values[0]	auto[1]	auto[0]	auto[1]	84	1			T26	3		T20	1		T27	2
all_values[0]	auto[1]	auto[1]	auto[1]	70	1			T7	2		T27	4		T30	4
all_values[1]	auto[0]	auto[0]	auto[0]	38	1			T26	3		T20	4		T30	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T7	2		T26	2		T27	6
all_values[1]	auto[0]	auto[1]	auto[0]	20	1			T257	2		T258	1		T259	1
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T20	2		T27	2		T30	6
all_values[1]	auto[1]	auto[0]	auto[1]	92	1			T7	1		T26	1		T20	1
all_values[1]	auto[1]	auto[1]	auto[1]	80	1			T7	4		T26	1		T27	4
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T7	1		T30	2		T254	3
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T7	1		T26	1		T20	3
all_values[2]	auto[0]	auto[1]	auto[0]	35	1			T254	1		T124	3		T260	3
all_values[2]	auto[0]	auto[1]	auto[1]	88	1			T7	2		T26	3		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	70	1			T7	1		T26	1		T20	2
all_values[2]	auto[1]	auto[1]	auto[1]	88	1			T7	2		T26	2		T20	1
all_values[3]	auto[0]	auto[0]	auto[0]	35	1			T125	1		T257	1		T258	2
all_values[3]	auto[0]	auto[0]	auto[1]	67	1			T7	1		T26	3		T20	1
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T27	3		T261	3		T259	4
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T7	1		T26	1		T20	3
all_values[3]	auto[1]	auto[0]	auto[1]	88	1			T7	3		T26	3		T20	2
all_values[3]	auto[1]	auto[1]	auto[1]	79	1			T7	2		T20	1		T27	3
all_values[4]	auto[0]	auto[0]	auto[0]	45	1			T7	1		T20	2		T262	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T7	2		T26	2		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	23	1			T27	1		T124	1		T262	2
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T7	1		T26	1		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T20	2		T27	1		T30	4
all_values[4]	auto[1]	auto[1]	auto[1]	72	1			T7	3		T26	4		T20	1
all_values[5]	auto[0]	auto[0]	auto[0]	41	1			T7	1		T26	1		T263	4
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T7	4		T26	3		T20	3
all_values[5]	auto[0]	auto[1]	auto[0]	28	1			T7	1		T124	2		T125	2
all_values[5]	auto[0]	auto[1]	auto[1]	84	1			T20	2		T27	4		T30	7
all_values[5]	auto[1]	auto[0]	auto[1]	89	1			T7	1		T26	3		T20	2
all_values[5]	auto[1]	auto[1]	auto[1]	70	1			T27	1		T30	4		T254	2
all_values[6]	auto[0]	auto[0]	auto[0]	44	1			T7	1		T26	3		T30	1
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T7	1		T20	1		T27	2
all_values[6]	auto[0]	auto[1]	auto[0]	12	1			T26	1		T27	1		T258	1
all_values[6]	auto[0]	auto[1]	auto[1]	96	1			T7	3		T26	2		T20	2
all_values[6]	auto[1]	auto[0]	auto[1]	90	1			T7	2		T20	1		T27	3
all_values[6]	auto[1]	auto[1]	auto[1]	63	1			T26	1		T20	3		T27	4
all_values[7]	auto[0]	auto[0]	auto[0]	34	1			T20	1		T30	1		T254	1
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T26	3		T20	1		T27	5
all_values[7]	auto[0]	auto[1]	auto[0]	23	1			T124	2		T125	1		T257	2
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T7	4		T26	2		T20	2
all_values[7]	auto[1]	auto[0]	auto[1]	98	1			T7	2		T26	1		T20	2
all_values[7]	auto[1]	auto[1]	auto[1]	60	1			T7	1		T26	1		T20	1
all_values[8]	auto[0]	auto[0]	auto[0]	27	1			T20	1		T262	1		T125	2
all_values[8]	auto[0]	auto[0]	auto[1]	84	1			T7	3		T27	4		T30	5
all_values[8]	auto[0]	auto[1]	auto[0]	20	1			T20	1		T27	2		T30	1
all_values[8]	auto[0]	auto[1]	auto[1]	87	1			T26	2		T20	1		T27	2
all_values[8]	auto[1]	auto[0]	auto[1]	90	1			T7	4		T26	4		T27	1
all_values[8]	auto[1]	auto[1]	auto[1]	82	1			T26	1		T20	4		T27	5
all_values[9]	auto[0]	auto[0]	auto[0]	45	1			T20	2		T254	1		T124	2
all_values[9]	auto[0]	auto[0]	auto[1]	74	1			T7	3		T26	1		T20	2
all_values[9]	auto[0]	auto[1]	auto[0]	31	1			T254	1		T124	2		T258	4
all_values[9]	auto[0]	auto[1]	auto[1]	89	1			T7	2		T26	1		T20	1
all_values[9]	auto[1]	auto[0]	auto[1]	87	1			T7	1		T26	3		T20	2
all_values[9]	auto[1]	auto[1]	auto[1]	64	1			T7	1		T26	2		T27	2
all_values[10]	auto[0]	auto[0]	auto[0]	35	1			T7	1		T26	5		T20	2
all_values[10]	auto[0]	auto[0]	auto[1]	75	1			T7	2		T20	1		T27	1
all_values[10]	auto[0]	auto[1]	auto[0]	18	1			T26	2		T262	1		T264	1
all_values[10]	auto[0]	auto[1]	auto[1]	88	1			T20	1		T27	6		T30	8
all_values[10]	auto[1]	auto[0]	auto[1]	99	1			T7	3		T20	2		T27	3
all_values[10]	auto[1]	auto[1]	auto[1]	75	1			T7	1		T20	1		T27	4
all_values[11]	auto[0]	auto[0]	auto[0]	30	1			T7	2		T30	3		T263	3
all_values[11]	auto[0]	auto[0]	auto[1]	69	1			T26	1		T20	2		T27	6
all_values[11]	auto[0]	auto[1]	auto[0]	29	1			T7	3		T30	1		T263	1
all_values[11]	auto[0]	auto[1]	auto[1]	88	1			T7	1		T26	2		T27	2
all_values[11]	auto[1]	auto[0]	auto[1]	87	1			T26	3		T20	1		T30	6
all_values[11]	auto[1]	auto[1]	auto[1]	87	1			T7	1		T26	1		T20	4
all_values[12]	auto[0]	auto[0]	auto[0]	45	1			T7	1		T26	2		T20	1
all_values[12]	auto[0]	auto[0]	auto[1]	84	1			T7	3		T26	3		T20	1
all_values[12]	auto[0]	auto[1]	auto[0]	28	1			T27	1		T30	6		T124	1
all_values[12]	auto[0]	auto[1]	auto[1]	72	1			T26	1		T27	6		T30	1
all_values[12]	auto[1]	auto[0]	auto[1]	78	1			T7	1		T26	1		T20	2
all_values[12]	auto[1]	auto[1]	auto[1]	83	1			T7	2		T20	3		T27	3
all_values[13]	auto[0]	auto[0]	auto[0]	31	1			T26	1		T20	1		T30	1
all_values[13]	auto[0]	auto[0]	auto[1]	81	1			T7	1		T26	3		T27	5
all_values[13]	auto[0]	auto[1]	auto[0]	11	1			T124	1		T259	1		T265	1
all_values[13]	auto[0]	auto[1]	auto[1]	100	1			T7	1		T26	1		T20	4
all_values[13]	auto[1]	auto[0]	auto[1]	80	1			T7	5		T26	1		T20	1
all_values[13]	auto[1]	auto[1]	auto[1]	87	1			T26	1		T20	1		T27	3
all_values[14]	auto[0]	auto[0]	auto[0]	28	1			T262	1		T125	1		T25	1
all_values[14]	auto[0]	auto[0]	auto[1]	76	1			T7	5		T26	1		T20	2
all_values[14]	auto[0]	auto[1]	auto[0]	25	1			T27	1		T262	3		T25	1
all_values[14]	auto[0]	auto[1]	auto[1]	97	1			T7	1		T26	2		T20	2
all_values[14]	auto[1]	auto[0]	auto[1]	86	1			T7	1		T26	1		T20	3
all_values[14]	auto[1]	auto[1]	auto[1]	78	1			T26	3		T27	7		T30	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal