Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	719852	1			T1	3		T2	3		T3	3
all_values[1]	719852	1			T1	3		T2	3		T3	3
all_values[2]	719852	1			T1	3		T2	3		T3	3
all_values[3]	719852	1			T1	3		T2	3		T3	3
all_values[4]	719852	1			T1	3		T2	3		T3	3
all_values[5]	719852	1			T1	3		T2	3		T3	3
all_values[6]	719852	1			T1	3		T2	3		T3	3
all_values[7]	719852	1			T1	3		T2	3		T3	3
all_values[8]	719852	1			T1	3		T2	3		T3	3
all_values[9]	719852	1			T1	3		T2	3		T3	3
all_values[10]	719852	1			T1	3		T2	3		T3	3
all_values[11]	719852	1			T1	3		T2	3		T3	3
all_values[12]	719852	1			T1	3		T2	3		T3	3
all_values[13]	719852	1			T1	3		T2	3		T3	3
all_values[14]	719852	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8888422

1

T1

39

T2

36

T3

40

auto[1]

1909358

1

T1

6

T2

9

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9437876

1

T1

45

T2

45

T3

45

auto[1]

1359904

1

T38

83184

T96

113

T28

593

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	87795	1			T1	1		T3	1		T7	516
all_values[0]	auto[0]	auto[1]	13684	1			T38	49		T28	37		T36	1822
all_values[0]	auto[1]	auto[0]	540541	1			T1	2		T2	3		T3	2
all_values[0]	auto[1]	auto[1]	77832	1			T38	6350		T96	5		T28	8
all_values[1]	auto[0]	auto[0]	628187	1			T1	3		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	91367	1			T38	6397		T96	3		T28	44
all_values[1]	auto[1]	auto[0]	128	1			T96	12		T252	1		T253	2
all_values[1]	auto[1]	auto[1]	170	1			T38	2		T96	2		T28	1
all_values[2]	auto[0]	auto[0]	628133	1			T1	3		T2	1		T3	3
all_values[2]	auto[0]	auto[1]	91369	1			T38	6397		T96	5		T28	44
all_values[2]	auto[1]	auto[0]	187	1			T2	2		T58	1		T57	1
all_values[2]	auto[1]	auto[1]	163	1			T38	2		T96	4		T28	2
all_values[3]	auto[0]	auto[0]	628342	1			T1	3		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	91349	1			T38	6395		T96	6		T28	45
all_values[3]	auto[1]	auto[1]	161	1			T38	4		T28	1		T36	3
all_values[4]	auto[0]	auto[0]	628291	1			T1	3		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	91357	1			T38	6396		T96	4		T28	44
all_values[4]	auto[1]	auto[0]	30	1			T22	1		T23	2		T177	1
all_values[4]	auto[1]	auto[1]	174	1			T38	1		T96	1		T28	2
all_values[5]	auto[0]	auto[0]	628388	1			T1	3		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	91287	1			T38	6398		T96	3		T36	17870
all_values[5]	auto[1]	auto[1]	177	1			T38	1		T96	6		T36	3
all_values[6]	auto[0]	auto[0]	628325	1			T1	3		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	91347	1			T38	6395		T96	6		T28	44
all_values[6]	auto[1]	auto[1]	180	1			T38	4		T96	3		T28	2
all_values[7]	auto[0]	auto[0]	609915	1			T1	2		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	82696	1			T96	7		T28	40		T36	17604
all_values[7]	auto[1]	auto[0]	24816	1			T1	1		T7	92		T20	158
all_values[7]	auto[1]	auto[1]	2425	1			T96	2		T28	6		T36	266
all_values[8]	auto[0]	auto[0]	628330	1			T1	3		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	91352	1			T38	6397		T96	6		T28	44
all_values[8]	auto[1]	auto[1]	170	1			T38	1		T96	2		T36	8
all_values[9]	auto[0]	auto[0]	164088	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	11487	1			T38	1042		T96	8		T28	42
all_values[9]	auto[1]	auto[0]	464262	1			T1	1		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	80015	1			T38	5357		T96	1		T28	4
all_values[10]	auto[0]	auto[0]	628362	1			T1	3		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	91344	1			T38	6396		T96	8		T36	17870
all_values[10]	auto[1]	auto[1]	146	1			T38	3		T96	1		T36	5
all_values[11]	auto[0]	auto[0]	2313	1			T1	1		T3	1		T7	4
all_values[11]	auto[0]	auto[1]	312	1			T38	14		T28	38		T36	32
all_values[11]	auto[1]	auto[0]	626034	1			T1	2		T2	3		T3	2
all_values[11]	auto[1]	auto[1]	91193	1			T38	6385		T96	5		T28	8
all_values[12]	auto[0]	auto[0]	634665	1			T1	3		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	84968	1			T96	5		T28	43		T36	17869
all_values[12]	auto[1]	auto[0]	68	1			T58	1		T57	1		T68	1
all_values[12]	auto[1]	auto[1]	151	1			T96	3		T28	3		T36	5
all_values[13]	auto[0]	auto[0]	628340	1			T1	3		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	91348	1			T38	6395		T96	6		T28	44
all_values[13]	auto[1]	auto[1]	164	1			T38	4		T96	3		T28	1
all_values[14]	auto[0]	auto[0]	628336	1			T1	3		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	91345	1			T38	6396		T96	6		T28	43
all_values[14]	auto[1]	auto[1]	171	1			T38	3		T96	2		T28	3