Group : i2c_env_pkg::i2c_scl_stretch_cg
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Group : i2c_env_pkg::i2c_scl_stretch_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv


Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group i2c_env_pkg::i2c_scl_stretch_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_fifo_size 2 0 2 100.00 100 1 1 0
cp_host_mode_stretch 1 0 1 100.00 100 1 1 0
cp_target_scl_stretch_addr_write 1 0 1 100.00 100 1 1 0
cp_tx_fifo_size 2 0 2 100.00 100 1 1 0


Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_target_scl_stretch_read 4 0 4 100.00 100 1 1 0


Summary for Variable cp_acq_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_acq_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 121818745 1 T5 2796 T6 10002 T8 910
empty 63116978 1 T1 272284 T5 226 T7 114257


Summary for Variable cp_host_mode_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stretch 41166770 1 T1 180410 T7 632922 T20 196077


Summary for Variable cp_target_scl_stretch_addr_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_target_scl_stretch_addr_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
addr_write_byte_stretch 608018 1 T50 7290 T55 43 T58 1


Summary for Variable cp_tx_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_tx_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 5219525 1 T5 1778 T6 9846 T8 631
empty 179779934 1 T1 272284 T5 1244 T6 156


Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for cp_target_scl_stretch_read

Bins
cp_acq_fifo_sizecp_tx_fifo_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
empty not_empty 2122 1 T270 20 T271 166 T272 56
empty empty 351425 1 T5 226 T9 56 T64 261


User Defined Cross Bins for cp_target_scl_stretch_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_byte_stretch 305515 1 T5 1018 T6 156 T8 95
scl_stretch_read_request 5522062 1 T5 2796 T6 10002 T8 726

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