Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	719852	1			T1	3		T2	3		T3	3
all_pins[1]	719852	1			T1	3		T2	3		T3	3
all_pins[2]	719852	1			T1	3		T2	3		T3	3
all_pins[3]	719852	1			T1	3		T2	3		T3	3
all_pins[4]	719852	1			T1	3		T2	3		T3	3
all_pins[5]	719852	1			T1	3		T2	3		T3	3
all_pins[6]	719852	1			T1	3		T2	3		T3	3
all_pins[7]	719852	1			T1	3		T2	3		T3	3
all_pins[8]	719852	1			T1	3		T2	3		T3	3
all_pins[9]	719852	1			T1	3		T2	3		T3	3
all_pins[10]	719852	1			T1	3		T2	3		T3	3
all_pins[11]	719852	1			T1	3		T2	3		T3	3
all_pins[12]	719852	1			T1	3		T2	3		T3	3
all_pins[13]	719852	1			T1	3		T2	3		T3	3
all_pins[14]	719852	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8895370	1			T1	39		T2	40		T3	40
values[0x1]	1902410	1			T1	6		T2	5		T3	5
transitions[0x0=>0x1]	1901933	1			T1	6		T2	5		T3	5
transitions[0x1=>0x0]	1900618	1			T1	5		T2	4		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	105348	1			T1	1		T3	1		T7	516
all_pins[0]	values[0x1]	614504	1			T1	2		T2	3		T3	2
all_pins[0]	transitions[0x0=>0x1]	614319	1			T1	2		T2	3		T3	2
all_pins[0]	transitions[0x1=>0x0]	51	1			T38	2		T28	1		T36	1
all_pins[1]	values[0x0]	719616	1			T1	3		T2	3		T3	3
all_pins[1]	values[0x1]	236	1			T38	2		T96	16		T252	1
all_pins[1]	transitions[0x0=>0x1]	222	1			T38	2		T96	15		T252	1
all_pins[1]	transitions[0x1=>0x0]	107	1			T58	1		T145	1		T260	1
all_pins[2]	values[0x0]	719731	1			T1	3		T2	3		T3	3
all_pins[2]	values[0x1]	121	1			T58	1		T145	1		T260	1
all_pins[2]	transitions[0x0=>0x1]	107	1			T58	1		T145	1		T260	1
all_pins[2]	transitions[0x1=>0x0]	69	1			T38	1		T36	2		T218	6
all_pins[3]	values[0x0]	719769	1			T1	3		T2	3		T3	3
all_pins[3]	values[0x1]	83	1			T38	1		T28	1		T36	2
all_pins[3]	transitions[0x0=>0x1]	60	1			T38	1		T28	1		T36	1
all_pins[3]	transitions[0x1=>0x0]	91	1			T22	2		T38	1		T96	1
all_pins[4]	values[0x0]	719738	1			T1	3		T2	3		T3	3
all_pins[4]	values[0x1]	114	1			T22	2		T38	1		T96	1
all_pins[4]	transitions[0x0=>0x1]	95	1			T22	2		T38	1		T96	1
all_pins[4]	transitions[0x1=>0x0]	70	1			T96	5		T36	1		T218	2
all_pins[5]	values[0x0]	719763	1			T1	3		T2	3		T3	3
all_pins[5]	values[0x1]	89	1			T96	5		T36	1		T218	6
all_pins[5]	transitions[0x0=>0x1]	70	1			T96	5		T36	1		T218	4
all_pins[5]	transitions[0x1=>0x0]	55	1			T96	1		T36	1		T218	2
all_pins[6]	values[0x0]	719778	1			T1	3		T2	3		T3	3
all_pins[6]	values[0x1]	74	1			T96	1		T36	1		T218	4
all_pins[6]	transitions[0x0=>0x1]	57	1			T96	1		T36	1		T218	4
all_pins[6]	transitions[0x1=>0x0]	29576	1			T1	1		T7	99		T20	184
all_pins[7]	values[0x0]	690259	1			T1	2		T2	3		T3	3
all_pins[7]	values[0x1]	29593	1			T1	1		T7	99		T20	184
all_pins[7]	transitions[0x0=>0x1]	29579	1			T1	1		T7	99		T20	184
all_pins[7]	transitions[0x1=>0x0]	67	1			T38	1		T96	1		T36	4
all_pins[8]	values[0x0]	719771	1			T1	3		T2	3		T3	3
all_pins[8]	values[0x1]	81	1			T38	1		T96	2		T36	4
all_pins[8]	transitions[0x0=>0x1]	68	1			T96	2		T36	2		T218	4
all_pins[8]	transitions[0x1=>0x0]	544201	1			T1	1		T2	1		T3	1
all_pins[9]	values[0x0]	175638	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	544214	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x0=>0x1]	544192	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x1=>0x0]	58	1			T96	1		T218	5		T118	2
all_pins[10]	values[0x0]	719772	1			T1	3		T2	3		T3	3
all_pins[10]	values[0x1]	80	1			T38	3		T96	1		T218	8
all_pins[10]	transitions[0x0=>0x1]	50	1			T38	2		T218	3		T118	2
all_pins[10]	transitions[0x1=>0x0]	712873	1			T1	2		T2	1		T3	2
all_pins[11]	values[0x0]	6949	1			T1	1		T2	2		T3	1
all_pins[11]	values[0x1]	712903	1			T1	2		T2	1		T3	2
all_pins[11]	transitions[0x0=>0x1]	712858	1			T1	2		T2	1		T3	2
all_pins[11]	transitions[0x1=>0x0]	98	1			T57	1		T68	1		T96	1
all_pins[12]	values[0x0]	719709	1			T1	3		T2	3		T3	3
all_pins[12]	values[0x1]	143	1			T58	1		T57	1		T68	1
all_pins[12]	transitions[0x0=>0x1]	128	1			T58	1		T57	1		T68	1
all_pins[12]	transitions[0x1=>0x0]	73	1			T38	4		T96	1		T36	2
all_pins[13]	values[0x0]	719764	1			T1	3		T2	3		T3	3
all_pins[13]	values[0x1]	88	1			T38	4		T96	1		T36	2
all_pins[13]	transitions[0x0=>0x1]	66	1			T38	2		T96	1		T36	2
all_pins[13]	transitions[0x1=>0x0]	65	1			T96	1		T36	2		T218	8
all_pins[14]	values[0x0]	719765	1			T1	3		T2	3		T3	3
all_pins[14]	values[0x1]	87	1			T38	2		T96	1		T36	2
all_pins[14]	transitions[0x0=>0x1]	62	1			T38	2		T36	2		T218	5
all_pins[14]	transitions[0x1=>0x0]	613164	1			T1	1		T2	2		T3	1