Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	380	1			T38	4		T96	7		T28	4
all_values[1]	380	1			T38	4		T96	7		T28	4
all_values[2]	380	1			T38	4		T96	7		T28	4
all_values[3]	380	1			T38	4		T96	7		T28	4
all_values[4]	380	1			T38	4		T96	7		T28	4
all_values[5]	380	1			T38	4		T96	7		T28	4
all_values[6]	380	1			T38	4		T96	7		T28	4
all_values[7]	380	1			T38	4		T96	7		T28	4
all_values[8]	380	1			T38	4		T96	7		T28	4
all_values[9]	380	1			T38	4		T96	7		T28	4
all_values[10]	380	1			T38	4		T96	7		T28	4
all_values[11]	380	1			T38	4		T96	7		T28	4
all_values[12]	380	1			T38	4		T96	7		T28	4
all_values[13]	380	1			T38	4		T96	7		T28	4
all_values[14]	380	1			T38	4		T96	7		T28	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3033

1

T38

28

T96

39

T28

32

auto[1]

2667

1

T38

32

T96

66

T28

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

904

1

T38

11

T96

22

T28

13

auto[1]

4796

1

T38

49

T96

83

T28

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3398

1

T38

36

T96

66

T28

33

auto[1]

2302

1

T38

24

T96

39

T28

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T96	2		T218	1		T118	2
all_values[0]	auto[0]	auto[0]	auto[1]	79	1			T38	3		T96	1		T28	1
all_values[0]	auto[0]	auto[1]	auto[0]	29	1			T96	2		T28	1		T218	1
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T36	2		T218	6		T120	5
all_values[0]	auto[1]	auto[0]	auto[1]	96	1			T38	1		T96	1		T28	2
all_values[0]	auto[1]	auto[1]	auto[1]	67	1			T96	1		T218	5		T118	1
all_values[1]	auto[0]	auto[0]	auto[0]	24	1			T96	2		T218	1		T261	1
all_values[1]	auto[0]	auto[0]	auto[1]	87	1			T38	2		T96	1		T28	1
all_values[1]	auto[0]	auto[1]	auto[0]	21	1			T96	2		T28	1		T218	1
all_values[1]	auto[0]	auto[1]	auto[1]	96	1			T28	1		T36	3		T218	4
all_values[1]	auto[1]	auto[0]	auto[1]	88	1			T96	1		T36	3		T218	6
all_values[1]	auto[1]	auto[1]	auto[1]	64	1			T38	2		T96	1		T28	1
all_values[2]	auto[0]	auto[0]	auto[0]	26	1			T119	2		T262	1		T263	1
all_values[2]	auto[0]	auto[0]	auto[1]	96	1			T96	1		T28	2		T36	3
all_values[2]	auto[0]	auto[1]	auto[0]	20	1			T119	1		T120	1		T263	1
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T38	2		T96	2		T36	4
all_values[2]	auto[1]	auto[0]	auto[1]	97	1			T38	2		T96	3		T28	1
all_values[2]	auto[1]	auto[1]	auto[1]	66	1			T96	1		T28	1		T36	1
all_values[3]	auto[0]	auto[0]	auto[0]	37	1			T96	2		T36	1		T264	1
all_values[3]	auto[0]	auto[0]	auto[1]	92	1			T38	2		T96	1		T36	6
all_values[3]	auto[0]	auto[1]	auto[0]	30	1			T96	1		T118	2		T119	1
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T96	1		T28	2		T36	2
all_values[3]	auto[1]	auto[0]	auto[1]	70	1			T38	2		T36	1		T218	5
all_values[3]	auto[1]	auto[1]	auto[1]	70	1			T96	2		T28	2		T36	2
all_values[4]	auto[0]	auto[0]	auto[0]	22	1			T36	1		T262	1		T264	2
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T28	2		T36	2		T218	2
all_values[4]	auto[0]	auto[1]	auto[0]	28	1			T38	2		T96	4		T119	1
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T38	1		T96	2		T36	4
all_values[4]	auto[1]	auto[0]	auto[1]	104	1			T96	1		T28	1		T36	4
all_values[4]	auto[1]	auto[1]	auto[1]	70	1			T38	1		T28	1		T36	1
all_values[5]	auto[0]	auto[0]	auto[0]	46	1			T28	3		T36	2		T218	1
all_values[5]	auto[0]	auto[0]	auto[1]	84	1			T38	1		T36	6		T218	6
all_values[5]	auto[0]	auto[1]	auto[0]	25	1			T28	1		T218	3		T118	1
all_values[5]	auto[0]	auto[1]	auto[1]	78	1			T38	2		T96	3		T36	2
all_values[5]	auto[1]	auto[0]	auto[1]	73	1			T38	1		T36	1		T218	4
all_values[5]	auto[1]	auto[1]	auto[1]	74	1			T96	4		T36	1		T218	8
all_values[6]	auto[0]	auto[0]	auto[0]	30	1			T36	3		T218	5		T120	1
all_values[6]	auto[0]	auto[0]	auto[1]	91	1			T38	2		T96	3		T36	1
all_values[6]	auto[0]	auto[1]	auto[0]	22	1			T36	1		T218	3		T118	1
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T28	1		T36	2		T218	3
all_values[6]	auto[1]	auto[0]	auto[1]	89	1			T38	2		T96	2		T28	2
all_values[6]	auto[1]	auto[1]	auto[1]	77	1			T96	2		T28	1		T36	1
all_values[7]	auto[0]	auto[0]	auto[0]	34	1			T36	4		T120	1		T263	1
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T96	1		T28	1		T36	2
all_values[7]	auto[0]	auto[1]	auto[0]	30	1			T38	4		T118	1		T119	5
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T96	3		T36	2		T218	9
all_values[7]	auto[1]	auto[0]	auto[1]	86	1			T28	2		T36	2		T218	5
all_values[7]	auto[1]	auto[1]	auto[1]	68	1			T96	3		T28	1		T36	2
all_values[8]	auto[0]	auto[0]	auto[0]	30	1			T28	1		T36	1		T218	2
all_values[8]	auto[0]	auto[0]	auto[1]	83	1			T38	2		T96	2		T36	3
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T38	1		T96	1		T28	1
all_values[8]	auto[0]	auto[1]	auto[1]	85	1			T96	2		T28	1		T36	3
all_values[8]	auto[1]	auto[0]	auto[1]	80	1			T28	1		T36	1		T218	4
all_values[8]	auto[1]	auto[1]	auto[1]	74	1			T38	1		T96	2		T36	3
all_values[9]	auto[0]	auto[0]	auto[0]	47	1			T218	1		T118	2		T119	2
all_values[9]	auto[0]	auto[0]	auto[1]	95	1			T28	2		T36	4		T218	4
all_values[9]	auto[0]	auto[1]	auto[0]	30	1			T218	1		T119	3		T262	1
all_values[9]	auto[0]	auto[1]	auto[1]	68	1			T38	1		T96	4		T36	4
all_values[9]	auto[1]	auto[0]	auto[1]	72	1			T28	1		T36	2		T218	2
all_values[9]	auto[1]	auto[1]	auto[1]	68	1			T38	3		T96	3		T28	1
all_values[10]	auto[0]	auto[0]	auto[0]	31	1			T28	2		T120	1		T264	1
all_values[10]	auto[0]	auto[0]	auto[1]	96	1			T96	1		T36	7		T218	5
all_values[10]	auto[0]	auto[1]	auto[0]	16	1			T28	2		T263	3		T265	1
all_values[10]	auto[0]	auto[1]	auto[1]	91	1			T38	1		T96	5		T218	11
all_values[10]	auto[1]	auto[0]	auto[1]	66	1			T36	4		T218	3		T120	2
all_values[10]	auto[1]	auto[1]	auto[1]	80	1			T38	3		T96	1		T36	1
all_values[11]	auto[0]	auto[0]	auto[0]	38	1			T96	2		T120	1		T121	3
all_values[11]	auto[0]	auto[0]	auto[1]	80	1			T38	2		T96	1		T28	1
all_values[11]	auto[0]	auto[1]	auto[0]	33	1			T96	2		T118	1		T120	1
all_values[11]	auto[0]	auto[1]	auto[1]	79	1			T38	1		T28	1		T36	5
all_values[11]	auto[1]	auto[0]	auto[1]	76	1			T36	4		T218	3		T120	6
all_values[11]	auto[1]	auto[1]	auto[1]	74	1			T38	1		T96	2		T28	2
all_values[12]	auto[0]	auto[0]	auto[0]	36	1			T38	4		T36	1		T218	1
all_values[12]	auto[0]	auto[0]	auto[1]	82	1			T96	1		T28	1		T36	2
all_values[12]	auto[0]	auto[1]	auto[0]	28	1			T96	1		T121	1		T263	2
all_values[12]	auto[0]	auto[1]	auto[1]	83	1			T96	2		T36	4		T218	6
all_values[12]	auto[1]	auto[0]	auto[1]	87	1			T96	2		T28	2		T36	2
all_values[12]	auto[1]	auto[1]	auto[1]	64	1			T96	1		T28	1		T36	3
all_values[13]	auto[0]	auto[0]	auto[0]	34	1			T218	1		T266	1		T263	3
all_values[13]	auto[0]	auto[0]	auto[1]	73	1			T96	3		T36	3		T218	6
all_values[13]	auto[0]	auto[1]	auto[0]	32	1			T28	1		T266	3		T121	1
all_values[13]	auto[0]	auto[1]	auto[1]	92	1			T38	1		T96	1		T28	1
all_values[13]	auto[1]	auto[0]	auto[1]	85	1			T96	1		T28	2		T36	2
all_values[13]	auto[1]	auto[1]	auto[1]	64	1			T38	3		T96	2		T36	3
all_values[14]	auto[0]	auto[0]	auto[0]	40	1			T96	1		T36	1		T119	1
all_values[14]	auto[0]	auto[0]	auto[1]	78	1			T38	1		T96	2		T28	1
all_values[14]	auto[0]	auto[1]	auto[0]	23	1			T118	1		T119	1		T120	1
all_values[14]	auto[0]	auto[1]	auto[1]	86	1			T38	1		T96	1		T28	1
all_values[14]	auto[1]	auto[0]	auto[1]	75	1			T38	1		T96	1		T36	1
all_values[14]	auto[1]	auto[1]	auto[1]	78	1			T38	1		T96	2		T28	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal