Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	635628	1			T1	2		T2	69		T3	1
all_values[1]	635628	1			T1	2		T2	69		T3	1
all_values[2]	635628	1			T1	2		T2	69		T3	1
all_values[3]	635628	1			T1	2		T2	69		T3	1
all_values[4]	635628	1			T1	2		T2	69		T3	1
all_values[5]	635628	1			T1	2		T2	69		T3	1
all_values[6]	635628	1			T1	2		T2	69		T3	1
all_values[7]	635628	1			T1	2		T2	69		T3	1
all_values[8]	635628	1			T1	2		T2	69		T3	1
all_values[9]	635628	1			T1	2		T2	69		T3	1
all_values[10]	635628	1			T1	2		T2	69		T3	1
all_values[11]	635628	1			T1	2		T2	69		T3	1
all_values[12]	635628	1			T1	2		T2	69		T3	1
all_values[13]	635628	1			T1	2		T2	69		T3	1
all_values[14]	635628	1			T1	2		T2	69		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7842781

1

T1

24

T2

925

T3

15

auto[1]

1691639

1

T1

6

T2

110

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9316766

1

T1

30

T2

1035

T3

15

auto[1]

217654

1

T83

68

T40

55695

T113

10372

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85846	1			T2	33		T3	1		T5	9
all_values[0]	auto[0]	auto[1]	3766	1			T83	4		T40	532		T113	512
all_values[0]	auto[1]	auto[0]	533834	1			T1	2		T2	36		T4	2
all_values[0]	auto[1]	auto[1]	12182	1			T83	1		T40	3753		T113	180
all_values[1]	auto[0]	auto[0]	619499	1			T1	2		T2	69		T3	1
all_values[1]	auto[0]	auto[1]	15768	1			T40	4282		T113	682		T42	10
all_values[1]	auto[1]	auto[0]	200	1			T267	1		T83	1		T250	1
all_values[1]	auto[1]	auto[1]	161	1			T40	1		T113	10		T42	2
all_values[2]	auto[0]	auto[0]	619492	1			T1	1		T2	69		T3	1
all_values[2]	auto[0]	auto[1]	15785	1			T83	4		T40	4282		T113	680
all_values[2]	auto[1]	auto[0]	190	1			T1	1		T7	1		T143	1
all_values[2]	auto[1]	auto[1]	161	1			T83	1		T40	1		T113	11
all_values[3]	auto[0]	auto[0]	620613	1			T1	2		T2	69		T3	1
all_values[3]	auto[0]	auto[1]	14842	1			T83	2		T40	4281		T113	681
all_values[3]	auto[1]	auto[1]	173	1			T83	4		T40	3		T113	10
all_values[4]	auto[0]	auto[0]	619689	1			T1	2		T2	69		T3	1
all_values[4]	auto[0]	auto[1]	15769	1			T83	4		T40	4283		T113	680
all_values[4]	auto[1]	auto[0]	18	1			T28	1		T249	1		T253	1
all_values[4]	auto[1]	auto[1]	152	1			T83	2		T40	2		T113	11
all_values[5]	auto[0]	auto[0]	629906	1			T1	2		T2	69		T3	1
all_values[5]	auto[0]	auto[1]	5558	1			T113	683		T42	9		T20	3115
all_values[5]	auto[1]	auto[1]	164	1			T113	9		T42	5		T20	5
all_values[6]	auto[0]	auto[0]	625606	1			T1	2		T2	69		T3	1
all_values[6]	auto[0]	auto[1]	9849	1			T83	2		T40	4281		T113	681
all_values[6]	auto[1]	auto[1]	173	1			T83	4		T40	4		T113	11
all_values[7]	auto[0]	auto[0]	593861	1			T1	2		T2	65		T3	1
all_values[7]	auto[0]	auto[1]	14443	1			T83	2		T40	4139		T113	561
all_values[7]	auto[1]	auto[0]	25846	1			T2	4		T18	2		T34	1
all_values[7]	auto[1]	auto[1]	1478	1			T83	4		T40	144		T113	130
all_values[8]	auto[0]	auto[0]	623978	1			T1	2		T2	69		T3	1
all_values[8]	auto[0]	auto[1]	11477	1			T83	4		T113	682		T42	6
all_values[8]	auto[1]	auto[1]	173	1			T83	2		T113	10		T42	8
all_values[9]	auto[0]	auto[0]	145393	1			T1	2		T2	65		T3	1
all_values[9]	auto[0]	auto[1]	7211	1			T40	1176		T113	674		T42	12
all_values[9]	auto[1]	auto[0]	474309	1			T2	4		T6	1		T7	1
all_values[9]	auto[1]	auto[1]	8715	1			T40	3109		T113	16		T42	2
all_values[10]	auto[0]	auto[0]	619680	1			T1	2		T2	69		T3	1
all_values[10]	auto[0]	auto[1]	15780	1			T83	4		T40	4282		T113	679
all_values[10]	auto[1]	auto[1]	168	1			T83	2		T40	1		T113	12
all_values[11]	auto[0]	auto[0]	2336	1			T2	3		T3	1		T5	9
all_values[11]	auto[0]	auto[1]	303	1			T83	5		T40	14		T113	16
all_values[11]	auto[1]	auto[0]	617359	1			T1	2		T2	66		T4	2
all_values[11]	auto[1]	auto[1]	15630	1			T83	1		T40	4271		T113	676
all_values[12]	auto[0]	auto[0]	619614	1			T1	1		T2	69		T3	1
all_values[12]	auto[0]	auto[1]	15786	1			T83	3		T40	4283		T113	684
all_values[12]	auto[1]	auto[0]	63	1			T1	1		T59	1		T69	1
all_values[12]	auto[1]	auto[1]	165	1			T83	2		T40	2		T113	8
all_values[13]	auto[0]	auto[0]	619701	1			T1	2		T2	69		T3	1
all_values[13]	auto[0]	auto[1]	15771	1			T83	4		T40	4284		T113	683
all_values[13]	auto[1]	auto[1]	156	1			T83	2		T40	1		T113	9
all_values[14]	auto[0]	auto[0]	619733	1			T1	2		T2	69		T3	1
all_values[14]	auto[0]	auto[1]	15726	1			T83	4		T40	4281		T113	683
all_values[14]	auto[1]	auto[1]	169	1			T83	1		T40	3		T113	8