Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	635628	1			T1	2		T2	69		T3	1
all_pins[1]	635628	1			T1	2		T2	69		T3	1
all_pins[2]	635628	1			T1	2		T2	69		T3	1
all_pins[3]	635628	1			T1	2		T2	69		T3	1
all_pins[4]	635628	1			T1	2		T2	69		T3	1
all_pins[5]	635628	1			T1	2		T2	69		T3	1
all_pins[6]	635628	1			T1	2		T2	69		T3	1
all_pins[7]	635628	1			T1	2		T2	69		T3	1
all_pins[8]	635628	1			T1	2		T2	69		T3	1
all_pins[9]	635628	1			T1	2		T2	69		T3	1
all_pins[10]	635628	1			T1	2		T2	69		T3	1
all_pins[11]	635628	1			T1	2		T2	69		T3	1
all_pins[12]	635628	1			T1	2		T2	69		T3	1
all_pins[13]	635628	1			T1	2		T2	69		T3	1
all_pins[14]	635628	1			T1	2		T2	69		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7849133	1			T1	27		T2	1031		T3	15
values[0x1]	1685287	1			T1	3		T2	4		T4	4
transitions[0x0=>0x1]	1684724	1			T1	3		T2	4		T4	4
transitions[0x1=>0x0]	1683412	1			T1	3		T2	4		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93089	1			T1	1		T2	69		T3	1
all_pins[0]	values[0x1]	542539	1			T1	1		T4	2		T6	2
all_pins[0]	transitions[0x0=>0x1]	542282	1			T1	1		T4	2		T6	2
all_pins[0]	transitions[0x1=>0x0]	60	1			T250	2		T113	3		T42	1
all_pins[1]	values[0x0]	635311	1			T1	2		T2	69		T3	1
all_pins[1]	values[0x1]	317	1			T267	1		T83	1		T250	2
all_pins[1]	transitions[0x0=>0x1]	300	1			T267	1		T83	1		T250	2
all_pins[1]	transitions[0x1=>0x0]	109	1			T7	1		T143	1		T83	1
all_pins[2]	values[0x0]	635502	1			T1	2		T2	69		T3	1
all_pins[2]	values[0x1]	126	1			T7	1		T143	1		T83	1
all_pins[2]	transitions[0x0=>0x1]	109	1			T7	1		T143	1		T83	1
all_pins[2]	transitions[0x1=>0x0]	51	1			T113	1		T42	2		T20	1
all_pins[3]	values[0x0]	635560	1			T1	2		T2	69		T3	1
all_pins[3]	values[0x1]	68	1			T113	1		T42	2		T20	1
all_pins[3]	transitions[0x0=>0x1]	57	1			T113	1		T42	2		T20	1
all_pins[3]	transitions[0x1=>0x0]	81	1			T28	1		T249	1		T253	1
all_pins[4]	values[0x0]	635536	1			T1	2		T2	69		T3	1
all_pins[4]	values[0x1]	92	1			T28	1		T249	1		T253	1
all_pins[4]	transitions[0x0=>0x1]	78	1			T28	1		T249	1		T253	1
all_pins[4]	transitions[0x1=>0x0]	73	1			T113	2		T20	3		T29	3
all_pins[5]	values[0x0]	635541	1			T1	2		T2	69		T3	1
all_pins[5]	values[0x1]	87	1			T113	4		T20	3		T29	4
all_pins[5]	transitions[0x0=>0x1]	67	1			T113	4		T20	3		T29	3
all_pins[5]	transitions[0x1=>0x0]	63	1			T83	2		T40	2		T113	4
all_pins[6]	values[0x0]	635545	1			T1	2		T2	69		T3	1
all_pins[6]	values[0x1]	83	1			T83	2		T40	2		T113	4
all_pins[6]	transitions[0x0=>0x1]	61	1			T83	2		T113	3		T20	1
all_pins[6]	transitions[0x1=>0x0]	29494	1			T34	1		T46	145		T35	1
all_pins[7]	values[0x0]	606112	1			T1	2		T2	69		T3	1
all_pins[7]	values[0x1]	29516	1			T34	1		T46	145		T35	1
all_pins[7]	transitions[0x0=>0x1]	29486	1			T34	1		T46	145		T35	1
all_pins[7]	transitions[0x1=>0x0]	59	1			T113	5		T42	6		T20	1
all_pins[8]	values[0x0]	635539	1			T1	2		T2	69		T3	1
all_pins[8]	values[0x1]	89	1			T83	1		T113	7		T42	8
all_pins[8]	transitions[0x0=>0x1]	74	1			T83	1		T113	7		T42	8
all_pins[8]	transitions[0x1=>0x0]	482953	1			T2	4		T6	1		T7	1
all_pins[9]	values[0x0]	152660	1			T1	2		T2	65		T3	1
all_pins[9]	values[0x1]	482968	1			T2	4		T6	1		T7	1
all_pins[9]	transitions[0x0=>0x1]	482949	1			T2	4		T6	1		T7	1
all_pins[9]	transitions[0x1=>0x0]	73	1			T83	1		T40	1		T113	4
all_pins[10]	values[0x0]	635536	1			T1	2		T2	69		T3	1
all_pins[10]	values[0x1]	92	1			T83	1		T40	1		T113	5
all_pins[10]	transitions[0x0=>0x1]	61	1			T83	1		T113	5		T20	2
all_pins[10]	transitions[0x1=>0x0]	628972	1			T1	1		T4	2		T6	2
all_pins[11]	values[0x0]	6625	1			T1	1		T2	69		T3	1
all_pins[11]	values[0x1]	629003	1			T1	1		T4	2		T6	2
all_pins[11]	transitions[0x0=>0x1]	628965	1			T1	1		T4	2		T6	2
all_pins[11]	transitions[0x1=>0x0]	114	1			T1	1		T59	1		T69	1
all_pins[12]	values[0x0]	635476	1			T1	1		T2	69		T3	1
all_pins[12]	values[0x1]	152	1			T1	1		T59	1		T69	1
all_pins[12]	transitions[0x0=>0x1]	129	1			T1	1		T59	1		T69	1
all_pins[12]	transitions[0x1=>0x0]	48	1			T113	2		T42	1		T29	4
all_pins[13]	values[0x0]	635557	1			T1	2		T2	69		T3	1
all_pins[13]	values[0x1]	71	1			T83	1		T40	1		T113	2
all_pins[13]	transitions[0x0=>0x1]	52	1			T83	1		T42	1		T29	4
all_pins[13]	transitions[0x1=>0x0]	65	1			T113	3		T42	3		T20	3
all_pins[14]	values[0x0]	635544	1			T1	2		T2	69		T3	1
all_pins[14]	values[0x1]	84	1			T40	1		T113	5		T42	3
all_pins[14]	transitions[0x0=>0x1]	54	1			T113	4		T42	3		T20	2
all_pins[14]	transitions[0x1=>0x0]	541197	1			T1	1		T4	1		T6	1