Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	379	1			T83	4		T40	4		T113	22
all_values[1]	379	1			T83	4		T40	4		T113	22
all_values[2]	379	1			T83	4		T40	4		T113	22
all_values[3]	379	1			T83	4		T40	4		T113	22
all_values[4]	379	1			T83	4		T40	4		T113	22
all_values[5]	379	1			T83	4		T40	4		T113	22
all_values[6]	379	1			T83	4		T40	4		T113	22
all_values[7]	379	1			T83	4		T40	4		T113	22
all_values[8]	379	1			T83	4		T40	4		T113	22
all_values[9]	379	1			T83	4		T40	4		T113	22
all_values[10]	379	1			T83	4		T40	4		T113	22
all_values[11]	379	1			T83	4		T40	4		T113	22
all_values[12]	379	1			T83	4		T40	4		T113	22
all_values[13]	379	1			T83	4		T40	4		T113	22
all_values[14]	379	1			T83	4		T40	4		T113	22

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3058

1

T83

38

T40

15

T113

164

auto[1]

2627

1

T83

22

T40

45

T113

166

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

898

1

T83

16

T40

18

T113

8

auto[1]

4787

1

T83

44

T40

42

T113

322

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3380

1

T83

40

T40

38

T113

196

auto[1]

2305

1

T83

20

T40

22

T113

134

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T83	1		T33	1		T275	1
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T83	1		T113	6		T42	3
all_values[0]	auto[0]	auto[1]	auto[0]	12	1			T30	1		T276	1		T277	2
all_values[0]	auto[0]	auto[1]	auto[1]	94	1			T83	1		T40	2		T113	5
all_values[0]	auto[1]	auto[0]	auto[1]	90	1			T113	6		T42	5		T20	1
all_values[0]	auto[1]	auto[1]	auto[1]	73	1			T83	1		T40	2		T113	5
all_values[1]	auto[0]	auto[0]	auto[0]	35	1			T83	1		T42	2		T278	1
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T40	1		T113	6		T42	4
all_values[1]	auto[0]	auto[1]	auto[0]	28	1			T83	3		T40	2		T279	1
all_values[1]	auto[0]	auto[1]	auto[1]	75	1			T113	6		T42	3		T20	3
all_values[1]	auto[1]	auto[0]	auto[1]	82	1			T40	1		T113	7		T42	2
all_values[1]	auto[1]	auto[1]	auto[1]	77	1			T113	3		T20	3		T29	3
all_values[2]	auto[0]	auto[0]	auto[0]	30	1			T83	1		T20	1		T280	2
all_values[2]	auto[0]	auto[0]	auto[1]	88	1			T113	3		T42	3		T20	3
all_values[2]	auto[0]	auto[1]	auto[0]	19	1			T40	2		T113	1		T280	3
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T83	2		T40	1		T113	7
all_values[2]	auto[1]	auto[0]	auto[1]	85	1			T113	4		T42	5		T29	2
all_values[2]	auto[1]	auto[1]	auto[1]	76	1			T83	1		T40	1		T113	7
all_values[3]	auto[0]	auto[0]	auto[0]	38	1			T29	1		T33	1		T275	2
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T83	1		T40	1		T113	8
all_values[3]	auto[0]	auto[1]	auto[0]	31	1			T40	1		T113	1		T33	3
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T113	3		T42	2		T29	2
all_values[3]	auto[1]	auto[0]	auto[1]	101	1			T83	3		T40	2		T113	7
all_values[3]	auto[1]	auto[1]	auto[1]	54	1			T113	3		T42	3		T20	1
all_values[4]	auto[0]	auto[0]	auto[0]	37	1			T20	1		T275	1		T30	2
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T83	1		T40	2		T113	6
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T113	1		T20	3		T29	1
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T83	1		T113	4		T42	2
all_values[4]	auto[1]	auto[0]	auto[1]	90	1			T83	1		T40	1		T113	5
all_values[4]	auto[1]	auto[1]	auto[1]	62	1			T83	1		T40	1		T113	6
all_values[5]	auto[0]	auto[0]	auto[0]	47	1			T83	1		T40	1		T20	1
all_values[5]	auto[0]	auto[0]	auto[1]	77	1			T113	6		T42	3		T20	3
all_values[5]	auto[0]	auto[1]	auto[0]	27	1			T83	3		T40	3		T29	1
all_values[5]	auto[0]	auto[1]	auto[1]	84	1			T113	7		T42	4		T20	2
all_values[5]	auto[1]	auto[0]	auto[1]	85	1			T113	5		T42	2		T29	2
all_values[5]	auto[1]	auto[1]	auto[1]	59	1			T113	4		T42	2		T20	2
all_values[6]	auto[0]	auto[0]	auto[0]	32	1			T42	1		T20	1		T30	1
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T83	2		T113	10		T42	1
all_values[6]	auto[0]	auto[1]	auto[0]	25	1			T20	3		T279	4		T275	2
all_values[6]	auto[0]	auto[1]	auto[1]	92	1			T83	1		T40	1		T113	2
all_values[6]	auto[1]	auto[0]	auto[1]	81	1			T83	1		T40	1		T113	4
all_values[6]	auto[1]	auto[1]	auto[1]	60	1			T40	2		T113	6		T42	1
all_values[7]	auto[0]	auto[0]	auto[0]	41	1			T42	1		T20	1		T29	1
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T83	2		T113	5		T42	3
all_values[7]	auto[0]	auto[1]	auto[0]	22	1			T40	2		T113	1		T29	1
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T40	1		T113	9		T42	1
all_values[7]	auto[1]	auto[0]	auto[1]	76	1			T83	2		T113	2		T42	5
all_values[7]	auto[1]	auto[1]	auto[1]	75	1			T40	1		T113	5		T42	1
all_values[8]	auto[0]	auto[0]	auto[0]	27	1			T33	1		T126	3		T281	1
all_values[8]	auto[0]	auto[0]	auto[1]	96	1			T83	2		T113	6		T20	2
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T40	4		T279	2		T33	3
all_values[8]	auto[0]	auto[1]	auto[1]	77	1			T113	5		T42	4		T20	4
all_values[8]	auto[1]	auto[0]	auto[1]	79	1			T83	2		T113	5		T42	2
all_values[8]	auto[1]	auto[1]	auto[1]	72	1			T113	6		T42	5		T20	1
all_values[9]	auto[0]	auto[0]	auto[0]	42	1			T83	2		T29	1		T30	2
all_values[9]	auto[0]	auto[0]	auto[1]	100	1			T40	2		T113	6		T42	4
all_values[9]	auto[0]	auto[1]	auto[0]	22	1			T83	2		T113	2		T29	1
all_values[9]	auto[0]	auto[1]	auto[1]	76	1			T113	8		T42	3		T20	2
all_values[9]	auto[1]	auto[0]	auto[1]	79	1			T40	1		T113	4		T42	4
all_values[9]	auto[1]	auto[1]	auto[1]	60	1			T40	1		T113	2		T20	4
all_values[10]	auto[0]	auto[0]	auto[0]	19	1			T33	1		T278	1		T282	1
all_values[10]	auto[0]	auto[0]	auto[1]	81	1			T83	2		T113	6		T42	4
all_values[10]	auto[0]	auto[1]	auto[0]	26	1			T40	2		T113	1		T279	1
all_values[10]	auto[0]	auto[1]	auto[1]	85	1			T40	1		T113	3		T42	4
all_values[10]	auto[1]	auto[0]	auto[1]	82	1			T83	2		T113	8		T42	2
all_values[10]	auto[1]	auto[1]	auto[1]	86	1			T40	1		T113	4		T42	1
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T33	1		T280	1		T278	1
all_values[11]	auto[0]	auto[0]	auto[1]	90	1			T83	3		T113	10		T42	1
all_values[11]	auto[0]	auto[1]	auto[0]	18	1			T279	1		T280	1		T126	1
all_values[11]	auto[0]	auto[1]	auto[1]	72	1			T40	2		T113	5		T42	3
all_values[11]	auto[1]	auto[0]	auto[1]	97	1			T83	1		T113	4		T42	5
all_values[11]	auto[1]	auto[1]	auto[1]	61	1			T40	2		T113	3		T42	2
all_values[12]	auto[0]	auto[0]	auto[0]	20	1			T83	1		T20	2		T33	1
all_values[12]	auto[0]	auto[0]	auto[1]	85	1			T113	5		T42	5		T29	2
all_values[12]	auto[0]	auto[1]	auto[0]	22	1			T20	2		T279	1		T33	1
all_values[12]	auto[0]	auto[1]	auto[1]	87	1			T83	1		T40	2		T113	9
all_values[12]	auto[1]	auto[0]	auto[1]	85	1			T113	5		T42	1		T20	1
all_values[12]	auto[1]	auto[1]	auto[1]	80	1			T83	2		T40	2		T113	3
all_values[13]	auto[0]	auto[0]	auto[0]	32	1			T20	1		T126	1		T283	3
all_values[13]	auto[0]	auto[0]	auto[1]	71	1			T113	7		T42	2		T29	2
all_values[13]	auto[0]	auto[1]	auto[0]	32	1			T20	3		T279	1		T283	1
all_values[13]	auto[0]	auto[1]	auto[1]	86	1			T83	2		T40	2		T113	10
all_values[13]	auto[1]	auto[0]	auto[1]	85	1			T83	1		T113	2		T42	4
all_values[13]	auto[1]	auto[1]	auto[1]	73	1			T83	1		T40	2		T113	3
all_values[14]	auto[0]	auto[0]	auto[0]	50	1			T83	1		T42	2		T29	2
all_values[14]	auto[0]	auto[0]	auto[1]	70	1			T83	2		T40	2		T113	6
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T40	1		T113	1		T42	1
all_values[14]	auto[0]	auto[1]	auto[1]	91	1			T113	9		T42	1		T20	4
all_values[14]	auto[1]	auto[0]	auto[1]	80	1			T83	1		T42	1		T20	1
all_values[14]	auto[1]	auto[1]	auto[1]	60	1			T40	1		T113	6		T42	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal