Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	697612	1			T1	8		T2	12		T3	680
all_values[1]	697612	1			T1	8		T2	12		T3	680
all_values[2]	697612	1			T1	8		T2	12		T3	680
all_values[3]	697612	1			T1	8		T2	12		T3	680
all_values[4]	697612	1			T1	8		T2	12		T3	680
all_values[5]	697612	1			T1	8		T2	12		T3	680
all_values[6]	697612	1			T1	8		T2	12		T3	680
all_values[7]	697612	1			T1	8		T2	12		T3	680
all_values[8]	697612	1			T1	8		T2	12		T3	680
all_values[9]	697612	1			T1	8		T2	12		T3	680
all_values[10]	697612	1			T1	8		T2	12		T3	680
all_values[11]	697612	1			T1	8		T2	12		T3	680
all_values[12]	697612	1			T1	8		T2	12		T3	680
all_values[13]	697612	1			T1	8		T2	12		T3	680
all_values[14]	697612	1			T1	8		T2	12		T3	680

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8641371

1

T1

105

T2

156

T3

9168

auto[1]

1822809

1

T1

15

T2

24

T3

1032

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10356872

1

T1

120

T2

180

T3

10200

auto[1]

107308

1

T178

258

T179

114

T116

8805

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114100	1			T1	2		T3	447		T14	1
all_values[0]	auto[0]	auto[1]	1768	1			T178	7		T179	4		T116	21
all_values[0]	auto[1]	auto[0]	576663	1			T1	6		T2	12		T3	233
all_values[0]	auto[1]	auto[1]	5081	1			T178	11		T179	5		T116	567
all_values[1]	auto[0]	auto[0]	690095	1			T1	8		T2	12		T3	680
all_values[1]	auto[0]	auto[1]	7189	1			T178	12		T179	5		T116	581
all_values[1]	auto[1]	auto[0]	140	1			T261	2		T262	1		T263	2
all_values[1]	auto[1]	auto[1]	188	1			T178	6		T179	3		T116	5
all_values[2]	auto[0]	auto[0]	690252	1			T1	8		T2	12		T3	680
all_values[2]	auto[0]	auto[1]	7014	1			T178	15		T179	6		T116	584
all_values[2]	auto[1]	auto[0]	189	1			T4	1		T51	1		T52	1
all_values[2]	auto[1]	auto[1]	157	1			T178	3		T179	2		T116	4
all_values[3]	auto[0]	auto[0]	690264	1			T1	8		T2	12		T3	680
all_values[3]	auto[0]	auto[1]	7179	1			T178	11		T179	6		T116	580
all_values[3]	auto[1]	auto[1]	169	1			T178	4		T179	3		T116	7
all_values[4]	auto[0]	auto[0]	691235	1			T1	8		T2	12		T3	680
all_values[4]	auto[0]	auto[1]	6199	1			T178	12		T179	3		T116	580
all_values[4]	auto[1]	auto[0]	21	1			T25	1		T252	2		T238	1
all_values[4]	auto[1]	auto[1]	157	1			T178	1		T179	1		T116	5
all_values[5]	auto[0]	auto[0]	690261	1			T1	8		T2	12		T3	680
all_values[5]	auto[0]	auto[1]	7161	1			T178	17		T179	2		T116	582
all_values[5]	auto[1]	auto[1]	190	1			T179	7		T116	5		T105	4
all_values[6]	auto[0]	auto[0]	690427	1			T1	8		T2	12		T3	680
all_values[6]	auto[0]	auto[1]	7004	1			T178	17		T179	3		T116	585
all_values[6]	auto[1]	auto[1]	181	1			T178	1		T179	3		T116	2
all_values[7]	auto[0]	auto[0]	659870	1			T1	5		T2	12		T3	569
all_values[7]	auto[0]	auto[1]	6360	1			T178	11		T179	5		T116	546
all_values[7]	auto[1]	auto[0]	30405	1			T1	3		T3	111		T14	1
all_values[7]	auto[1]	auto[1]	977	1			T178	6		T179	3		T116	41
all_values[8]	auto[0]	auto[0]	690553	1			T1	8		T2	12		T3	680
all_values[8]	auto[0]	auto[1]	6896	1			T178	14		T179	4		T116	587
all_values[8]	auto[1]	auto[1]	163	1			T178	4		T179	2		T233	8
all_values[9]	auto[0]	auto[0]	180688	1			T1	8		T2	12		T3	670
all_values[9]	auto[0]	auto[1]	4405	1			T178	10		T179	7		T116	568
all_values[9]	auto[1]	auto[0]	509579	1			T3	10		T4	1		T7	1
all_values[9]	auto[1]	auto[1]	2940	1			T178	7		T179	1		T116	20
all_values[10]	auto[0]	auto[0]	691064	1			T1	8		T2	12		T3	680
all_values[10]	auto[0]	auto[1]	6393	1			T178	15		T179	5		T116	582
all_values[10]	auto[1]	auto[1]	155	1			T178	3		T179	4		T116	5
all_values[11]	auto[0]	auto[0]	2440	1			T1	2		T3	2		T14	1
all_values[11]	auto[0]	auto[1]	282	1			T178	7		T179	4		T116	22
all_values[11]	auto[1]	auto[0]	687834	1			T1	6		T2	12		T3	678
all_values[11]	auto[1]	auto[1]	7056	1			T178	11		T179	1		T116	566
all_values[12]	auto[0]	auto[0]	690188	1			T1	8		T2	12		T3	680
all_values[12]	auto[0]	auto[1]	7192	1			T178	13		T179	7		T116	582
all_values[12]	auto[1]	auto[0]	61	1			T51	1		T52	1		T264	1
all_values[12]	auto[1]	auto[1]	171	1			T178	5		T179	1		T116	5
all_values[13]	auto[0]	auto[0]	690268	1			T1	8		T2	12		T3	680
all_values[13]	auto[0]	auto[1]	7184	1			T178	15		T179	6		T116	583
all_values[13]	auto[1]	auto[1]	160	1			T178	2		T179	2		T116	3
all_values[14]	auto[0]	auto[0]	690275	1			T1	8		T2	12		T3	680
all_values[14]	auto[0]	auto[1]	7165	1			T178	15		T179	6		T116	579
all_values[14]	auto[1]	auto[1]	172	1			T178	3		T179	3		T116	8