Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	697612	1			T1	8		T2	12		T3	680
all_pins[1]	697612	1			T1	8		T2	12		T3	680
all_pins[2]	697612	1			T1	8		T2	12		T3	680
all_pins[3]	697612	1			T1	8		T2	12		T3	680
all_pins[4]	697612	1			T1	8		T2	12		T3	680
all_pins[5]	697612	1			T1	8		T2	12		T3	680
all_pins[6]	697612	1			T1	8		T2	12		T3	680
all_pins[7]	697612	1			T1	8		T2	12		T3	680
all_pins[8]	697612	1			T1	8		T2	12		T3	680
all_pins[9]	697612	1			T1	8		T2	12		T3	680
all_pins[10]	697612	1			T1	8		T2	12		T3	680
all_pins[11]	697612	1			T1	8		T2	12		T3	680
all_pins[12]	697612	1			T1	8		T2	12		T3	680
all_pins[13]	697612	1			T1	8		T2	12		T3	680
all_pins[14]	697612	1			T1	8		T2	12		T3	680

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8647666	1			T1	105		T2	156		T3	9165
values[0x1]	1816514	1			T1	15		T2	24		T3	1035
transitions[0x0=>0x1]	1815986	1			T1	15		T2	24		T3	1035
transitions[0x1=>0x0]	1814677	1			T1	14		T2	23		T3	1034

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	119360	1			T1	2		T3	447		T5	1
all_pins[0]	values[0x1]	578252	1			T1	6		T2	12		T3	233
all_pins[0]	transitions[0x0=>0x1]	578057	1			T1	6		T2	12		T3	233
all_pins[0]	transitions[0x1=>0x0]	57	1			T178	1		T116	1		T105	1
all_pins[1]	values[0x0]	697360	1			T1	8		T2	12		T3	680
all_pins[1]	values[0x1]	252	1			T271	1		T178	2		T179	1
all_pins[1]	transitions[0x0=>0x1]	227	1			T271	1		T178	2		T179	1
all_pins[1]	transitions[0x1=>0x0]	111	1			T4	1		T264	1		T272	1
all_pins[2]	values[0x0]	697476	1			T1	8		T2	12		T3	680
all_pins[2]	values[0x1]	136	1			T4	1		T264	1		T272	1
all_pins[2]	transitions[0x0=>0x1]	119	1			T4	1		T264	1		T272	1
all_pins[2]	transitions[0x1=>0x0]	67	1			T178	1		T179	1		T116	4
all_pins[3]	values[0x0]	697528	1			T1	8		T2	12		T3	680
all_pins[3]	values[0x1]	84	1			T178	2		T179	1		T116	4
all_pins[3]	transitions[0x0=>0x1]	72	1			T178	2		T179	1		T116	4
all_pins[3]	transitions[0x1=>0x0]	86	1			T25	1		T246	1		T252	2
all_pins[4]	values[0x0]	697514	1			T1	8		T2	12		T3	680
all_pins[4]	values[0x1]	98	1			T25	1		T246	1		T252	2
all_pins[4]	transitions[0x0=>0x1]	79	1			T25	1		T246	1		T252	2
all_pins[4]	transitions[0x1=>0x0]	82	1			T179	5		T116	2		T233	8
all_pins[5]	values[0x0]	697511	1			T1	8		T2	12		T3	680
all_pins[5]	values[0x1]	101	1			T179	5		T116	2		T233	10
all_pins[5]	transitions[0x0=>0x1]	67	1			T179	5		T116	2		T233	6
all_pins[5]	transitions[0x1=>0x0]	69	1			T116	1		T233	3		T273	2
all_pins[6]	values[0x0]	697509	1			T1	8		T2	12		T3	680
all_pins[6]	values[0x1]	103	1			T116	1		T233	7		T273	2
all_pins[6]	transitions[0x0=>0x1]	84	1			T116	1		T233	4		T273	2
all_pins[6]	transitions[0x1=>0x0]	33725	1			T1	3		T3	114		T14	1
all_pins[7]	values[0x0]	663868	1			T1	5		T2	12		T3	566
all_pins[7]	values[0x1]	33744	1			T1	3		T3	114		T14	1
all_pins[7]	transitions[0x0=>0x1]	33721	1			T1	3		T3	114		T14	1
all_pins[7]	transitions[0x1=>0x0]	60	1			T178	2		T233	2		T273	2
all_pins[8]	values[0x0]	697529	1			T1	8		T2	12		T3	680
all_pins[8]	values[0x1]	83	1			T178	2		T233	5		T273	3
all_pins[8]	transitions[0x0=>0x1]	61	1			T178	1		T233	2		T273	1
all_pins[8]	transitions[0x1=>0x0]	512437	1			T3	10		T4	1		T7	1
all_pins[9]	values[0x0]	185153	1			T1	8		T2	12		T3	670
all_pins[9]	values[0x1]	512459	1			T3	10		T4	1		T7	1
all_pins[9]	transitions[0x0=>0x1]	512440	1			T3	10		T4	1		T7	1
all_pins[9]	transitions[0x1=>0x0]	56	1			T178	1		T179	2		T116	1
all_pins[10]	values[0x0]	697537	1			T1	8		T2	12		T3	680
all_pins[10]	values[0x1]	75	1			T178	1		T179	2		T116	1
all_pins[10]	transitions[0x0=>0x1]	55	1			T178	1		T179	2		T116	1
all_pins[10]	transitions[0x1=>0x0]	690779	1			T1	6		T2	12		T3	678
all_pins[11]	values[0x0]	6813	1			T1	2		T3	2		T5	1
all_pins[11]	values[0x1]	690799	1			T1	6		T2	12		T3	678
all_pins[11]	transitions[0x0=>0x1]	690763	1			T1	6		T2	12		T3	678
all_pins[11]	transitions[0x1=>0x0]	116	1			T51	1		T52	1		T67	1
all_pins[12]	values[0x0]	697460	1			T1	8		T2	12		T3	680
all_pins[12]	values[0x1]	152	1			T51	1		T52	1		T264	1
all_pins[12]	transitions[0x0=>0x1]	125	1			T51	1		T52	1		T264	1
all_pins[12]	transitions[0x1=>0x0]	63	1			T178	1		T116	2		T105	1
all_pins[13]	values[0x0]	697522	1			T1	8		T2	12		T3	680
all_pins[13]	values[0x1]	90	1			T178	1		T116	2		T105	1
all_pins[13]	transitions[0x0=>0x1]	69	1			T178	1		T116	1		T105	1
all_pins[13]	transitions[0x1=>0x0]	65	1			T178	3		T179	3		T233	1
all_pins[14]	values[0x0]	697526	1			T1	8		T2	12		T3	680
all_pins[14]	values[0x1]	86	1			T178	3		T179	3		T116	1
all_pins[14]	transitions[0x0=>0x1]	47	1			T178	1		T179	1		T233	3
all_pins[14]	transitions[0x1=>0x0]	576904	1			T1	5		T2	11		T3	232