Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	389	1			T178	7		T179	7		T116	11
all_values[1]	389	1			T178	7		T179	7		T116	11
all_values[2]	389	1			T178	7		T179	7		T116	11
all_values[3]	389	1			T178	7		T179	7		T116	11
all_values[4]	389	1			T178	7		T179	7		T116	11
all_values[5]	389	1			T178	7		T179	7		T116	11
all_values[6]	389	1			T178	7		T179	7		T116	11
all_values[7]	389	1			T178	7		T179	7		T116	11
all_values[8]	389	1			T178	7		T179	7		T116	11
all_values[9]	389	1			T178	7		T179	7		T116	11
all_values[10]	389	1			T178	7		T179	7		T116	11
all_values[11]	389	1			T178	7		T179	7		T116	11
all_values[12]	389	1			T178	7		T179	7		T116	11
all_values[13]	389	1			T178	7		T179	7		T116	11
all_values[14]	389	1			T178	7		T179	7		T116	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3092

1

T178

59

T179

66

T116

87

auto[1]

2743

1

T178

46

T179

39

T116

78

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

913

1

T178

12

T179

21

T116

15

auto[1]

4922

1

T178

93

T179

84

T116

150

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3446

1

T178

60

T179

61

T116

95

auto[1]

2389

1

T178

45

T179

44

T116

70

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1			T105	1		T233	3		T118	2
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T178	2		T179	1		T116	2
all_values[0]	auto[0]	auto[1]	auto[0]	32	1			T233	8		T119	2		T120	1
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T178	2		T179	1		T116	3
all_values[0]	auto[1]	auto[0]	auto[1]	71	1			T178	1		T179	4		T116	1
all_values[0]	auto[1]	auto[1]	auto[1]	84	1			T178	2		T179	1		T116	5
all_values[1]	auto[0]	auto[0]	auto[0]	27	1			T179	1		T116	2		T273	1
all_values[1]	auto[0]	auto[0]	auto[1]	84	1			T179	2		T116	3		T105	1
all_values[1]	auto[0]	auto[1]	auto[0]	7	1			T274	1		T275	1		T276	1
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T178	1		T179	1		T116	1
all_values[1]	auto[1]	auto[0]	auto[1]	117	1			T178	5		T179	2		T116	3
all_values[1]	auto[1]	auto[1]	auto[1]	71	1			T178	1		T179	1		T116	2
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T179	1		T117	1		T118	4
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T178	3		T179	2		T233	3
all_values[2]	auto[0]	auto[1]	auto[0]	23	1			T233	3		T119	1		T120	2
all_values[2]	auto[0]	auto[1]	auto[1]	86	1			T178	1		T179	2		T116	7
all_values[2]	auto[1]	auto[0]	auto[1]	82	1			T178	1		T179	1		T116	3
all_values[2]	auto[1]	auto[1]	auto[1]	75	1			T178	2		T179	1		T116	1
all_values[3]	auto[0]	auto[0]	auto[0]	35	1			T178	3		T116	1		T105	1
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T178	2		T179	1		T116	3
all_values[3]	auto[0]	auto[1]	auto[0]	26	1			T274	1		T277	1		T278	2
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T178	1		T179	2		T116	2
all_values[3]	auto[1]	auto[0]	auto[1]	77	1			T179	2		T116	2		T105	1
all_values[3]	auto[1]	auto[1]	auto[1]	85	1			T178	1		T179	2		T116	3
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T178	1		T179	2		T116	2
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T179	1		T116	2		T233	2
all_values[4]	auto[0]	auto[1]	auto[0]	47	1			T178	4		T179	3		T116	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T178	1		T116	1		T105	2
all_values[4]	auto[1]	auto[0]	auto[1]	99	1			T179	1		T116	4		T233	1
all_values[4]	auto[1]	auto[1]	auto[1]	58	1			T178	1		T116	1		T105	1
all_values[5]	auto[0]	auto[0]	auto[0]	29	1			T178	1		T273	2		T117	1
all_values[5]	auto[0]	auto[0]	auto[1]	82	1			T178	3		T116	4		T105	1
all_values[5]	auto[0]	auto[1]	auto[0]	26	1			T116	1		T273	2		T279	1
all_values[5]	auto[0]	auto[1]	auto[1]	84	1			T178	1		T179	2		T116	1
all_values[5]	auto[1]	auto[0]	auto[1]	91	1			T178	1		T179	3		T116	2
all_values[5]	auto[1]	auto[1]	auto[1]	77	1			T178	1		T179	2		T116	3
all_values[6]	auto[0]	auto[0]	auto[0]	37	1			T179	3		T116	1		T105	1
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T178	3		T179	2		T233	2
all_values[6]	auto[0]	auto[1]	auto[0]	19	1			T233	1		T274	1		T118	2
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T178	2		T116	6		T105	1
all_values[6]	auto[1]	auto[0]	auto[1]	83	1			T178	2		T179	2		T116	1
all_values[6]	auto[1]	auto[1]	auto[1]	77	1			T116	3		T105	1		T233	6
all_values[7]	auto[0]	auto[0]	auto[0]	35	1			T179	1		T274	1		T118	1
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T178	3		T179	2		T116	1
all_values[7]	auto[0]	auto[1]	auto[0]	34	1			T178	1		T116	1		T233	1
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T179	1		T116	3		T105	2
all_values[7]	auto[1]	auto[0]	auto[1]	74	1			T178	3		T179	1		T116	3
all_values[7]	auto[1]	auto[1]	auto[1]	71	1			T179	2		T116	3		T105	1
all_values[8]	auto[0]	auto[0]	auto[0]	33	1			T179	1		T105	1		T117	2
all_values[8]	auto[0]	auto[0]	auto[1]	91	1			T178	1		T179	1		T116	2
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T179	2		T116	1		T105	3
all_values[8]	auto[0]	auto[1]	auto[1]	88	1			T178	3		T116	5		T233	5
all_values[8]	auto[1]	auto[0]	auto[1]	84	1			T178	2		T179	3		T116	2
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T178	1		T116	1		T233	4
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T178	1		T179	1		T117	1
all_values[9]	auto[0]	auto[0]	auto[1]	76	1			T116	3		T105	1		T233	3
all_values[9]	auto[0]	auto[1]	auto[0]	31	1			T105	1		T279	2		T277	3
all_values[9]	auto[0]	auto[1]	auto[1]	96	1			T178	4		T179	3		T116	5
all_values[9]	auto[1]	auto[0]	auto[1]	81	1			T179	3		T116	2		T233	1
all_values[9]	auto[1]	auto[1]	auto[1]	73	1			T178	2		T116	1		T105	2
all_values[10]	auto[0]	auto[0]	auto[0]	33	1			T117	1		T118	1		T280	2
all_values[10]	auto[0]	auto[0]	auto[1]	94	1			T178	3		T179	2		T116	3
all_values[10]	auto[0]	auto[1]	auto[0]	31	1			T116	1		T274	1		T117	3
all_values[10]	auto[0]	auto[1]	auto[1]	76	1			T178	1		T179	1		T116	2
all_values[10]	auto[1]	auto[0]	auto[1]	95	1			T178	2		T179	3		T116	5
all_values[10]	auto[1]	auto[1]	auto[1]	60	1			T178	1		T179	1		T105	2
all_values[11]	auto[0]	auto[0]	auto[0]	36	1			T179	3		T117	3		T281	1
all_values[11]	auto[0]	auto[0]	auto[1]	98	1			T178	3		T179	2		T116	4
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T179	1		T105	1		T233	1
all_values[11]	auto[0]	auto[1]	auto[1]	91	1			T178	1		T116	2		T105	1
all_values[11]	auto[1]	auto[0]	auto[1]	77	1			T178	2		T179	1		T116	4
all_values[11]	auto[1]	auto[1]	auto[1]	66	1			T178	1		T116	1		T105	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1			T179	1		T274	1		T117	1
all_values[12]	auto[0]	auto[0]	auto[1]	82	1			T178	2		T179	3		T116	4
all_values[12]	auto[0]	auto[1]	auto[0]	17	1			T116	1		T105	1		T274	4
all_values[12]	auto[0]	auto[1]	auto[1]	88	1			T179	2		T116	1		T233	7
all_values[12]	auto[1]	auto[0]	auto[1]	89	1			T178	3		T179	1		T116	5
all_values[12]	auto[1]	auto[1]	auto[1]	82	1			T178	2		T105	1		T233	4
all_values[13]	auto[0]	auto[0]	auto[0]	43	1			T179	1		T116	1		T273	2
all_values[13]	auto[0]	auto[0]	auto[1]	89	1			T178	1		T179	1		T116	2
all_values[13]	auto[0]	auto[1]	auto[0]	19	1			T178	1		T116	1		T117	1
all_values[13]	auto[0]	auto[1]	auto[1]	75	1			T178	2		T179	1		T116	3
all_values[13]	auto[1]	auto[0]	auto[1]	88	1			T178	1		T179	1		T116	2
all_values[13]	auto[1]	auto[1]	auto[1]	75	1			T178	2		T179	3		T116	2
all_values[14]	auto[0]	auto[0]	auto[0]	44	1			T120	2		T282	1		T283	1
all_values[14]	auto[0]	auto[0]	auto[1]	70	1			T178	2		T179	1		T116	4
all_values[14]	auto[0]	auto[1]	auto[0]	25	1			T116	1		T105	2		T233	2
all_values[14]	auto[0]	auto[1]	auto[1]	91	1			T179	3		T116	1		T105	1
all_values[14]	auto[1]	auto[0]	auto[1]	92	1			T178	2		T179	2		T116	4
all_values[14]	auto[1]	auto[1]	auto[1]	67	1			T178	3		T179	1		T116	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal