Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	632632	1			T1	5210		T2	3		T3	2
all_values[1]	632632	1			T1	5210		T2	3		T3	2
all_values[2]	632632	1			T1	5210		T2	3		T3	2
all_values[3]	632632	1			T1	5210		T2	3		T3	2
all_values[4]	632632	1			T1	5210		T2	3		T3	2
all_values[5]	632632	1			T1	5210		T2	3		T3	2
all_values[6]	632632	1			T1	5210		T2	3		T3	2
all_values[7]	632632	1			T1	5210		T2	3		T3	2
all_values[8]	632632	1			T1	5210		T2	3		T3	2
all_values[9]	632632	1			T1	5210		T2	3		T3	2
all_values[10]	632632	1			T1	5210		T2	3		T3	2
all_values[11]	632632	1			T1	5210		T2	3		T3	2
all_values[12]	632632	1			T1	5210		T2	3		T3	2
all_values[13]	632632	1			T1	5210		T2	3		T3	2
all_values[14]	632632	1			T1	5210		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7818147

1

T1

62628

T2

39

T3

26

auto[1]

1671333

1

T1

15522

T2

6

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8811333

1

T1

78150

T2

45

T3

30

auto[1]

678147

1

T191

12671

T192

355

T193

127

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99844	1			T1	113		T2	1		T4	2371
all_values[0]	auto[0]	auto[1]	6402	1			T191	605		T192	18		T193	5
all_values[0]	auto[1]	auto[0]	486949	1			T1	5097		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	39437	1			T191	240		T192	6		T193	3
all_values[1]	auto[0]	auto[0]	588470	1			T1	5210		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	43692	1			T191	841		T192	16		T193	4
all_values[1]	auto[1]	auto[0]	302	1			T32	6		T46	5		T27	9
all_values[1]	auto[1]	auto[1]	168	1			T191	4		T192	9		T193	4
all_values[2]	auto[0]	auto[0]	586587	1			T1	5210		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	45673	1			T191	841		T192	20		T193	5
all_values[2]	auto[1]	auto[0]	185	1			T5	2		T249	2		T59	1
all_values[2]	auto[1]	auto[1]	187	1			T191	4		T192	5		T193	4
all_values[3]	auto[0]	auto[0]	586771	1			T1	5210		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	45670	1			T191	840		T192	19		T193	3
all_values[3]	auto[1]	auto[1]	191	1			T191	3		T192	5		T193	6
all_values[4]	auto[0]	auto[0]	586759	1			T1	5210		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	45701	1			T191	841		T192	19		T193	5
all_values[4]	auto[1]	auto[0]	16	1			T25	2		T280	1		T281	1
all_values[4]	auto[1]	auto[1]	156	1			T191	1		T192	5		T193	3
all_values[5]	auto[0]	auto[0]	591866	1			T1	5210		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	40564	1			T191	841		T192	15		T193	6
all_values[5]	auto[1]	auto[1]	202	1			T191	5		T192	9		T193	3
all_values[6]	auto[0]	auto[0]	586788	1			T1	5210		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	45627	1			T191	840		T192	17		T193	5
all_values[6]	auto[1]	auto[1]	217	1			T191	4		T192	8		T193	4
all_values[7]	auto[0]	auto[0]	564493	1			T1	5083		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	41019	1			T191	804		T192	16		T193	6
all_values[7]	auto[1]	auto[0]	24836	1			T1	127		T2	1		T4	259
all_values[7]	auto[1]	auto[1]	2284	1			T191	40		T192	5		T193	3
all_values[8]	auto[0]	auto[0]	586785	1			T1	5210		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	45663	1			T191	844		T192	23		T193	5
all_values[8]	auto[1]	auto[1]	184	1			T191	2		T192	2		T193	4
all_values[9]	auto[0]	auto[0]	137402	1			T1	113		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	9942	1			T191	826		T192	13		T193	6
all_values[9]	auto[1]	auto[0]	449379	1			T1	5097		T2	1		T4	13969
all_values[9]	auto[1]	auto[1]	35909	1			T191	18		T192	4		T193	3
all_values[10]	auto[0]	auto[0]	586788	1			T1	5210		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	45681	1			T191	842		T192	17		T193	3
all_values[10]	auto[1]	auto[1]	163	1			T191	4		T192	7		T193	2
all_values[11]	auto[0]	auto[0]	2296	1			T1	9		T2	1		T4	9
all_values[11]	auto[0]	auto[1]	378	1			T191	12		T192	16		T193	6
all_values[11]	auto[1]	auto[0]	584470	1			T1	5201		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	45488	1			T191	834		T192	9		T193	3
all_values[12]	auto[0]	auto[0]	586719	1			T1	5210		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	45685	1			T191	841		T192	19		T193	6
all_values[12]	auto[1]	auto[0]	57	1			T59	1		T74	1		T75	1
all_values[12]	auto[1]	auto[1]	171	1			T191	3		T192	6		T193	3
all_values[13]	auto[0]	auto[0]	586789	1			T1	5210		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	45659	1			T191	844		T192	21		T193	7
all_values[13]	auto[1]	auto[1]	184	1			T191	1		T192	4		T193	2
all_values[14]	auto[0]	auto[0]	586782	1			T1	5210		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	45652	1			T191	844		T192	17		T193	5
all_values[14]	auto[1]	auto[1]	198	1			T191	2		T192	5		T193	3